diff -urN linux-2.4.10/Documentation/Configure.help linux-2.4.10-lia/Documentation/Configure.help --- linux-2.4.10/Documentation/Configure.help Mon Sep 24 15:06:08 2001 +++ linux-2.4.10-lia/Documentation/Configure.help Mon Sep 24 21:34:01 2001 @@ -2563,6 +2563,16 @@ the GLX component for XFree86 3.3.6, which can be downloaded from http://utah-glx.sourceforge.net/ . +Intel 460GX support +CONFIG_AGP_I460 + This option gives you AGP support for the Intel 460GX chipset. This + chipset, the first to support Intel Itanium processors, is new and + this option is correspondingly a little experimental. + + If you don't have a 460GX based machine (such as BigSur) with an AGP + slot then this option isn't going to do you much good. If you're + dying to do Direct Rendering on IA-64, this is what you're looking for. + Intel I810/I810 DC100/I810e support CONFIG_AGP_I810 This option gives you AGP support for the Xserver on the Intel 810 @@ -12680,6 +12690,18 @@ Say Y here if you would like to be able to read the hard disk partition table format used by SGI machines. +Intel EFI GUID partition support +CONFIG_EFI_PARTITION + Say Y here if you would like to use hard disks under Linux which + were partitioned using EFI GPT. Presently only useful on the + IA-64 platform. + +/dev/guid support (EXPERIMENTAL) +CONFIG_DEVFS_GUID + Say Y here if you would like to access disks and partitions by + their Globally Unique Identifiers (GUIDs) which will appear as + symbolic links in /dev/guid. + Ultrix partition support CONFIG_ULTRIX_PARTITION Say Y here if you would like to be able to read the hard disk @@ -18664,11 +18686,22 @@ so the "DIG-compliant" option is usually the right choice. HP-simulator For the HP simulator (http://software.hp.com/ia64linux/). - SN1-simulator For the SGI SN1 simulator. + SGI-SN1 For SGI SN1 Platforms. + SGI-SN2 For SGI SN2 Platforms. DIG-compliant For DIG ("Developer's Interface Guide") compliant system. If you don't know what to do, choose "generic". +CONFIG_IA64_SGI_SN_SIM + Build a kernel that runs on both the SGI simulator AND on hardware. + There is a very slight performance penalty on hardware for including this + option. + +CONFIG_IA64_SGI_SN_DEBUG + This enables addition debug code that helps isolate + platform/kernel bugs. There is a small but measurable performance + degradation when this option is enabled. + Kernel page size CONFIG_IA64_PAGE_SIZE_4KB @@ -18686,56 +18719,13 @@ If you don't know what to do, choose 8KB. -Enable Itanium A-step specific code -CONFIG_ITANIUM_ASTEP_SPECIFIC - Select this option to build a kernel for an Itanium prototype system - with an A-step CPU. You have an A-step CPU if the "revision" field in - /proc/cpuinfo is 0. - Enable Itanium B-step specific code CONFIG_ITANIUM_BSTEP_SPECIFIC Select this option to build a kernel for an Itanium prototype system - with a B-step CPU. You have a B-step CPU if the "revision" field in - /proc/cpuinfo has a value in the range from 1 to 4. - -Enable Itanium B0-step specific code -CONFIG_ITANIUM_B0_SPECIFIC - Select this option to bild a kernel for an Itanium prototype system - with a B0-step CPU. You have a B0-step CPU if the "revision" field in - /proc/cpuinfo is 1. - -Force interrupt redirection -CONFIG_IA64_HAVE_IRQREDIR - Select this option if you know that your system has the ability to - redirect interrupts to different CPUs. Select N here if you're - unsure. - -Enable use of global TLB purge instruction (ptc.g) -CONFIG_ITANIUM_PTCG - Say Y here if you want the kernel to use the IA-64 "ptc.g" - instruction to flush the TLB on all CPUs. Select N here if - you're unsure. - -Enable SoftSDV hacks -CONFIG_IA64_SOFTSDV_HACKS - Say Y here to enable hacks to make the kernel work on the Intel - SoftSDV simulator. Select N here if you're unsure. - -Enable AzusA hacks -CONFIG_IA64_AZUSA_HACKS - Say Y here to enable hacks to make the kernel work on the NEC - AzusA platform. Select N here if you're unsure. - -Force socket buffers below 4GB? -CONFIG_SKB_BELOW_4GB - Most of today's network interface cards (NICs) support DMA to - the low 32 bits of the address space only. On machines with - more then 4GB of memory, this can cause the system to slow - down if there is no I/O TLB hardware. Turning this option on - avoids the slow-down by forcing socket buffers to be allocated - from memory below 4GB. The downside is that your system could - run out of memory below 4GB before all memory has been used up. - If you're unsure how to answer this question, answer Y. + with a B-step CPU. Only B3 step CPUs are supported. You have a B3-step + CPU if the "revision" field in /proc/cpuinfo is equal to 4. If the + "revision" field shows a number bigger than 4, you do not have to turn + on this option. Enable IA-64 Machine Check Abort CONFIG_IA64_MCA @@ -18755,6 +18745,15 @@ Layer) information in /proc/pal. This contains useful information about the processors in your systems, such as cache and TLB sizes and the PAL firmware version in use. + + To use this option, you have to check that the "/proc file system + support" (CONFIG_PROC_FS) is enabled, too. + +/proc/efi/vars support +CONFIG_EFI_VARS + If you say Y here, you are able to get EFI (Extensible Firmware + Interface) variable information in /proc/efi/vars. You may read, + write, create, and destroy EFI variables through this interface. To use this option, you have to check that the "/proc file system support" (CONFIG_PROC_FS) is enabled, too. diff -urN linux-2.4.10/Makefile linux-2.4.10-lia/Makefile --- linux-2.4.10/Makefile Mon Sep 24 15:06:10 2001 +++ linux-2.4.10-lia/Makefile Mon Sep 24 15:21:25 2001 @@ -87,7 +87,7 @@ CPPFLAGS := -D__KERNEL__ -I$(HPATH) -CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -O2 \ +CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -g -O2 \ -fomit-frame-pointer -fno-strict-aliasing -fno-common AFLAGS := -D__ASSEMBLY__ $(CPPFLAGS) @@ -136,7 +136,8 @@ drivers/net/net.o \ drivers/media/media.o DRIVERS-$(CONFIG_AGP) += drivers/char/agp/agp.o -DRIVERS-$(CONFIG_DRM) += drivers/char/drm/drm.o +DRIVERS-$(CONFIG_DRM_NEW) += drivers/char/drm/drm.o +DRIVERS-$(CONFIG_DRM_OLD) += drivers/char/drm-4.0/drm.o DRIVERS-$(CONFIG_NUBUS) += drivers/nubus/nubus.a DRIVERS-$(CONFIG_ISDN) += drivers/isdn/isdn.a DRIVERS-$(CONFIG_NET_FC) += drivers/net/fc/fc.o @@ -240,14 +241,14 @@ include arch/$(ARCH)/Makefile -export CPPFLAGS CFLAGS AFLAGS +export CPPFLAGS CFLAGS CFLAGS_KERNEL AFLAGS AFLAGS_KERNEL export NETWORKS DRIVERS LIBS HEAD LDFLAGS LINKFLAGS MAKEBOOT ASFLAGS .S.s: - $(CPP) $(AFLAGS) -traditional -o $*.s $< + $(CPP) $(AFLAGS) $(AFLAGS_KERNEL) -traditional -o $*.s $< .S.o: - $(CC) $(AFLAGS) -traditional -c -o $*.o $< + $(CC) $(AFLAGS) $(AFLAGS_KERNEL) -traditional -c -o $*.o $< Version: dummy @rm -f include/linux/compile.h diff -urN linux-2.4.10/arch/i386/lib/usercopy.c linux-2.4.10-lia/arch/i386/lib/usercopy.c --- linux-2.4.10/arch/i386/lib/usercopy.c Mon Sep 24 15:06:13 2001 +++ linux-2.4.10-lia/arch/i386/lib/usercopy.c Mon Sep 24 15:21:33 2001 @@ -14,6 +14,7 @@ unsigned long __generic_copy_to_user(void *to, const void *from, unsigned long n) { + prefetch(from); if (access_ok(VERIFY_WRITE, to, n)) { if(n<512) @@ -27,6 +28,7 @@ unsigned long __generic_copy_from_user(void *to, const void *from, unsigned long n) { + prefetchw(to); if (access_ok(VERIFY_READ, from, n)) { if(n<512) diff -urN linux-2.4.10/arch/ia64/Makefile linux-2.4.10-lia/arch/ia64/Makefile --- linux-2.4.10/arch/ia64/Makefile Tue Jul 31 10:30:08 2001 +++ linux-2.4.10-lia/arch/ia64/Makefile Mon Sep 24 22:20:41 2001 @@ -17,7 +17,9 @@ AFLAGS_KERNEL := -mconstant-gp EXTRA = -CFLAGS := $(CFLAGS) -pipe $(EXTRA) -ffixed-r13 -mfixed-range=f10-f15,f32-f127 -falign-functions=32 +CFLAGS := $(CFLAGS) -pipe $(EXTRA) -ffixed-r13 -mfixed-range=f10-f15,f32-f127 \ + -falign-functions=32 --param max-inline-insns=400 +# -ffunction-sections CFLAGS_KERNEL := -mconstant-gp GCC_VERSION=$(shell $(CROSS_COMPILE)$(HOSTCC) -v 2>&1 | fgrep 'gcc version' | cut -f3 -d' ' | cut -f1 -d'.') @@ -32,7 +34,7 @@ ifdef CONFIG_IA64_GENERIC CORE_FILES := arch/$(ARCH)/hp/hp.a \ - arch/$(ARCH)/sn/sn.a \ + arch/$(ARCH)/sn/sn.o \ arch/$(ARCH)/dig/dig.a \ arch/$(ARCH)/sn/io/sgiio.o \ $(CORE_FILES) @@ -52,15 +54,14 @@ $(CORE_FILES) endif -ifdef CONFIG_IA64_SGI_SN1 +ifdef CONFIG_IA64_SGI_SN CFLAGS += -DBRINGUP - SUBDIRS := arch/$(ARCH)/sn/sn1 \ - arch/$(ARCH)/sn \ + SUBDIRS := arch/$(ARCH)/sn/kernel \ arch/$(ARCH)/sn/io \ arch/$(ARCH)/sn/fprom \ $(SUBDIRS) - CORE_FILES := arch/$(ARCH)/sn/sn.a \ - arch/$(ARCH)/sn/io/sgiio.o\ + CORE_FILES := arch/$(ARCH)/sn/kernel/sn.o \ + arch/$(ARCH)/sn/io/sgiio.o \ $(CORE_FILES) endif @@ -105,7 +106,7 @@ compressed: vmlinux $(OBJCOPY) --strip-all vmlinux vmlinux-tmp - gzip -9 vmlinux-tmp + gzip vmlinux-tmp mv vmlinux-tmp.gz vmlinux.gz rawboot: diff -urN linux-2.4.10/arch/ia64/config.in linux-2.4.10-lia/arch/ia64/config.in --- linux-2.4.10/arch/ia64/config.in Tue Jul 31 10:30:08 2001 +++ linux-2.4.10-lia/arch/ia64/config.in Mon Sep 24 21:43:20 2001 @@ -28,6 +28,7 @@ if [ "$CONFIG_IA64_HP_SIM" = "n" ]; then define_bool CONFIG_ACPI y + define_bool CONFIG_ACPI_EFI y define_bool CONFIG_ACPI_INTERPRETER y define_bool CONFIG_ACPI_KERNEL_CONFIG y fi @@ -40,7 +41,8 @@ "generic CONFIG_IA64_GENERIC \ DIG-compliant CONFIG_IA64_DIG \ HP-simulator CONFIG_IA64_HP_SIM \ - SGI-SN1 CONFIG_IA64_SGI_SN1" generic + SGI-SN1 CONFIG_IA64_SGI_SN1 \ + SGI-SN2 CONFIG_IA64_SGI_SN2" generic choice 'Kernel page size' \ "4KB CONFIG_IA64_PAGE_SIZE_4KB \ @@ -51,25 +53,6 @@ if [ "$CONFIG_ITANIUM" = "y" ]; then define_bool CONFIG_IA64_BRL_EMU y bool ' Enable Itanium B-step specific code' CONFIG_ITANIUM_BSTEP_SPECIFIC - if [ "$CONFIG_ITANIUM_BSTEP_SPECIFIC" = "y" ]; then - bool ' Enable Itanium B0-step specific code' CONFIG_ITANIUM_B0_SPECIFIC - fi - if [ "$CONFIG_ITANIUM_BSTEP_SPECIFIC" = "y" ]; then - bool ' Enable Itanium B1-step specific code' CONFIG_ITANIUM_B1_SPECIFIC - fi - if [ "$CONFIG_ITANIUM_BSTEP_SPECIFIC" = "y" ]; then - bool ' Enable Itanium B2-step specific code' CONFIG_ITANIUM_B2_SPECIFIC - fi - bool ' Enable Itanium C-step specific code' CONFIG_ITANIUM_CSTEP_SPECIFIC - if [ "$CONFIG_ITANIUM_CSTEP_SPECIFIC" = "y" ]; then - bool ' Enable Itanium C0-step specific code' CONFIG_ITANIUM_C0_SPECIFIC - fi - if [ "$CONFIG_ITANIUM_B0_SPECIFIC" = "y" \ - -o "$CONFIG_ITANIUM_B1_SPECIFIC" = "y" -o "$CONFIG_ITANIUM_B2_SPECIFIC" = "y" ]; then - define_bool CONFIG_ITANIUM_PTCG n - else - define_bool CONFIG_ITANIUM_PTCG y - fi if [ "$CONFIG_IA64_SGI_SN1" = "y" ]; then define_int CONFIG_IA64_L1_CACHE_SHIFT 7 # align cache-sensitive data to 128 bytes else @@ -78,7 +61,6 @@ fi if [ "$CONFIG_MCKINLEY" = "y" ]; then - define_bool CONFIG_ITANIUM_PTCG y define_int CONFIG_IA64_L1_CACHE_SHIFT 7 bool ' Enable McKinley A-step specific code' CONFIG_MCKINLEY_ASTEP_SPECIFIC if [ "$CONFIG_MCKINLEY_ASTEP_SPECIFIC" = "y" ]; then @@ -87,28 +69,32 @@ fi if [ "$CONFIG_IA64_DIG" = "y" ]; then - bool ' Force interrupt redirection' CONFIG_IA64_HAVE_IRQREDIR bool ' Enable IA-64 Machine Check Abort' CONFIG_IA64_MCA define_bool CONFIG_PM y fi -if [ "$CONFIG_IA64_SGI_SN1" = "y" ]; then - bool ' Enable SGI Medusa Simulator Support' CONFIG_IA64_SGI_SN1_SIM - define_bool CONFIG_DEVFS_DEBUG y +if [ "$CONFIG_IA64_SGI_SN1" = "y" ] || [ "$CONFIG_IA64_SGI_SN2" = "y" ]; then + define_bool CONFIG_IA64_SGI_SN y + bool ' Enable extra debugging code' CONFIG_IA64_SGI_SN_DEBUG n + bool ' Enable SGI Medusa Simulator Support' CONFIG_IA64_SGI_SN_SIM + bool ' Enable autotest (llsc). Option to run cache test instead of booting' \ + CONFIG_IA64_SGI_AUTOTEST n define_bool CONFIG_DEVFS_FS y - define_bool CONFIG_IA64_BRL_EMU y + if [ "$CONFIG_DEVFS_FS" = "y" ]; then + bool ' Enable DEVFS Debug Code' CONFIG_DEVFS_DEBUG n + fi + bool ' Enable protocol mode for the L1 console' CONFIG_SERIAL_SGI_L1_PROTOCOL y + define_bool CONFIG_DISCONTIGMEM y define_bool CONFIG_IA64_MCA y - define_bool CONFIG_ITANIUM y - define_bool CONFIG_SGI_IOC3_ETH y + define_bool CONFIG_NUMA y define_bool CONFIG_PERCPU_IRQ y - define_int CONFIG_CACHE_LINE_SHIFT 7 - bool ' Enable DISCONTIGMEM support' CONFIG_DISCONTIGMEM - bool ' Enable NUMA support' CONFIG_NUMA + tristate ' PCIBA support' CONFIG_PCIBA fi define_bool CONFIG_KCORE_ELF y # On IA-64, we always want an ELF /proc/kcore. bool 'SMP support' CONFIG_SMP +tristate 'Support running of Linux/x86 binaries' CONFIG_IA32_SUPPORT bool 'Performance monitor support' CONFIG_PERFMON tristate '/proc/pal support' CONFIG_IA64_PALINFO tristate '/proc/efi/vars support' CONFIG_EFI_VARS @@ -270,19 +256,19 @@ mainmenu_option next_comment comment 'Kernel hacking' -#bool 'Debug kmalloc/kfree' CONFIG_DEBUG_MALLOC -if [ "$CONFIG_EXPERIMENTAL" = "y" ]; then - tristate 'Kernel support for IA-32 emulation' CONFIG_IA32_SUPPORT - tristate 'Kernel FP software completion' CONFIG_MATHEMU -else - define_bool CONFIG_MATHEMU y +bool 'Kernel debugging' CONFIG_DEBUG_KERNEL +if [ "$CONFIG_DEBUG_KERNEL" != "n" ]; then + bool ' Print possible IA64 hazards to console' CONFIG_IA64_PRINT_HAZARDS + bool ' Disable VHPT' CONFIG_DISABLE_VHPT + bool ' Magic SysRq key' CONFIG_MAGIC_SYSRQ + +# early printk is currently broken for SMP: the secondary processors get stuck... +# bool ' Early printk support (requires VGA!)' CONFIG_IA64_EARLY_PRINTK + + bool ' Debug memory allocations' CONFIG_DEBUG_SLAB + bool ' Spinlock debugging' CONFIG_DEBUG_SPINLOCK + bool ' Turn on compare-and-exchange bug checking (slow!)' CONFIG_IA64_DEBUG_CMPXCHG + bool ' Turn on irq debug checks (slow!)' CONFIG_IA64_DEBUG_IRQ fi - -bool 'Magic SysRq key' CONFIG_MAGIC_SYSRQ -bool 'Early printk support (requires VGA!)' CONFIG_IA64_EARLY_PRINTK -bool 'Turn on compare-and-exchange bug checking (slow!)' CONFIG_IA64_DEBUG_CMPXCHG -bool 'Turn on irq debug checks (slow!)' CONFIG_IA64_DEBUG_IRQ -bool 'Print possible IA64 hazards to console' CONFIG_IA64_PRINT_HAZARDS -bool 'Disable VHPT' CONFIG_DISABLE_VHPT endmenu diff -urN linux-2.4.10/arch/ia64/defconfig linux-2.4.10-lia/arch/ia64/defconfig --- linux-2.4.10/arch/ia64/defconfig Thu Jun 22 07:09:44 2000 +++ linux-2.4.10-lia/arch/ia64/defconfig Mon Sep 24 22:23:50 2001 @@ -3,53 +3,131 @@ # # +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODVERSIONS=y +# CONFIG_KMOD is not set + +# # General setup # CONFIG_IA64=y # CONFIG_ISA is not set +# CONFIG_EISA is not set +# CONFIG_MCA is not set # CONFIG_SBUS is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set +CONFIG_ACPI=y +CONFIG_ACPI_EFI=y +CONFIG_ACPI_INTERPRETER=y +CONFIG_ACPI_KERNEL_CONFIG=y +CONFIG_ITANIUM=y +# CONFIG_MCKINLEY is not set # CONFIG_IA64_GENERIC is not set -CONFIG_IA64_HP_SIM=y -# CONFIG_IA64_SGI_SN1_SIM is not set -# CONFIG_IA64_DIG is not set +CONFIG_IA64_DIG=y +# CONFIG_IA64_HP_SIM is not set +# CONFIG_IA64_SGI_SN1 is not set +# CONFIG_IA64_SGI_SN2 is not set # CONFIG_IA64_PAGE_SIZE_4KB is not set # CONFIG_IA64_PAGE_SIZE_8KB is not set CONFIG_IA64_PAGE_SIZE_16KB=y # CONFIG_IA64_PAGE_SIZE_64KB is not set +CONFIG_IA64_BRL_EMU=y +CONFIG_ITANIUM_BSTEP_SPECIFIC=y +CONFIG_IA64_L1_CACHE_SHIFT=6 +CONFIG_IA64_MCA=y +CONFIG_PM=y CONFIG_KCORE_ELF=y -# CONFIG_SMP is not set -# CONFIG_PERFMON is not set -# CONFIG_NET is not set -# CONFIG_SYSVIPC is not set +CONFIG_SMP=y +CONFIG_IA32_SUPPORT=y +CONFIG_PERFMON=y +CONFIG_IA64_PALINFO=y +CONFIG_EFI_VARS=y +CONFIG_NET=y +CONFIG_SYSVIPC=y # CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_SYSCTL is not set -# CONFIG_BINFMT_ELF is not set +CONFIG_SYSCTL=y +CONFIG_BINFMT_ELF=y # CONFIG_BINFMT_MISC is not set +# CONFIG_ACPI_DEBUG is not set +# CONFIG_ACPI_BUSMGR is not set +# CONFIG_ACPI_SYS is not set +# CONFIG_ACPI_CPU is not set +# CONFIG_ACPI_BUTTON is not set +# CONFIG_ACPI_AC is not set +# CONFIG_ACPI_EC is not set +# CONFIG_ACPI_CMBATT is not set +# CONFIG_ACPI_THERMAL is not set CONFIG_PCI=y CONFIG_PCI_NAMES=y # CONFIG_HOTPLUG is not set # CONFIG_PCMCIA is not set # -# Code maturity level options +# Parallel port support # -CONFIG_EXPERIMENTAL=y +# CONFIG_PARPORT is not set # -# Loadable module support +# Networking options # -# CONFIG_MODULES is not set +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +# CONFIG_NETLINK is not set +# CONFIG_NETFILTER is not set +CONFIG_FILTER=y +CONFIG_UNIX=y +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_INET_ECN is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_IPV6 is not set +# CONFIG_KHTTPD is not set +# CONFIG_ATM is not set + +# +# +# +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_DECNET is not set +# CONFIG_BRIDGE is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_LLC is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_FASTROUTE is not set +# CONFIG_NET_HW_FLOWCONTROL is not set # -# Parallel port support +# QoS and/or fair queueing # -# CONFIG_PARPORT is not set +# CONFIG_NET_SCHED is not set + +# +# Memory Technology Devices (MTD) +# +# CONFIG_MTD is not set # # Plug and Play configuration # # CONFIG_PNP is not set # CONFIG_ISAPNP is not set +# CONFIG_PNPBIOS is not set # # Block devices @@ -58,14 +136,12 @@ # CONFIG_BLK_DEV_XD is not set # CONFIG_PARIDE is not set # CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set - -# -# Additional Block Devices -# -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_MD is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_RAM is not set +# CONFIG_BLK_DEV_INITRD is not set # # I2O device support @@ -73,10 +149,23 @@ # CONFIG_I2O is not set # CONFIG_I2O_PCI is not set # CONFIG_I2O_BLOCK is not set +# CONFIG_I2O_LAN is not set # CONFIG_I2O_SCSI is not set # CONFIG_I2O_PROC is not set # +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set +# CONFIG_BLK_DEV_MD is not set +# CONFIG_MD_LINEAR is not set +# CONFIG_MD_RAID0 is not set +# CONFIG_MD_RAID1 is not set +# CONFIG_MD_RAID5 is not set +# CONFIG_MD_MULTIPATH is not set +# CONFIG_BLK_DEV_LVM is not set + +# # ATA/IDE/MFM/RLL support # CONFIG_IDE=y @@ -92,12 +181,21 @@ # CONFIG_BLK_DEV_HD_IDE is not set # CONFIG_BLK_DEV_HD is not set CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set +CONFIG_IDEDISK_MULTI_MODE=y +# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set +# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set +# CONFIG_BLK_DEV_IDEDISK_IBM is not set +# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set +# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set +# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set +# CONFIG_BLK_DEV_IDEDISK_WD is not set +# CONFIG_BLK_DEV_COMMERIAL is not set +# CONFIG_BLK_DEV_TIVO is not set # CONFIG_BLK_DEV_IDECS is not set CONFIG_BLK_DEV_IDECD=y # CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set -# CONFIG_BLK_DEV_IDESCSI is not set +CONFIG_BLK_DEV_IDEFLOPPY=y +CONFIG_BLK_DEV_IDESCSI=y # # IDE chipset support/bugfixes @@ -109,45 +207,209 @@ CONFIG_BLK_DEV_IDEPCI=y CONFIG_IDEPCI_SHARE_IRQ=y CONFIG_BLK_DEV_IDEDMA_PCI=y +CONFIG_BLK_DEV_ADMA=y # CONFIG_BLK_DEV_OFFBOARD is not set -CONFIG_IDEDMA_PCI_AUTO=y +# CONFIG_IDEDMA_PCI_AUTO is not set CONFIG_BLK_DEV_IDEDMA=y -CONFIG_IDEDMA_PCI_EXPERIMENTAL=y # CONFIG_IDEDMA_PCI_WIP is not set # CONFIG_IDEDMA_NEW_DRIVE_LISTINGS is not set -# CONFIG_BLK_DEV_AEC6210 is not set -# CONFIG_AEC6210_TUNING is not set +# CONFIG_BLK_DEV_AEC62XX is not set +# CONFIG_AEC62XX_TUNING is not set # CONFIG_BLK_DEV_ALI15X3 is not set # CONFIG_WDC_ALI15X3 is not set -# CONFIG_BLK_DEV_AMD7409 is not set -# CONFIG_AMD7409_OVERRIDE is not set +# CONFIG_BLK_DEV_AMD74XX is not set +# CONFIG_AMD74XX_OVERRIDE is not set # CONFIG_BLK_DEV_CMD64X is not set -# CONFIG_CMD64X_RAID is not set # CONFIG_BLK_DEV_CY82C693 is not set # CONFIG_BLK_DEV_CS5530 is not set # CONFIG_BLK_DEV_HPT34X is not set # CONFIG_HPT34X_AUTODMA is not set # CONFIG_BLK_DEV_HPT366 is not set -# CONFIG_HPT366_FIP is not set -# CONFIG_HPT366_MODE3 is not set CONFIG_BLK_DEV_PIIX=y -CONFIG_PIIX_TUNING=y +# CONFIG_PIIX_TUNING is not set # CONFIG_BLK_DEV_NS87415 is not set # CONFIG_BLK_DEV_OPTI621 is not set # CONFIG_BLK_DEV_PDC202XX is not set # CONFIG_PDC202XX_BURST is not set -# CONFIG_PDC202XX_MASTER is not set +# CONFIG_PDC202XX_FORCE is not set +# CONFIG_BLK_DEV_SVWKS is not set # CONFIG_BLK_DEV_SIS5513 is not set +# CONFIG_BLK_DEV_SLC90E66 is not set # CONFIG_BLK_DEV_TRM290 is not set # CONFIG_BLK_DEV_VIA82CXXX is not set # CONFIG_IDE_CHIPSETS is not set -CONFIG_IDEDMA_AUTO=y +# CONFIG_IDEDMA_AUTO is not set +# CONFIG_IDEDMA_IVB is not set +# CONFIG_DMA_NONPCI is not set CONFIG_BLK_DEV_IDE_MODES=y +# CONFIG_BLK_DEV_ATARAID is not set +# CONFIG_BLK_DEV_ATARAID_PDC is not set +# CONFIG_BLK_DEV_ATARAID_HPT is not set # # SCSI support # -# CONFIG_SCSI is not set +CONFIG_SCSI=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +CONFIG_SD_EXTRA_DEVS=40 +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +CONFIG_SCSI_DEBUG_QUEUES=y +# CONFIG_SCSI_MULTI_LUN is not set +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y + +# +# SCSI low-level drivers +# +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_7000FASST is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AHA152X is not set +# CONFIG_SCSI_AHA1542 is not set +# CONFIG_SCSI_AHA1740 is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_DPT_I2O is not set +# CONFIG_SCSI_ADVANSYS is not set +# CONFIG_SCSI_IN2000 is not set +# CONFIG_SCSI_AM53C974 is not set +# CONFIG_SCSI_MEGARAID is not set +# CONFIG_SCSI_BUSLOGIC is not set +# CONFIG_SCSI_CPQFCTS is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_DTC3280 is not set +# CONFIG_SCSI_EATA is not set +# CONFIG_SCSI_EATA_DMA is not set +# CONFIG_SCSI_EATA_PIO is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_GDTH is not set +# CONFIG_SCSI_GENERIC_NCR5380 is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_NCR53C406A is not set +# CONFIG_SCSI_NCR_D700 is not set +# CONFIG_SCSI_NCR53C7xx is not set +# CONFIG_SCSI_NCR53C8XX is not set +# CONFIG_SCSI_SYM53C8XX is not set +# CONFIG_SCSI_PAS16 is not set +# CONFIG_SCSI_PCI2000 is not set +# CONFIG_SCSI_PCI2220I is not set +# CONFIG_SCSI_PSI240I is not set +# CONFIG_SCSI_QLOGIC_FAS is not set +# CONFIG_SCSI_QLOGIC_ISP is not set +# CONFIG_SCSI_QLOGIC_FC is not set +CONFIG_SCSI_QLOGIC_1280=y +# CONFIG_SCSI_QLOGIC_QLA2100 is not set +# CONFIG_SCSI_SIM710 is not set +# CONFIG_SCSI_SYM53C416 is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_T128 is not set +# CONFIG_SCSI_U14_34F is not set +# CONFIG_SCSI_DEBUG is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y + +# +# ARCnet devices +# +# CONFIG_ARCNET is not set +CONFIG_DUMMY=y +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +# CONFIG_SUNLANCE is not set +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNBMAC is not set +# CONFIG_SUNQE is not set +# CONFIG_SUNLANCE is not set +# CONFIG_SUNGEM is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_LANCE is not set +# CONFIG_NET_VENDOR_SMC is not set +# CONFIG_NET_VENDOR_RACAL is not set +# CONFIG_HP100 is not set +# CONFIG_NET_ISA is not set +CONFIG_NET_PCI=y +# CONFIG_PCNET32 is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_APRICOT is not set +# CONFIG_CS89x0 is not set +# CONFIG_TULIP is not set +# CONFIG_DE4X5 is not set +# CONFIG_DGRS is not set +# CONFIG_DM9102 is not set +CONFIG_EEPRO100=y +# CONFIG_LNE390 is not set +# CONFIG_FEALNX is not set +# CONFIG_NATSEMI is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_NE3210 is not set +# CONFIG_ES3210 is not set +# CONFIG_8139TOO is not set +# CONFIG_8139TOO_PIO is not set +# CONFIG_8139TOO_TUNE_TWISTER is not set +# CONFIG_8139TOO_8129 is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_WINBOND_840 is not set +# CONFIG_LAN_SAA9730 is not set +# CONFIG_NET_POCKET is not set + +# +# Ethernet (1000 Mbit) +# +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_MYRI_SBUS is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_SK98LIN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PLIP is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Token Ring devices +# +# CONFIG_TR is not set +# CONFIG_NET_FC is not set +# CONFIG_RCPCI is not set +# CONFIG_SHAPER is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set # # Amateur Radio support @@ -165,13 +427,27 @@ # CONFIG_CD_NO_IDESCSI is not set # +# Input core support +# +CONFIG_INPUT=y +CONFIG_INPUT_KEYBDEV=y +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y + +# # Character devices # -# CONFIG_VT is not set -# CONFIG_SERIAL is not set +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_SERIAL_CONSOLE=y # CONFIG_SERIAL_EXTENDED is not set # CONFIG_SERIAL_NONSTANDARD is not set -# CONFIG_UNIX98_PTYS is not set +CONFIG_UNIX98_PTYS=y +CONFIG_UNIX98_PTY_COUNT=256 # # I2C support @@ -182,97 +458,382 @@ # Mice # # CONFIG_BUSMOUSE is not set -# CONFIG_MOUSE is not set +CONFIG_MOUSE=y +CONFIG_PSMOUSE=y +# CONFIG_82C710_MOUSE is not set +# CONFIG_PC110_PAD is not set + +# +# Joysticks +# +# CONFIG_INPUT_GAMEPORT is not set +# CONFIG_INPUT_NS558 is not set +# CONFIG_INPUT_LIGHTNING is not set +# CONFIG_INPUT_PCIGAME is not set +# CONFIG_INPUT_CS461X is not set +# CONFIG_INPUT_EMU10K1 is not set +CONFIG_INPUT_SERIO=y +CONFIG_INPUT_SERPORT=y # # Joysticks # -# CONFIG_JOYSTICK is not set +# CONFIG_INPUT_ANALOG is not set +# CONFIG_INPUT_A3D is not set +# CONFIG_INPUT_ADI is not set +# CONFIG_INPUT_COBRA is not set +# CONFIG_INPUT_GF2K is not set +# CONFIG_INPUT_GRIP is not set +# CONFIG_INPUT_INTERACT is not set +# CONFIG_INPUT_TMDC is not set +# CONFIG_INPUT_SIDEWINDER is not set +# CONFIG_INPUT_IFORCE_USB is not set +# CONFIG_INPUT_IFORCE_232 is not set +# CONFIG_INPUT_WARRIOR is not set +# CONFIG_INPUT_MAGELLAN is not set +# CONFIG_INPUT_SPACEORB is not set +# CONFIG_INPUT_SPACEBALL is not set +# CONFIG_INPUT_STINGER is not set +# CONFIG_INPUT_DB9 is not set +# CONFIG_INPUT_GAMECON is not set +# CONFIG_INPUT_TURBOGRAFX is not set # CONFIG_QIC02_TAPE is not set # # Watchdog Cards # # CONFIG_WATCHDOG is not set +# CONFIG_INTEL_RNG is not set # CONFIG_NVRAM is not set # CONFIG_RTC is not set CONFIG_EFI_RTC=y - -# -# Video For Linux -# -# CONFIG_VIDEO_DEV is not set # CONFIG_DTLK is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set +# CONFIG_SONYPI is not set # # Ftape, the floppy tape device driver # # CONFIG_FTAPE is not set -# CONFIG_DRM is not set -# CONFIG_DRM_TDFX is not set -# CONFIG_AGP is not set +CONFIG_AGP=y +# CONFIG_AGP_INTEL is not set +CONFIG_AGP_I460=y +# CONFIG_AGP_I810 is not set +# CONFIG_AGP_VIA is not set +# CONFIG_AGP_AMD is not set +# CONFIG_AGP_SIS is not set +# CONFIG_AGP_ALI is not set +# CONFIG_AGP_SWORKS is not set +CONFIG_DRM=y +# CONFIG_DRM_NEW is not set +CONFIG_DRM_OLD=y +CONFIG_DRM40_TDFX=y +# CONFIG_DRM40_GAMMA is not set +# CONFIG_DRM40_R128 is not set +# CONFIG_DRM40_RADEON is not set +# CONFIG_DRM40_I810 is not set +# CONFIG_DRM40_MGA is not set # -# USB support +# Multimedia devices +# +CONFIG_VIDEO_DEV=y + +# +# Video For Linux # -# CONFIG_USB is not set +CONFIG_VIDEO_PROC_FS=y +# CONFIG_I2C_PARPORT is not set + +# +# Video Adapters +# +# CONFIG_VIDEO_PMS is not set +# CONFIG_VIDEO_CPIA is not set +# CONFIG_VIDEO_SAA5249 is not set +# CONFIG_TUNER_3036 is not set +# CONFIG_VIDEO_STRADIS is not set +# CONFIG_VIDEO_ZORAN is not set +# CONFIG_VIDEO_ZR36120 is not set +# CONFIG_VIDEO_MEYE is not set + +# +# Radio Adapters +# +# CONFIG_RADIO_CADET is not set +# CONFIG_RADIO_RTRACK is not set +# CONFIG_RADIO_RTRACK2 is not set +# CONFIG_RADIO_AZTECH is not set +# CONFIG_RADIO_GEMTEK is not set +# CONFIG_RADIO_GEMTEK_PCI is not set +# CONFIG_RADIO_MAXIRADIO is not set +# CONFIG_RADIO_MAESTRO is not set +# CONFIG_RADIO_MIROPCM20 is not set +# CONFIG_RADIO_MIROPCM20_RDS is not set +# CONFIG_RADIO_SF16FMI is not set +# CONFIG_RADIO_TERRATEC is not set +# CONFIG_RADIO_TRUST is not set +# CONFIG_RADIO_TYPHOON is not set +# CONFIG_RADIO_ZOLTRIX is not set # # File systems # # CONFIG_QUOTA is not set -# CONFIG_AUTOFS_FS is not set +CONFIG_AUTOFS_FS=y # CONFIG_AUTOFS4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_REISERFS_CHECK is not set # CONFIG_ADFS_FS is not set +# CONFIG_ADFS_FS_RW is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set # CONFIG_BFS_FS is not set -# CONFIG_FAT_FS is not set -# CONFIG_MSDOS_FS is not set +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y # CONFIG_UMSDOS_FS is not set -# CONFIG_VFAT_FS is not set +CONFIG_VFAT_FS=y # CONFIG_EFS_FS is not set +# CONFIG_JFFS_FS is not set # CONFIG_CRAMFS is not set -# CONFIG_ISO9660_FS is not set +# CONFIG_TMPFS is not set +# CONFIG_RAMFS is not set +CONFIG_ISO9660_FS=y # CONFIG_JOLIET is not set # CONFIG_MINIX_FS is not set +# CONFIG_VXFS_FS is not set # CONFIG_NTFS_FS is not set +# CONFIG_NTFS_RW is not set # CONFIG_HPFS_FS is not set -# CONFIG_PROC_FS is not set +CONFIG_PROC_FS=y # CONFIG_DEVFS_FS is not set # CONFIG_DEVFS_MOUNT is not set # CONFIG_DEVFS_DEBUG is not set -# CONFIG_DEVPTS_FS is not set +CONFIG_DEVPTS_FS=y # CONFIG_QNX4FS_FS is not set +# CONFIG_QNX4FS_RW is not set # CONFIG_ROMFS_FS is not set -# CONFIG_EXT2_FS is not set +CONFIG_EXT2_FS=y # CONFIG_SYSV_FS is not set # CONFIG_UDF_FS is not set +# CONFIG_UDF_RW is not set # CONFIG_UFS_FS is not set +# CONFIG_UFS_FS_WRITE is not set + +# +# Network File Systems +# +# CONFIG_CODA_FS is not set +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_ROOT_NFS is not set +CONFIG_NFSD=y +CONFIG_NFSD_V3=y +CONFIG_SUNRPC=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +# CONFIG_SMB_FS is not set +# CONFIG_NCP_FS is not set +# CONFIG_NCPFS_PACKET_SIGNING is not set +# CONFIG_NCPFS_IOCTL_LOCKING is not set +# CONFIG_NCPFS_STRONG is not set +# CONFIG_NCPFS_NFS_NS is not set +# CONFIG_NCPFS_OS2_NS is not set +# CONFIG_NCPFS_SMALLDOS is not set +# CONFIG_NCPFS_NLS is not set +# CONFIG_NCPFS_EXTRAS is not set # # Partition Types # -# CONFIG_PARTITION_ADVANCED is not set +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set CONFIG_MSDOS_PARTITION=y -# CONFIG_NLS is not set -# CONFIG_NLS is not set +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +CONFIG_EFI_PARTITION=y +# CONFIG_DEVFS_GUID is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_SMB_NLS is not set +CONFIG_NLS=y + +# +# Native Language Support +# +CONFIG_NLS_DEFAULT="iso8859-1" +# CONFIG_NLS_CODEPAGE_437 is not set +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Console drivers +# +CONFIG_VGA_CONSOLE=y + +# +# Frame-buffer support +# +# CONFIG_FB is not set # # Sound # -# CONFIG_SOUND is not set +CONFIG_SOUND=y +# CONFIG_SOUND_BT878 is not set +# CONFIG_SOUND_CMPCI is not set +# CONFIG_SOUND_EMU10K1 is not set +# CONFIG_MIDI_EMU10K1 is not set +# CONFIG_SOUND_FUSION is not set +CONFIG_SOUND_CS4281=y +# CONFIG_SOUND_ES1370 is not set +# CONFIG_SOUND_ES1371 is not set +# CONFIG_SOUND_ESSSOLO1 is not set +# CONFIG_SOUND_MAESTRO is not set +# CONFIG_SOUND_MAESTRO3 is not set +# CONFIG_SOUND_ICH is not set +# CONFIG_SOUND_RME96XX is not set +# CONFIG_SOUND_SONICVIBES is not set +# CONFIG_SOUND_TRIDENT is not set +# CONFIG_SOUND_MSNDCLAS is not set +# CONFIG_SOUND_MSNDPIN is not set +# CONFIG_SOUND_VIA82CXXX is not set +# CONFIG_MIDI_VIA82CXXX is not set +# CONFIG_SOUND_OSS is not set +# CONFIG_SOUND_TVMIXER is not set + +# +# USB support +# +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +# CONFIG_USB_BANDWIDTH is not set + +# +# USB Controllers +# +CONFIG_USB_UHCI_ALT=y +CONFIG_USB_OHCI=y + +# +# USB Device Class drivers +# +# CONFIG_USB_AUDIO is not set +# CONFIG_USB_BLUETOOTH is not set +# CONFIG_USB_STORAGE is not set +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set + +# +# USB Human Interface Devices (HID) +# +# CONFIG_USB_HID is not set +CONFIG_USB_KBD=y +CONFIG_USB_MOUSE=y +# CONFIG_USB_WACOM is not set + +# +# USB Imaging devices +# +# CONFIG_USB_DC2XX is not set +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_SCANNER is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB Multimedia devices +# +CONFIG_USB_IBMCAM=y +# CONFIG_USB_OV511 is not set +# CONFIG_USB_PWC is not set +# CONFIG_USB_SE401 is not set +# CONFIG_USB_DSBR is not set +# CONFIG_USB_DABUSB is not set + +# +# USB Network adaptors +# +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_CATC is not set +# CONFIG_USB_CDCETHER is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_USBNET is not set + +# +# USB port drivers +# +# CONFIG_USB_USS720 is not set + +# +# USB Serial Converter support +# +# CONFIG_USB_SERIAL is not set + +# +# USB misc drivers +# +# CONFIG_USB_RIO500 is not set + +# +# Bluetooth support +# +# CONFIG_BLUEZ is not set # # Kernel hacking # -# CONFIG_IA32_SUPPORT is not set -# CONFIG_MATHEMU is not set -# CONFIG_MAGIC_SYSRQ is not set -# CONFIG_IA64_EARLY_PRINTK is not set +CONFIG_DEBUG_KERNEL=y +CONFIG_IA64_PRINT_HAZARDS=y +# CONFIG_DISABLE_VHPT is not set +CONFIG_MAGIC_SYSRQ=y +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_SPINLOCK is not set # CONFIG_IA64_DEBUG_CMPXCHG is not set # CONFIG_IA64_DEBUG_IRQ is not set -# CONFIG_IA64_PRINT_HAZARDS is not set -# CONFIG_KDB is not set diff -urN linux-2.4.10/arch/ia64/ia32/binfmt_elf32.c linux-2.4.10-lia/arch/ia64/ia32/binfmt_elf32.c --- linux-2.4.10/arch/ia64/ia32/binfmt_elf32.c Tue Jul 31 10:30:08 2001 +++ linux-2.4.10-lia/arch/ia64/ia32/binfmt_elf32.c Mon Sep 24 21:43:45 2001 @@ -3,10 +3,11 @@ * * Copyright (C) 1999 Arun Sharma * Copyright (C) 2001 Hewlett-Packard Co - * Copyright (C) 2001 David Mosberger-Tang + * David Mosberger-Tang * * 06/16/00 A. Mallick initialize csd/ssd/tssd/cflg for ia32_load_state * 04/13/01 D. Mosberger dropped saving tssd in ar.k1---it's not needed + * 09/14/01 D. Mosberger fixed memory management for gdt/tss page */ #include @@ -41,51 +42,32 @@ extern void ia64_elf32_init (struct pt_regs *regs); extern void put_dirty_page (struct task_struct * tsk, struct page *page, unsigned long address); +static void elf32_set_personality (void); + #define ELF_PLAT_INIT(_r) ia64_elf32_init(_r) #define setup_arg_pages(bprm) ia32_setup_arg_pages(bprm) -#define elf_map elf_map32 +#define elf_map elf32_map +#define SET_PERSONALITY(ex, ibcs2) elf32_set_personality() /* Ugly but avoids duplication */ #include "../../../fs/binfmt_elf.c" -/* Global descriptor table */ -unsigned long *ia32_gdt_table, *ia32_tss; +extern struct page *ia32_shared_page[]; +extern unsigned long *ia32_gdt; struct page * -put_shared_page (struct task_struct * tsk, struct page *page, unsigned long address) +ia32_install_shared_page (struct vm_area_struct *vma, unsigned long address, int no_share) { - pgd_t * pgd; - pmd_t * pmd; - pte_t * pte; - - if (page_count(page) != 1) - printk("mem_map disagrees with %p at %08lx\n", (void *) page, address); + struct page *pg = ia32_shared_page[(address - vma->vm_start)/PAGE_SIZE]; - pgd = pgd_offset(tsk->mm, address); - - spin_lock(&tsk->mm->page_table_lock); - { - pmd = pmd_alloc(tsk->mm, pgd, address); - if (!pmd) - goto out; - pte = pte_alloc(tsk->mm, pmd, address); - if (!pte) - goto out; - if (!pte_none(*pte)) - goto out; - flush_page_to_ram(page); - set_pte(pte, pte_mkwrite(mk_pte(page, PAGE_SHARED))); - } - spin_unlock(&tsk->mm->page_table_lock); - /* no need for flush_tlb */ - return page; - - out: - spin_unlock(&tsk->mm->page_table_lock); - __free_page(page); - return 0; + get_page(pg); + return pg; } +static struct vm_operations_struct ia32_shared_page_vm_ops = { + nopage: ia32_install_shared_page +}; + void ia64_elf32_init (struct pt_regs *regs) { @@ -97,9 +79,23 @@ * it with privilege level 3 because the IVE uses non-privileged accesses to these * tables. IA-32 segmentation is used to protect against IA-32 accesses to them. */ - put_shared_page(current, virt_to_page(ia32_gdt_table), IA32_GDT_OFFSET); - if (PAGE_SHIFT <= IA32_PAGE_SHIFT) - put_shared_page(current, virt_to_page(ia32_tss), IA32_TSS_OFFSET); + vma = kmem_cache_alloc(vm_area_cachep, SLAB_KERNEL); + if (vma) { + vma->vm_mm = current->mm; + vma->vm_start = IA32_GDT_OFFSET; + vma->vm_end = vma->vm_start + max(PAGE_SIZE, 2*IA32_PAGE_SIZE); + vma->vm_page_prot = PAGE_SHARED; + vma->vm_flags = VM_READ|VM_MAYREAD; + vma->vm_ops = &ia32_shared_page_vm_ops; + vma->vm_pgoff = 0; + vma->vm_file = NULL; + vma->vm_private_data = NULL; + down_write(¤t->mm->mmap_sem); + { + insert_vm_struct(current->mm, vma); + } + up_write(¤t->mm->mmap_sem); + } /* * Install LDT as anonymous memory. This gives us all-zero segment descriptors @@ -116,25 +112,25 @@ vma->vm_pgoff = 0; vma->vm_file = NULL; vma->vm_private_data = NULL; - insert_vm_struct(current->mm, vma); + down_write(¤t->mm->mmap_sem); + { + insert_vm_struct(current->mm, vma); + } + up_write(¤t->mm->mmap_sem); } nr = smp_processor_id(); - current->thread.map_base = IA32_PAGE_OFFSET/3; - current->thread.task_size = IA32_PAGE_OFFSET; /* use what Linux/x86 uses... */ - set_fs(USER_DS); /* set addr limit for new TASK_SIZE */ - /* Setup the segment selectors */ regs->r16 = (__USER_DS << 16) | __USER_DS; /* ES == DS, GS, FS are zero */ regs->r17 = (__USER_DS << 16) | __USER_CS; /* SS, CS; ia32_load_state() sets TSS and LDT */ /* Setup the segment descriptors */ - regs->r24 = IA32_SEG_UNSCRAMBLE(ia32_gdt_table[__USER_DS >> 3]); /* ESD */ - regs->r27 = IA32_SEG_UNSCRAMBLE(ia32_gdt_table[__USER_DS >> 3]); /* DSD */ + regs->r24 = IA32_SEG_UNSCRAMBLE(ia32_gdt[__USER_DS >> 3]); /* ESD */ + regs->r27 = IA32_SEG_UNSCRAMBLE(ia32_gdt[__USER_DS >> 3]); /* DSD */ regs->r28 = 0; /* FSD (null) */ regs->r29 = 0; /* GSD (null) */ - regs->r30 = IA32_SEG_UNSCRAMBLE(ia32_gdt_table[_LDT(nr)]); /* LDTD */ + regs->r30 = IA32_SEG_UNSCRAMBLE(ia32_gdt[_LDT(nr)]); /* LDTD */ /* * Setup GDTD. Note: GDTD is the descrambled version of the pseudo-descriptor @@ -164,9 +160,9 @@ current->thread.fcr = IA32_FCR_DEFAULT; current->thread.fir = 0; current->thread.fdr = 0; - current->thread.csd = IA32_SEG_UNSCRAMBLE(ia32_gdt_table[__USER_CS >> 3]); - current->thread.ssd = IA32_SEG_UNSCRAMBLE(ia32_gdt_table[__USER_DS >> 3]); - current->thread.tssd = IA32_SEG_UNSCRAMBLE(ia32_gdt_table[_TSS(nr)]); + current->thread.csd = IA32_SEG_UNSCRAMBLE(ia32_gdt[__USER_CS >> 3]); + current->thread.ssd = IA32_SEG_UNSCRAMBLE(ia32_gdt[__USER_DS >> 3]); + current->thread.tssd = IA32_SEG_UNSCRAMBLE(ia32_gdt[_TSS(nr)]); ia32_load_state(current); } @@ -189,6 +185,7 @@ if (!mpnt) return -ENOMEM; + down_write(¤t->mm->mmap_sem); { mpnt->vm_mm = current->mm; mpnt->vm_start = PAGE_MASK & (unsigned long) bprm->p; @@ -204,54 +201,32 @@ } for (i = 0 ; i < MAX_ARG_PAGES ; i++) { - if (bprm->page[i]) { - put_dirty_page(current,bprm->page[i],stack_base); + struct page *page = bprm->page[i]; + if (page) { + bprm->page[i] = NULL; + put_dirty_page(current, page, stack_base); } stack_base += PAGE_SIZE; } + up_write(¤t->mm->mmap_sem); return 0; } -static unsigned long -ia32_mm_addr (unsigned long addr) +static void +elf32_set_personality (void) { - struct vm_area_struct *vma; - - if ((vma = find_vma(current->mm, addr)) == NULL) - return ELF_PAGESTART(addr); - if (vma->vm_start > addr) - return ELF_PAGESTART(addr); - return ELF_PAGEALIGN(addr); + set_personality(PER_LINUX32); + current->thread.map_base = IA32_PAGE_OFFSET/3; + current->thread.task_size = IA32_PAGE_OFFSET; /* use what Linux/x86 uses... */ + set_fs(USER_DS); /* set addr limit for new TASK_SIZE */ } -/* - * Normally we would do an `mmap' to map in the process's text section. - * This doesn't work with IA32 processes as the ELF file might specify - * a non page size aligned address. Instead we will just allocate - * memory and read the data in from the file. Slightly less efficient - * but it works. - */ -extern long ia32_do_mmap (struct file *filep, unsigned int len, unsigned int prot, - unsigned int flags, unsigned int fd, unsigned int offset); - static unsigned long -elf_map32 (struct file *filep, unsigned long addr, struct elf_phdr *eppnt, int prot, int type) +elf32_map (struct file *filep, unsigned long addr, struct elf_phdr *eppnt, int prot, int type) { - unsigned long retval; - - if (eppnt->p_memsz >= (1UL<<32) || addr > (1UL<<32) - eppnt->p_memsz) - return -EINVAL; + unsigned long pgoff = (eppnt->p_vaddr) & ~IA32_PAGE_MASK; - /* - * Make sure the elf interpreter doesn't get loaded at location 0 - * so that NULL pointers correctly cause segfaults. - */ - if (addr == 0) - addr += PAGE_SIZE; - set_brk(ia32_mm_addr(addr), addr + eppnt->p_memsz); - memset((char *) addr + eppnt->p_filesz, 0, eppnt->p_memsz - eppnt->p_filesz); - kernel_read(filep, eppnt->p_offset, (char *) addr, eppnt->p_filesz); - retval = (unsigned long) addr; - return retval; + return ia32_do_mmap(filep, (addr & IA32_PAGE_MASK), eppnt->p_filesz + pgoff, prot, type, + eppnt->p_offset - pgoff); } diff -urN linux-2.4.10/arch/ia64/ia32/ia32_entry.S linux-2.4.10-lia/arch/ia64/ia32/ia32_entry.S --- linux-2.4.10/arch/ia64/ia32/ia32_entry.S Tue Jul 31 10:30:08 2001 +++ linux-2.4.10-lia/arch/ia64/ia32/ia32_entry.S Mon Sep 24 21:44:23 2001 @@ -2,7 +2,7 @@ #include #include -#include "../kernel/entry.h" +#include "../kernel/minstate.h" /* * execve() is special because in case of success, we need to @@ -14,13 +14,13 @@ alloc loc1=ar.pfs,3,2,4,0 mov loc0=rp .body - mov out0=in0 // filename + zxt4 out0=in0 // filename ;; // stop bit between alloc and call - mov out1=in1 // argv - mov out2=in2 // envp + zxt4 out1=in1 // argv + zxt4 out2=in2 // envp add out3=16,sp // regs br.call.sptk.few rp=sys32_execve -1: cmp4.ge p6,p0=r8,r0 +1: cmp.ge p6,p0=r8,r0 mov ar.pfs=loc1 // restore ar.pfs ;; (p6) mov ar.pfs=r0 // clear ar.pfs in case of success @@ -29,6 +29,25 @@ br.ret.sptk.few rp END(ia32_execve) +ENTRY(ia32_clone) + .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(2) + alloc r16=ar.pfs,2,2,4,0 + DO_SAVE_SWITCH_STACK + mov loc0=rp + mov loc1=r16 // save ar.pfs across do_fork + .body + zxt4 out1=in1 // newsp + mov out3=0 // stacksize + adds out2=IA64_SWITCH_STACK_SIZE+16,sp // out2 = ®s + zxt4 out0=in0 // out0 = clone_flags + br.call.sptk.many rp=do_fork +.ret0: .restore sp + adds sp=IA64_SWITCH_STACK_SIZE,sp // pop the switch stack + mov ar.pfs=loc1 + mov rp=loc0 + br.ret.sptk.many rp +END(ia32_clone) + // // Get possibly unaligned sigmask argument into an aligned // kernel buffer @@ -38,7 +57,8 @@ // r32 is still the first argument which is the signal mask. // We copy this 4-byte aligned value to an 8-byte aligned buffer // in the task structure and then jump to the IA64 code. - + zxt4 r32=r32 + ;; EX(.Lfail, ld4 r2=[r32],4) // load low part of sigmask ;; EX(.Lfail, ld4 r3=[r32]) // load high part of sigmask @@ -54,6 +74,24 @@ .Lfail: br.ret.sptk.many rp // failed to read sigmask END(ia32_rt_sigsuspend) +GLOBAL_ENTRY(ia32_ret_from_clone) + PT_REGS_UNWIND_INFO(0) + /* + * We need to call schedule_tail() to complete the scheduling process. + * Called by ia64_switch_to after do_fork()->copy_thread(). r8 contains the + * address of the previously executing task. + */ + br.call.sptk.many rp=ia64_invoke_schedule_tail +.ret1: adds r2=IA64_TASK_PTRACE_OFFSET,r13 + ;; + ld8 r2=[r2] + ;; + mov r8=0 + tbit.nz p6,p0=r2,PT_TRACESYS_BIT +(p6) br.cond.spnt .ia32_strace_check_retval + ;; // prevent RAW on r8 +END(ia32_ret_from_clone) + // fall thrugh GLOBAL_ENTRY(ia32_ret_from_syscall) PT_REGS_UNWIND_INFO(0) @@ -77,15 +115,20 @@ // GLOBAL_ENTRY(ia32_trace_syscall) PT_REGS_UNWIND_INFO(0) + mov r3=-38 + adds r2=IA64_PT_REGS_R8_OFFSET+16,sp + ;; + st8 [r2]=r3 // initialize return code to -ENOSYS br.call.sptk.few rp=invoke_syscall_trace // give parent a chance to catch syscall args -.ret0: br.call.sptk.few rp=b6 // do the syscall -.ret1: cmp.lt p6,p0=r8,r0 // syscall failed? +.ret2: br.call.sptk.few rp=b6 // do the syscall +.ia32_strace_check_retval: + cmp.lt p6,p0=r8,r0 // syscall failed? adds r2=IA64_PT_REGS_R8_OFFSET+16,sp // r2 = &pt_regs.r8 ;; st8.spill [r2]=r8 // store return value in slot for r8 br.call.sptk.few rp=invoke_syscall_trace // give parent a chance to catch return value -.ret2: alloc r2=ar.pfs,0,0,0,0 // drop the syscall argument frame - br.cond.sptk.many ia64_leave_kernel // rp MUST be != ia64_leave_kernel! +.ret4: alloc r2=ar.pfs,0,0,0,0 // drop the syscall argument frame + br.cond.sptk.many ia64_leave_kernel END(ia32_trace_syscall) GLOBAL_ENTRY(sys32_vfork) @@ -110,7 +153,7 @@ mov out3=0 adds out2=IA64_SWITCH_STACK_SIZE+16,sp // out2 = ®s br.call.sptk.few rp=do_fork -.ret3: mov ar.pfs=loc1 +.ret5: mov ar.pfs=loc1 .restore sp adds sp=IA64_SWITCH_STACK_SIZE,sp // pop the switch stack mov rp=loc0 @@ -137,21 +180,21 @@ data8 sys32_time data8 sys_mknod data8 sys_chmod /* 15 */ - data8 sys_lchown + data8 sys_lchown /* 16-bit version */ data8 sys32_ni_syscall /* old break syscall holder */ data8 sys32_ni_syscall data8 sys32_lseek data8 sys_getpid /* 20 */ data8 sys_mount data8 sys_oldumount - data8 sys_setuid - data8 sys_getuid + data8 sys_setuid /* 16-bit version */ + data8 sys_getuid /* 16-bit version */ data8 sys32_ni_syscall /* sys_stime is not supported on IA64 */ /* 25 */ data8 sys32_ptrace data8 sys32_alarm data8 sys32_ni_syscall - data8 sys_pause - data8 ia32_utime /* 30 */ + data8 sys32_pause + data8 sys32_utime /* 30 */ data8 sys32_ni_syscall /* old stty syscall holder */ data8 sys32_ni_syscall /* old gtty syscall holder */ data8 sys_access @@ -167,15 +210,15 @@ data8 sys32_times data8 sys32_ni_syscall /* old prof syscall holder */ data8 sys_brk /* 45 */ - data8 sys_setgid - data8 sys_getgid + data8 sys_setgid /* 16-bit version */ + data8 sys_getgid /* 16-bit version */ data8 sys32_signal - data8 sys_geteuid - data8 sys_getegid /* 50 */ + data8 sys_geteuid /* 16-bit version */ + data8 sys_getegid /* 16-bit version */ /* 50 */ data8 sys_acct data8 sys_umount /* recycled never used phys( */ data8 sys32_ni_syscall /* old lock syscall holder */ - data8 ia32_ioctl + data8 sys32_ioctl data8 sys32_fcntl /* 55 */ data8 sys32_ni_syscall /* old mpx syscall holder */ data8 sys_setpgid @@ -191,19 +234,19 @@ data8 sys32_sigaction data8 sys32_ni_syscall data8 sys32_ni_syscall - data8 sys_setreuid /* 70 */ - data8 sys_setregid + data8 sys_setreuid /* 16-bit version */ /* 70 */ + data8 sys_setregid /* 16-bit version */ data8 sys32_ni_syscall - data8 sys_sigpending + data8 sys32_sigpending data8 sys_sethostname data8 sys32_setrlimit /* 75 */ - data8 sys32_getrlimit + data8 sys32_old_getrlimit data8 sys32_getrusage data8 sys32_gettimeofday data8 sys32_settimeofday - data8 sys_getgroups /* 80 */ - data8 sys_setgroups - data8 old_select + data8 sys32_getgroups16 /* 80 */ + data8 sys32_setgroups16 + data8 sys32_old_select data8 sys_symlink data8 sys32_ni_syscall data8 sys_readlink /* 85 */ @@ -212,17 +255,17 @@ data8 sys_reboot data8 sys32_readdir data8 sys32_mmap /* 90 */ - data8 sys_munmap + data8 sys32_munmap data8 sys_truncate data8 sys_ftruncate data8 sys_fchmod - data8 sys_fchown /* 95 */ + data8 sys_fchown /* 16-bit version */ /* 95 */ data8 sys_getpriority data8 sys_setpriority data8 sys32_ni_syscall /* old profil syscall holder */ data8 sys32_statfs data8 sys32_fstatfs /* 100 */ - data8 sys_ioperm + data8 sys32_ioperm data8 sys32_socketcall data8 sys_syslog data8 sys32_setitimer @@ -231,36 +274,36 @@ data8 sys32_newlstat data8 sys32_newfstat data8 sys32_ni_syscall - data8 sys_iopl /* 110 */ + data8 sys32_iopl /* 110 */ data8 sys_vhangup data8 sys32_ni_syscall /* used to be sys_idle */ data8 sys32_ni_syscall data8 sys32_wait4 data8 sys_swapoff /* 115 */ - data8 sys_sysinfo + data8 sys32_sysinfo data8 sys32_ipc data8 sys_fsync data8 sys32_sigreturn - data8 sys_clone /* 120 */ + data8 ia32_clone /* 120 */ data8 sys_setdomainname data8 sys32_newuname data8 sys32_modify_ldt - data8 sys_adjtimex + data8 sys32_ni_syscall /* adjtimex */ data8 sys32_mprotect /* 125 */ - data8 sys_sigprocmask - data8 sys_create_module - data8 sys_init_module - data8 sys_delete_module - data8 sys_get_kernel_syms /* 130 */ - data8 sys_quotactl + data8 sys32_sigprocmask + data8 sys32_ni_syscall /* create_module */ + data8 sys32_ni_syscall /* init_module */ + data8 sys32_ni_syscall /* delete_module */ + data8 sys32_ni_syscall /* get_kernel_syms */ /* 130 */ + data8 sys32_quotactl data8 sys_getpgid data8 sys_fchdir - data8 sys_bdflush - data8 sys_sysfs /* 135 */ - data8 sys_personality + data8 sys32_ni_syscall /* sys_bdflush */ + data8 sys_sysfs /* 135 */ + data8 sys32_personality data8 sys32_ni_syscall /* for afs_syscall */ - data8 sys_setfsuid - data8 sys_setfsgid + data8 sys_setfsuid /* 16-bit version */ + data8 sys_setfsgid /* 16-bit version */ data8 sys_llseek /* 140 */ data8 sys32_getdents data8 sys32_select @@ -282,68 +325,68 @@ data8 sys_sched_yield data8 sys_sched_get_priority_max data8 sys_sched_get_priority_min /* 160 */ - data8 sys_sched_rr_get_interval + data8 sys32_sched_rr_get_interval data8 sys32_nanosleep data8 sys_mremap - data8 sys_setresuid - data8 sys32_getresuid /* 165 */ - data8 sys_vm86 - data8 sys_query_module + data8 sys_setresuid /* 16-bit version */ + data8 sys32_getresuid16 /* 16-bit version */ /* 165 */ + data8 sys32_ni_syscall /* vm86 */ + data8 sys32_ni_syscall /* sys_query_module */ data8 sys_poll - data8 sys_nfsservctl + data8 sys32_ni_syscall /* nfsservctl */ data8 sys_setresgid /* 170 */ - data8 sys32_getresgid + data8 sys32_getresgid16 data8 sys_prctl data8 sys32_rt_sigreturn data8 sys32_rt_sigaction data8 sys32_rt_sigprocmask /* 175 */ data8 sys_rt_sigpending - data8 sys_rt_sigtimedwait - data8 sys_rt_sigqueueinfo + data8 sys32_rt_sigtimedwait + data8 sys32_rt_sigqueueinfo data8 ia32_rt_sigsuspend - data8 sys_pread /* 180 */ - data8 sys_pwrite - data8 sys_chown + data8 sys32_pread /* 180 */ + data8 sys32_pwrite + data8 sys_chown /* 16-bit version */ data8 sys_getcwd data8 sys_capget data8 sys_capset /* 185 */ data8 sys32_sigaltstack - data8 sys_sendfile + data8 sys32_sendfile data8 sys32_ni_syscall /* streams1 */ data8 sys32_ni_syscall /* streams2 */ data8 sys32_vfork /* 190 */ - data8 sys_ni_syscall - data8 sys_ni_syscall - data8 sys_ni_syscall - data8 sys_ni_syscall - data8 sys_ni_syscall /* 195 */ - data8 sys_ni_syscall - data8 sys_ni_syscall - data8 sys_ni_syscall - data8 sys_ni_syscall - data8 sys_ni_syscall /* 200 */ - data8 sys_ni_syscall - data8 sys_ni_syscall - data8 sys_ni_syscall - data8 sys_ni_syscall - data8 sys_ni_syscall /* 205 */ - data8 sys_ni_syscall - data8 sys_ni_syscall - data8 sys_ni_syscall - data8 sys_ni_syscall - data8 sys_ni_syscall /* 210 */ - data8 sys_ni_syscall - data8 sys_ni_syscall - data8 sys_ni_syscall - data8 sys_ni_syscall - data8 sys_ni_syscall /* 215 */ - data8 sys_ni_syscall - data8 sys_ni_syscall - data8 sys_ni_syscall - data8 sys_ni_syscall - data8 sys_ni_syscall /* 220 */ - data8 sys_ni_syscall - data8 sys_ni_syscall + data8 sys32_getrlimit + data8 sys32_mmap2 + data8 sys32_truncate64 + data8 sys32_ftruncate64 + data8 sys32_stat64 /* 195 */ + data8 sys32_lstat64 + data8 sys32_fstat64 + data8 sys_lchown + data8 sys_getuid + data8 sys_getgid /* 200 */ + data8 sys_geteuid + data8 sys_getegid + data8 sys_setreuid + data8 sys_setregid + data8 sys_getgroups /* 205 */ + data8 sys_setgroups + data8 sys_fchown + data8 sys_setresuid + data8 sys_getresuid + data8 sys_setresgid /* 210 */ + data8 sys_getresgid + data8 sys_chown + data8 sys_setuid + data8 sys_setgid + data8 sys_setfsuid /* 215 */ + data8 sys_setfsgid + data8 sys_pivot_root + data8 sys_mincore + data8 sys_madvise + data8 sys_getdents64 /* 220 */ + data8 sys32_fcntl64 + data8 sys_ni_syscall /* reserved for TUX */ /* * CAUTION: If any system calls are added beyond this point * then the check in `arch/ia64/kernel/ivt.S' will have diff -urN linux-2.4.10/arch/ia64/ia32/ia32_ioctl.c linux-2.4.10-lia/arch/ia64/ia32/ia32_ioctl.c --- linux-2.4.10/arch/ia64/ia32/ia32_ioctl.c Thu Jan 4 12:50:17 2001 +++ linux-2.4.10-lia/arch/ia64/ia32/ia32_ioctl.c Mon Sep 24 21:44:39 2001 @@ -36,12 +36,13 @@ _ret; \ }) -#define P(i) ((void *)(long)(i)) +#define P(i) ((void *)(unsigned long)(i)) asmlinkage long sys_ioctl(unsigned int fd, unsigned int cmd, unsigned long arg); -asmlinkage long ia32_ioctl(unsigned int fd, unsigned int cmd, unsigned int arg) +asmlinkage long +sys32_ioctl (unsigned int fd, unsigned int cmd, unsigned int arg) { long ret; @@ -81,7 +82,7 @@ if (copy_to_user(P(arg), &ver32, sizeof(ver32))) return -EFAULT; } - return(ret); + return ret; } case IOCTL_NR(DRM_IOCTL_GET_UNIQUE): @@ -137,10 +138,6 @@ case IOCTL_NR(DRM_IOCTL_I810_GETBUF): case IOCTL_NR(DRM_IOCTL_I810_COPY): - /* Rage 128 specific ioctls */ - - case IOCTL_NR(DRM_IOCTL_R128_PACKET): - case IOCTL_NR(VFAT_IOCTL_READDIR_BOTH): case IOCTL_NR(VFAT_IOCTL_READDIR_SHORT): case IOCTL_NR(MTIOCGET): @@ -206,9 +203,9 @@ case IOCTL_NR(I2OHTML): break; default: - return(sys_ioctl(fd, cmd, (unsigned long)arg)); + return sys_ioctl(fd, cmd, (unsigned long)arg); } printk("%x:unimplemented IA32 ioctl system call\n", cmd); - return(-EINVAL); + return -EINVAL; } diff -urN linux-2.4.10/arch/ia64/ia32/ia32_ldt.c linux-2.4.10-lia/arch/ia64/ia32/ia32_ldt.c --- linux-2.4.10/arch/ia64/ia32/ia32_ldt.c Tue Jul 31 10:30:08 2001 +++ linux-2.4.10-lia/arch/ia64/ia32/ia32_ldt.c Mon Sep 24 21:44:52 2001 @@ -16,6 +16,8 @@ #include #include +#define P(p) ((void *) (unsigned long) (p)) + /* * read_ldt() is not really atomic - this is not a problem since synchronization of reads * and writes done to the LDT has to be assured by user-space anyway. Writes are atomic, @@ -101,19 +103,19 @@ } asmlinkage int -sys32_modify_ldt (int func, void *ptr, unsigned int bytecount) +sys32_modify_ldt (int func, unsigned int ptr, unsigned int bytecount) { int ret = -ENOSYS; switch (func) { case 0: - ret = read_ldt(ptr, bytecount); + ret = read_ldt(P(ptr), bytecount); break; case 1: - ret = write_ldt(ptr, bytecount, 1); + ret = write_ldt(P(ptr), bytecount, 1); break; case 0x11: - ret = write_ldt(ptr, bytecount, 0); + ret = write_ldt(P(ptr), bytecount, 0); break; } return ret; diff -urN linux-2.4.10/arch/ia64/ia32/ia32_signal.c linux-2.4.10-lia/arch/ia64/ia32/ia32_signal.c --- linux-2.4.10/arch/ia64/ia32/ia32_signal.c Mon Oct 9 17:54:53 2000 +++ linux-2.4.10-lia/arch/ia64/ia32/ia32_signal.c Mon Sep 24 21:45:00 2001 @@ -1,8 +1,8 @@ /* * IA32 Architecture-specific signal handling support. * - * Copyright (C) 1999 Hewlett-Packard Co - * Copyright (C) 1999 David Mosberger-Tang + * Copyright (C) 1999, 2001 Hewlett-Packard Co + * David Mosberger-Tang * Copyright (C) 1999 Arun Sharma * Copyright (C) 2000 VA Linux Co * Copyright (C) 2000 Don Dugger @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -31,6 +32,8 @@ #define DEBUG_SIG 0 #define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP))) +#define __IA32_NR_sigreturn 119 +#define __IA32_NR_rt_sigreturn 173 struct sigframe_ia32 { @@ -54,12 +57,51 @@ char retcode[8]; }; -static int +int +copy_siginfo_from_user32 (siginfo_t *to, siginfo_t32 *from) +{ + unsigned long tmp; + int err; + + if (!access_ok(VERIFY_READ, from, sizeof(siginfo_t32))) + return -EFAULT; + + err = __get_user(to->si_signo, &from->si_signo); + err |= __get_user(to->si_errno, &from->si_errno); + err |= __get_user(to->si_code, &from->si_code); + + if (from->si_code < 0) + err |= __copy_from_user(&to->_sifields._pad, &from->_sifields._pad, SI_PAD_SIZE); + else { + switch (from->si_code >> 16) { + case __SI_CHLD >> 16: + err |= __get_user(to->si_utime, &from->si_utime); + err |= __get_user(to->si_stime, &from->si_stime); + err |= __get_user(to->si_status, &from->si_status); + default: + err |= __get_user(to->si_pid, &from->si_pid); + err |= __get_user(to->si_uid, &from->si_uid); + break; + case __SI_FAULT >> 16: + err |= __get_user(tmp, &from->si_addr); + to->si_addr = (void *) tmp; + break; + case __SI_POLL >> 16: + err |= __get_user(to->si_band, &from->si_band); + err |= __get_user(to->si_fd, &from->si_fd); + break; + /* case __SI_RT: This is not generated by the kernel as of now. */ + } + } + return err; +} + +int copy_siginfo_to_user32 (siginfo_t32 *to, siginfo_t *from) { int err; - if (!access_ok (VERIFY_WRITE, to, sizeof(siginfo_t32))) + if (!access_ok(VERIFY_WRITE, to, sizeof(siginfo_t32))) return -EFAULT; /* If you change siginfo_t structure, please be sure @@ -100,80 +142,81 @@ static int -setup_sigcontext_ia32(struct sigcontext_ia32 *sc, struct _fpstate_ia32 *fpstate, - struct pt_regs *regs, unsigned long mask) +setup_sigcontext_ia32 (struct sigcontext_ia32 *sc, struct _fpstate_ia32 *fpstate, + struct pt_regs *regs, unsigned long mask) { - int err = 0; - unsigned long flag; + int err = 0; + unsigned long flag; - err |= __put_user((regs->r16 >> 32) & 0xffff , (unsigned int *)&sc->fs); - err |= __put_user((regs->r16 >> 48) & 0xffff , (unsigned int *)&sc->gs); + err |= __put_user((regs->r16 >> 32) & 0xffff , (unsigned int *)&sc->fs); + err |= __put_user((regs->r16 >> 48) & 0xffff , (unsigned int *)&sc->gs); - err |= __put_user((regs->r16 >> 56) & 0xffff, (unsigned int *)&sc->es); - err |= __put_user(regs->r16 & 0xffff, (unsigned int *)&sc->ds); - err |= __put_user(regs->r15, &sc->edi); - err |= __put_user(regs->r14, &sc->esi); - err |= __put_user(regs->r13, &sc->ebp); - err |= __put_user(regs->r12, &sc->esp); - err |= __put_user(regs->r11, &sc->ebx); - err |= __put_user(regs->r10, &sc->edx); - err |= __put_user(regs->r9, &sc->ecx); - err |= __put_user(regs->r8, &sc->eax); + err |= __put_user((regs->r16 >> 56) & 0xffff, (unsigned int *)&sc->es); + err |= __put_user(regs->r16 & 0xffff, (unsigned int *)&sc->ds); + err |= __put_user(regs->r15, &sc->edi); + err |= __put_user(regs->r14, &sc->esi); + err |= __put_user(regs->r13, &sc->ebp); + err |= __put_user(regs->r12, &sc->esp); + err |= __put_user(regs->r11, &sc->ebx); + err |= __put_user(regs->r10, &sc->edx); + err |= __put_user(regs->r9, &sc->ecx); + err |= __put_user(regs->r8, &sc->eax); #if 0 - err |= __put_user(current->tss.trap_no, &sc->trapno); - err |= __put_user(current->tss.error_code, &sc->err); + err |= __put_user(current->tss.trap_no, &sc->trapno); + err |= __put_user(current->tss.error_code, &sc->err); #endif - err |= __put_user(regs->cr_iip, &sc->eip); - err |= __put_user(regs->r17 & 0xffff, (unsigned int *)&sc->cs); - /* - * `eflags' is in an ar register for this context - */ - asm volatile ("mov %0=ar.eflag ;;" : "=r"(flag)); - err |= __put_user((unsigned int)flag, &sc->eflags); - - err |= __put_user(regs->r12, &sc->esp_at_signal); - err |= __put_user((regs->r17 >> 16) & 0xffff, (unsigned int *)&sc->ss); + err |= __put_user(regs->cr_iip, &sc->eip); + err |= __put_user(regs->r17 & 0xffff, (unsigned int *)&sc->cs); + /* + * `eflags' is in an ar register for this context + */ + asm volatile ("mov %0=ar.eflag ;;" : "=r"(flag)); + err |= __put_user((unsigned int)flag, &sc->eflags); + err |= __put_user(regs->r12, &sc->esp_at_signal); + err |= __put_user((regs->r17 >> 16) & 0xffff, (unsigned int *)&sc->ss); #if 0 - tmp = save_i387(fpstate); - if (tmp < 0) - err = 1; - else - err |= __put_user(tmp ? fpstate : NULL, &sc->fpstate); + tmp = save_i387(fpstate); + if (tmp < 0) + err = 1; + else + err |= __put_user(tmp ? fpstate : NULL, &sc->fpstate); - /* non-iBCS2 extensions.. */ + /* non-iBCS2 extensions.. */ #endif - err |= __put_user(mask, &sc->oldmask); + err |= __put_user(mask, &sc->oldmask); #if 0 - err |= __put_user(current->tss.cr2, &sc->cr2); + err |= __put_user(current->tss.cr2, &sc->cr2); #endif - - return err; + return err; } static int -restore_sigcontext_ia32(struct pt_regs *regs, struct sigcontext_ia32 *sc, int *peax) +restore_sigcontext_ia32 (struct pt_regs *regs, struct sigcontext_ia32 *sc, int *peax) { unsigned int err = 0; -#define COPY(ia64x, ia32x) err |= __get_user(regs->ia64x, &sc->ia32x) +#define COPY(ia64x, ia32x) err |= __get_user(regs->ia64x, &sc->ia32x) -#define copyseg_gs(tmp) (regs->r16 |= (unsigned long) tmp << 48) -#define copyseg_fs(tmp) (regs->r16 |= (unsigned long) tmp << 32) -#define copyseg_cs(tmp) (regs->r17 |= tmp) -#define copyseg_ss(tmp) (regs->r17 |= (unsigned long) tmp << 16) -#define copyseg_es(tmp) (regs->r16 |= (unsigned long) tmp << 16) -#define copyseg_ds(tmp) (regs->r16 |= tmp) - -#define COPY_SEG(seg) \ - { unsigned short tmp; \ - err |= __get_user(tmp, &sc->seg); \ - copyseg_##seg(tmp); } - -#define COPY_SEG_STRICT(seg) \ - { unsigned short tmp; \ - err |= __get_user(tmp, &sc->seg); \ - copyseg_##seg(tmp|3); } +#define copyseg_gs(tmp) (regs->r16 |= (unsigned long) tmp << 48) +#define copyseg_fs(tmp) (regs->r16 |= (unsigned long) tmp << 32) +#define copyseg_cs(tmp) (regs->r17 |= tmp) +#define copyseg_ss(tmp) (regs->r17 |= (unsigned long) tmp << 16) +#define copyseg_es(tmp) (regs->r16 |= (unsigned long) tmp << 16) +#define copyseg_ds(tmp) (regs->r16 |= tmp) + +#define COPY_SEG(seg) \ + { \ + unsigned short tmp; \ + err |= __get_user(tmp, &sc->seg); \ + copyseg_##seg(tmp); \ + } +#define COPY_SEG_STRICT(seg) \ + { \ + unsigned short tmp; \ + err |= __get_user(tmp, &sc->seg); \ + copyseg_##seg(tmp|3); \ + } /* To make COPY_SEGs easier, we zero r16, r17 */ regs->r16 = 0; @@ -198,9 +241,8 @@ unsigned long flag; /* - * IA32 `eflags' is not part of `pt_regs', it's - * in an ar register which is part of the thread - * context. Fortunately, we are executing in the + * IA32 `eflags' is not part of `pt_regs', it's in an ar register which + * is part of the thread context. Fortunately, we are executing in the * IA32 process's context. */ err |= __get_user(tmpflags, &sc->eflags); @@ -227,7 +269,7 @@ err |= __get_user(*peax, &sc->eax); return err; -#if 0 +#if 0 badframe: return 1; #endif @@ -238,158 +280,164 @@ * Determine which stack to use.. */ static inline void * -get_sigframe(struct k_sigaction *ka, struct pt_regs * regs, size_t frame_size) +get_sigframe (struct k_sigaction *ka, struct pt_regs * regs, size_t frame_size) { - unsigned long esp; - unsigned int xss; + unsigned long esp; - /* Default to using normal stack */ - esp = regs->r12; - xss = regs->r16 >> 16; - - /* This is the X/Open sanctioned signal stack switching. */ - if (ka->sa.sa_flags & SA_ONSTACK) { - if (! on_sig_stack(esp)) - esp = current->sas_ss_sp + current->sas_ss_size; - } - /* Legacy stack switching not supported */ - - return (void *)((esp - frame_size) & -8ul); + /* Default to using normal stack (truncate off sign-extension of bit 31: */ + esp = (unsigned int) regs->r12; + + /* This is the X/Open sanctioned signal stack switching. */ + if (ka->sa.sa_flags & SA_ONSTACK) { + if (!on_sig_stack(esp)) + esp = current->sas_ss_sp + current->sas_ss_size; + } + /* Legacy stack switching not supported */ + + return (void *)((esp - frame_size) & -8ul); } static int -setup_frame_ia32(int sig, struct k_sigaction *ka, sigset_t *set, - struct pt_regs * regs) -{ - struct sigframe_ia32 *frame; - int err = 0; - - frame = get_sigframe(ka, regs, sizeof(*frame)); - - if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame))) - goto give_sigsegv; - - err |= __put_user((current->exec_domain - && current->exec_domain->signal_invmap - && sig < 32 - ? (int)(current->exec_domain->signal_invmap[sig]) - : sig), - &frame->sig); - - err |= setup_sigcontext_ia32(&frame->sc, &frame->fpstate, regs, set->sig[0]); - - if (_IA32_NSIG_WORDS > 1) { - err |= __copy_to_user(frame->extramask, &set->sig[1], - sizeof(frame->extramask)); - } +setup_frame_ia32 (int sig, struct k_sigaction *ka, sigset_t *set, struct pt_regs * regs) +{ + struct sigframe_ia32 *frame; + int err = 0; - /* Set up to return from userspace. If provided, use a stub - already in userspace. */ - err |= __put_user((long)frame->retcode, &frame->pretcode); - /* This is popl %eax ; movl $,%eax ; int $0x80 */ - err |= __put_user(0xb858, (short *)(frame->retcode+0)); -#define __IA32_NR_sigreturn 119 - err |= __put_user(__IA32_NR_sigreturn & 0xffff, (short *)(frame->retcode+2)); - err |= __put_user(__IA32_NR_sigreturn >> 16, (short *)(frame->retcode+4)); - err |= __put_user(0x80cd, (short *)(frame->retcode+6)); - - if (err) - goto give_sigsegv; - - /* Set up registers for signal handler */ - regs->r12 = (unsigned long) frame; - regs->cr_iip = (unsigned long) ka->sa.sa_handler; - - set_fs(USER_DS); - regs->r16 = (__USER_DS << 16) | (__USER_DS); /* ES == DS, GS, FS are zero */ - regs->r17 = (__USER_DS << 16) | __USER_CS; + frame = get_sigframe(ka, regs, sizeof(*frame)); + + if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame))) + goto give_sigsegv; + + err |= __put_user((current->exec_domain + && current->exec_domain->signal_invmap + && sig < 32 + ? (int)(current->exec_domain->signal_invmap[sig]) + : sig), + &frame->sig); + + err |= setup_sigcontext_ia32(&frame->sc, &frame->fpstate, regs, set->sig[0]); + + if (_IA32_NSIG_WORDS > 1) + err |= __copy_to_user(frame->extramask, (char *) &set->sig + 4, + sizeof(frame->extramask)); + + /* Set up to return from userspace. If provided, use a stub + already in userspace. */ + if (ka->sa.sa_flags & SA_RESTORER) { + unsigned int restorer = IA32_SA_RESTORER(ka); + err |= __put_user(restorer, &frame->pretcode); + } else { + err |= __put_user((long)frame->retcode, &frame->pretcode); + /* This is popl %eax ; movl $,%eax ; int $0x80 */ + err |= __put_user(0xb858, (short *)(frame->retcode+0)); + err |= __put_user(__IA32_NR_sigreturn & 0xffff, (short *)(frame->retcode+2)); + err |= __put_user(__IA32_NR_sigreturn >> 16, (short *)(frame->retcode+4)); + err |= __put_user(0x80cd, (short *)(frame->retcode+6)); + } + + if (err) + goto give_sigsegv; + + /* Set up registers for signal handler */ + regs->r12 = (unsigned long) frame; + regs->cr_iip = IA32_SA_HANDLER(ka); + + set_fs(USER_DS); + regs->r16 = (__USER_DS << 16) | (__USER_DS); /* ES == DS, GS, FS are zero */ + regs->r17 = (__USER_DS << 16) | __USER_CS; #if 0 - regs->eflags &= ~TF_MASK; + regs->eflags &= ~TF_MASK; #endif #if 0 - printk("SIG deliver (%s:%d): sig=%d sp=%p pc=%lx ra=%x\n", + printk("SIG deliver (%s:%d): sig=%d sp=%p pc=%lx ra=%x\n", current->comm, current->pid, sig, (void *) frame, regs->cr_iip, frame->pretcode); #endif - return 1; + return 1; -give_sigsegv: - if (sig == SIGSEGV) - ka->sa.sa_handler = SIG_DFL; - force_sig(SIGSEGV, current); - return 0; + give_sigsegv: + if (sig == SIGSEGV) + ka->sa.sa_handler = SIG_DFL; + force_sig(SIGSEGV, current); + return 0; } static int -setup_rt_frame_ia32(int sig, struct k_sigaction *ka, siginfo_t *info, - sigset_t *set, struct pt_regs * regs) +setup_rt_frame_ia32 (int sig, struct k_sigaction *ka, siginfo_t *info, + sigset_t *set, struct pt_regs * regs) { - struct rt_sigframe_ia32 *frame; - int err = 0; + struct rt_sigframe_ia32 *frame; + int err = 0; - frame = get_sigframe(ka, regs, sizeof(*frame)); + frame = get_sigframe(ka, regs, sizeof(*frame)); - if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame))) - goto give_sigsegv; - - err |= __put_user((current->exec_domain - && current->exec_domain->signal_invmap - && sig < 32 - ? current->exec_domain->signal_invmap[sig] - : sig), - &frame->sig); - err |= __put_user((long)&frame->info, &frame->pinfo); - err |= __put_user((long)&frame->uc, &frame->puc); - err |= copy_siginfo_to_user32(&frame->info, info); - - /* Create the ucontext. */ - err |= __put_user(0, &frame->uc.uc_flags); - err |= __put_user(0, &frame->uc.uc_link); - err |= __put_user(current->sas_ss_sp, &frame->uc.uc_stack.ss_sp); - err |= __put_user(sas_ss_flags(regs->r12), - &frame->uc.uc_stack.ss_flags); - err |= __put_user(current->sas_ss_size, &frame->uc.uc_stack.ss_size); - err |= setup_sigcontext_ia32(&frame->uc.uc_mcontext, &frame->fpstate, - regs, set->sig[0]); - err |= __copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set)); - - err |= __put_user((long)frame->retcode, &frame->pretcode); - /* This is movl $,%eax ; int $0x80 */ - err |= __put_user(0xb8, (char *)(frame->retcode+0)); -#define __IA32_NR_rt_sigreturn 173 - err |= __put_user(__IA32_NR_rt_sigreturn, (int *)(frame->retcode+1)); - err |= __put_user(0x80cd, (short *)(frame->retcode+5)); + if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame))) + goto give_sigsegv; + + err |= __put_user((current->exec_domain + && current->exec_domain->signal_invmap + && sig < 32 + ? current->exec_domain->signal_invmap[sig] + : sig), + &frame->sig); + err |= __put_user((long)&frame->info, &frame->pinfo); + err |= __put_user((long)&frame->uc, &frame->puc); + err |= copy_siginfo_to_user32(&frame->info, info); + + /* Create the ucontext. */ + err |= __put_user(0, &frame->uc.uc_flags); + err |= __put_user(0, &frame->uc.uc_link); + err |= __put_user(current->sas_ss_sp, &frame->uc.uc_stack.ss_sp); + err |= __put_user(sas_ss_flags(regs->r12), &frame->uc.uc_stack.ss_flags); + err |= __put_user(current->sas_ss_size, &frame->uc.uc_stack.ss_size); + err |= setup_sigcontext_ia32(&frame->uc.uc_mcontext, &frame->fpstate, regs, set->sig[0]); + err |= __copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set)); + if (err) + goto give_sigsegv; + + /* Set up to return from userspace. If provided, use a stub + already in userspace. */ + if (ka->sa.sa_flags & SA_RESTORER) { + unsigned int restorer = IA32_SA_RESTORER(ka); + err |= __put_user(restorer, &frame->pretcode); + } else { + err |= __put_user((long)frame->retcode, &frame->pretcode); + /* This is movl $,%eax ; int $0x80 */ + err |= __put_user(0xb8, (char *)(frame->retcode+0)); + err |= __put_user(__IA32_NR_rt_sigreturn, (int *)(frame->retcode+1)); + err |= __put_user(0x80cd, (short *)(frame->retcode+5)); + } - if (err) - goto give_sigsegv; + if (err) + goto give_sigsegv; - /* Set up registers for signal handler */ - regs->r12 = (unsigned long) frame; - regs->cr_iip = (unsigned long) ka->sa.sa_handler; + /* Set up registers for signal handler */ + regs->r12 = (unsigned long) frame; + regs->cr_iip = IA32_SA_HANDLER(ka); - set_fs(USER_DS); + set_fs(USER_DS); - regs->r16 = (__USER_DS << 16) | (__USER_DS); /* ES == DS, GS, FS are zero */ - regs->r17 = (__USER_DS << 16) | __USER_CS; + regs->r16 = (__USER_DS << 16) | (__USER_DS); /* ES == DS, GS, FS are zero */ + regs->r17 = (__USER_DS << 16) | __USER_CS; #if 0 - regs->eflags &= ~TF_MASK; + regs->eflags &= ~TF_MASK; #endif #if 0 - printk("SIG deliver (%s:%d): sp=%p pc=%lx ra=%x\n", + printk("SIG deliver (%s:%d): sp=%p pc=%lx ra=%x\n", current->comm, current->pid, (void *) frame, regs->cr_iip, frame->pretcode); #endif - return 1; + return 1; give_sigsegv: - if (sig == SIGSEGV) - ka->sa.sa_handler = SIG_DFL; - force_sig(SIGSEGV, current); - return 0; + if (sig == SIGSEGV) + ka->sa.sa_handler = SIG_DFL; + force_sig(SIGSEGV, current); + return 0; } int @@ -398,95 +446,79 @@ { /* Set up the stack frame */ if (ka->sa.sa_flags & SA_SIGINFO) - return(setup_rt_frame_ia32(sig, ka, info, set, regs)); + return setup_rt_frame_ia32(sig, ka, info, set, regs); else - return(setup_frame_ia32(sig, ka, set, regs)); + return setup_frame_ia32(sig, ka, set, regs); } -asmlinkage int -sys32_sigreturn( -int arg0, -int arg1, -int arg2, -int arg3, -int arg4, -int arg5, -int arg6, -int arg7, -unsigned long stack) -{ - struct pt_regs *regs = (struct pt_regs *) &stack; - struct sigframe_ia32 *frame = (struct sigframe_ia32 *)(regs->r12- 8); - sigset_t set; - int eax; - - if (verify_area(VERIFY_READ, frame, sizeof(*frame))) - goto badframe; - - if (__get_user(set.sig[0], &frame->sc.oldmask) - || (_IA32_NSIG_WORDS > 1 - && __copy_from_user((((char *) &set.sig) + 4), - &frame->extramask, - sizeof(frame->extramask)))) - goto badframe; - - sigdelsetmask(&set, ~_BLOCKABLE); - spin_lock_irq(¤t->sigmask_lock); - current->blocked = (sigset_t) set; - recalc_sigpending(current); - spin_unlock_irq(¤t->sigmask_lock); - - if (restore_sigcontext_ia32(regs, &frame->sc, &eax)) - goto badframe; - return eax; - -badframe: - force_sig(SIGSEGV, current); - return 0; -} - -asmlinkage int -sys32_rt_sigreturn( -int arg0, -int arg1, -int arg2, -int arg3, -int arg4, -int arg5, -int arg6, -int arg7, -unsigned long stack) -{ - struct pt_regs *regs = (struct pt_regs *) &stack; - struct rt_sigframe_ia32 *frame = (struct rt_sigframe_ia32 *)(regs->r12 - 4); - sigset_t set; - stack_t st; - int eax; - - if (verify_area(VERIFY_READ, frame, sizeof(*frame))) - goto badframe; - if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set))) - goto badframe; - - sigdelsetmask(&set, ~_BLOCKABLE); - spin_lock_irq(¤t->sigmask_lock); - current->blocked = set; - recalc_sigpending(current); - spin_unlock_irq(¤t->sigmask_lock); - - if (restore_sigcontext_ia32(regs, &frame->uc.uc_mcontext, &eax)) - goto badframe; - - if (__copy_from_user(&st, &frame->uc.uc_stack, sizeof(st))) - goto badframe; - /* It is more difficult to avoid calling this function than to - call it and ignore errors. */ - do_sigaltstack(&st, NULL, regs->r12); - - return eax; +asmlinkage long +sys32_sigreturn (int arg0, int arg1, int arg2, int arg3, int arg4, int arg5, int arg6, int arg7, + unsigned long stack) +{ + struct pt_regs *regs = (struct pt_regs *) &stack; + unsigned long esp = (unsigned int) regs->r12; + struct sigframe_ia32 *frame = (struct sigframe_ia32 *)(esp - 8); + sigset_t set; + int eax; + + if (verify_area(VERIFY_READ, frame, sizeof(*frame))) + goto badframe; + + if (__get_user(set.sig[0], &frame->sc.oldmask) + || (_IA32_NSIG_WORDS > 1 && __copy_from_user((char *) &set.sig + 4, &frame->extramask, + sizeof(frame->extramask)))) + goto badframe; + + sigdelsetmask(&set, ~_BLOCKABLE); + spin_lock_irq(¤t->sigmask_lock); + current->blocked = (sigset_t) set; + recalc_sigpending(current); + spin_unlock_irq(¤t->sigmask_lock); + + if (restore_sigcontext_ia32(regs, &frame->sc, &eax)) + goto badframe; + return eax; + + badframe: + force_sig(SIGSEGV, current); + return 0; +} -badframe: - force_sig(SIGSEGV, current); - return 0; -} +asmlinkage long +sys32_rt_sigreturn (int arg0, int arg1, int arg2, int arg3, int arg4, int arg5, int arg6, int arg7, + unsigned long stack) +{ + struct pt_regs *regs = (struct pt_regs *) &stack; + unsigned long esp = (unsigned int) regs->r12; + struct rt_sigframe_ia32 *frame = (struct rt_sigframe_ia32 *)(esp - 4); + sigset_t set; + stack_t st; + int eax; + + if (verify_area(VERIFY_READ, frame, sizeof(*frame))) + goto badframe; + if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set))) + goto badframe; + + sigdelsetmask(&set, ~_BLOCKABLE); + spin_lock_irq(¤t->sigmask_lock); + current->blocked = set; + recalc_sigpending(current); + spin_unlock_irq(¤t->sigmask_lock); + + if (restore_sigcontext_ia32(regs, &frame->uc.uc_mcontext, &eax)) + goto badframe; + + if (__copy_from_user(&st, &frame->uc.uc_stack, sizeof(st))) + goto badframe; + /* It is more difficult to avoid calling this function than to + call it and ignore errors. */ + do_sigaltstack(&st, NULL, esp); + + return eax; + + badframe: + force_sig(SIGSEGV, current); + return 0; +} diff -urN linux-2.4.10/arch/ia64/ia32/ia32_support.c linux-2.4.10-lia/arch/ia64/ia32/ia32_support.c --- linux-2.4.10/arch/ia64/ia32/ia32_support.c Tue Jul 31 10:30:08 2001 +++ linux-2.4.10-lia/arch/ia64/ia32/ia32_support.c Mon Sep 24 21:45:11 2001 @@ -4,15 +4,17 @@ * Copyright (C) 1999 Arun Sharma * Copyright (C) 2000 Asit K. Mallick * Copyright (C) 2001 Hewlett-Packard Co - * Copyright (C) 2001 David Mosberger-Tang + * David Mosberger-Tang * * 06/16/00 A. Mallick added csd/ssd/tssd for ia32 thread context * 02/19/01 D. Mosberger dropped tssd; it's not needed + * 09/14/01 D. Mosberger fixed memory management for gdt/tss page */ #include #include #include +#include #include #include @@ -21,10 +23,12 @@ #include #include -extern unsigned long *ia32_gdt_table, *ia32_tss; - extern void die_if_kernel (char *str, struct pt_regs *regs, long err); +struct exec_domain ia32_exec_domain; +struct page *ia32_shared_page[(2*IA32_PAGE_SIZE + PAGE_SIZE - 1)/PAGE_SIZE]; +unsigned long *ia32_gdt; + void ia32_save_state (struct task_struct *t) { @@ -85,36 +89,34 @@ void ia32_gdt_init (void) { - unsigned long gdt_and_tss_page, ldt_size; + unsigned long *tss; + unsigned long ldt_size; int nr; - /* allocate two IA-32 pages of memory: */ - gdt_and_tss_page = __get_free_pages(GFP_KERNEL, - (IA32_PAGE_SHIFT < PAGE_SHIFT) - ? 0 : (IA32_PAGE_SHIFT + 1) - PAGE_SHIFT); - ia32_gdt_table = (unsigned long *) gdt_and_tss_page; - ia32_tss = (unsigned long *) (gdt_and_tss_page + IA32_PAGE_SIZE); - - /* Zero the gdt and tss */ - memset((void *) gdt_and_tss_page, 0, 2*IA32_PAGE_SIZE); + ia32_shared_page[0] = alloc_page(GFP_KERNEL); + ia32_gdt = page_address(ia32_shared_page[0]); + tss = ia32_gdt + IA32_PAGE_SIZE/sizeof(ia32_gdt[0]); + + if (IA32_PAGE_SIZE == PAGE_SIZE) { + ia32_shared_page[1] = alloc_page(GFP_KERNEL); + tss = page_address(ia32_shared_page[1]); + } /* CS descriptor in IA-32 (scrambled) format */ - ia32_gdt_table[__USER_CS >> 3] = - IA32_SEG_DESCRIPTOR(0, (IA32_PAGE_OFFSET - 1) >> IA32_PAGE_SHIFT, - 0xb, 1, 3, 1, 1, 1, 1); + ia32_gdt[__USER_CS >> 3] = IA32_SEG_DESCRIPTOR(0, (IA32_PAGE_OFFSET-1) >> IA32_PAGE_SHIFT, + 0xb, 1, 3, 1, 1, 1, 1); /* DS descriptor in IA-32 (scrambled) format */ - ia32_gdt_table[__USER_DS >> 3] = - IA32_SEG_DESCRIPTOR(0, (IA32_PAGE_OFFSET - 1) >> IA32_PAGE_SHIFT, - 0x3, 1, 3, 1, 1, 1, 1); + ia32_gdt[__USER_DS >> 3] = IA32_SEG_DESCRIPTOR(0, (IA32_PAGE_OFFSET-1) >> IA32_PAGE_SHIFT, + 0x3, 1, 3, 1, 1, 1, 1); /* We never change the TSS and LDT descriptors, so we can share them across all CPUs. */ ldt_size = PAGE_ALIGN(IA32_LDT_ENTRIES*IA32_LDT_ENTRY_SIZE); for (nr = 0; nr < NR_CPUS; ++nr) { - ia32_gdt_table[_TSS(nr)] = IA32_SEG_DESCRIPTOR(IA32_TSS_OFFSET, 235, - 0xb, 0, 3, 1, 1, 1, 0); - ia32_gdt_table[_LDT(nr)] = IA32_SEG_DESCRIPTOR(IA32_LDT_OFFSET, ldt_size - 1, - 0x2, 0, 3, 1, 1, 1, 0); + ia32_gdt[_TSS(nr)] = IA32_SEG_DESCRIPTOR(IA32_TSS_OFFSET, 235, + 0xb, 0, 3, 1, 1, 1, 0); + ia32_gdt[_LDT(nr)] = IA32_SEG_DESCRIPTOR(IA32_LDT_OFFSET, ldt_size - 1, + 0x2, 0, 3, 1, 1, 1, 0); } } @@ -133,3 +135,18 @@ siginfo.si_code = TRAP_BRKPT; force_sig_info(SIGTRAP, &siginfo, current); } + +static int __init +ia32_init (void) +{ + ia32_exec_domain.name = "Linux/x86"; + ia32_exec_domain.handler = NULL; + ia32_exec_domain.pers_low = PER_LINUX32; + ia32_exec_domain.pers_high = PER_LINUX32; + ia32_exec_domain.signal_map = default_exec_domain.signal_map; + ia32_exec_domain.signal_invmap = default_exec_domain.signal_invmap; + register_exec_domain(&ia32_exec_domain); + return 0; +} + +__initcall(ia32_init); diff -urN linux-2.4.10/arch/ia64/ia32/sys_ia32.c linux-2.4.10-lia/arch/ia64/ia32/sys_ia32.c --- linux-2.4.10/arch/ia64/ia32/sys_ia32.c Mon Aug 20 10:18:26 2001 +++ linux-2.4.10-lia/arch/ia64/ia32/sys_ia32.c Mon Sep 24 21:45:20 2001 @@ -1,14 +1,13 @@ /* - * sys_ia32.c: Conversion between 32bit and 64bit native syscalls. Based on - * sys_sparc32 + * sys_ia32.c: Conversion between 32bit and 64bit native syscalls. Derived from sys_sparc32.c. * * Copyright (C) 2000 VA Linux Co * Copyright (C) 2000 Don Dugger * Copyright (C) 1999 Arun Sharma * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz) * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu) - * Copyright (C) 2000 Hewlett-Packard Co. - * Copyright (C) 2000 David Mosberger-Tang + * Copyright (C) 2000-2001 Hewlett-Packard Co + * David Mosberger-Tang * * These routines maintain argument size conversion between 32bit and 64bit * environment. @@ -53,7 +52,6 @@ #include #include #include -#include #include #include @@ -66,18 +64,23 @@ extern asmlinkage long sys_execve (char *, char **, char **, struct pt_regs *); extern asmlinkage long sys_mprotect (unsigned long, size_t, unsigned long); +extern asmlinkage long sys_munmap (unsigned long, size_t); + +/* forward declaration: */ +asmlinkage long sys32_mprotect (unsigned int, unsigned int, int); static int nargs (unsigned int arg, char **ap) { - int n, err, addr; + unsigned int addr; + int n, err; if (!arg) return 0; n = 0; do { - err = get_user(addr, (int *)A(arg)); + err = get_user(addr, (unsigned int *)A(arg)); if (err) return err; if (ap) @@ -124,14 +127,16 @@ old_map_base = current->thread.map_base; old_task_size = current->thread.task_size; - /* we may be exec'ing a 64-bit process: reset map base & task-size: */ + /* we may be exec'ing a 64-bit process: reset map base, task-size, and io-base: */ current->thread.map_base = DEFAULT_MAP_BASE; current->thread.task_size = DEFAULT_TASK_SIZE; + ia64_set_kr(IA64_KR_IO_BASE, current->thread.old_iob); set_fs(KERNEL_DS); r = sys_execve(filename, av, ae, regs); if (r < 0) { - /* oops, execve failed, switch back to old map base & task-size: */ + /* oops, execve failed, switch back to old values... */ + ia64_set_kr(IA64_KR_IO_BASE, IA32_IOBASE); current->thread.map_base = old_map_base; current->thread.task_size = old_task_size; set_fs(USER_DS); /* establish new task-size as the address-limit */ @@ -142,30 +147,33 @@ } static inline int -putstat(struct stat32 *ubuf, struct stat *kbuf) +putstat (struct stat32 *ubuf, struct stat *kbuf) { int err; - err = put_user (kbuf->st_dev, &ubuf->st_dev); - err |= __put_user (kbuf->st_ino, &ubuf->st_ino); - err |= __put_user (kbuf->st_mode, &ubuf->st_mode); - err |= __put_user (kbuf->st_nlink, &ubuf->st_nlink); - err |= __put_user (kbuf->st_uid, &ubuf->st_uid); - err |= __put_user (kbuf->st_gid, &ubuf->st_gid); - err |= __put_user (kbuf->st_rdev, &ubuf->st_rdev); - err |= __put_user (kbuf->st_size, &ubuf->st_size); - err |= __put_user (kbuf->st_atime, &ubuf->st_atime); - err |= __put_user (kbuf->st_mtime, &ubuf->st_mtime); - err |= __put_user (kbuf->st_ctime, &ubuf->st_ctime); - err |= __put_user (kbuf->st_blksize, &ubuf->st_blksize); - err |= __put_user (kbuf->st_blocks, &ubuf->st_blocks); + if (clear_user(ubuf, sizeof(*ubuf))) + return 1; + + err = __put_user(kbuf->st_dev, &ubuf->st_dev); + err |= __put_user(kbuf->st_ino, &ubuf->st_ino); + err |= __put_user(kbuf->st_mode, &ubuf->st_mode); + err |= __put_user(kbuf->st_nlink, &ubuf->st_nlink); + err |= __put_user(kbuf->st_uid, &ubuf->st_uid); + err |= __put_user(kbuf->st_gid, &ubuf->st_gid); + err |= __put_user(kbuf->st_rdev, &ubuf->st_rdev); + err |= __put_user(kbuf->st_size, &ubuf->st_size); + err |= __put_user(kbuf->st_atime, &ubuf->st_atime); + err |= __put_user(kbuf->st_mtime, &ubuf->st_mtime); + err |= __put_user(kbuf->st_ctime, &ubuf->st_ctime); + err |= __put_user(kbuf->st_blksize, &ubuf->st_blksize); + err |= __put_user(kbuf->st_blocks, &ubuf->st_blocks); return err; } -extern asmlinkage long sys_newstat(char * filename, struct stat * statbuf); +extern asmlinkage long sys_newstat (char * filename, struct stat * statbuf); asmlinkage long -sys32_newstat(char * filename, struct stat32 *statbuf) +sys32_newstat (char *filename, struct stat32 *statbuf) { int ret; struct stat s; @@ -173,8 +181,8 @@ set_fs(KERNEL_DS); ret = sys_newstat(filename, &s); - set_fs (old_fs); - if (putstat (statbuf, &s)) + set_fs(old_fs); + if (putstat(statbuf, &s)) return -EFAULT; return ret; } @@ -182,16 +190,16 @@ extern asmlinkage long sys_newlstat(char * filename, struct stat * statbuf); asmlinkage long -sys32_newlstat(char * filename, struct stat32 *statbuf) +sys32_newlstat (char *filename, struct stat32 *statbuf) { - int ret; - struct stat s; mm_segment_t old_fs = get_fs(); + struct stat s; + int ret; - set_fs (KERNEL_DS); + set_fs(KERNEL_DS); ret = sys_newlstat(filename, &s); - set_fs (old_fs); - if (putstat (statbuf, &s)) + set_fs(old_fs); + if (putstat(statbuf, &s)) return -EFAULT; return ret; } @@ -199,112 +207,171 @@ extern asmlinkage long sys_newfstat(unsigned int fd, struct stat * statbuf); asmlinkage long -sys32_newfstat(unsigned int fd, struct stat32 *statbuf) +sys32_newfstat (unsigned int fd, struct stat32 *statbuf) { - int ret; - struct stat s; mm_segment_t old_fs = get_fs(); + struct stat s; + int ret; - set_fs (KERNEL_DS); + set_fs(KERNEL_DS); ret = sys_newfstat(fd, &s); - set_fs (old_fs); - if (putstat (statbuf, &s)) + set_fs(old_fs); + if (putstat(statbuf, &s)) return -EFAULT; return ret; } #define OFFSET4K(a) ((a) & 0xfff) -unsigned long -do_mmap_fake(struct file *file, unsigned long addr, unsigned long len, - unsigned long prot, unsigned long flags, loff_t off) +#if PAGE_SHIFT > IA32_PAGE_SHIFT + +/* + * Determine whether address ADDR is readable. This must be done *without* actually + * touching memory because otherwise the stack auto-expansion may *make* the address + * readable, which is not at all what we want. --davidm 01/09/20 + */ +static inline long +is_readable (unsigned long addr) +{ + struct vm_area_struct *vma = find_vma(current->mm, addr); + return vma && (vma->vm_start <= addr) && (vma->vm_flags & VM_READ); +} + +static unsigned long +do_mmap_fake (struct file *file, unsigned long addr, unsigned long len, int prot, int flags, + loff_t off) { + unsigned long faddr = (addr & PAGE_MASK), end, front_len, back_len, retval; + void *front = 0, *back = 0; struct inode *inode; - void *front, *back; - unsigned long baddr; - int r; - char c; - if (OFFSET4K(addr) || OFFSET4K(off)) - return -EINVAL; + /* + * Allow any kind of access: this lets us avoid having to figure out what the + * protection of the partial front and back pages is... + */ prot |= PROT_WRITE; - front = NULL; - back = NULL; - if ((baddr = (addr & PAGE_MASK)) != addr && get_user(c, (char *)baddr) == 0) { - front = kmalloc(addr - baddr, GFP_KERNEL); - if (!front) - return -ENOMEM; - __copy_user(front, (void *)baddr, addr - baddr); + + if (OFFSET4K(addr)) + return -EINVAL; + + end = addr + len; + front_len = addr - faddr; + back_len = (end & ~PAGE_MASK); + + if (front_len && is_readable(faddr)) { + front = kmalloc(front_len, GFP_KERNEL); + if (!front) { + addr = -ENOMEM; + goto fail; + } + copy_from_user(front, (void *)faddr, front_len); } - if (addr && ((addr + len) & ~PAGE_MASK) && get_user(c, (char *)(addr + len)) == 0) { - back = kmalloc(PAGE_SIZE - ((addr + len) & ~PAGE_MASK), GFP_KERNEL); + + if (addr && back_len && is_readable(end)) { + back = kmalloc(PAGE_SIZE - back_len, GFP_KERNEL); if (!back) { - if (front) - kfree(front); - return -ENOMEM; + addr = -ENOMEM; + goto fail; } - __copy_user(back, (char *)addr + len, PAGE_SIZE - ((addr + len) & ~PAGE_MASK)); + copy_from_user(back, (char *)end, PAGE_SIZE - back_len); } + down_write(¤t->mm->mmap_sem); - r = do_mmap(0, baddr, len + (addr - baddr), prot, flags | MAP_ANONYMOUS, 0); + { + retval = do_mmap(0, faddr, len + front_len, prot, flags | MAP_ANONYMOUS, 0); + } up_write(¤t->mm->mmap_sem); - if (r < 0) - return(r); - if (addr == 0) - addr = r; + + if (IS_ERR((void *) retval)) { + addr = retval; + goto fail; + } + + if (!addr) + addr = retval; + + end = addr + len; + if (back) { - __copy_user((char *)addr + len, back, PAGE_SIZE - ((addr + len) & ~PAGE_MASK)); + if (copy_to_user((char *) end, back, PAGE_SIZE - back_len)) { + addr = -EINVAL; + goto fail; + } kfree(back); } if (front) { - __copy_user((void *)baddr, front, addr - baddr); + if (copy_to_user((void *) faddr, front, front_len)) { + addr = -EINVAL; + goto fail; + } kfree(front); } - if (flags & MAP_ANONYMOUS) { - clear_user((char *)addr, len); - return(addr); + + if (!(flags & MAP_ANONYMOUS)) { + inode = file->f_dentry->d_inode; + if (!inode->i_fop + || !file->f_op->read + || (*file->f_op->read)(file, (char *)addr, len, &off) < 0) + { + sys_munmap(addr, len + front_len); + return -EINVAL; + } } - if (!file) - return -EINVAL; - inode = file->f_dentry->d_inode; - if (!inode->i_fop) - return -EINVAL; - if (!file->f_op->read) - return -EINVAL; - r = file->f_op->read(file, (char *)addr, len, &off); - return (r < 0) ? -EINVAL : addr; + return addr; + + fail: if (front) + kfree(front); + if (back) + kfree(back); + return addr; } -long -ia32_do_mmap (struct file *file, unsigned int addr, unsigned int len, unsigned int prot, - unsigned int flags, unsigned int fd, unsigned int offset) +#endif /* PAGE_SHIFT > IA32_PAGE_SHIFT */ + +unsigned long +ia32_do_mmap (struct file *file, unsigned long addr, unsigned long len, int prot, int flags, + loff_t offset) { - long error = -EFAULT; - unsigned int poff; + if (file && (!file->f_op || !file->f_op->mmap)) + return -ENODEV; - flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE); - prot |= PROT_EXEC; + len = IA32_PAGE_ALIGN(len); + if (len == 0) + return addr; + + if (len > IA32_PAGE_OFFSET || addr > IA32_PAGE_OFFSET - len) + return -EINVAL; + + if (OFFSET4K(offset)) + return -EINVAL; + + if (prot & (PROT_READ | PROT_WRITE)) + prot |= PROT_EXEC; /* x86 has no "execute" permission bit... */ +#if PAGE_SHIFT > IA32_PAGE_SHIFT if ((flags & MAP_FIXED) && ((addr & ~PAGE_MASK) || (offset & ~PAGE_MASK))) - error = do_mmap_fake(file, addr, len, prot, flags, (loff_t)offset); - else { - poff = offset & PAGE_MASK; - len += offset - poff; + addr = do_mmap_fake(file, addr, len, prot, flags, offset); + else +#endif + { + loff_t pgoff = offset & PAGE_MASK; + len += offset - pgoff; down_write(¤t->mm->mmap_sem); - error = do_mmap_pgoff(file, addr, len, prot, flags, poff >> PAGE_SHIFT); + { + addr = do_mmap(file, addr, len, prot, flags, pgoff); + } up_write(¤t->mm->mmap_sem); - if (!IS_ERR((void *) error)) - error += offset - poff; + if (!IS_ERR((void *) addr)) + addr += offset - pgoff; } - return error; + return addr; } /* - * Linux/i386 didn't use to be able to handle more than - * 4 system call parameters, so these system calls used a memory - * block for parameter passing.. + * Linux/i386 didn't use to be able to handle more than 4 system call parameters, so these + * system calls used a memory block for parameter passing.. */ struct mmap_arg_struct { @@ -317,56 +384,147 @@ }; asmlinkage long -sys32_mmap(struct mmap_arg_struct *arg) +sys32_mmap (struct mmap_arg_struct *arg) { struct mmap_arg_struct a; struct file *file = NULL; - long retval; + unsigned long addr; + int flags; if (copy_from_user(&a, arg, sizeof(a))) return -EFAULT; - if (PAGE_ALIGN(a.len) == 0) - return a.addr; + if (OFFSET4K(a.offset)) + return -EINVAL; + + flags = a.flags; - if (!(a.flags & MAP_ANONYMOUS)) { + flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE); + if (!(flags & MAP_ANONYMOUS)) { file = fget(a.fd); if (!file) return -EBADF; } -#ifdef CONFIG_IA64_PAGE_SIZE_4KB - if ((a.offset & ~PAGE_MASK) != 0) - return -EINVAL; - down_write(¤t->mm->mmap_sem); - retval = do_mmap_pgoff(file, a.addr, a.len, a.prot, a.flags, a.offset >> PAGE_SHIFT); - up_write(¤t->mm->mmap_sem); -#else - retval = ia32_do_mmap(file, a.addr, a.len, a.prot, a.flags, a.fd, a.offset); -#endif + addr = ia32_do_mmap(file, a.addr, a.len, a.prot, flags, a.offset); + + if (file) + fput(file); + return addr; +} + +asmlinkage long +sys32_mmap2 (unsigned int addr, unsigned int len, unsigned int prot, unsigned int flags, + unsigned int fd, unsigned int pgoff) +{ + struct file *file = NULL; + unsigned long retval; + + flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE); + if (!(flags & MAP_ANONYMOUS)) { + file = fget(fd); + if (!file) + return -EBADF; + } + + retval = ia32_do_mmap(file, addr, len, prot, flags, + (unsigned long) pgoff << IA32_PAGE_SHIFT); + if (file) fput(file); return retval; } asmlinkage long -sys32_mprotect(unsigned long start, size_t len, unsigned long prot) +sys32_munmap (unsigned int start, unsigned int len) +{ + unsigned int end = start + len; + +#if PAGE_SHIFT > IA32_PAGE_SHIFT + if (start > end) + return -EINVAL; + + start = PAGE_ALIGN(start); + end = end & PAGE_MASK; + + if (start >= end) + return 0; +#endif + return sys_munmap(start, end - start); +} + +#if PAGE_SHIFT > IA32_PAGE_SHIFT + +/* + * When mprotect()ing a partial page, we set the permission to the union of the old + * settings and the new settings. In other words, it's only possible to make access to a + * partial page less restrictive. + */ +static long +mprotect_partial_page (unsigned long address, int new_prot) +{ + int old_prot; + + if (new_prot == PROT_NONE) + return 0; /* optimize case where nothing changes... */ + + /* + * We cannot easily determine the existing protection on this page because we have + * to relinquish the mmap-semaphore before calling sys_mprotect(), which would + * create a window during which another task could change the protection settings + * underneath us. To avoid this, we conservatively assume that the page is + * RWXable. + */ + old_prot = PROT_READ | PROT_WRITE | PROT_EXEC; + return sys_mprotect(address, PAGE_SIZE, new_prot | old_prot); +} + +#endif /* PAGE_SHIFT > IA32_PAGE_SHIFT */ + +asmlinkage long +sys32_mprotect (unsigned int start, unsigned int len, int prot) { + unsigned long end = start + len; +#if PAGE_SHIFT > IA32_PAGE_SHIFT + long retval; +#endif -#ifdef CONFIG_IA64_PAGE_SIZE_4KB - return(sys_mprotect(start, len, prot)); -#else // CONFIG_IA64_PAGE_SIZE_4KB - if (prot == 0) - return(0); - len += start & ~PAGE_MASK; - if ((start & ~PAGE_MASK) && (prot & PROT_WRITE)) + if (prot & (PROT_READ | PROT_WRITE)) + /* on x86, PROT_WRITE implies PROT_READ and PROT_READ implies PROT_EXEC... */ prot |= PROT_EXEC; - return(sys_mprotect(start & PAGE_MASK, len & PAGE_MASK, prot)); -#endif // CONFIG_IA64_PAGE_SIZE_4KB + +#if PAGE_SHIFT > IA32_PAGE_SHIFT + if (OFFSET4K(start)) + return -EINVAL; + + end = IA32_PAGE_ALIGN(end); + if (end < start) + return -EINVAL; + + if (start & ~PAGE_MASK) { + /* start address is 4KB aligned but not page aligned. */ + retval = mprotect_partial_page(start & PAGE_MASK, prot); + if (retval < 0) + return retval; + + start = PAGE_ALIGN(start); + if (start >= end) + return 0; + } + + if (end & ~PAGE_MASK) { + /* end address is 4KB aligned but not page aligned. */ + retval = mprotect_partial_page(end & PAGE_MASK, prot); + if (retval < 0) + return retval; + end &= PAGE_MASK; + } +#endif + return sys_mprotect(start, end - start, prot); } asmlinkage long -sys32_pipe(int *fd) +sys32_pipe (int *fd) { int retval; int fds[2]; @@ -380,119 +538,154 @@ return retval; } +static inline void +sigact_set_handler (struct k_sigaction *sa, unsigned int handler, unsigned int restorer) +{ + if (handler + 1 <= 2) + /* SIG_DFL, SIG_IGN, or SIG_ERR: must sign-extend to 64-bits */ + sa->sa.sa_handler = (__sighandler_t) A((int) handler); + else + sa->sa.sa_handler = (__sighandler_t) (((unsigned long) restorer << 32) | handler); +} + asmlinkage long sys32_signal (int sig, unsigned int handler) { struct k_sigaction new_sa, old_sa; int ret; - new_sa.sa.sa_handler = (__sighandler_t) A(handler); + sigact_set_handler(&new_sa, handler, 0); new_sa.sa.sa_flags = SA_ONESHOT | SA_NOMASK; ret = do_sigaction(sig, &new_sa, &old_sa); - return ret ? ret : (unsigned long)old_sa.sa.sa_handler; + return ret ? ret : IA32_SA_HANDLER(&old_sa); } asmlinkage long -sys32_rt_sigaction(int sig, struct sigaction32 *act, - struct sigaction32 *oact, unsigned int sigsetsize) +sys32_rt_sigaction (int sig, struct sigaction32 *act, + struct sigaction32 *oact, unsigned int sigsetsize) { struct k_sigaction new_ka, old_ka; + unsigned int handler, restorer; int ret; - sigset32_t set32; /* XXX: Don't preclude handling different sized sigset_t's. */ if (sigsetsize != sizeof(sigset32_t)) return -EINVAL; if (act) { - ret = get_user((long)new_ka.sa.sa_handler, &act->sa_handler); - ret |= __copy_from_user(&set32, &act->sa_mask, - sizeof(sigset32_t)); - switch (_NSIG_WORDS) { - case 4: new_ka.sa.sa_mask.sig[3] = set32.sig[6] - | (((long)set32.sig[7]) << 32); - case 3: new_ka.sa.sa_mask.sig[2] = set32.sig[4] - | (((long)set32.sig[5]) << 32); - case 2: new_ka.sa.sa_mask.sig[1] = set32.sig[2] - | (((long)set32.sig[3]) << 32); - case 1: new_ka.sa.sa_mask.sig[0] = set32.sig[0] - | (((long)set32.sig[1]) << 32); - } - ret |= __get_user(new_ka.sa.sa_flags, &act->sa_flags); - + ret = get_user(handler, &act->sa_handler); + ret |= get_user(new_ka.sa.sa_flags, &act->sa_flags); + ret |= get_user(restorer, &act->sa_restorer); + ret |= copy_from_user(&new_ka.sa.sa_mask, &act->sa_mask, sizeof(sigset32_t)); if (ret) return -EFAULT; + + sigact_set_handler(&new_ka, handler, restorer); } ret = do_sigaction(sig, act ? &new_ka : NULL, oact ? &old_ka : NULL); if (!ret && oact) { - switch (_NSIG_WORDS) { - case 4: - set32.sig[7] = (old_ka.sa.sa_mask.sig[3] >> 32); - set32.sig[6] = old_ka.sa.sa_mask.sig[3]; - case 3: - set32.sig[5] = (old_ka.sa.sa_mask.sig[2] >> 32); - set32.sig[4] = old_ka.sa.sa_mask.sig[2]; - case 2: - set32.sig[3] = (old_ka.sa.sa_mask.sig[1] >> 32); - set32.sig[2] = old_ka.sa.sa_mask.sig[1]; - case 1: - set32.sig[1] = (old_ka.sa.sa_mask.sig[0] >> 32); - set32.sig[0] = old_ka.sa.sa_mask.sig[0]; - } - ret = put_user((long)old_ka.sa.sa_handler, &oact->sa_handler); - ret |= __copy_to_user(&oact->sa_mask, &set32, - sizeof(sigset32_t)); - ret |= __put_user(old_ka.sa.sa_flags, &oact->sa_flags); + ret = put_user(IA32_SA_HANDLER(&old_ka), &oact->sa_handler); + ret |= put_user(old_ka.sa.sa_flags, &oact->sa_flags); + ret |= put_user(IA32_SA_RESTORER(&old_ka), &oact->sa_restorer); + ret |= copy_to_user(&oact->sa_mask, &old_ka.sa.sa_mask, sizeof(sigset32_t)); } - return ret; } -extern asmlinkage long sys_rt_sigprocmask(int how, sigset_t *set, sigset_t *oset, - size_t sigsetsize); +extern asmlinkage long sys_rt_sigprocmask (int how, sigset_t *set, sigset_t *oset, + size_t sigsetsize); asmlinkage long -sys32_rt_sigprocmask(int how, sigset32_t *set, sigset32_t *oset, - unsigned int sigsetsize) +sys32_rt_sigprocmask (int how, sigset32_t *set, sigset32_t *oset, unsigned int sigsetsize) { - sigset_t s; - sigset32_t s32; - int ret; mm_segment_t old_fs = get_fs(); + sigset_t s; + long ret; + + if (sigsetsize > sizeof(s)) + return -EINVAL; if (set) { - if (copy_from_user (&s32, set, sizeof(sigset32_t))) + memset(&s, 0, sizeof(s)); + if (copy_from_user(&s.sig, set, sigsetsize)) return -EFAULT; - switch (_NSIG_WORDS) { - case 4: s.sig[3] = s32.sig[6] | (((long)s32.sig[7]) << 32); - case 3: s.sig[2] = s32.sig[4] | (((long)s32.sig[5]) << 32); - case 2: s.sig[1] = s32.sig[2] | (((long)s32.sig[3]) << 32); - case 1: s.sig[0] = s32.sig[0] | (((long)s32.sig[1]) << 32); - } } - set_fs (KERNEL_DS); - ret = sys_rt_sigprocmask(how, set ? &s : NULL, oset ? &s : NULL, - sigsetsize); - set_fs (old_fs); - if (ret) return ret; + set_fs(KERNEL_DS); + ret = sys_rt_sigprocmask(how, set ? &s : NULL, oset ? &s : NULL, sizeof(s)); + set_fs(old_fs); + if (ret) + return ret; if (oset) { - switch (_NSIG_WORDS) { - case 4: s32.sig[7] = (s.sig[3] >> 32); s32.sig[6] = s.sig[3]; - case 3: s32.sig[5] = (s.sig[2] >> 32); s32.sig[4] = s.sig[2]; - case 2: s32.sig[3] = (s.sig[1] >> 32); s32.sig[2] = s.sig[1]; - case 1: s32.sig[1] = (s.sig[0] >> 32); s32.sig[0] = s.sig[0]; - } - if (copy_to_user (oset, &s32, sizeof(sigset32_t))) + if (copy_to_user(oset, &s.sig, sigsetsize)) return -EFAULT; } return 0; } +asmlinkage long +sys32_sigprocmask (int how, unsigned int *set, unsigned int *oset) +{ + return sys32_rt_sigprocmask(how, (sigset32_t *) set, (sigset32_t *) oset, sizeof(*set)); +} + +struct timespec32 { + int tv_sec; + int tv_nsec; +}; + +asmlinkage long +sys32_rt_sigtimedwait (sigset32_t *uthese, siginfo_t32 *uinfo, struct timespec32 *uts, + unsigned int sigsetsize) +{ + extern asmlinkage long sys_rt_sigtimedwait (const sigset_t *, siginfo_t *, + const struct timespec *, size_t); + extern int copy_siginfo_to_user32 (siginfo_t32 *, siginfo_t *); + mm_segment_t old_fs = get_fs(); + struct timespec t; + siginfo_t info; + sigset_t s; + int ret; + + if (copy_from_user(&s.sig, uthese, sizeof(sigset32_t))) + return -EFAULT; + if (uts) { + ret = get_user(t.tv_sec, &uts->tv_sec); + ret |= get_user(t.tv_nsec, &uts->tv_nsec); + if (ret) + return -EFAULT; + } + set_fs(KERNEL_DS); + ret = sys_rt_sigtimedwait(&s, &info, &t, sigsetsize); + set_fs(old_fs); + if (ret >= 0 && uinfo) { + if (copy_siginfo_to_user32(uinfo, &info)) + return -EFAULT; + } + return ret; +} + +asmlinkage long +sys32_rt_sigqueueinfo (int pid, int sig, siginfo_t32 *uinfo) +{ + extern asmlinkage long sys_rt_sigqueueinfo (int, int, siginfo_t *); + extern int copy_siginfo_from_user32 (siginfo_t *to, siginfo_t32 *from); + mm_segment_t old_fs = get_fs(); + siginfo_t info; + int ret; + + if (copy_siginfo_from_user32(&info, uinfo)) + return -EFAULT; + set_fs(KERNEL_DS); + ret = sys_rt_sigqueueinfo(pid, sig, &info); + set_fs(old_fs); + return ret; +} + static inline int put_statfs (struct statfs32 *ubuf, struct statfs *kbuf) { @@ -514,15 +707,15 @@ extern asmlinkage long sys_statfs(const char * path, struct statfs * buf); asmlinkage long -sys32_statfs(const char * path, struct statfs32 *buf) +sys32_statfs (const char *path, struct statfs32 *buf) { int ret; struct statfs s; mm_segment_t old_fs = get_fs(); - set_fs (KERNEL_DS); - ret = sys_statfs((const char *)path, &s); - set_fs (old_fs); + set_fs(KERNEL_DS); + ret = sys_statfs(path, &s); + set_fs(old_fs); if (put_statfs(buf, &s)) return -EFAULT; return ret; @@ -531,15 +724,15 @@ extern asmlinkage long sys_fstatfs(unsigned int fd, struct statfs * buf); asmlinkage long -sys32_fstatfs(unsigned int fd, struct statfs32 *buf) +sys32_fstatfs (unsigned int fd, struct statfs32 *buf) { int ret; struct statfs s; mm_segment_t old_fs = get_fs(); - set_fs (KERNEL_DS); + set_fs(KERNEL_DS); ret = sys_fstatfs(fd, &s); - set_fs (old_fs); + set_fs(old_fs); if (put_statfs(buf, &s)) return -EFAULT; return ret; @@ -557,7 +750,7 @@ }; static inline long -get_tv32(struct timeval *o, struct timeval32 *i) +get_tv32 (struct timeval *o, struct timeval32 *i) { return (!access_ok(VERIFY_READ, i, sizeof(*i)) || (__get_user(o->tv_sec, &i->tv_sec) | @@ -565,7 +758,7 @@ } static inline long -put_tv32(struct timeval32 *o, struct timeval *i) +put_tv32 (struct timeval32 *o, struct timeval *i) { return (!access_ok(VERIFY_WRITE, o, sizeof(*o)) || (__put_user(i->tv_sec, &o->tv_sec) | @@ -573,7 +766,7 @@ } static inline long -get_it32(struct itimerval *o, struct itimerval32 *i) +get_it32 (struct itimerval *o, struct itimerval32 *i) { return (!access_ok(VERIFY_READ, i, sizeof(*i)) || (__get_user(o->it_interval.tv_sec, &i->it_interval.tv_sec) | @@ -583,7 +776,7 @@ } static inline long -put_it32(struct itimerval32 *o, struct itimerval *i) +put_it32 (struct itimerval32 *o, struct itimerval *i) { return (!access_ok(VERIFY_WRITE, o, sizeof(*o)) || (__put_user(i->it_interval.tv_sec, &o->it_interval.tv_sec) | @@ -592,10 +785,10 @@ __put_user(i->it_value.tv_usec, &o->it_value.tv_usec))); } -extern int do_getitimer(int which, struct itimerval *value); +extern int do_getitimer (int which, struct itimerval *value); asmlinkage long -sys32_getitimer(int which, struct itimerval32 *it) +sys32_getitimer (int which, struct itimerval32 *it) { struct itimerval kit; int error; @@ -607,10 +800,10 @@ return error; } -extern int do_setitimer(int which, struct itimerval *, struct itimerval *); +extern int do_setitimer (int which, struct itimerval *, struct itimerval *); asmlinkage long -sys32_setitimer(int which, struct itimerval32 *in, struct itimerval32 *out) +sys32_setitimer (int which, struct itimerval32 *in, struct itimerval32 *out) { struct itimerval kin, kout; int error; @@ -630,8 +823,9 @@ return 0; } + asmlinkage unsigned long -sys32_alarm(unsigned int seconds) +sys32_alarm (unsigned int seconds) { struct itimerval it_new, it_old; unsigned int oldalarm; @@ -660,7 +854,7 @@ extern asmlinkage long sys_gettimeofday (struct timeval *tv, struct timezone *tz); asmlinkage long -ia32_utime(char * filename, struct utimbuf_32 *times32) +sys32_utime (char *filename, struct utimbuf_32 *times32) { mm_segment_t old_fs = get_fs(); struct timeval tv[2], *tvp; @@ -673,20 +867,20 @@ if (get_user(tv[1].tv_sec, ×32->mtime)) return -EFAULT; tv[1].tv_usec = 0; - set_fs (KERNEL_DS); + set_fs(KERNEL_DS); tvp = tv; } else tvp = NULL; ret = sys_utimes(filename, tvp); - set_fs (old_fs); + set_fs(old_fs); return ret; } extern struct timezone sys_tz; -extern int do_sys_settimeofday(struct timeval *tv, struct timezone *tz); +extern int do_sys_settimeofday (struct timeval *tv, struct timezone *tz); asmlinkage long -sys32_gettimeofday(struct timeval32 *tv, struct timezone *tz) +sys32_gettimeofday (struct timeval32 *tv, struct timezone *tz) { if (tv) { struct timeval ktv; @@ -702,7 +896,7 @@ } asmlinkage long -sys32_settimeofday(struct timeval32 *tv, struct timezone *tz) +sys32_settimeofday (struct timeval32 *tv, struct timezone *tz) { struct timeval ktv; struct timezone ktz; @@ -775,7 +969,7 @@ } asmlinkage long -sys32_getdents (unsigned int fd, void * dirent, unsigned int count) +sys32_getdents (unsigned int fd, struct linux32_dirent *dirent, unsigned int count) { struct file * file; struct linux32_dirent * lastdirent; @@ -787,7 +981,7 @@ if (!file) goto out; - buf.current_dir = (struct linux32_dirent *) dirent; + buf.current_dir = dirent; buf.previous = NULL; buf.count = count; buf.error = 0; @@ -831,7 +1025,7 @@ } asmlinkage long -sys32_readdir (unsigned int fd, void * dirent, unsigned int count) +sys32_readdir (unsigned int fd, void *dirent, unsigned int count) { int error; struct file * file; @@ -866,7 +1060,7 @@ #define ROUND_UP_TIME(x,y) (((x)+(y)-1)/(y)) asmlinkage long -sys32_select(int n, fd_set *inp, fd_set *outp, fd_set *exp, struct timeval32 *tvp32) +sys32_select (int n, fd_set *inp, fd_set *outp, fd_set *exp, struct timeval32 *tvp32) { fd_set_bits fds; char *bits; @@ -878,8 +1072,7 @@ time_t sec, usec; ret = -EFAULT; - if (get_user(sec, &tvp32->tv_sec) - || get_user(usec, &tvp32->tv_usec)) + if (get_user(sec, &tvp32->tv_sec) || get_user(usec, &tvp32->tv_usec)) goto out_nofds; ret = -EINVAL; @@ -933,9 +1126,7 @@ usec = timeout % HZ; usec *= (1000000/HZ); } - if (put_user(sec, (int *)&tvp32->tv_sec) - || put_user(usec, (int *)&tvp32->tv_usec)) - { + if (put_user(sec, &tvp32->tv_sec) || put_user(usec, &tvp32->tv_usec)) { ret = -EFAULT; goto out; } @@ -969,50 +1160,43 @@ }; asmlinkage long -old_select(struct sel_arg_struct *arg) +sys32_old_select (struct sel_arg_struct *arg) { struct sel_arg_struct a; if (copy_from_user(&a, arg, sizeof(a))) return -EFAULT; - return sys32_select(a.n, (fd_set *)A(a.inp), (fd_set *)A(a.outp), (fd_set *)A(a.exp), - (struct timeval32 *)A(a.tvp)); + return sys32_select(a.n, (fd_set *) A(a.inp), (fd_set *) A(a.outp), (fd_set *) A(a.exp), + (struct timeval32 *) A(a.tvp)); } -struct timespec32 { - int tv_sec; - int tv_nsec; -}; - -extern asmlinkage long sys_nanosleep(struct timespec *rqtp, struct timespec *rmtp); +extern asmlinkage long sys_nanosleep (struct timespec *rqtp, struct timespec *rmtp); asmlinkage long -sys32_nanosleep(struct timespec32 *rqtp, struct timespec32 *rmtp) +sys32_nanosleep (struct timespec32 *rqtp, struct timespec32 *rmtp) { struct timespec t; int ret; mm_segment_t old_fs = get_fs (); - if (get_user (t.tv_sec, &rqtp->tv_sec) || - __get_user (t.tv_nsec, &rqtp->tv_nsec)) + if (get_user (t.tv_sec, &rqtp->tv_sec) || get_user (t.tv_nsec, &rqtp->tv_nsec)) return -EFAULT; - set_fs (KERNEL_DS); + set_fs(KERNEL_DS); ret = sys_nanosleep(&t, rmtp ? &t : NULL); - set_fs (old_fs); + set_fs(old_fs); if (rmtp && ret == -EINTR) { - if (__put_user (t.tv_sec, &rmtp->tv_sec) || - __put_user (t.tv_nsec, &rmtp->tv_nsec)) + if (put_user(t.tv_sec, &rmtp->tv_sec) || put_user(t.tv_nsec, &rmtp->tv_nsec)) return -EFAULT; } return ret; } struct iovec32 { unsigned int iov_base; int iov_len; }; -asmlinkage ssize_t sys_readv(unsigned long,const struct iovec *,unsigned long); -asmlinkage ssize_t sys_writev(unsigned long,const struct iovec *,unsigned long); +asmlinkage ssize_t sys_readv (unsigned long,const struct iovec *,unsigned long); +asmlinkage ssize_t sys_writev (unsigned long,const struct iovec *,unsigned long); static struct iovec * -get_iovec32(struct iovec32 *iov32, struct iovec *iov_buf, u32 count, int type) +get_iovec32 (struct iovec32 *iov32, struct iovec *iov_buf, u32 count, int type) { int i; u32 buf, len; @@ -1022,24 +1206,23 @@ if (!count) return 0; - if(verify_area(VERIFY_READ, iov32, sizeof(struct iovec32)*count)) - return(struct iovec *)0; + if (verify_area(VERIFY_READ, iov32, sizeof(struct iovec32)*count)) + return NULL; if (count > UIO_MAXIOV) - return(struct iovec *)0; + return NULL; if (count > UIO_FASTIOV) { iov = kmalloc(count*sizeof(struct iovec), GFP_KERNEL); if (!iov) - return((struct iovec *)0); + return NULL; } else iov = iov_buf; ivp = iov; for (i = 0; i < count; i++) { - if (__get_user(len, &iov32->iov_len) || - __get_user(buf, &iov32->iov_base)) { + if (__get_user(len, &iov32->iov_len) || __get_user(buf, &iov32->iov_base)) { if (iov != iov_buf) kfree(iov); - return((struct iovec *)0); + return NULL; } if (verify_area(type, (void *)A(buf), len)) { if (iov != iov_buf) @@ -1047,22 +1230,23 @@ return((struct iovec *)0); } ivp->iov_base = (void *)A(buf); - ivp->iov_len = (__kernel_size_t)len; + ivp->iov_len = (__kernel_size_t) len; iov32++; ivp++; } - return(iov); + return iov; } asmlinkage long -sys32_readv(int fd, struct iovec32 *vector, u32 count) +sys32_readv (int fd, struct iovec32 *vector, u32 count) { struct iovec iovstack[UIO_FASTIOV]; struct iovec *iov; - int ret; + long ret; mm_segment_t old_fs = get_fs(); - if ((iov = get_iovec32(vector, iovstack, count, VERIFY_WRITE)) == (struct iovec *)0) + iov = get_iovec32(vector, iovstack, count, VERIFY_WRITE); + if (!iov) return -EFAULT; set_fs(KERNEL_DS); ret = sys_readv(fd, iov, count); @@ -1073,14 +1257,15 @@ } asmlinkage long -sys32_writev(int fd, struct iovec32 *vector, u32 count) +sys32_writev (int fd, struct iovec32 *vector, u32 count) { struct iovec iovstack[UIO_FASTIOV]; struct iovec *iov; - int ret; + long ret; mm_segment_t old_fs = get_fs(); - if ((iov = get_iovec32(vector, iovstack, count, VERIFY_READ)) == (struct iovec *)0) + iov = get_iovec32(vector, iovstack, count, VERIFY_READ); + if (!iov) return -EFAULT; set_fs(KERNEL_DS); ret = sys_writev(fd, iov, count); @@ -1098,45 +1283,66 @@ int rlim_max; }; -extern asmlinkage long sys_getrlimit(unsigned int resource, struct rlimit *rlim); +extern asmlinkage long sys_getrlimit (unsigned int resource, struct rlimit *rlim); asmlinkage long -sys32_getrlimit(unsigned int resource, struct rlimit32 *rlim) +sys32_old_getrlimit (unsigned int resource, struct rlimit32 *rlim) { + mm_segment_t old_fs = get_fs(); struct rlimit r; int ret; - mm_segment_t old_fs = get_fs (); - set_fs (KERNEL_DS); + set_fs(KERNEL_DS); + ret = sys_getrlimit(resource, &r); + set_fs(old_fs); + if (!ret) { + ret = put_user(RESOURCE32(r.rlim_cur), &rlim->rlim_cur); + ret |= put_user(RESOURCE32(r.rlim_max), &rlim->rlim_max); + } + return ret; +} + +asmlinkage long +sys32_getrlimit (unsigned int resource, struct rlimit32 *rlim) +{ + mm_segment_t old_fs = get_fs(); + struct rlimit r; + int ret; + + set_fs(KERNEL_DS); ret = sys_getrlimit(resource, &r); - set_fs (old_fs); + set_fs(old_fs); if (!ret) { - ret = put_user (RESOURCE32(r.rlim_cur), &rlim->rlim_cur); - ret |= __put_user (RESOURCE32(r.rlim_max), &rlim->rlim_max); + if (r.rlim_cur >= 0xffffffff) + r.rlim_cur = 0xffffffff; + if (r.rlim_max >= 0xffffffff) + r.rlim_max = 0xffffffff; + ret = put_user(r.rlim_cur, &rlim->rlim_cur); + ret |= put_user(r.rlim_max, &rlim->rlim_max); } return ret; } -extern asmlinkage long sys_setrlimit(unsigned int resource, struct rlimit *rlim); +extern asmlinkage long sys_setrlimit (unsigned int resource, struct rlimit *rlim); asmlinkage long -sys32_setrlimit(unsigned int resource, struct rlimit32 *rlim) +sys32_setrlimit (unsigned int resource, struct rlimit32 *rlim) { struct rlimit r; int ret; - mm_segment_t old_fs = get_fs (); + mm_segment_t old_fs = get_fs(); - if (resource >= RLIM_NLIMITS) return -EINVAL; - if (get_user (r.rlim_cur, &rlim->rlim_cur) || - __get_user (r.rlim_max, &rlim->rlim_max)) + if (resource >= RLIM_NLIMITS) + return -EINVAL; + if (get_user(r.rlim_cur, &rlim->rlim_cur) || get_user(r.rlim_max, &rlim->rlim_max)) return -EFAULT; if (r.rlim_cur == RLIM_INFINITY32) r.rlim_cur = RLIM_INFINITY; if (r.rlim_max == RLIM_INFINITY32) r.rlim_max = RLIM_INFINITY; - set_fs (KERNEL_DS); + set_fs(KERNEL_DS); ret = sys_setrlimit(resource, &r); - set_fs (old_fs); + set_fs(old_fs); return ret; } @@ -1155,7 +1361,7 @@ }; static inline int -shape_msg(struct msghdr *mp, struct msghdr32 *mp32) +shape_msg (struct msghdr *mp, struct msghdr32 *mp32) { int ret; unsigned int i; @@ -1187,7 +1393,7 @@ */ static inline int -verify_iovec32(struct msghdr *m, struct iovec *iov, char *address, int mode) +verify_iovec32 (struct msghdr *m, struct iovec *iov, char *address, int mode) { int size, err, ct; struct iovec32 *iov32; @@ -1222,8 +1428,8 @@ return err; } -extern __inline__ void -sockfd_put(struct socket *sock) +static inline void +sockfd_put (struct socket *sock) { fput(sock->file); } @@ -1234,13 +1440,14 @@ 24 for IPv6, about 80 for AX.25 */ -extern struct socket *sockfd_lookup(int fd, int *err); +extern struct socket *sockfd_lookup (int fd, int *err); /* * BSD sendmsg interface */ -int sys32_sendmsg(int fd, struct msghdr32 *msg, unsigned flags) +int +sys32_sendmsg (int fd, struct msghdr32 *msg, unsigned flags) { struct socket *sock; char address[MAX_SOCK_ADDR]; @@ -1404,9 +1611,9 @@ /* Argument list sizes for sys_socketcall */ #define AL(x) ((x) * sizeof(u32)) -static unsigned char nas[18]={AL(0),AL(3),AL(3),AL(3),AL(2),AL(3), - AL(3),AL(3),AL(4),AL(4),AL(4),AL(6), - AL(6),AL(2),AL(5),AL(5),AL(3),AL(3)}; +static const unsigned char nas[18]={AL(0),AL(3),AL(3),AL(3),AL(2),AL(3), + AL(3),AL(3),AL(4),AL(4),AL(4),AL(6), + AL(6),AL(2),AL(5),AL(5),AL(3),AL(3)}; #undef AL extern asmlinkage long sys_bind(int fd, struct sockaddr *umyaddr, int addrlen); @@ -1435,7 +1642,8 @@ extern asmlinkage long sys_shutdown(int fd, int how); extern asmlinkage long sys_listen(int fd, int backlog); -asmlinkage long sys32_socketcall(int call, u32 *args) +asmlinkage long +sys32_socketcall (int call, u32 *args) { int ret; u32 a[6]; @@ -1463,16 +1671,13 @@ ret = sys_listen(a0, a1); break; case SYS_ACCEPT: - ret = sys_accept(a0, (struct sockaddr *)A(a1), - (int *)A(a[2])); + ret = sys_accept(a0, (struct sockaddr *)A(a1), (int *)A(a[2])); break; case SYS_GETSOCKNAME: - ret = sys_getsockname(a0, (struct sockaddr *)A(a1), - (int *)A(a[2])); + ret = sys_getsockname(a0, (struct sockaddr *)A(a1), (int *)A(a[2])); break; case SYS_GETPEERNAME: - ret = sys_getpeername(a0, (struct sockaddr *)A(a1), - (int *)A(a[2])); + ret = sys_getpeername(a0, (struct sockaddr *)A(a1), (int *)A(a[2])); break; case SYS_SOCKETPAIR: ret = sys_socketpair(a0, a1, a[2], (int *)A(a[3])); @@ -1500,12 +1705,10 @@ ret = sys_getsockopt(a0, a1, a[2], a[3], a[4]); break; case SYS_SENDMSG: - ret = sys32_sendmsg(a0, (struct msghdr32 *)A(a1), - a[2]); + ret = sys32_sendmsg(a0, (struct msghdr32 *) A(a1), a[2]); break; case SYS_RECVMSG: - ret = sys32_recvmsg(a0, (struct msghdr32 *)A(a1), - a[2]); + ret = sys32_recvmsg(a0, (struct msghdr32 *) A(a1), a[2]); break; default: ret = EINVAL; @@ -1572,10 +1775,27 @@ unsigned short shm_nattch; }; +struct ipc_kludge { + struct msgbuf *msgp; + long msgtyp; +}; + +#define SEMOP 1 +#define SEMGET 2 +#define SEMCTL 3 +#define MSGSND 11 +#define MSGRCV 12 +#define MSGGET 13 +#define MSGCTL 14 +#define SHMAT 21 +#define SHMDT 22 +#define SHMGET 23 +#define SHMCTL 24 + #define IPCOP_MASK(__x) (1UL << (__x)) static int -do_sys32_semctl(int first, int second, int third, void *uptr) +do_sys32_semctl (int first, int second, int third, void *uptr) { union semun fourth; u32 pad; @@ -1588,7 +1808,7 @@ return -EINVAL; if (get_user(pad, (u32 *)uptr)) return -EFAULT; - if(third == SETVAL) + if (third == SETVAL) fourth.val = (int)pad; else fourth.__pad = (void *)A(pad); @@ -1605,44 +1825,38 @@ case GETALL: case SETVAL: case SETALL: - err = sys_semctl (first, second, third, fourth); + err = sys_semctl(first, second, third, fourth); break; case IPC_STAT: case SEM_STAT: usp = (struct semid_ds32 *)A(pad); fourth.__pad = &s; - old_fs = get_fs (); - set_fs (KERNEL_DS); - err = sys_semctl (first, second, third, fourth); - set_fs (old_fs); + old_fs = get_fs(); + set_fs(KERNEL_DS); + err = sys_semctl(first, second, third, fourth); + set_fs(old_fs); err2 = put_user(s.sem_perm.key, &usp->sem_perm.key); - err2 |= __put_user(s.sem_perm.uid, &usp->sem_perm.uid); - err2 |= __put_user(s.sem_perm.gid, &usp->sem_perm.gid); - err2 |= __put_user(s.sem_perm.cuid, - &usp->sem_perm.cuid); - err2 |= __put_user (s.sem_perm.cgid, - &usp->sem_perm.cgid); - err2 |= __put_user (s.sem_perm.mode, - &usp->sem_perm.mode); - err2 |= __put_user (s.sem_perm.seq, &usp->sem_perm.seq); - err2 |= __put_user (s.sem_otime, &usp->sem_otime); - err2 |= __put_user (s.sem_ctime, &usp->sem_ctime); - err2 |= __put_user (s.sem_nsems, &usp->sem_nsems); + err2 |= put_user(s.sem_perm.uid, &usp->sem_perm.uid); + err2 |= put_user(s.sem_perm.gid, &usp->sem_perm.gid); + err2 |= put_user(s.sem_perm.cuid, &usp->sem_perm.cuid); + err2 |= put_user(s.sem_perm.cgid, &usp->sem_perm.cgid); + err2 |= put_user(s.sem_perm.mode, &usp->sem_perm.mode); + err2 |= put_user(s.sem_perm.seq, &usp->sem_perm.seq); + err2 |= put_user(s.sem_otime, &usp->sem_otime); + err2 |= put_user(s.sem_ctime, &usp->sem_ctime); + err2 |= put_user(s.sem_nsems, &usp->sem_nsems); if (err2) err = -EFAULT; break; - } - return err; } static int do_sys32_msgsnd (int first, int second, int third, void *uptr) { - struct msgbuf *p = kmalloc (second + sizeof (struct msgbuf) - + 4, GFP_USER); + struct msgbuf *p = kmalloc (second + sizeof(struct msgbuf) + 4, GFP_USER); struct msgbuf32 *up = (struct msgbuf32 *)uptr; mm_segment_t old_fs; int err; @@ -1654,17 +1868,16 @@ if (err) goto out; old_fs = get_fs (); - set_fs (KERNEL_DS); + set_fs(KERNEL_DS); err = sys_msgsnd (first, p, second, third); - set_fs (old_fs); + set_fs(old_fs); out: kfree (p); return err; } static int -do_sys32_msgrcv (int first, int second, int msgtyp, int third, - int version, void *uptr) +do_sys32_msgrcv (int first, int second, int msgtyp, int third, int version, void *uptr) { struct msgbuf32 *up; struct msgbuf *p; @@ -1689,9 +1902,9 @@ if (!p) goto out; old_fs = get_fs (); - set_fs (KERNEL_DS); + set_fs(KERNEL_DS); err = sys_msgrcv (first, p, second + 4, msgtyp, third); - set_fs (old_fs); + set_fs(old_fs); if (err < 0) goto free_then_out; up = (struct msgbuf32 *)uptr; @@ -1718,49 +1931,47 @@ case IPC_INFO: case IPC_RMID: case MSG_INFO: - err = sys_msgctl (first, second, (struct msqid_ds *)uptr); + err = sys_msgctl(first, second, (struct msqid_ds *)uptr); break; case IPC_SET: - err = get_user (m.msg_perm.uid, &up->msg_perm.uid); - err |= __get_user (m.msg_perm.gid, &up->msg_perm.gid); - err |= __get_user (m.msg_perm.mode, &up->msg_perm.mode); - err |= __get_user (m.msg_qbytes, &up->msg_qbytes); + err = get_user(m.msg_perm.uid, &up->msg_perm.uid); + err |= get_user(m.msg_perm.gid, &up->msg_perm.gid); + err |= get_user(m.msg_perm.mode, &up->msg_perm.mode); + err |= get_user(m.msg_qbytes, &up->msg_qbytes); if (err) break; - old_fs = get_fs (); - set_fs (KERNEL_DS); - err = sys_msgctl (first, second, &m); - set_fs (old_fs); + old_fs = get_fs(); + set_fs(KERNEL_DS); + err = sys_msgctl(first, second, &m); + set_fs(old_fs); break; case IPC_STAT: case MSG_STAT: - old_fs = get_fs (); - set_fs (KERNEL_DS); - err = sys_msgctl (first, second, (void *) &m64); - set_fs (old_fs); - err2 = put_user (m64.msg_perm.key, &up->msg_perm.key); - err2 |= __put_user(m64.msg_perm.uid, &up->msg_perm.uid); - err2 |= __put_user(m64.msg_perm.gid, &up->msg_perm.gid); - err2 |= __put_user(m64.msg_perm.cuid, &up->msg_perm.cuid); - err2 |= __put_user(m64.msg_perm.cgid, &up->msg_perm.cgid); - err2 |= __put_user(m64.msg_perm.mode, &up->msg_perm.mode); - err2 |= __put_user(m64.msg_perm.seq, &up->msg_perm.seq); - err2 |= __put_user(m64.msg_stime, &up->msg_stime); - err2 |= __put_user(m64.msg_rtime, &up->msg_rtime); - err2 |= __put_user(m64.msg_ctime, &up->msg_ctime); - err2 |= __put_user(m64.msg_cbytes, &up->msg_cbytes); - err2 |= __put_user(m64.msg_qnum, &up->msg_qnum); - err2 |= __put_user(m64.msg_qbytes, &up->msg_qbytes); - err2 |= __put_user(m64.msg_lspid, &up->msg_lspid); - err2 |= __put_user(m64.msg_lrpid, &up->msg_lrpid); + old_fs = get_fs(); + set_fs(KERNEL_DS); + err = sys_msgctl(first, second, (void *) &m64); + set_fs(old_fs); + err2 = put_user(m64.msg_perm.key, &up->msg_perm.key); + err2 |= put_user(m64.msg_perm.uid, &up->msg_perm.uid); + err2 |= put_user(m64.msg_perm.gid, &up->msg_perm.gid); + err2 |= put_user(m64.msg_perm.cuid, &up->msg_perm.cuid); + err2 |= put_user(m64.msg_perm.cgid, &up->msg_perm.cgid); + err2 |= put_user(m64.msg_perm.mode, &up->msg_perm.mode); + err2 |= put_user(m64.msg_perm.seq, &up->msg_perm.seq); + err2 |= put_user(m64.msg_stime, &up->msg_stime); + err2 |= put_user(m64.msg_rtime, &up->msg_rtime); + err2 |= put_user(m64.msg_ctime, &up->msg_ctime); + err2 |= put_user(m64.msg_cbytes, &up->msg_cbytes); + err2 |= put_user(m64.msg_qnum, &up->msg_qnum); + err2 |= put_user(m64.msg_qbytes, &up->msg_qbytes); + err2 |= put_user(m64.msg_lspid, &up->msg_lspid); + err2 |= put_user(m64.msg_lrpid, &up->msg_lrpid); if (err2) err = -EFAULT; break; - } - return err; } @@ -1772,8 +1983,8 @@ int err; if (version == 1) - return -EINVAL; - err = sys_shmat (first, uptr, second, &raddr); + return -EINVAL; /* iBCS2 emulator entry point: unsupported */ + err = sys_shmat(first, uptr, second, &raddr); if (err) return err; return put_user(raddr, uaddr); @@ -1804,60 +2015,55 @@ break; case IPC_SET: err = get_user (s.shm_perm.uid, &up->shm_perm.uid); - err |= __get_user (s.shm_perm.gid, &up->shm_perm.gid); - err |= __get_user (s.shm_perm.mode, &up->shm_perm.mode); + err |= get_user(s.shm_perm.gid, &up->shm_perm.gid); + err |= get_user(s.shm_perm.mode, &up->shm_perm.mode); if (err) break; - old_fs = get_fs (); - set_fs (KERNEL_DS); - err = sys_shmctl (first, second, &s); - set_fs (old_fs); + old_fs = get_fs(); + set_fs(KERNEL_DS); + err = sys_shmctl(first, second, &s); + set_fs(old_fs); break; case IPC_STAT: case SHM_STAT: - old_fs = get_fs (); - set_fs (KERNEL_DS); + old_fs = get_fs(); + set_fs(KERNEL_DS); err = sys_shmctl (first, second, (void *) &s64); - set_fs (old_fs); + set_fs(old_fs); if (err < 0) break; - err2 = put_user (s64.shm_perm.key, &up->shm_perm.key); - err2 |= __put_user (s64.shm_perm.uid, &up->shm_perm.uid); - err2 |= __put_user (s64.shm_perm.gid, &up->shm_perm.gid); - err2 |= __put_user (s64.shm_perm.cuid, - &up->shm_perm.cuid); - err2 |= __put_user (s64.shm_perm.cgid, - &up->shm_perm.cgid); - err2 |= __put_user (s64.shm_perm.mode, - &up->shm_perm.mode); - err2 |= __put_user (s64.shm_perm.seq, &up->shm_perm.seq); - err2 |= __put_user (s64.shm_atime, &up->shm_atime); - err2 |= __put_user (s64.shm_dtime, &up->shm_dtime); - err2 |= __put_user (s64.shm_ctime, &up->shm_ctime); - err2 |= __put_user (s64.shm_segsz, &up->shm_segsz); - err2 |= __put_user (s64.shm_nattch, &up->shm_nattch); - err2 |= __put_user (s64.shm_cpid, &up->shm_cpid); - err2 |= __put_user (s64.shm_lpid, &up->shm_lpid); + err2 = put_user(s64.shm_perm.key, &up->shm_perm.key); + err2 |= put_user(s64.shm_perm.uid, &up->shm_perm.uid); + err2 |= put_user(s64.shm_perm.gid, &up->shm_perm.gid); + err2 |= put_user(s64.shm_perm.cuid, &up->shm_perm.cuid); + err2 |= put_user(s64.shm_perm.cgid, &up->shm_perm.cgid); + err2 |= put_user(s64.shm_perm.mode, &up->shm_perm.mode); + err2 |= put_user(s64.shm_perm.seq, &up->shm_perm.seq); + err2 |= put_user(s64.shm_atime, &up->shm_atime); + err2 |= put_user(s64.shm_dtime, &up->shm_dtime); + err2 |= put_user(s64.shm_ctime, &up->shm_ctime); + err2 |= put_user(s64.shm_segsz, &up->shm_segsz); + err2 |= put_user(s64.shm_nattch, &up->shm_nattch); + err2 |= put_user(s64.shm_cpid, &up->shm_cpid); + err2 |= put_user(s64.shm_lpid, &up->shm_lpid); if (err2) err = -EFAULT; break; case SHM_INFO: - old_fs = get_fs (); - set_fs (KERNEL_DS); - err = sys_shmctl (first, second, (void *)&si); - set_fs (old_fs); + old_fs = get_fs(); + set_fs(KERNEL_DS); + err = sys_shmctl(first, second, (void *)&si); + set_fs(old_fs); if (err < 0) break; - err2 = put_user (si.used_ids, &uip->used_ids); - err2 |= __put_user (si.shm_tot, &uip->shm_tot); - err2 |= __put_user (si.shm_rss, &uip->shm_rss); - err2 |= __put_user (si.shm_swp, &uip->shm_swp); - err2 |= __put_user (si.swap_attempts, - &uip->swap_attempts); - err2 |= __put_user (si.swap_successes, - &uip->swap_successes); + err2 = put_user(si.used_ids, &uip->used_ids); + err2 |= put_user(si.shm_tot, &uip->shm_tot); + err2 |= put_user(si.shm_rss, &uip->shm_rss); + err2 |= put_user(si.shm_swp, &uip->shm_swp); + err2 |= put_user(si.swap_attempts, &uip->swap_attempts); + err2 |= put_user(si.swap_successes, &uip->swap_successes); if (err2) err = -EFAULT; break; @@ -1875,53 +2081,48 @@ call &= 0xffff; switch (call) { - - case SEMOP: + case SEMOP: /* struct sembuf is the same on 32 and 64bit :)) */ - err = sys_semop (first, (struct sembuf *)AA(ptr), - second); - break; - case SEMGET: - err = sys_semget (first, second, third); - break; - case SEMCTL: - err = do_sys32_semctl (first, second, third, - (void *)AA(ptr)); - break; + return sys_semop(first, (struct sembuf *)AA(ptr), second); + case SEMGET: + return sys_semget(first, second, third); + case SEMCTL: + if (third & IPC_64) { + printk("sys32_ipc(SEMCTL): no IPC_64 version; please fix me."); + return -ENOSYS; + } + return do_sys32_semctl(first, second, third, (void *)AA(ptr)); - case MSGSND: - err = do_sys32_msgsnd (first, second, third, - (void *)AA(ptr)); - break; - case MSGRCV: - err = do_sys32_msgrcv (first, second, fifth, third, - version, (void *)AA(ptr)); - break; - case MSGGET: - err = sys_msgget ((key_t) first, second); - break; - case MSGCTL: - err = do_sys32_msgctl (first, second, (void *)AA(ptr)); - break; + case MSGSND: + return do_sys32_msgsnd(first, second, third, (void *)AA(ptr)); + case MSGRCV: + return do_sys32_msgrcv(first, second, fifth, third, version, (void *)AA(ptr)); + case MSGGET: + return sys_msgget((key_t) first, second); + case MSGCTL: + if (second & IPC_64) { + printk("sys32_ipc(MSGCTL): no IPC_64 version; please fix me."); + return -ENOSYS; + } + return do_sys32_msgctl(first, second, (void *)AA(ptr)); - case SHMAT: - err = do_sys32_shmat (first, second, third, version, (void *)AA(ptr)); + case SHMAT: + err = do_sys32_shmat(first, second, third, version, (void *)AA(ptr)); break; - case SHMDT: - err = sys_shmdt ((char *)AA(ptr)); - break; - case SHMGET: - err = sys_shmget (first, second, third); - break; - case SHMCTL: - err = do_sys32_shmctl (first, second, (void *)AA(ptr)); - break; - default: - err = -EINVAL; - break; - } + case SHMDT: + return sys_shmdt((char *)AA(ptr)); + case SHMGET: + return sys_shmget(first, second, third); + case SHMCTL: + if (second & IPC_64) { + printk("sys32_ipc(SHMCTL): no IPC_64 version; please fix me."); + return -ENOSYS; + } + return do_sys32_shmctl(first, second, (void *)AA(ptr)); - return err; + default: + return -EINVAL; + } } /* @@ -1929,7 +2130,8 @@ * sys_gettimeofday(). IA64 did this but i386 Linux did not * so we have to implement this system call here. */ -asmlinkage long sys32_time(int * tloc) +asmlinkage long +sys32_time (int *tloc) { int i; @@ -1937,7 +2139,7 @@ stuff it to user space. No side effects */ i = CURRENT_TIME; if (tloc) { - if (put_user(i,tloc)) + if (put_user(i, tloc)) i = -EFAULT; } return i; @@ -1989,8 +2191,7 @@ } asmlinkage long -sys32_wait4(__kernel_pid_t32 pid, unsigned int *stat_addr, int options, - struct rusage32 *ru) +sys32_wait4 (int pid, unsigned int *stat_addr, int options, struct rusage32 *ru) { if (!ru) return sys_wait4(pid, stat_addr, options, NULL); @@ -2000,37 +2201,38 @@ unsigned int status; mm_segment_t old_fs = get_fs(); - set_fs (KERNEL_DS); + set_fs(KERNEL_DS); ret = sys_wait4(pid, stat_addr ? &status : NULL, options, &r); - set_fs (old_fs); - if (put_rusage (ru, &r)) return -EFAULT; - if (stat_addr && put_user (status, stat_addr)) + set_fs(old_fs); + if (put_rusage(ru, &r)) + return -EFAULT; + if (stat_addr && put_user(status, stat_addr)) return -EFAULT; return ret; } } asmlinkage long -sys32_waitpid(__kernel_pid_t32 pid, unsigned int *stat_addr, int options) +sys32_waitpid (int pid, unsigned int *stat_addr, int options) { return sys32_wait4(pid, stat_addr, options, NULL); } -extern asmlinkage long -sys_getrusage(int who, struct rusage *ru); +extern asmlinkage long sys_getrusage (int who, struct rusage *ru); asmlinkage long -sys32_getrusage(int who, struct rusage32 *ru) +sys32_getrusage (int who, struct rusage32 *ru) { struct rusage r; int ret; mm_segment_t old_fs = get_fs(); - set_fs (KERNEL_DS); + set_fs(KERNEL_DS); ret = sys_getrusage(who, &r); - set_fs (old_fs); - if (put_rusage (ru, &r)) return -EFAULT; + set_fs(old_fs); + if (put_rusage (ru, &r)) + return -EFAULT; return ret; } @@ -2041,41 +2243,41 @@ __kernel_clock_t32 tms_cstime; }; -extern asmlinkage long sys_times(struct tms * tbuf); +extern asmlinkage long sys_times (struct tms * tbuf); asmlinkage long -sys32_times(struct tms32 *tbuf) +sys32_times (struct tms32 *tbuf) { + mm_segment_t old_fs = get_fs(); struct tms t; long ret; - mm_segment_t old_fs = get_fs (); int err; - set_fs (KERNEL_DS); + set_fs(KERNEL_DS); ret = sys_times(tbuf ? &t : NULL); - set_fs (old_fs); + set_fs(old_fs); if (tbuf) { err = put_user (IA32_TICK(t.tms_utime), &tbuf->tms_utime); - err |= __put_user (IA32_TICK(t.tms_stime), &tbuf->tms_stime); - err |= __put_user (IA32_TICK(t.tms_cutime), &tbuf->tms_cutime); - err |= __put_user (IA32_TICK(t.tms_cstime), &tbuf->tms_cstime); + err |= put_user (IA32_TICK(t.tms_stime), &tbuf->tms_stime); + err |= put_user (IA32_TICK(t.tms_cutime), &tbuf->tms_cutime); + err |= put_user (IA32_TICK(t.tms_cstime), &tbuf->tms_cstime); if (err) ret = -EFAULT; } return IA32_TICK(ret); } -unsigned int +static unsigned int ia32_peek (struct pt_regs *regs, struct task_struct *child, unsigned long addr, unsigned int *val) { size_t copied; unsigned int ret; copied = access_process_vm(child, addr, val, sizeof(*val), 0); - return(copied != sizeof(ret) ? -EIO : 0); + return (copied != sizeof(ret)) ? -EIO : 0; } -unsigned int +static unsigned int ia32_poke (struct pt_regs *regs, struct task_struct *child, unsigned long addr, unsigned int val) { @@ -2105,113 +2307,70 @@ #define PT_UESP 15 #define PT_SS 16 -unsigned int -getreg(struct task_struct *child, int regno) +static unsigned int +getreg (struct task_struct *child, int regno) { struct pt_regs *child_regs; child_regs = ia64_task_regs(child); switch (regno / sizeof(int)) { - - case PT_EBX: - return(child_regs->r11); - case PT_ECX: - return(child_regs->r9); - case PT_EDX: - return(child_regs->r10); - case PT_ESI: - return(child_regs->r14); - case PT_EDI: - return(child_regs->r15); - case PT_EBP: - return(child_regs->r13); - case PT_EAX: - case PT_ORIG_EAX: - return(child_regs->r8); - case PT_EIP: - return(child_regs->cr_iip); - case PT_UESP: - return(child_regs->r12); - case PT_EFL: - return(child->thread.eflag); - case PT_DS: - case PT_ES: - case PT_FS: - case PT_GS: - case PT_SS: - return((unsigned int)__USER_DS); - case PT_CS: - return((unsigned int)__USER_CS); - default: - printk(KERN_ERR "getregs:unknown register %d\n", regno); + case PT_EBX: return child_regs->r11; + case PT_ECX: return child_regs->r9; + case PT_EDX: return child_regs->r10; + case PT_ESI: return child_regs->r14; + case PT_EDI: return child_regs->r15; + case PT_EBP: return child_regs->r13; + case PT_EAX: return child_regs->r8; + case PT_ORIG_EAX: return child_regs->r1; /* see dispatch_to_ia32_handler() */ + case PT_EIP: return child_regs->cr_iip; + case PT_UESP: return child_regs->r12; + case PT_EFL: return child->thread.eflag; + case PT_DS: case PT_ES: case PT_FS: case PT_GS: case PT_SS: + return __USER_DS; + case PT_CS: return __USER_CS; + default: + printk(KERN_ERR "getreg:unknown register %d\n", regno); break; - } - return(0); + return 0; } -void -putreg(struct task_struct *child, int regno, unsigned int value) +static void +putreg (struct task_struct *child, int regno, unsigned int value) { struct pt_regs *child_regs; child_regs = ia64_task_regs(child); switch (regno / sizeof(int)) { - - case PT_EBX: - child_regs->r11 = value; - break; - case PT_ECX: - child_regs->r9 = value; - break; - case PT_EDX: - child_regs->r10 = value; - break; - case PT_ESI: - child_regs->r14 = value; - break; - case PT_EDI: - child_regs->r15 = value; - break; - case PT_EBP: - child_regs->r13 = value; - break; - case PT_EAX: - case PT_ORIG_EAX: - child_regs->r8 = value; - break; - case PT_EIP: - child_regs->cr_iip = value; - break; - case PT_UESP: - child_regs->r12 = value; - break; - case PT_EFL: - child->thread.eflag = value; - break; - case PT_DS: - case PT_ES: - case PT_FS: - case PT_GS: - case PT_SS: + case PT_EBX: child_regs->r11 = value; break; + case PT_ECX: child_regs->r9 = value; break; + case PT_EDX: child_regs->r10 = value; break; + case PT_ESI: child_regs->r14 = value; break; + case PT_EDI: child_regs->r15 = value; break; + case PT_EBP: child_regs->r13 = value; break; + case PT_EAX: child_regs->r8 = value; break; + case PT_ORIG_EAX: child_regs->r1 = value; break; + case PT_EIP: child_regs->cr_iip = value; break; + case PT_UESP: child_regs->r12 = value; break; + case PT_EFL: child->thread.eflag = value; break; + case PT_DS: case PT_ES: case PT_FS: case PT_GS: case PT_SS: if (value != __USER_DS) printk(KERN_ERR "setregs:try to set invalid segment register %d = %x\n", regno, value); break; - case PT_CS: + case PT_CS: if (value != __USER_CS) printk(KERN_ERR "setregs:try to set invalid segment register %d = %x\n", regno, value); break; - default: - printk(KERN_ERR "getregs:unknown register %d\n", regno); + default: + printk(KERN_ERR "putreg:unknown register %d\n", regno); break; - } } static inline void -ia32f2ia64f(void *dst, void *src) +ia32f2ia64f (void *dst, void *src) { __asm__ ("ldfe f6=[%1] ;;\n\t" @@ -2222,7 +2381,7 @@ } static inline void -ia64f2ia32f(void *dst, void *src) +ia64f2ia32f (void *dst, void *src) { __asm__ ("ldf.fill f6=[%1] ;;\n\t" @@ -2232,8 +2391,9 @@ return; } -void -put_fpreg(int regno, struct _fpreg_ia32 *reg, struct pt_regs *ptp, struct switch_stack *swp, int tos) +static void +put_fpreg (int regno, struct _fpreg_ia32 *reg, struct pt_regs *ptp, struct switch_stack *swp, + int tos) { struct _fpreg_ia32 *f; char buf[32]; @@ -2262,8 +2422,9 @@ __copy_to_user(reg, f, sizeof(*reg)); } -void -get_fpreg(int regno, struct _fpreg_ia32 *reg, struct pt_regs *ptp, struct switch_stack *swp, int tos) +static void +get_fpreg (int regno, struct _fpreg_ia32 *reg, struct pt_regs *ptp, struct switch_stack *swp, + int tos) { if ((regno += tos) >= 8) @@ -2289,8 +2450,8 @@ return; } -int -save_ia32_fpstate(struct task_struct *tsk, struct _fpstate_ia32 *save) +static int +save_ia32_fpstate (struct task_struct *tsk, struct _fpstate_ia32 *save) { struct switch_stack *swp; struct pt_regs *ptp; @@ -2313,11 +2474,11 @@ tos = (tsk->thread.fsr >> 11) & 3; for (i = 0; i < 8; i++) put_fpreg(i, &save->_st[i], ptp, swp, tos); - return(0); + return 0; } -int -restore_ia32_fpstate(struct task_struct *tsk, struct _fpstate_ia32 *save) +static int +restore_ia32_fpstate (struct task_struct *tsk, struct _fpstate_ia32 *save) { struct switch_stack *swp; struct pt_regs *ptp; @@ -2340,10 +2501,11 @@ tos = (tsk->thread.fsr >> 11) & 3; for (i = 0; i < 8; i++) get_fpreg(i, &save->_st[i], ptp, swp, tos); - return(ret ? -EFAULT : 0); + return ret ? -EFAULT : 0; } -asmlinkage long sys_ptrace(long, pid_t, unsigned long, unsigned long, long, long, long, long, long); +extern asmlinkage long sys_ptrace (long, pid_t, unsigned long, unsigned long, long, long, long, + long, long); /* * Note that the IA32 version of `ptrace' calls the IA64 routine for @@ -2358,13 +2520,12 @@ { struct pt_regs *regs = (struct pt_regs *) &stack; struct task_struct *child; + unsigned int value, tmp; long i, ret; - unsigned int value; lock_kernel(); if (request == PTRACE_TRACEME) { - ret = sys_ptrace(request, pid, addr, data, - arg4, arg5, arg6, arg7, stack); + ret = sys_ptrace(request, pid, addr, data, arg4, arg5, arg6, arg7, stack); goto out; } @@ -2379,8 +2540,7 @@ goto out; if (request == PTRACE_ATTACH) { - ret = sys_ptrace(request, pid, addr, data, - arg4, arg5, arg6, arg7, stack); + ret = sys_ptrace(request, pid, addr, data, arg4, arg5, arg6, arg7, stack); goto out; } ret = -ESRCH; @@ -2398,21 +2558,32 @@ case PTRACE_PEEKDATA: /* read word at location addr */ ret = ia32_peek(regs, child, addr, &value); if (ret == 0) - ret = put_user(value, (unsigned int *)A(data)); + ret = put_user(value, (unsigned int *) A(data)); else ret = -EIO; goto out; case PTRACE_POKETEXT: case PTRACE_POKEDATA: /* write the word at location addr */ - ret = ia32_poke(regs, child, addr, (unsigned int)data); + ret = ia32_poke(regs, child, addr, data); goto out; case PTRACE_PEEKUSR: /* read word at addr in USER area */ - ret = 0; + ret = -EIO; + if ((addr & 3) || addr > 17*sizeof(int)) + break; + + tmp = getreg(child, addr); + if (!put_user(tmp, (unsigned int *) A(data))) + ret = 0; break; case PTRACE_POKEUSR: /* write word at addr in USER area */ + ret = -EIO; + if ((addr & 3) || addr > 17*sizeof(int)) + break; + + putreg(child, addr, data); ret = 0; break; @@ -2421,28 +2592,25 @@ ret = -EIO; break; } - for ( i = 0; i < 17*sizeof(int); i += sizeof(int) ) { - __put_user(getreg(child, i), (unsigned int *) A(data)); + for (i = 0; i < 17*sizeof(int); i += sizeof(int) ) { + put_user(getreg(child, i), (unsigned int *) A(data)); data += sizeof(int); } ret = 0; break; case IA32_PTRACE_SETREGS: - { - unsigned int tmp; if (!access_ok(VERIFY_READ, (int *) A(data), 17*sizeof(int))) { ret = -EIO; break; } - for ( i = 0; i < 17*sizeof(int); i += sizeof(int) ) { - __get_user(tmp, (unsigned int *) A(data)); + for (i = 0; i < 17*sizeof(int); i += sizeof(int) ) { + get_user(tmp, (unsigned int *) A(data)); putreg(child, i, tmp); data += sizeof(int); } ret = 0; break; - } case IA32_PTRACE_GETFPREGS: ret = save_ia32_fpstate(child, (struct _fpstate_ia32 *) A(data)); @@ -2457,10 +2625,8 @@ case PTRACE_KILL: case PTRACE_SINGLESTEP: /* execute chile for one instruction */ case PTRACE_DETACH: /* detach a process */ - unlock_kernel(); - ret = sys_ptrace(request, pid, addr, data, - arg4, arg5, arg6, arg7, stack); - return(ret); + ret = sys_ptrace(request, pid, addr, data, arg4, arg5, arg6, arg7, stack); + break; default: ret = -EIO; @@ -2498,35 +2664,35 @@ return err; } -extern asmlinkage long sys_fcntl(unsigned int fd, unsigned int cmd, - unsigned long arg); +extern asmlinkage long sys_fcntl (unsigned int fd, unsigned int cmd, unsigned long arg); asmlinkage long -sys32_fcntl(unsigned int fd, unsigned int cmd, int arg) +sys32_fcntl (unsigned int fd, unsigned int cmd, unsigned int arg) { - struct flock f; mm_segment_t old_fs; + struct flock f; long ret; switch (cmd) { - case F_GETLK: - case F_SETLK: - case F_SETLKW: - if(get_flock32(&f, (struct flock32 *)((long)arg))) + case F_GETLK: + case F_SETLK: + case F_SETLKW: + if (get_flock32(&f, (struct flock32 *) A(arg))) return -EFAULT; old_fs = get_fs(); set_fs(KERNEL_DS); - ret = sys_fcntl(fd, cmd, (unsigned long)&f); + ret = sys_fcntl(fd, cmd, (unsigned long) &f); set_fs(old_fs); - if(cmd == F_GETLK && put_flock32(&f, (struct flock32 *)((long)arg))) + if (cmd == F_GETLK && put_flock32(&f, (struct flock32 *) A(arg))) return -EFAULT; return ret; - default: + + default: /* * `sys_fcntl' lies about arg, for the F_SETOWN * sub-function arg can have a negative value. */ - return sys_fcntl(fd, cmd, (unsigned long)((long)arg)); + return sys_fcntl(fd, cmd, arg); } } @@ -2534,25 +2700,30 @@ sys32_sigaction (int sig, struct old_sigaction32 *act, struct old_sigaction32 *oact) { struct k_sigaction new_ka, old_ka; + unsigned int handler, restorer; int ret; if (act) { old_sigset32_t mask; - ret = get_user((long)new_ka.sa.sa_handler, &act->sa_handler); - ret |= __get_user(new_ka.sa.sa_flags, &act->sa_flags); - ret |= __get_user(mask, &act->sa_mask); + ret = get_user(handler, &act->sa_handler); + ret |= get_user(new_ka.sa.sa_flags, &act->sa_flags); + ret |= get_user(restorer, &act->sa_restorer); + ret |= get_user(mask, &act->sa_mask); if (ret) return ret; + + sigact_set_handler(&new_ka, handler, restorer); siginitset(&new_ka.sa.sa_mask, mask); } ret = do_sigaction(sig, act ? &new_ka : NULL, oact ? &old_ka : NULL); if (!ret && oact) { - ret = put_user((long)old_ka.sa.sa_handler, &oact->sa_handler); - ret |= __put_user(old_ka.sa.sa_flags, &oact->sa_flags); - ret |= __put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask); + ret = put_user(IA32_SA_HANDLER(&old_ka), &oact->sa_handler); + ret |= put_user(old_ka.sa.sa_flags, &oact->sa_flags); + ret |= put_user(IA32_SA_RESTORER(&old_ka), &oact->sa_restorer); + ret |= put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask); } return ret; @@ -2561,8 +2732,8 @@ asmlinkage long sys_ni_syscall(void); asmlinkage long -sys32_ni_syscall(int dummy0, int dummy1, int dummy2, int dummy3, - int dummy4, int dummy5, int dummy6, int dummy7, int stack) +sys32_ni_syscall (int dummy0, int dummy1, int dummy2, int dummy3, int dummy4, int dummy5, + int dummy6, int dummy7, int stack) { struct pt_regs *regs = (struct pt_regs *)&stack; @@ -2577,7 +2748,7 @@ #define IOLEN ((65536 / 4) * 4096) asmlinkage long -sys_iopl (int level) +sys32_iopl (int level) { extern unsigned long ia64_iobase; int fd; @@ -2612,7 +2783,6 @@ up_write(¤t->mm->mmap_sem); if (addr >= 0) { - ia64_set_kr(IA64_KR_IO_BASE, addr); old = (old & ~0x3000) | (level << 12); __asm__ __volatile__("mov ar.eflag=%0 ;;" :: "r"(old)); } @@ -2623,7 +2793,7 @@ } asmlinkage long -sys_ioperm (unsigned int from, unsigned int num, int on) +sys32_ioperm (unsigned int from, unsigned int num, int on) { /* @@ -2636,7 +2806,7 @@ * XXX proper ioperm() support should be emulated by * manipulating the page protections... */ - return sys_iopl(3); + return sys32_iopl(3); } typedef struct { @@ -2646,10 +2816,8 @@ } ia32_stack_t; asmlinkage long -sys32_sigaltstack (const ia32_stack_t *uss32, ia32_stack_t *uoss32, -long arg2, long arg3, long arg4, -long arg5, long arg6, long arg7, -long stack) +sys32_sigaltstack (ia32_stack_t *uss32, ia32_stack_t *uoss32, + long arg2, long arg3, long arg4, long arg5, long arg6, long arg7, long stack) { struct pt_regs *pt = (struct pt_regs *) &stack; stack_t uss, uoss; @@ -2658,8 +2826,8 @@ mm_segment_t old_fs = get_fs(); if (uss32) - if (copy_from_user(&buf32, (void *)A(uss32), sizeof(ia32_stack_t))) - return(-EFAULT); + if (copy_from_user(&buf32, uss32, sizeof(ia32_stack_t))) + return -EFAULT; uss.ss_sp = (void *) (long) buf32.ss_sp; uss.ss_flags = buf32.ss_flags; uss.ss_size = buf32.ss_size; @@ -2672,34 +2840,34 @@ buf32.ss_sp = (long) uoss.ss_sp; buf32.ss_flags = uoss.ss_flags; buf32.ss_size = uoss.ss_size; - if (copy_to_user((void*)A(uoss32), &buf32, sizeof(ia32_stack_t))) - return(-EFAULT); + if (copy_to_user(uoss32, &buf32, sizeof(ia32_stack_t))) + return -EFAULT; } - return(ret); + return ret; } asmlinkage int -sys_pause (void) +sys32_pause (void) { current->state = TASK_INTERRUPTIBLE; schedule(); return -ERESTARTNOHAND; } -asmlinkage long sys_msync(unsigned long start, size_t len, int flags); +asmlinkage long sys_msync (unsigned long start, size_t len, int flags); asmlinkage int -sys32_msync(unsigned int start, unsigned int len, int flags) +sys32_msync (unsigned int start, unsigned int len, int flags) { unsigned int addr; if (OFFSET4K(start)) return -EINVAL; addr = start & PAGE_MASK; - return(sys_msync(addr, len + (start - addr), flags)); + return sys_msync(addr, len + (start - addr), flags); } -struct sysctl_ia32 { +struct sysctl32 { unsigned int name; int nlen; unsigned int oldval; @@ -2712,16 +2880,16 @@ extern asmlinkage long sys_sysctl(struct __sysctl_args *args); asmlinkage long -sys32_sysctl(struct sysctl_ia32 *args32) +sys32_sysctl (struct sysctl32 *args) { - struct sysctl_ia32 a32; + struct sysctl32 a32; mm_segment_t old_fs = get_fs (); void *oldvalp, *newvalp; size_t oldlen; int *namep; long ret; - if (copy_from_user(&a32, args32, sizeof (a32))) + if (copy_from_user(&a32, args, sizeof(a32))) return -EFAULT; /* @@ -2754,7 +2922,7 @@ } asmlinkage long -sys32_newuname(struct new_utsname * name) +sys32_newuname (struct new_utsname *name) { extern asmlinkage long sys_newuname(struct new_utsname * name); int ret = sys_newuname(name); @@ -2765,10 +2933,10 @@ return ret; } -extern asmlinkage long sys_getresuid(uid_t *ruid, uid_t *euid, uid_t *suid); +extern asmlinkage long sys_getresuid (uid_t *ruid, uid_t *euid, uid_t *suid); asmlinkage long -sys32_getresuid (u16 *ruid, u16 *euid, u16 *suid) +sys32_getresuid16 (u16 *ruid, u16 *euid, u16 *suid) { uid_t a, b, c; int ret; @@ -2786,7 +2954,7 @@ extern asmlinkage long sys_getresgid (gid_t *rgid, gid_t *egid, gid_t *sgid); asmlinkage long -sys32_getresgid(u16 *rgid, u16 *egid, u16 *sgid) +sys32_getresgid16 (u16 *rgid, u16 *egid, u16 *sgid) { gid_t a, b, c; int ret; @@ -2796,15 +2964,13 @@ ret = sys_getresgid(&a, &b, &c); set_fs(old_fs); - if (!ret) { - ret = put_user(a, rgid); - ret |= put_user(b, egid); - ret |= put_user(c, sgid); - } - return ret; + if (ret) + return ret; + + return put_user(a, rgid) | put_user(b, egid) | put_user(c, sgid); } -int +asmlinkage long sys32_lseek (unsigned int fd, int offset, unsigned int whence) { extern off_t sys_lseek (unsigned int fd, off_t offset, unsigned int origin); @@ -2813,190 +2979,448 @@ return sys_lseek(fd, offset, whence); } -#ifdef NOTYET /* UNTESTED FOR IA64 FROM HERE DOWN */ +extern asmlinkage long sys_getgroups (int gidsetsize, gid_t *grouplist); -/* In order to reduce some races, while at the same time doing additional - * checking and hopefully speeding things up, we copy filenames to the - * kernel data space before using them.. - * - * POSIX.1 2.4: an empty pathname is invalid (ENOENT). - */ -static inline int -do_getname32(const char *filename, char *page) +asmlinkage long +sys32_getgroups16 (int gidsetsize, short *grouplist) { - int retval; + mm_segment_t old_fs = get_fs(); + gid_t gl[NGROUPS]; + int ret, i; - /* 32bit pointer will be always far below TASK_SIZE :)) */ - retval = strncpy_from_user((char *)page, (char *)filename, PAGE_SIZE); - if (retval > 0) { - if (retval < PAGE_SIZE) - return 0; - return -ENAMETOOLONG; - } else if (!retval) - retval = -ENOENT; - return retval; + set_fs(KERNEL_DS); + ret = sys_getgroups(gidsetsize, gl); + set_fs(old_fs); + + if (gidsetsize && ret > 0 && ret <= NGROUPS) + for (i = 0; i < ret; i++, grouplist++) + if (put_user(gl[i], grouplist)) + return -EFAULT; + return ret; } -char * -getname32(const char *filename) -{ - char *tmp, *result; +extern asmlinkage long sys_setgroups (int gidsetsize, gid_t *grouplist); - result = ERR_PTR(-ENOMEM); - tmp = (char *)__get_free_page(GFP_KERNEL); - if (tmp) { - int retval = do_getname32(filename, tmp); +asmlinkage long +sys32_setgroups16 (int gidsetsize, short *grouplist) +{ + mm_segment_t old_fs = get_fs(); + gid_t gl[NGROUPS]; + int ret, i; - result = tmp; - if (retval < 0) { - putname(tmp); - result = ERR_PTR(retval); - } - } - return result; + if ((unsigned) gidsetsize > NGROUPS) + return -EINVAL; + for (i = 0; i < gidsetsize; i++, grouplist++) + if (get_user(gl[i], grouplist)) + return -EFAULT; + set_fs(KERNEL_DS); + ret = sys_setgroups(gidsetsize, gl); + set_fs(old_fs); + return ret; } -/* 32-bit timeval and related flotsam. */ - -extern asmlinkage long sys_ioperm(unsigned long from, unsigned long num, int on); +/* + * Unfortunately, the x86 compiler aligns variables of type "long long" to a 4 byte boundary + * only, which means that the x86 version of "struct flock64" doesn't match the ia64 version + * of struct flock. + */ -asmlinkage long -sys32_ioperm(u32 from, u32 num, int on) +static inline long +ia32_put_flock (struct flock *l, unsigned long addr) { - return sys_ioperm((unsigned long)from, (unsigned long)num, on); + return (put_user(l->l_type, (short *) addr) + | put_user(l->l_whence, (short *) (addr + 2)) + | put_user(l->l_start, (long *) (addr + 4)) + | put_user(l->l_len, (long *) (addr + 12)) + | put_user(l->l_pid, (int *) (addr + 20))); } -struct dqblk32 { - __u32 dqb_bhardlimit; - __u32 dqb_bsoftlimit; - __u32 dqb_curblocks; - __u32 dqb_ihardlimit; - __u32 dqb_isoftlimit; - __u32 dqb_curinodes; - __kernel_time_t32 dqb_btime; - __kernel_time_t32 dqb_itime; -}; - -extern asmlinkage long sys_quotactl(int cmd, const char *special, int id, - caddr_t addr); +static inline long +ia32_get_flock (struct flock *l, unsigned long addr) +{ + unsigned int start_lo, start_hi, len_lo, len_hi; + int err = (get_user(l->l_type, (short *) addr) + | get_user(l->l_whence, (short *) (addr + 2)) + | get_user(start_lo, (int *) (addr + 4)) + | get_user(start_hi, (int *) (addr + 8)) + | get_user(len_lo, (int *) (addr + 12)) + | get_user(len_hi, (int *) (addr + 16)) + | get_user(l->l_pid, (int *) (addr + 20))); + l->l_start = ((unsigned long) start_hi << 32) | start_lo; + l->l_len = ((unsigned long) len_hi << 32) | len_lo; + return err; +} asmlinkage long -sys32_quotactl(int cmd, const char *special, int id, unsigned long addr) +sys32_fcntl64 (unsigned int fd, unsigned int cmd, unsigned int arg) { - int cmds = cmd >> SUBCMDSHIFT; - int err; - struct dqblk d; mm_segment_t old_fs; - char *spec; + struct flock f; + long ret; - switch (cmds) { - case Q_GETQUOTA: - break; - case Q_SETQUOTA: - case Q_SETUSE: - case Q_SETQLIM: - if (copy_from_user (&d, (struct dqblk32 *)addr, - sizeof (struct dqblk32))) + switch (cmd) { + case F_GETLK64: + case F_SETLK64: + case F_SETLKW64: + if (ia32_get_flock(&f, arg)) return -EFAULT; - d.dqb_itime = ((struct dqblk32 *)&d)->dqb_itime; - d.dqb_btime = ((struct dqblk32 *)&d)->dqb_btime; - break; - default: - return sys_quotactl(cmd, special, - id, (caddr_t)addr); - } - spec = getname32 (special); - err = PTR_ERR(spec); - if (IS_ERR(spec)) return err; - old_fs = get_fs (); - set_fs (KERNEL_DS); - err = sys_quotactl(cmd, (const char *)spec, id, (caddr_t)&d); - set_fs (old_fs); - putname (spec); - if (cmds == Q_GETQUOTA) { - __kernel_time_t b = d.dqb_btime, i = d.dqb_itime; - ((struct dqblk32 *)&d)->dqb_itime = i; - ((struct dqblk32 *)&d)->dqb_btime = b; - if (copy_to_user ((struct dqblk32 *)addr, &d, - sizeof (struct dqblk32))) + old_fs = get_fs(); + set_fs(KERNEL_DS); + ret = sys_fcntl(fd, cmd, (unsigned long) &f); + set_fs(old_fs); + if (cmd == F_GETLK && ia32_put_flock(&f, arg)) return -EFAULT; + break; + + default: + ret = sys32_fcntl(fd, cmd, arg); + break; } - return err; + return ret; } -extern asmlinkage long sys_utime(char * filename, struct utimbuf * times); +asmlinkage long +sys32_truncate64 (unsigned int path, unsigned int len_lo, unsigned int len_hi) +{ + extern asmlinkage long sys_truncate (const char *path, unsigned long length); -struct utimbuf32 { - __kernel_time_t32 actime, modtime; -}; + return sys_truncate((const char *) A(path), ((unsigned long) len_hi << 32) | len_lo); +} asmlinkage long -sys32_utime(char * filename, struct utimbuf32 *times) +sys32_ftruncate64 (int fd, unsigned int len_lo, unsigned int len_hi) { - struct utimbuf t; - mm_segment_t old_fs; - int ret; - char *filenam; + extern asmlinkage long sys_ftruncate (int fd, unsigned long length); - if (!times) - return sys_utime(filename, NULL); - if (get_user (t.actime, ×->actime) || - __get_user (t.modtime, ×->modtime)) - return -EFAULT; - filenam = getname32 (filename); - ret = PTR_ERR(filenam); - if (!IS_ERR(filenam)) { - old_fs = get_fs(); - set_fs (KERNEL_DS); - ret = sys_utime(filenam, &t); - set_fs (old_fs); - putname (filenam); - } - return ret; + return sys_ftruncate(fd, ((unsigned long) len_hi << 32) | len_lo); } -/* - * Ooo, nasty. We need here to frob 32-bit unsigned longs to - * 64-bit unsigned longs. - */ - -static inline int -get_fd_set32(unsigned long n, unsigned long *fdset, u32 *ufdset) +static int +putstat64 (struct stat64 *ubuf, struct stat *kbuf) { - if (ufdset) { - unsigned long odd; + int err; - if (verify_area(VERIFY_WRITE, ufdset, n*sizeof(u32))) - return -EFAULT; + if (clear_user(ubuf, sizeof(*ubuf))) + return 1; - odd = n & 1UL; - n &= ~1UL; - while (n) { - unsigned long h, l; - __get_user(l, ufdset); - __get_user(h, ufdset+1); - ufdset += 2; - *fdset++ = h << 32 | l; - n -= 2; - } - if (odd) - __get_user(*fdset, ufdset); - } else { - /* Tricky, must clear full unsigned long in the - * kernel fdset at the end, this makes sure that - * actually happens. - */ - memset(fdset, 0, ((n + 1) & ~1)*sizeof(u32)); - } - return 0; + err = __put_user(kbuf->st_dev, &ubuf->st_dev); + err |= __put_user(kbuf->st_ino, &ubuf->__st_ino); + err |= __put_user(kbuf->st_ino, &ubuf->st_ino_lo); + err |= __put_user(kbuf->st_ino >> 32, &ubuf->st_ino_hi); + err |= __put_user(kbuf->st_mode, &ubuf->st_mode); + err |= __put_user(kbuf->st_nlink, &ubuf->st_nlink); + err |= __put_user(kbuf->st_uid, &ubuf->st_uid); + err |= __put_user(kbuf->st_gid, &ubuf->st_gid); + err |= __put_user(kbuf->st_rdev, &ubuf->st_rdev); + err |= __put_user(kbuf->st_size, &ubuf->st_size_lo); + err |= __put_user((kbuf->st_size >> 32), &ubuf->st_size_hi); + err |= __put_user(kbuf->st_atime, &ubuf->st_atime); + err |= __put_user(kbuf->st_mtime, &ubuf->st_mtime); + err |= __put_user(kbuf->st_ctime, &ubuf->st_ctime); + err |= __put_user(kbuf->st_blksize, &ubuf->st_blksize); + err |= __put_user(kbuf->st_blocks, &ubuf->st_blocks); + return err; } -static inline void -set_fd_set32(unsigned long n, u32 *ufdset, unsigned long *fdset) +asmlinkage long +sys32_stat64 (char *filename, struct stat64 *statbuf) { - unsigned long odd; - - if (!ufdset) + mm_segment_t old_fs = get_fs(); + struct stat s; + long ret; + + set_fs(KERNEL_DS); + ret = sys_newstat(filename, &s); + set_fs(old_fs); + if (putstat64(statbuf, &s)) + return -EFAULT; + return ret; +} + +asmlinkage long +sys32_lstat64 (char *filename, struct stat64 *statbuf) +{ + mm_segment_t old_fs = get_fs(); + struct stat s; + long ret; + + set_fs(KERNEL_DS); + ret = sys_newlstat(filename, &s); + set_fs(old_fs); + if (putstat64(statbuf, &s)) + return -EFAULT; + return ret; +} + +asmlinkage long +sys32_fstat64 (unsigned int fd, struct stat64 *statbuf) +{ + mm_segment_t old_fs = get_fs(); + struct stat s; + long ret; + + set_fs(KERNEL_DS); + ret = sys_newfstat(fd, &s); + set_fs(old_fs); + if (putstat64(statbuf, &s)) + return -EFAULT; + return ret; +} + +asmlinkage long +sys32_sigpending (unsigned int *set) +{ + return do_sigpending(set, sizeof(*set)); +} + +struct sysinfo32 { + s32 uptime; + u32 loads[3]; + u32 totalram; + u32 freeram; + u32 sharedram; + u32 bufferram; + u32 totalswap; + u32 freeswap; + unsigned short procs; + char _f[22]; +}; + +asmlinkage long +sys32_sysinfo (struct sysinfo32 *info) +{ + extern asmlinkage long sys_sysinfo (struct sysinfo *); + mm_segment_t old_fs = get_fs(); + struct sysinfo s; + long ret, err; + + set_fs(KERNEL_DS); + ret = sys_sysinfo(&s); + set_fs(old_fs); + + if (!access_ok(VERIFY_WRITE, info, sizeof(*info))) + return -EFAULT; + + err = __put_user(s.uptime, &info->uptime); + err |= __put_user(s.loads[0], &info->loads[0]); + err |= __put_user(s.loads[1], &info->loads[1]); + err |= __put_user(s.loads[2], &info->loads[2]); + err |= __put_user(s.totalram, &info->totalram); + err |= __put_user(s.freeram, &info->freeram); + err |= __put_user(s.sharedram, &info->sharedram); + err |= __put_user(s.bufferram, &info->bufferram); + err |= __put_user(s.totalswap, &info->totalswap); + err |= __put_user(s.freeswap, &info->freeswap); + err |= __put_user(s.procs, &info->procs); + if (err) + return -EFAULT; + return ret; +} + +/* In order to reduce some races, while at the same time doing additional + * checking and hopefully speeding things up, we copy filenames to the + * kernel data space before using them.. + * + * POSIX.1 2.4: an empty pathname is invalid (ENOENT). + */ +static inline int +do_getname32 (const char *filename, char *page) +{ + int retval; + + /* 32bit pointer will be always far below TASK_SIZE :)) */ + retval = strncpy_from_user((char *)page, (char *)filename, PAGE_SIZE); + if (retval > 0) { + if (retval < PAGE_SIZE) + return 0; + return -ENAMETOOLONG; + } else if (!retval) + retval = -ENOENT; + return retval; +} + +static char * +getname32 (const char *filename) +{ + char *tmp, *result; + + result = ERR_PTR(-ENOMEM); + tmp = (char *)__get_free_page(GFP_KERNEL); + if (tmp) { + int retval = do_getname32(filename, tmp); + + result = tmp; + if (retval < 0) { + putname(tmp); + result = ERR_PTR(retval); + } + } + return result; +} + +struct dqblk32 { + __u32 dqb_bhardlimit; + __u32 dqb_bsoftlimit; + __u32 dqb_curblocks; + __u32 dqb_ihardlimit; + __u32 dqb_isoftlimit; + __u32 dqb_curinodes; + __kernel_time_t32 dqb_btime; + __kernel_time_t32 dqb_itime; +}; + +asmlinkage long +sys32_quotactl (int cmd, unsigned int special, int id, struct dqblk32 *addr) +{ + extern asmlinkage long sys_quotactl (int, const char *, int, caddr_t); + int cmds = cmd >> SUBCMDSHIFT; + mm_segment_t old_fs; + struct dqblk d; + char *spec; + long err; + + switch (cmds) { + case Q_GETQUOTA: + break; + case Q_SETQUOTA: + case Q_SETUSE: + case Q_SETQLIM: + if (copy_from_user (&d, addr, sizeof(struct dqblk32))) + return -EFAULT; + d.dqb_itime = ((struct dqblk32 *)&d)->dqb_itime; + d.dqb_btime = ((struct dqblk32 *)&d)->dqb_btime; + break; + default: + return sys_quotactl(cmd, (void *) A(special), id, (caddr_t) addr); + } + spec = getname32((void *) A(special)); + err = PTR_ERR(spec); + if (IS_ERR(spec)) + return err; + old_fs = get_fs (); + set_fs(KERNEL_DS); + err = sys_quotactl(cmd, (const char *)spec, id, (caddr_t)&d); + set_fs(old_fs); + putname(spec); + if (cmds == Q_GETQUOTA) { + __kernel_time_t b = d.dqb_btime, i = d.dqb_itime; + ((struct dqblk32 *)&d)->dqb_itime = i; + ((struct dqblk32 *)&d)->dqb_btime = b; + if (copy_to_user(addr, &d, sizeof(struct dqblk32))) + return -EFAULT; + } + return err; +} + +asmlinkage long +sys32_sched_rr_get_interval (pid_t pid, struct timespec32 *interval) +{ + extern asmlinkage long sys_sched_rr_get_interval (pid_t, struct timespec *); + mm_segment_t old_fs = get_fs(); + struct timespec t; + long ret; + + set_fs(KERNEL_DS); + ret = sys_sched_rr_get_interval(pid, &t); + set_fs(old_fs); + if (put_user (t.tv_sec, &interval->tv_sec) || put_user (t.tv_nsec, &interval->tv_nsec)) + return -EFAULT; + return ret; +} + +asmlinkage long +sys32_pread (unsigned int fd, void *buf, unsigned int count, u32 pos_lo, u32 pos_hi) +{ + extern asmlinkage long sys_pread (unsigned int, char *, size_t, loff_t); + return sys_pread(fd, buf, count, ((unsigned long) pos_hi << 32) | pos_lo); +} + +asmlinkage long +sys32_pwrite (unsigned int fd, void *buf, unsigned int count, u32 pos_lo, u32 pos_hi) +{ + extern asmlinkage long sys_pwrite (unsigned int, const char *, size_t, loff_t); + return sys_pwrite(fd, buf, count, ((unsigned long) pos_hi << 32) | pos_lo); +} + +asmlinkage long +sys32_sendfile (int out_fd, int in_fd, int *offset, unsigned int count) +{ + extern asmlinkage long sys_sendfile (int, int, off_t *, size_t); + mm_segment_t old_fs = get_fs(); + long ret; + off_t of; + + if (offset && get_user(of, offset)) + return -EFAULT; + + set_fs(KERNEL_DS); + ret = sys_sendfile(out_fd, in_fd, offset ? &of : NULL, count); + set_fs(old_fs); + + if (!ret && offset && put_user(of, offset)) + return -EFAULT; + + return ret; +} + +asmlinkage long +sys32_personality (unsigned int personality) +{ + extern asmlinkage long sys_personality (unsigned long); + long ret; + + if (current->personality == PER_LINUX32 && personality == PER_LINUX) + personality = PER_LINUX32; + ret = sys_personality(personality); + if (ret == PER_LINUX32) + ret = PER_LINUX; + return ret; +} + +#ifdef NOTYET /* UNTESTED FOR IA64 FROM HERE DOWN */ + +/* + * Ooo, nasty. We need here to frob 32-bit unsigned longs to + * 64-bit unsigned longs. + */ + +static inline int +get_fd_set32(unsigned long n, unsigned long *fdset, u32 *ufdset) +{ + if (ufdset) { + unsigned long odd; + + if (verify_area(VERIFY_WRITE, ufdset, n*sizeof(u32))) + return -EFAULT; + + odd = n & 1UL; + n &= ~1UL; + while (n) { + unsigned long h, l; + __get_user(l, ufdset); + __get_user(h, ufdset+1); + ufdset += 2; + *fdset++ = h << 32 | l; + n -= 2; + } + if (odd) + __get_user(*fdset, ufdset); + } else { + /* Tricky, must clear full unsigned long in the + * kernel fdset at the end, this makes sure that + * actually happens. + */ + memset(fdset, 0, ((n + 1) & ~1)*sizeof(u32)); + } + return 0; +} + +static inline void +set_fd_set32(unsigned long n, u32 *ufdset, unsigned long *fdset) +{ + unsigned long odd; + + if (!ufdset) return; odd = n & 1UL; @@ -3014,20 +3438,11 @@ __put_user(*fdset, ufdset); } -extern asmlinkage long sys_sysfs(int option, unsigned long arg1, - unsigned long arg2); - -asmlinkage long -sys32_sysfs(int option, u32 arg1, u32 arg2) -{ - return sys_sysfs(option, arg1, arg2); -} - struct ncp_mount_data32 { int version; unsigned int ncp_fd; __kernel_uid_t32 mounted_uid; - __kernel_pid_t32 wdog_pid; + int wdog_pid; unsigned char mounted_vol[NCP_VOLNAME_LEN + 1]; unsigned int time_out; unsigned int retry_count; @@ -3174,269 +3589,7 @@ } } -struct sysinfo32 { - s32 uptime; - u32 loads[3]; - u32 totalram; - u32 freeram; - u32 sharedram; - u32 bufferram; - u32 totalswap; - u32 freeswap; - unsigned short procs; - char _f[22]; -}; - -extern asmlinkage long sys_sysinfo(struct sysinfo *info); - -asmlinkage long -sys32_sysinfo(struct sysinfo32 *info) -{ - struct sysinfo s; - int ret, err; - mm_segment_t old_fs = get_fs (); - - set_fs (KERNEL_DS); - ret = sys_sysinfo(&s); - set_fs (old_fs); - err = put_user (s.uptime, &info->uptime); - err |= __put_user (s.loads[0], &info->loads[0]); - err |= __put_user (s.loads[1], &info->loads[1]); - err |= __put_user (s.loads[2], &info->loads[2]); - err |= __put_user (s.totalram, &info->totalram); - err |= __put_user (s.freeram, &info->freeram); - err |= __put_user (s.sharedram, &info->sharedram); - err |= __put_user (s.bufferram, &info->bufferram); - err |= __put_user (s.totalswap, &info->totalswap); - err |= __put_user (s.freeswap, &info->freeswap); - err |= __put_user (s.procs, &info->procs); - if (err) - return -EFAULT; - return ret; -} - -extern asmlinkage long sys_sched_rr_get_interval(pid_t pid, - struct timespec *interval); - -asmlinkage long -sys32_sched_rr_get_interval(__kernel_pid_t32 pid, struct timespec32 *interval) -{ - struct timespec t; - int ret; - mm_segment_t old_fs = get_fs (); - - set_fs (KERNEL_DS); - ret = sys_sched_rr_get_interval(pid, &t); - set_fs (old_fs); - if (put_user (t.tv_sec, &interval->tv_sec) || - __put_user (t.tv_nsec, &interval->tv_nsec)) - return -EFAULT; - return ret; -} - -extern asmlinkage long sys_sigprocmask(int how, old_sigset_t *set, - old_sigset_t *oset); - -asmlinkage long -sys32_sigprocmask(int how, old_sigset_t32 *set, old_sigset_t32 *oset) -{ - old_sigset_t s; - int ret; - mm_segment_t old_fs = get_fs(); - - if (set && get_user (s, set)) return -EFAULT; - set_fs (KERNEL_DS); - ret = sys_sigprocmask(how, set ? &s : NULL, oset ? &s : NULL); - set_fs (old_fs); - if (ret) return ret; - if (oset && put_user (s, oset)) return -EFAULT; - return 0; -} - -extern asmlinkage long sys_sigpending(old_sigset_t *set); - -asmlinkage long -sys32_sigpending(old_sigset_t32 *set) -{ - old_sigset_t s; - int ret; - mm_segment_t old_fs = get_fs(); - - set_fs (KERNEL_DS); - ret = sys_sigpending(&s); - set_fs (old_fs); - if (put_user (s, set)) return -EFAULT; - return ret; -} - -extern asmlinkage long sys_rt_sigpending(sigset_t *set, size_t sigsetsize); - -asmlinkage long -sys32_rt_sigpending(sigset_t32 *set, __kernel_size_t32 sigsetsize) -{ - sigset_t s; - sigset_t32 s32; - int ret; - mm_segment_t old_fs = get_fs(); - - set_fs (KERNEL_DS); - ret = sys_rt_sigpending(&s, sigsetsize); - set_fs (old_fs); - if (!ret) { - switch (_NSIG_WORDS) { - case 4: s32.sig[7] = (s.sig[3] >> 32); s32.sig[6] = s.sig[3]; - case 3: s32.sig[5] = (s.sig[2] >> 32); s32.sig[4] = s.sig[2]; - case 2: s32.sig[3] = (s.sig[1] >> 32); s32.sig[2] = s.sig[1]; - case 1: s32.sig[1] = (s.sig[0] >> 32); s32.sig[0] = s.sig[0]; - } - if (copy_to_user (set, &s32, sizeof(sigset_t32))) - return -EFAULT; - } - return ret; -} - -siginfo_t32 * -siginfo64to32(siginfo_t32 *d, siginfo_t *s) -{ - memset(d, 0, sizeof(siginfo_t32)); - d->si_signo = s->si_signo; - d->si_errno = s->si_errno; - d->si_code = s->si_code; - if (s->si_signo >= SIGRTMIN) { - d->si_pid = s->si_pid; - d->si_uid = s->si_uid; - /* XXX: Ouch, how to find this out??? */ - d->si_int = s->si_int; - } else switch (s->si_signo) { - /* XXX: What about POSIX1.b timers */ - case SIGCHLD: - d->si_pid = s->si_pid; - d->si_status = s->si_status; - d->si_utime = s->si_utime; - d->si_stime = s->si_stime; - break; - case SIGSEGV: - case SIGBUS: - case SIGFPE: - case SIGILL: - d->si_addr = (long)(s->si_addr); - /* XXX: Do we need to translate this from ia64 to ia32 traps? */ - d->si_trapno = s->si_trapno; - break; - case SIGPOLL: - d->si_band = s->si_band; - d->si_fd = s->si_fd; - break; - default: - d->si_pid = s->si_pid; - d->si_uid = s->si_uid; - break; - } - return d; -} - -siginfo_t * -siginfo32to64(siginfo_t *d, siginfo_t32 *s) -{ - d->si_signo = s->si_signo; - d->si_errno = s->si_errno; - d->si_code = s->si_code; - if (s->si_signo >= SIGRTMIN) { - d->si_pid = s->si_pid; - d->si_uid = s->si_uid; - /* XXX: Ouch, how to find this out??? */ - d->si_int = s->si_int; - } else switch (s->si_signo) { - /* XXX: What about POSIX1.b timers */ - case SIGCHLD: - d->si_pid = s->si_pid; - d->si_status = s->si_status; - d->si_utime = s->si_utime; - d->si_stime = s->si_stime; - break; - case SIGSEGV: - case SIGBUS: - case SIGFPE: - case SIGILL: - d->si_addr = (void *)A(s->si_addr); - /* XXX: Do we need to translate this from ia32 to ia64 traps? */ - d->si_trapno = s->si_trapno; - break; - case SIGPOLL: - d->si_band = s->si_band; - d->si_fd = s->si_fd; - break; - default: - d->si_pid = s->si_pid; - d->si_uid = s->si_uid; - break; - } - return d; -} - -extern asmlinkage long -sys_rt_sigtimedwait(const sigset_t *uthese, siginfo_t *uinfo, - const struct timespec *uts, size_t sigsetsize); - -asmlinkage long -sys32_rt_sigtimedwait(sigset_t32 *uthese, siginfo_t32 *uinfo, - struct timespec32 *uts, __kernel_size_t32 sigsetsize) -{ - sigset_t s; - sigset_t32 s32; - struct timespec t; - int ret; - mm_segment_t old_fs = get_fs(); - siginfo_t info; - siginfo_t32 info32; - - if (copy_from_user (&s32, uthese, sizeof(sigset_t32))) - return -EFAULT; - switch (_NSIG_WORDS) { - case 4: s.sig[3] = s32.sig[6] | (((long)s32.sig[7]) << 32); - case 3: s.sig[2] = s32.sig[4] | (((long)s32.sig[5]) << 32); - case 2: s.sig[1] = s32.sig[2] | (((long)s32.sig[3]) << 32); - case 1: s.sig[0] = s32.sig[0] | (((long)s32.sig[1]) << 32); - } - if (uts) { - ret = get_user (t.tv_sec, &uts->tv_sec); - ret |= __get_user (t.tv_nsec, &uts->tv_nsec); - if (ret) - return -EFAULT; - } - set_fs (KERNEL_DS); - ret = sys_rt_sigtimedwait(&s, &info, &t, sigsetsize); - set_fs (old_fs); - if (ret >= 0 && uinfo) { - if (copy_to_user (uinfo, siginfo64to32(&info32, &info), - sizeof(siginfo_t32))) - return -EFAULT; - } - return ret; -} - -extern asmlinkage long -sys_rt_sigqueueinfo(int pid, int sig, siginfo_t *uinfo); - -asmlinkage long -sys32_rt_sigqueueinfo(int pid, int sig, siginfo_t32 *uinfo) -{ - siginfo_t info; - siginfo_t32 info32; - int ret; - mm_segment_t old_fs = get_fs(); - - if (copy_from_user (&info32, uinfo, sizeof(siginfo_t32))) - return -EFAULT; - /* XXX: Is this correct? */ - siginfo32to64(&info, &info32); - set_fs (KERNEL_DS); - ret = sys_rt_sigqueueinfo(pid, sig, &info); - set_fs (old_fs); - return ret; -} - -extern asmlinkage long sys_setreuid(uid_t ruid, uid_t euid); +extern asmlinkage long sys_setreuid(uid_t ruid, uid_t euid); asmlinkage long sys32_setreuid(__kernel_uid_t32 ruid, __kernel_uid_t32 euid) { @@ -3461,24 +3614,6 @@ return sys_setresuid(sruid, seuid, ssuid); } -extern asmlinkage long sys_getresuid(uid_t *ruid, uid_t *euid, uid_t *suid); - -asmlinkage long -sys32_getresuid(__kernel_uid_t32 *ruid, __kernel_uid_t32 *euid, - __kernel_uid_t32 *suid) -{ - uid_t a, b, c; - int ret; - mm_segment_t old_fs = get_fs(); - - set_fs (KERNEL_DS); - ret = sys_getresuid(&a, &b, &c); - set_fs (old_fs); - if (put_user (a, ruid) || put_user (b, euid) || put_user (c, suid)) - return -EFAULT; - return ret; -} - extern asmlinkage long sys_setregid(gid_t rgid, gid_t egid); asmlinkage long @@ -3505,46 +3640,6 @@ return sys_setresgid(srgid, segid, ssgid); } -extern asmlinkage long sys_getgroups(int gidsetsize, gid_t *grouplist); - -asmlinkage long -sys32_getgroups(int gidsetsize, __kernel_gid_t32 *grouplist) -{ - gid_t gl[NGROUPS]; - int ret, i; - mm_segment_t old_fs = get_fs (); - - set_fs (KERNEL_DS); - ret = sys_getgroups(gidsetsize, gl); - set_fs (old_fs); - if (gidsetsize && ret > 0 && ret <= NGROUPS) - for (i = 0; i < ret; i++, grouplist++) - if (__put_user (gl[i], grouplist)) - return -EFAULT; - return ret; -} - -extern asmlinkage long sys_setgroups(int gidsetsize, gid_t *grouplist); - -asmlinkage long -sys32_setgroups(int gidsetsize, __kernel_gid_t32 *grouplist) -{ - gid_t gl[NGROUPS]; - int ret, i; - mm_segment_t old_fs = get_fs (); - - if ((unsigned) gidsetsize > NGROUPS) - return -EINVAL; - for (i = 0; i < gidsetsize; i++, grouplist++) - if (__get_user (gl[i], grouplist)) - return -EFAULT; - set_fs (KERNEL_DS); - ret = sys_setgroups(gidsetsize, gl); - set_fs (old_fs); - return ret; -} - - /* XXX These as well... */ extern __inline__ struct socket * socki_lookup(struct inode *inode) @@ -3946,601 +4041,165 @@ kcmsg32->cmsg_len = clen32; ucmsg = (struct cmsghdr *) (((char *)ucmsg) + - CMSG_ALIGN(clen64)); - wp = (((char *)kcmsg32) + CMSG32_ALIGN(clen32)); - } - - /* Copy back fixed up data, and adjust pointers. */ - bufsz = (wp - workbuf); - copy_to_user((void *)orig_cmsg_uptr, workbuf, bufsz); - - kmsg->msg_control = (struct cmsghdr *) - (((char *)orig_cmsg_uptr) + bufsz); - kmsg->msg_controllen = space_avail - bufsz; - - kfree(workbuf); - return; - -fail: - /* If we leave the 64-bit format CMSG chunks in there, - * the application could get confused and crash. So to - * ensure greater recovery, we report no CMSGs. - */ - kmsg->msg_controllen += bufsz; - kmsg->msg_control = (void *) orig_cmsg_uptr; -} - -asmlinkage long -sys32_sendmsg(int fd, struct msghdr32 *user_msg, unsigned user_flags) -{ - struct socket *sock; - char address[MAX_SOCK_ADDR]; - struct iovec iov[UIO_FASTIOV]; - unsigned char ctl[sizeof(struct cmsghdr) + 20]; - unsigned char *ctl_buf = ctl; - struct msghdr kern_msg; - int err, total_len; - - if(msghdr_from_user32_to_kern(&kern_msg, user_msg)) - return -EFAULT; - if(kern_msg.msg_iovlen > UIO_MAXIOV) - return -EINVAL; - err = verify_iovec32(&kern_msg, iov, address, VERIFY_READ); - if (err < 0) - goto out; - total_len = err; - - if(kern_msg.msg_controllen) { - err = cmsghdr_from_user32_to_kern(&kern_msg, ctl, sizeof(ctl)); - if(err) - goto out_freeiov; - ctl_buf = kern_msg.msg_control; - } - kern_msg.msg_flags = user_flags; - - sock = sockfd_lookup(fd, &err); - if (sock != NULL) { - if (sock->file->f_flags & O_NONBLOCK) - kern_msg.msg_flags |= MSG_DONTWAIT; - err = sock_sendmsg(sock, &kern_msg, total_len); - sockfd_put(sock); - } - - /* N.B. Use kfree here, as kern_msg.msg_controllen might change? */ - if(ctl_buf != ctl) - kfree(ctl_buf); -out_freeiov: - if(kern_msg.msg_iov != iov) - kfree(kern_msg.msg_iov); -out: - return err; -} - -asmlinkage long -sys32_recvmsg(int fd, struct msghdr32 *user_msg, unsigned int user_flags) -{ - struct iovec iovstack[UIO_FASTIOV]; - struct msghdr kern_msg; - char addr[MAX_SOCK_ADDR]; - struct socket *sock; - struct iovec *iov = iovstack; - struct sockaddr *uaddr; - int *uaddr_len; - unsigned long cmsg_ptr; - int err, total_len, len = 0; - - if(msghdr_from_user32_to_kern(&kern_msg, user_msg)) - return -EFAULT; - if(kern_msg.msg_iovlen > UIO_MAXIOV) - return -EINVAL; - - uaddr = kern_msg.msg_name; - uaddr_len = &user_msg->msg_namelen; - err = verify_iovec32(&kern_msg, iov, addr, VERIFY_WRITE); - if (err < 0) - goto out; - total_len = err; - - cmsg_ptr = (unsigned long) kern_msg.msg_control; - kern_msg.msg_flags = 0; - - sock = sockfd_lookup(fd, &err); - if (sock != NULL) { - struct scm_cookie scm; - - if (sock->file->f_flags & O_NONBLOCK) - user_flags |= MSG_DONTWAIT; - memset(&scm, 0, sizeof(scm)); - lock_kernel(); - err = sock->ops->recvmsg(sock, &kern_msg, total_len, - user_flags, &scm); - if(err >= 0) { - len = err; - if(!kern_msg.msg_control) { - if(sock->passcred || scm.fp) - kern_msg.msg_flags |= MSG_CTRUNC; - if(scm.fp) - __scm_destroy(&scm); - } else { - /* If recvmsg processing itself placed some - * control messages into user space, it's is - * using 64-bit CMSG processing, so we need - * to fix it up before we tack on more stuff. - */ - if((unsigned long) kern_msg.msg_control - != cmsg_ptr) - cmsg32_recvmsg_fixup(&kern_msg, - cmsg_ptr); - - /* Wheee... */ - if(sock->passcred) - put_cmsg32(&kern_msg, - SOL_SOCKET, SCM_CREDENTIALS, - sizeof(scm.creds), - &scm.creds); - if(scm.fp != NULL) - scm_detach_fds32(&kern_msg, &scm); - } - } - unlock_kernel(); - sockfd_put(sock); - } - - if(uaddr != NULL && err >= 0) - err = move_addr_to_user(addr, kern_msg.msg_namelen, uaddr, - uaddr_len); - if(cmsg_ptr != 0 && err >= 0) { - unsigned long ucmsg_ptr = ((unsigned long)kern_msg.msg_control); - __kernel_size_t32 uclen = (__kernel_size_t32) (ucmsg_ptr - - cmsg_ptr); - err |= __put_user(uclen, &user_msg->msg_controllen); - } - if(err >= 0) - err = __put_user(kern_msg.msg_flags, &user_msg->msg_flags); - if(kern_msg.msg_iov != iov) - kfree(kern_msg.msg_iov); -out: - if(err < 0) - return err; - return len; -} - -extern void check_pending(int signum); - -#ifdef CONFIG_MODULES - -extern asmlinkage unsigned long sys_create_module(const char *name_user, - size_t size); - -asmlinkage unsigned long -sys32_create_module(const char *name_user, __kernel_size_t32 size) -{ - return sys_create_module(name_user, (size_t)size); -} - -extern asmlinkage long sys_init_module(const char *name_user, - struct module *mod_user); - -/* Hey, when you're trying to init module, take time and prepare us a nice 64bit - * module structure, even if from 32bit modutils... Why to pollute kernel... :)) - */ -asmlinkage long -sys32_init_module(const char *name_user, struct module *mod_user) -{ - return sys_init_module(name_user, mod_user); -} - -extern asmlinkage long sys_delete_module(const char *name_user); - -asmlinkage long -sys32_delete_module(const char *name_user) -{ - return sys_delete_module(name_user); -} - -struct module_info32 { - u32 addr; - u32 size; - u32 flags; - s32 usecount; -}; - -/* Query various bits about modules. */ - -static inline long -get_mod_name(const char *user_name, char **buf) -{ - unsigned long page; - long retval; - - if ((unsigned long)user_name >= TASK_SIZE - && !segment_eq(get_fs (), KERNEL_DS)) - return -EFAULT; - - page = __get_free_page(GFP_KERNEL); - if (!page) - return -ENOMEM; - - retval = strncpy_from_user((char *)page, user_name, PAGE_SIZE); - if (retval > 0) { - if (retval < PAGE_SIZE) { - *buf = (char *)page; - return retval; - } - retval = -ENAMETOOLONG; - } else if (!retval) - retval = -EINVAL; - - free_page(page); - return retval; -} - -static inline void -put_mod_name(char *buf) -{ - free_page((unsigned long)buf); -} - -static __inline__ struct module * -find_module(const char *name) -{ - struct module *mod; - - for (mod = module_list; mod ; mod = mod->next) { - if (mod->flags & MOD_DELETED) - continue; - if (!strcmp(mod->name, name)) - break; - } - - return mod; -} - -static int -qm_modules(char *buf, size_t bufsize, __kernel_size_t32 *ret) -{ - struct module *mod; - size_t nmod, space, len; - - nmod = space = 0; - - for (mod = module_list; mod->next != NULL; mod = mod->next, ++nmod) { - len = strlen(mod->name)+1; - if (len > bufsize) - goto calc_space_needed; - if (copy_to_user(buf, mod->name, len)) - return -EFAULT; - buf += len; - bufsize -= len; - space += len; - } - - if (put_user(nmod, ret)) - return -EFAULT; - else - return 0; - -calc_space_needed: - space += len; - while ((mod = mod->next)->next != NULL) - space += strlen(mod->name)+1; - - if (put_user(space, ret)) - return -EFAULT; - else - return -ENOSPC; -} - -static int -qm_deps(struct module *mod, char *buf, size_t bufsize, __kernel_size_t32 *ret) -{ - size_t i, space, len; - - if (mod->next == NULL) - return -EINVAL; - if ((mod->flags & (MOD_RUNNING | MOD_DELETED)) != MOD_RUNNING) - if (put_user(0, ret)) - return -EFAULT; - else - return 0; - - space = 0; - for (i = 0; i < mod->ndeps; ++i) { - const char *dep_name = mod->deps[i].dep->name; - - len = strlen(dep_name)+1; - if (len > bufsize) - goto calc_space_needed; - if (copy_to_user(buf, dep_name, len)) - return -EFAULT; - buf += len; - bufsize -= len; - space += len; - } - - if (put_user(i, ret)) - return -EFAULT; - else - return 0; - -calc_space_needed: - space += len; - while (++i < mod->ndeps) - space += strlen(mod->deps[i].dep->name)+1; - - if (put_user(space, ret)) - return -EFAULT; - else - return -ENOSPC; -} - -static int -qm_refs(struct module *mod, char *buf, size_t bufsize, __kernel_size_t32 *ret) -{ - size_t nrefs, space, len; - struct module_ref *ref; - - if (mod->next == NULL) - return -EINVAL; - if ((mod->flags & (MOD_RUNNING | MOD_DELETED)) != MOD_RUNNING) - if (put_user(0, ret)) - return -EFAULT; - else - return 0; - - space = 0; - for (nrefs = 0, ref = mod->refs; ref ; ++nrefs, ref = ref->next_ref) { - const char *ref_name = ref->ref->name; - - len = strlen(ref_name)+1; - if (len > bufsize) - goto calc_space_needed; - if (copy_to_user(buf, ref_name, len)) - return -EFAULT; - buf += len; - bufsize -= len; - space += len; - } - - if (put_user(nrefs, ret)) - return -EFAULT; - else - return 0; - -calc_space_needed: - space += len; - while ((ref = ref->next_ref) != NULL) - space += strlen(ref->ref->name)+1; - - if (put_user(space, ret)) - return -EFAULT; - else - return -ENOSPC; -} - -static inline int -qm_symbols(struct module *mod, char *buf, size_t bufsize, - __kernel_size_t32 *ret) -{ - size_t i, space, len; - struct module_symbol *s; - char *strings; - unsigned *vals; - - if ((mod->flags & (MOD_RUNNING | MOD_DELETED)) != MOD_RUNNING) - if (put_user(0, ret)) - return -EFAULT; - else - return 0; - - space = mod->nsyms * 2*sizeof(u32); - - i = len = 0; - s = mod->syms; - - if (space > bufsize) - goto calc_space_needed; - - if (!access_ok(VERIFY_WRITE, buf, space)) - return -EFAULT; - - bufsize -= space; - vals = (unsigned *)buf; - strings = buf+space; - - for (; i < mod->nsyms ; ++i, ++s, vals += 2) { - len = strlen(s->name)+1; - if (len > bufsize) - goto calc_space_needed; - - if (copy_to_user(strings, s->name, len) - || __put_user(s->value, vals+0) - || __put_user(space, vals+1)) - return -EFAULT; - - strings += len; - bufsize -= len; - space += len; - } - - if (put_user(i, ret)) - return -EFAULT; - else - return 0; - -calc_space_needed: - for (; i < mod->nsyms; ++i, ++s) - space += strlen(s->name)+1; - - if (put_user(space, ret)) - return -EFAULT; - else - return -ENOSPC; -} - -static inline int -qm_info(struct module *mod, char *buf, size_t bufsize, __kernel_size_t32 *ret) -{ - int error = 0; - - if (mod->next == NULL) - return -EINVAL; + CMSG_ALIGN(clen64)); + wp = (((char *)kcmsg32) + CMSG32_ALIGN(clen32)); + } - if (sizeof(struct module_info32) <= bufsize) { - struct module_info32 info; - info.addr = (unsigned long)mod; - info.size = mod->size; - info.flags = mod->flags; - info.usecount = - ((mod_member_present(mod, can_unload) - && mod->can_unload) - ? -1 : atomic_read(&mod->uc.usecount)); + /* Copy back fixed up data, and adjust pointers. */ + bufsz = (wp - workbuf); + copy_to_user((void *)orig_cmsg_uptr, workbuf, bufsz); - if (copy_to_user(buf, &info, sizeof(struct module_info32))) - return -EFAULT; - } else - error = -ENOSPC; + kmsg->msg_control = (struct cmsghdr *) + (((char *)orig_cmsg_uptr) + bufsz); + kmsg->msg_controllen = space_avail - bufsz; - if (put_user(sizeof(struct module_info32), ret)) - return -EFAULT; + kfree(workbuf); + return; - return error; +fail: + /* If we leave the 64-bit format CMSG chunks in there, + * the application could get confused and crash. So to + * ensure greater recovery, we report no CMSGs. + */ + kmsg->msg_controllen += bufsz; + kmsg->msg_control = (void *) orig_cmsg_uptr; } asmlinkage long -sys32_query_module(char *name_user, int which, char *buf, - __kernel_size_t32 bufsize, u32 ret) +sys32_sendmsg(int fd, struct msghdr32 *user_msg, unsigned user_flags) { - struct module *mod; - int err; + struct socket *sock; + char address[MAX_SOCK_ADDR]; + struct iovec iov[UIO_FASTIOV]; + unsigned char ctl[sizeof(struct cmsghdr) + 20]; + unsigned char *ctl_buf = ctl; + struct msghdr kern_msg; + int err, total_len; - lock_kernel(); - if (name_user == 0) { - /* This finds "kernel_module" which is not exported. */ - for(mod = module_list; mod->next != NULL; mod = mod->next) - ; - } else { - long namelen; - char *name; + if(msghdr_from_user32_to_kern(&kern_msg, user_msg)) + return -EFAULT; + if(kern_msg.msg_iovlen > UIO_MAXIOV) + return -EINVAL; + err = verify_iovec32(&kern_msg, iov, address, VERIFY_READ); + if (err < 0) + goto out; + total_len = err; - if ((namelen = get_mod_name(name_user, &name)) < 0) { - err = namelen; - goto out; - } - err = -ENOENT; - if (namelen == 0) { - /* This finds "kernel_module" which is not exported. */ - for(mod = module_list; - mod->next != NULL; - mod = mod->next) ; - } else if ((mod = find_module(name)) == NULL) { - put_mod_name(name); - goto out; - } - put_mod_name(name); + if(kern_msg.msg_controllen) { + err = cmsghdr_from_user32_to_kern(&kern_msg, ctl, sizeof(ctl)); + if(err) + goto out_freeiov; + ctl_buf = kern_msg.msg_control; } + kern_msg.msg_flags = user_flags; - switch (which) - { - case 0: - err = 0; - break; - case QM_MODULES: - err = qm_modules(buf, bufsize, (__kernel_size_t32 *)AA(ret)); - break; - case QM_DEPS: - err = qm_deps(mod, buf, bufsize, (__kernel_size_t32 *)AA(ret)); - break; - case QM_REFS: - err = qm_refs(mod, buf, bufsize, (__kernel_size_t32 *)AA(ret)); - break; - case QM_SYMBOLS: - err = qm_symbols(mod, buf, bufsize, - (__kernel_size_t32 *)AA(ret)); - break; - case QM_INFO: - err = qm_info(mod, buf, bufsize, (__kernel_size_t32 *)AA(ret)); - break; - default: - err = -EINVAL; - break; + sock = sockfd_lookup(fd, &err); + if (sock != NULL) { + if (sock->file->f_flags & O_NONBLOCK) + kern_msg.msg_flags |= MSG_DONTWAIT; + err = sock_sendmsg(sock, &kern_msg, total_len); + sockfd_put(sock); } + + /* N.B. Use kfree here, as kern_msg.msg_controllen might change? */ + if(ctl_buf != ctl) + kfree(ctl_buf); +out_freeiov: + if(kern_msg.msg_iov != iov) + kfree(kern_msg.msg_iov); out: - unlock_kernel(); return err; } -struct kernel_sym32 { - u32 value; - char name[60]; -}; - -extern asmlinkage long sys_get_kernel_syms(struct kernel_sym *table); - asmlinkage long -sys32_get_kernel_syms(struct kernel_sym32 *table) +sys32_recvmsg(int fd, struct msghdr32 *user_msg, unsigned int user_flags) { - int len, i; - struct kernel_sym *tbl; - mm_segment_t old_fs; - - len = sys_get_kernel_syms(NULL); - if (!table) return len; - tbl = kmalloc (len * sizeof (struct kernel_sym), GFP_KERNEL); - if (!tbl) return -ENOMEM; - old_fs = get_fs(); - set_fs (KERNEL_DS); - sys_get_kernel_syms(tbl); - set_fs (old_fs); - for (i = 0; i < len; i++, table += sizeof (struct kernel_sym32)) { - if (put_user (tbl[i].value, &table->value) || - copy_to_user (table->name, tbl[i].name, 60)) - break; - } - kfree (tbl); - return i; -} + struct iovec iovstack[UIO_FASTIOV]; + struct msghdr kern_msg; + char addr[MAX_SOCK_ADDR]; + struct socket *sock; + struct iovec *iov = iovstack; + struct sockaddr *uaddr; + int *uaddr_len; + unsigned long cmsg_ptr; + int err, total_len, len = 0; -#else /* CONFIG_MODULES */ + if(msghdr_from_user32_to_kern(&kern_msg, user_msg)) + return -EFAULT; + if(kern_msg.msg_iovlen > UIO_MAXIOV) + return -EINVAL; -asmlinkage unsigned long -sys32_create_module(const char *name_user, size_t size) -{ - return -ENOSYS; -} + uaddr = kern_msg.msg_name; + uaddr_len = &user_msg->msg_namelen; + err = verify_iovec32(&kern_msg, iov, addr, VERIFY_WRITE); + if (err < 0) + goto out; + total_len = err; -asmlinkage long -sys32_init_module(const char *name_user, struct module *mod_user) -{ - return -ENOSYS; -} + cmsg_ptr = (unsigned long) kern_msg.msg_control; + kern_msg.msg_flags = 0; -asmlinkage long -sys32_delete_module(const char *name_user) -{ - return -ENOSYS; -} + sock = sockfd_lookup(fd, &err); + if (sock != NULL) { + struct scm_cookie scm; -asmlinkage long -sys32_query_module(const char *name_user, int which, char *buf, size_t bufsize, - size_t *ret) -{ - /* Let the program know about the new interface. Not that - it'll do them much good. */ - if (which == 0) - return 0; + if (sock->file->f_flags & O_NONBLOCK) + user_flags |= MSG_DONTWAIT; + memset(&scm, 0, sizeof(scm)); + lock_kernel(); + err = sock->ops->recvmsg(sock, &kern_msg, total_len, + user_flags, &scm); + if(err >= 0) { + len = err; + if(!kern_msg.msg_control) { + if(sock->passcred || scm.fp) + kern_msg.msg_flags |= MSG_CTRUNC; + if(scm.fp) + __scm_destroy(&scm); + } else { + /* If recvmsg processing itself placed some + * control messages into user space, it's is + * using 64-bit CMSG processing, so we need + * to fix it up before we tack on more stuff. + */ + if((unsigned long) kern_msg.msg_control + != cmsg_ptr) + cmsg32_recvmsg_fixup(&kern_msg, + cmsg_ptr); - return -ENOSYS; -} + /* Wheee... */ + if(sock->passcred) + put_cmsg32(&kern_msg, + SOL_SOCKET, SCM_CREDENTIALS, + sizeof(scm.creds), + &scm.creds); + if(scm.fp != NULL) + scm_detach_fds32(&kern_msg, &scm); + } + } + unlock_kernel(); + sockfd_put(sock); + } -asmlinkage long -sys32_get_kernel_syms(struct kernel_sym *table) -{ - return -ENOSYS; + if(uaddr != NULL && err >= 0) + err = move_addr_to_user(addr, kern_msg.msg_namelen, uaddr, + uaddr_len); + if(cmsg_ptr != 0 && err >= 0) { + unsigned long ucmsg_ptr = ((unsigned long)kern_msg.msg_control); + __kernel_size_t32 uclen = (__kernel_size_t32) (ucmsg_ptr + - cmsg_ptr); + err |= __put_user(uclen, &user_msg->msg_controllen); + } + if(err >= 0) + err = __put_user(kern_msg.msg_flags, &user_msg->msg_flags); + if(kern_msg.msg_iov != iov) + kfree(kern_msg.msg_iov); +out: + if(err < 0) + return err; + return len; } -#endif /* CONFIG_MODULES */ - /* Stuff for NFS server syscalls... */ struct nfsctl_svc32 { u16 svc32_port; @@ -4820,152 +4479,12 @@ return err; } -asmlinkage long sys_utimes(char *, struct timeval *); - -asmlinkage long -sys32_utimes(char *filename, struct timeval32 *tvs) -{ - char *kfilename; - struct timeval ktvs[2]; - mm_segment_t old_fs; - int ret; - - kfilename = getname32(filename); - ret = PTR_ERR(kfilename); - if (!IS_ERR(kfilename)) { - if (tvs) { - if (get_tv32(&ktvs[0], tvs) || - get_tv32(&ktvs[1], 1+tvs)) - return -EFAULT; - } - - old_fs = get_fs(); - set_fs(KERNEL_DS); - ret = sys_utimes(kfilename, &ktvs[0]); - set_fs(old_fs); - - putname(kfilename); - } - return ret; -} - -/* These are here just in case some old ia32 binary calls it. */ -asmlinkage long -sys32_pause(void) -{ - current->state = TASK_INTERRUPTIBLE; - schedule(); - return -ERESTARTNOHAND; -} - -/* PCI config space poking. */ -extern asmlinkage long sys_pciconfig_read(unsigned long bus, - unsigned long dfn, - unsigned long off, - unsigned long len, - unsigned char *buf); - -extern asmlinkage long sys_pciconfig_write(unsigned long bus, - unsigned long dfn, - unsigned long off, - unsigned long len, - unsigned char *buf); - -asmlinkage long -sys32_pciconfig_read(u32 bus, u32 dfn, u32 off, u32 len, u32 ubuf) -{ - return sys_pciconfig_read((unsigned long) bus, - (unsigned long) dfn, - (unsigned long) off, - (unsigned long) len, - (unsigned char *)AA(ubuf)); -} - -asmlinkage long -sys32_pciconfig_write(u32 bus, u32 dfn, u32 off, u32 len, u32 ubuf) -{ - return sys_pciconfig_write((unsigned long) bus, - (unsigned long) dfn, - (unsigned long) off, - (unsigned long) len, - (unsigned char *)AA(ubuf)); -} - -extern asmlinkage long sys_prctl(int option, unsigned long arg2, - unsigned long arg3, unsigned long arg4, - unsigned long arg5); - -asmlinkage long -sys32_prctl(int option, u32 arg2, u32 arg3, u32 arg4, u32 arg5) -{ - return sys_prctl(option, - (unsigned long) arg2, - (unsigned long) arg3, - (unsigned long) arg4, - (unsigned long) arg5); -} - - -extern asmlinkage ssize_t sys_pread(unsigned int fd, char * buf, - size_t count, loff_t pos); - -extern asmlinkage ssize_t sys_pwrite(unsigned int fd, const char * buf, - size_t count, loff_t pos); - -typedef __kernel_ssize_t32 ssize_t32; - -asmlinkage ssize_t32 -sys32_pread(unsigned int fd, char *ubuf, __kernel_size_t32 count, - u32 poshi, u32 poslo) -{ - return sys_pread(fd, ubuf, count, - ((loff_t)AA(poshi) << 32) | AA(poslo)); -} - -asmlinkage ssize_t32 -sys32_pwrite(unsigned int fd, char *ubuf, __kernel_size_t32 count, - u32 poshi, u32 poslo) -{ - return sys_pwrite(fd, ubuf, count, - ((loff_t)AA(poshi) << 32) | AA(poslo)); -} - - -extern asmlinkage long sys_personality(unsigned long); - -asmlinkage long -sys32_personality(unsigned long personality) -{ - int ret; - if (current->personality == PER_LINUX32 && personality == PER_LINUX) - personality = PER_LINUX32; - ret = sys_personality(personality); - if (ret == PER_LINUX32) - ret = PER_LINUX; - return ret; -} - extern asmlinkage ssize_t sys_sendfile(int out_fd, int in_fd, off_t *offset, size_t count); asmlinkage long sys32_sendfile(int out_fd, int in_fd, __kernel_off_t32 *offset, s32 count) { - mm_segment_t old_fs = get_fs(); - int ret; - off_t of; - - if (offset && get_user(of, offset)) - return -EFAULT; - - set_fs(KERNEL_DS); - ret = sys_sendfile(out_fd, in_fd, offset ? &of : NULL, count); - set_fs(old_fs); - - if (!ret && offset && put_user(of, offset)) - return -EFAULT; - - return ret; } /* Handle adjtimex compatability. */ diff -urN linux-2.4.10/arch/ia64/kernel/acpi.c linux-2.4.10-lia/arch/ia64/kernel/acpi.c --- linux-2.4.10/arch/ia64/kernel/acpi.c Tue Jul 31 10:30:08 2001 +++ linux-2.4.10-lia/arch/ia64/kernel/acpi.c Mon Sep 24 21:45:43 2001 @@ -9,7 +9,7 @@ * Copyright (C) 2000 Hewlett-Packard Co. * Copyright (C) 2000 David Mosberger-Tang * Copyright (C) 2000 Intel Corp. - * Copyright (C) 2000 J.I. Lee + * Copyright (C) 2000,2001 J.I. Lee * ACPI based kernel configuration manager. * ACPI 2.0 & IA64 ext 0.71 */ @@ -34,6 +34,9 @@ #undef ACPI_DEBUG /* Guess what this does? */ +/* global array to record platform interrupt vectors for generic int routing */ +int platform_irq_list[ACPI_MAX_PLATFORM_IRQS]; + /* These are ugly but will be reclaimed by the kernel */ int __initdata available_cpus; int __initdata total_cpus; @@ -42,7 +45,9 @@ void (*pm_power_off) (void); asm (".weak iosapic_register_legacy_irq"); +asm (".weak iosapic_register_platform_irq"); asm (".weak iosapic_init"); +asm (".weak iosapic_version"); const char * acpi_get_sysname (void) @@ -55,6 +60,8 @@ return "hpsim"; # elif defined (CONFIG_IA64_SGI_SN1) return "sn1"; +# elif defined (CONFIG_IA64_SGI_SN2) + return "sn2"; # elif defined (CONFIG_IA64_DIG) return "dig"; # else @@ -65,6 +72,25 @@ } /* + * Interrupt routing API for device drivers. + * Provides the interrupt vector for a generic platform event + * (currently only CPEI implemented) + */ +int +acpi_request_vector(u32 int_type) +{ + int vector = -1; + + if (int_type < ACPI_MAX_PLATFORM_IRQS) { + /* correctable platform error interrupt */ + vector = platform_irq_list[int_type]; + } else + printk("acpi_request_vector(): invalid interrupt type\n"); + + return vector; +} + +/* * Configure legacy IRQ information. */ static void __init @@ -139,15 +165,93 @@ } /* - * Info on platform interrupt sources: NMI. PMI, INIT, etc. + * Extract iosapic info from madt (again) to determine which iosapic + * this platform interrupt resides in + */ +static int __init +acpi20_which_iosapic (int global_vector, acpi_madt_t *madt, u32 *irq_base, char **iosapic_address) +{ + acpi_entry_iosapic_t *iosapic; + char *p, *end; + int ver, max_pin; + + p = (char *) (madt + 1); + end = p + (madt->header.length - sizeof(acpi_madt_t)); + + while (p < end) { + switch (*p) { + case ACPI20_ENTRY_IO_SAPIC: + /* collect IOSAPIC info for platform int use later */ + iosapic = (acpi_entry_iosapic_t *)p; + *irq_base = iosapic->irq_base; + *iosapic_address = ioremap(iosapic->address, 0); + /* is this the iosapic we're looking for? */ + ver = iosapic_version(*iosapic_address); + max_pin = (ver >> 16) & 0xff; + if ((global_vector - *irq_base) <= max_pin) + return 0; /* found it! */ + break; + default: + break; + } + p += p[1]; + } + return 1; +} + +/* + * Info on platform interrupt sources: NMI, PMI, INIT, etc. */ static void __init -acpi20_platform (char *p) +acpi20_platform (char *p, acpi_madt_t *madt) { + int vector; + u32 irq_base; + char *iosapic_address; + unsigned long polarity = 0, trigger = 0; acpi20_entry_platform_src_t *plat = (acpi20_entry_platform_src_t *) p; printk("PLATFORM: IOSAPIC %x -> Vector %x on CPU %.04u:%.04u\n", plat->iosapic_vector, plat->global_vector, plat->eid, plat->id); + + /* record platform interrupt vectors for generic int routing code */ + + if (!iosapic_register_platform_irq) { + printk("acpi20_platform(): no ACPI platform IRQ support\n"); + return; + } + + /* extract polarity and trigger info from flags */ + switch (plat->flags) { + case 0x5: polarity = 1; trigger = 1; break; + case 0x7: polarity = 0; trigger = 1; break; + case 0xd: polarity = 1; trigger = 0; break; + case 0xf: polarity = 0; trigger = 0; break; + default: + printk("acpi20_platform(): unknown flags 0x%x\n", plat->flags); + break; + } + + /* which iosapic does this IRQ belong to? */ + if (acpi20_which_iosapic(plat->global_vector, madt, &irq_base, &iosapic_address)) { + printk("acpi20_platform(): I/O SAPIC not found!\n"); + return; + } + + /* + * get vector assignment for this IRQ, set attributes, and program the IOSAPIC + * routing table + */ + vector = iosapic_register_platform_irq(plat->int_type, + plat->global_vector, + plat->iosapic_vector, + plat->eid, + plat->id, + polarity, + trigger, + irq_base, + iosapic_address); + platform_irq_list[plat->int_type] = vector; } /* @@ -173,8 +277,10 @@ static void __init acpi20_parse_madt (acpi_madt_t *madt) { - acpi_entry_iosapic_t *iosapic; + acpi_entry_iosapic_t *iosapic = NULL; + acpi20_entry_lsapic_t *lsapic = NULL; char *p, *end; + int i; /* Base address of IPI Message Block */ if (madt->lapic_address) { @@ -186,23 +292,27 @@ p = (char *) (madt + 1); end = p + (madt->header.length - sizeof(acpi_madt_t)); + /* Initialize platform interrupt vector array */ + for (i = 0; i < ACPI_MAX_PLATFORM_IRQS; i++) + platform_irq_list[i] = -1; + /* - * Splitted entry parsing to ensure ordering. + * Split-up entry parsing to ensure ordering. */ - while (p < end) { switch (*p) { - case ACPI20_ENTRY_LOCAL_APIC_ADDR_OVERRIDE: + case ACPI20_ENTRY_LOCAL_APIC_ADDR_OVERRIDE: printk("ACPI 2.0 MADT: LOCAL APIC Override\n"); acpi20_lapic_addr_override(p); break; - case ACPI20_ENTRY_LOCAL_SAPIC: + case ACPI20_ENTRY_LOCAL_SAPIC: printk("ACPI 2.0 MADT: LOCAL SAPIC\n"); + lsapic = (acpi20_entry_lsapic_t *) p; acpi20_lsapic(p); break; - case ACPI20_ENTRY_IO_SAPIC: + case ACPI20_ENTRY_IO_SAPIC: iosapic = (acpi_entry_iosapic_t *) p; if (iosapic_init) /* @@ -218,26 +328,25 @@ ); break; - case ACPI20_ENTRY_PLATFORM_INT_SOURCE: + case ACPI20_ENTRY_PLATFORM_INT_SOURCE: printk("ACPI 2.0 MADT: PLATFORM INT SOURCE\n"); - acpi20_platform(p); + acpi20_platform(p, madt); break; - case ACPI20_ENTRY_LOCAL_APIC: + case ACPI20_ENTRY_LOCAL_APIC: printk("ACPI 2.0 MADT: LOCAL APIC entry\n"); break; - case ACPI20_ENTRY_IO_APIC: + case ACPI20_ENTRY_IO_APIC: printk("ACPI 2.0 MADT: IO APIC entry\n"); break; - case ACPI20_ENTRY_NMI_SOURCE: + case ACPI20_ENTRY_NMI_SOURCE: printk("ACPI 2.0 MADT: NMI SOURCE entry\n"); break; - case ACPI20_ENTRY_LOCAL_APIC_NMI: + case ACPI20_ENTRY_LOCAL_APIC_NMI: printk("ACPI 2.0 MADT: LOCAL APIC NMI entry\n"); break; - case ACPI20_ENTRY_INT_SRC_OVERRIDE: + case ACPI20_ENTRY_INT_SRC_OVERRIDE: break; - default: + default: printk("ACPI 2.0 MADT: unknown entry skip\n"); break; break; } - p += p[1]; } @@ -245,16 +354,35 @@ end = p + (madt->header.length - sizeof(acpi_madt_t)); while (p < end) { + switch (*p) { + case ACPI20_ENTRY_LOCAL_APIC: + if (lsapic) break; + printk("ACPI 2.0 MADT: LOCAL APIC entry\n"); + /* parse local apic if there's no local Sapic */ + break; + case ACPI20_ENTRY_IO_APIC: + if (iosapic) break; + printk("ACPI 2.0 MADT: IO APIC entry\n"); + /* parse ioapic if there's no ioSapic */ + break; + default: + break; + } + p += p[1]; + } + p = (char *) (madt + 1); + end = p + (madt->header.length - sizeof(acpi_madt_t)); + + while (p < end) { switch (*p) { - case ACPI20_ENTRY_INT_SRC_OVERRIDE: + case ACPI20_ENTRY_INT_SRC_OVERRIDE: printk("ACPI 2.0 MADT: INT SOURCE Override\n"); acpi_legacy_irq(p); break; - default: + default: break; } - p += p[1]; } diff -urN linux-2.4.10/arch/ia64/kernel/efi.c linux-2.4.10-lia/arch/ia64/kernel/efi.c --- linux-2.4.10/arch/ia64/kernel/efi.c Tue Jul 31 10:30:08 2001 +++ linux-2.4.10-lia/arch/ia64/kernel/efi.c Mon Aug 13 23:51:59 2001 @@ -482,5 +482,7 @@ static void __exit efivars_exit(void) { +#ifdef CONFIG_PROC_FS remove_proc_entry(efi_dir->name, NULL); +#endif } diff -urN linux-2.4.10/arch/ia64/kernel/efi_stub.S linux-2.4.10-lia/arch/ia64/kernel/efi_stub.S --- linux-2.4.10/arch/ia64/kernel/efi_stub.S Thu Apr 5 12:51:47 2001 +++ linux-2.4.10-lia/arch/ia64/kernel/efi_stub.S Mon Sep 24 21:45:52 2001 @@ -1,8 +1,8 @@ /* * EFI call stub. * - * Copyright (C) 1999-2000 Hewlett-Packard Co - * Copyright (C) 1999-2000 David Mosberger + * Copyright (C) 1999-2001 Hewlett-Packard Co + * David Mosberger * * This stub allows us to make EFI calls in physical mode with interrupts * turned off. We need this because we can't call SetVirtualMap() until @@ -68,17 +68,17 @@ ;; andcm r16=loc3,r16 // get psr with IT, DT, and RT bits cleared mov out3=in4 - br.call.sptk.few rp=ia64_switch_mode + br.call.sptk.many rp=ia64_switch_mode .ret0: mov out4=in5 mov out5=in6 mov out6=in7 - br.call.sptk.few rp=b6 // call the EFI function + br.call.sptk.many rp=b6 // call the EFI function .ret1: mov ar.rsc=0 // put RSE in enforced lazy, LE mode mov r16=loc3 - br.call.sptk.few rp=ia64_switch_mode // return to virtual mode + br.call.sptk.many rp=ia64_switch_mode // return to virtual mode .ret2: mov ar.rsc=loc4 // restore RSE configuration mov ar.pfs=loc1 mov rp=loc0 mov gp=loc2 - br.ret.sptk.few rp + br.ret.sptk.many rp END(efi_call_phys) diff -urN linux-2.4.10/arch/ia64/kernel/efivars.c linux-2.4.10-lia/arch/ia64/kernel/efivars.c --- linux-2.4.10/arch/ia64/kernel/efivars.c Tue Jul 31 10:30:08 2001 +++ linux-2.4.10-lia/arch/ia64/kernel/efivars.c Mon Sep 24 21:46:04 2001 @@ -276,21 +276,20 @@ if (!capable(CAP_SYS_ADMIN)) return -EACCES; - spin_lock(&efivars_lock); MOD_INC_USE_COUNT; var_data = kmalloc(size, GFP_KERNEL); if (!var_data) { MOD_DEC_USE_COUNT; - spin_unlock(&efivars_lock); return -ENOMEM; } if (copy_from_user(var_data, buffer, size)) { MOD_DEC_USE_COUNT; - spin_unlock(&efivars_lock); + kfree(var_data); return -EFAULT; } + spin_lock(&efivars_lock); /* Since the data ptr we've currently got is probably for a different variable find the right variable. diff -urN linux-2.4.10/arch/ia64/kernel/entry.S linux-2.4.10-lia/arch/ia64/kernel/entry.S --- linux-2.4.10/arch/ia64/kernel/entry.S Tue Jul 31 10:30:08 2001 +++ linux-2.4.10-lia/arch/ia64/kernel/entry.S Mon Sep 24 21:46:12 2001 @@ -55,7 +55,7 @@ mov out1=in1 // argv mov out2=in2 // envp add out3=16,sp // regs - br.call.sptk.few rp=sys_execve + br.call.sptk.many rp=sys_execve .ret0: cmp4.ge p6,p7=r8,r0 mov ar.pfs=loc1 // restore ar.pfs sxt4 r8=r8 // return 64-bit result @@ -64,7 +64,7 @@ (p6) cmp.ne pKern,pUser=r0,r0 // a successful execve() lands us in user-mode... mov rp=loc0 (p6) mov ar.pfs=r0 // clear ar.pfs on success -(p7) br.ret.sptk.few rp +(p7) br.ret.sptk.many rp /* * In theory, we'd have to zap this state only to prevent leaking of @@ -85,7 +85,7 @@ ldf.fill f26=[sp]; ldf.fill f27=[sp]; mov f28=f0 ldf.fill f29=[sp]; ldf.fill f30=[sp]; mov f31=f0 mov ar.lc=0 - br.ret.sptk.few rp + br.ret.sptk.many rp END(ia64_execve) GLOBAL_ENTRY(sys_clone2) @@ -99,7 +99,7 @@ mov out3=in2 adds out2=IA64_SWITCH_STACK_SIZE+16,sp // out2 = ®s mov out0=in0 // out0 = clone_flags - br.call.sptk.few rp=do_fork + br.call.sptk.many rp=do_fork .ret1: .restore sp adds sp=IA64_SWITCH_STACK_SIZE,sp // pop the switch stack mov ar.pfs=loc1 @@ -118,7 +118,7 @@ mov out3=0 adds out2=IA64_SWITCH_STACK_SIZE+16,sp // out2 = ®s mov out0=in0 // out0 = clone_flags - br.call.sptk.few rp=do_fork + br.call.sptk.many rp=do_fork .ret2: .restore sp adds sp=IA64_SWITCH_STACK_SIZE,sp // pop the switch stack mov ar.pfs=loc1 @@ -143,7 +143,7 @@ shr.u r26=r20,KERNEL_PG_SHIFT mov r16=KERNEL_PG_NUM ;; - cmp.ne p6,p7=r26,r16 // check >= 64M && < 128M + cmp.ne p6,p7=r26,r16 // check whether r26 != KERNEL_PG_NUM adds r21=IA64_TASK_THREAD_KSP_OFFSET,in0 ;; /* @@ -151,12 +151,13 @@ * again. */ (p6) cmp.eq p7,p6=r26,r27 -(p6) br.cond.dpnt.few .map +(p6) br.cond.dpnt .map ;; -.done: ld8 sp=[r21] // load kernel stack pointer of new task +.done: (p6) ssm psr.ic // if we we had to map, renable the psr.ic bit FIRST!!! ;; (p6) srlz.d + ld8 sp=[r21] // load kernel stack pointer of new task mov IA64_KR(CURRENT)=r20 // update "current" application register mov r8=r13 // return pointer to previously running task mov r13=in0 // set "current" pointer @@ -167,7 +168,7 @@ #ifdef CONFIG_SMP sync.i // ensure "fc"s done by this CPU are visible on other CPUs #endif - br.ret.sptk.few rp // boogie on out in new context + br.ret.sptk.many rp // boogie on out in new context .map: rsm psr.i | psr.ic @@ -184,7 +185,7 @@ mov IA64_KR(CURRENT_STACK)=r26 // remember last page we mapped... ;; itr.d dtr[r25]=r23 // wire in new mapping... - br.cond.sptk.many .done + br.cond.sptk .done END(ia64_switch_to) /* @@ -212,24 +213,18 @@ .save @priunat,r17 mov r17=ar.unat // preserve caller's .body -#if !(defined(CONFIG_ITANIUM_B0_SPECIFIC) || defined(CONFIG_ITANIUM_B1_SPECIFIC)) adds r3=80,sp ;; lfetch.fault.excl.nt1 [r3],128 -#endif mov ar.rsc=0 // put RSE in mode: enforced lazy, little endian, pl 0 -#if !(defined(CONFIG_ITANIUM_B0_SPECIFIC) || defined(CONFIG_ITANIUM_B1_SPECIFIC)) adds r2=16+128,sp ;; lfetch.fault.excl.nt1 [r2],128 lfetch.fault.excl.nt1 [r3],128 -#endif adds r14=SW(R4)+16,sp -#if !(defined(CONFIG_ITANIUM_B0_SPECIFIC) || defined(CONFIG_ITANIUM_B1_SPECIFIC)) ;; lfetch.fault.excl [r2] lfetch.fault.excl [r3] -#endif adds r15=SW(R5)+16,sp ;; mov r18=ar.fpsr // preserve fpsr @@ -309,7 +304,7 @@ st8 [r2]=r20 // save ar.bspstore st8 [r3]=r21 // save predicate registers mov ar.rsc=3 // put RSE back into eager mode, pl 0 - br.cond.sptk.few b7 + br.cond.sptk.many b7 END(save_switch_stack) /* @@ -321,11 +316,9 @@ ENTRY(load_switch_stack) .prologue .altrp b7 - .body -#if !(defined(CONFIG_ITANIUM_B0_SPECIFIC) || defined(CONFIG_ITANIUM_B1_SPECIFIC)) + .body lfetch.fault.nt1 [sp] -#endif adds r2=SW(AR_BSPSTORE)+16,sp adds r3=SW(AR_UNAT)+16,sp mov ar.rsc=0 // put RSE into enforced lazy mode @@ -426,7 +419,7 @@ ;; (p6) st4 [r2]=r8 (p6) mov r8=-1 - br.ret.sptk.few rp + br.ret.sptk.many rp END(__ia64_syscall) /* @@ -441,11 +434,11 @@ .body mov loc2=b6 ;; - br.call.sptk.few rp=syscall_trace + br.call.sptk.many rp=syscall_trace .ret3: mov rp=loc0 mov ar.pfs=loc1 mov b6=loc2 - br.ret.sptk.few rp + br.ret.sptk.many rp END(invoke_syscall_trace) /* @@ -462,21 +455,21 @@ GLOBAL_ENTRY(ia64_trace_syscall) PT_REGS_UNWIND_INFO(0) - br.call.sptk.few rp=invoke_syscall_trace // give parent a chance to catch syscall args -.ret6: br.call.sptk.few rp=b6 // do the syscall + br.call.sptk.many rp=invoke_syscall_trace // give parent a chance to catch syscall args +.ret6: br.call.sptk.many rp=b6 // do the syscall strace_check_retval: cmp.lt p6,p0=r8,r0 // syscall failed? adds r2=PT(R8)+16,sp // r2 = &pt_regs.r8 adds r3=PT(R10)+16,sp // r3 = &pt_regs.r10 mov r10=0 -(p6) br.cond.sptk.few strace_error // syscall failed -> +(p6) br.cond.sptk strace_error // syscall failed -> ;; // avoid RAW on r10 strace_save_retval: .mem.offset 0,0; st8.spill [r2]=r8 // store return value in slot for r8 .mem.offset 8,0; st8.spill [r3]=r10 // clear error indication in slot for r10 ia64_strace_leave_kernel: - br.call.sptk.few rp=invoke_syscall_trace // give parent a chance to catch return value -.rety: br.cond.sptk.many ia64_leave_kernel + br.call.sptk.many rp=invoke_syscall_trace // give parent a chance to catch return value +.rety: br.cond.sptk ia64_leave_kernel strace_error: ld8 r3=[r2] // load pt_regs.r8 @@ -487,7 +480,7 @@ ;; (p6) mov r10=-1 (p6) mov r8=r9 - br.cond.sptk.few strace_save_retval + br.cond.sptk strace_save_retval END(ia64_trace_syscall) GLOBAL_ENTRY(ia64_ret_from_clone) @@ -497,7 +490,7 @@ * Called by ia64_switch_to after do_fork()->copy_thread(). r8 contains the * address of the previously executing task. */ - br.call.sptk.few rp=invoke_schedule_tail + br.call.sptk.many rp=ia64_invoke_schedule_tail .ret8: adds r2=IA64_TASK_PTRACE_OFFSET,r13 ;; @@ -505,7 +498,7 @@ ;; mov r8=0 tbit.nz p6,p0=r2,PT_TRACESYS_BIT -(p6) br strace_check_retval +(p6) br.cond.spnt strace_check_retval ;; // added stop bits to prevent r8 dependency END(ia64_ret_from_clone) // fall through @@ -519,7 +512,7 @@ (p6) st8.spill [r2]=r8 // store return value in slot for r8 and set unat bit .mem.offset 8,0 (p6) st8.spill [r3]=r0 // clear error indication in slot for r10 and set unat bit -(p7) br.cond.spnt.few handle_syscall_error // handle potential syscall failure +(p7) br.cond.spnt handle_syscall_error // handle potential syscall failure END(ia64_ret_from_syscall) // fall through GLOBAL_ENTRY(ia64_leave_kernel) @@ -527,22 +520,22 @@ lfetch.fault [sp] movl r14=.restart ;; - MOVBR(.ret.sptk,rp,r14,.restart) + mov.ret.sptk rp=r14,.restart .restart: adds r17=IA64_TASK_NEED_RESCHED_OFFSET,r13 adds r18=IA64_TASK_SIGPENDING_OFFSET,r13 #ifdef CONFIG_PERFMON - adds r19=IA64_TASK_PFM_NOTIFY_OFFSET,r13 + adds r19=IA64_TASK_PFM_MUST_BLOCK_OFFSET,r13 #endif ;; #ifdef CONFIG_PERFMON - ld8 r19=[r19] // load current->task.pfm_notify +(pUser) ld8 r19=[r19] // load current->thread.pfm_must_block #endif - ld8 r17=[r17] // load current->need_resched - ld4 r18=[r18] // load current->sigpending +(pUser) ld8 r17=[r17] // load current->need_resched +(pUser) ld4 r18=[r18] // load current->sigpending ;; #ifdef CONFIG_PERFMON - cmp.ne p9,p0=r19,r0 // current->task.pfm_notify != 0? +(pUser) cmp.ne.unc p9,p0=r19,r0 // current->thread.pfm_must_block != 0? #endif (pUser) cmp.ne.unc p7,p0=r17,r0 // current->need_resched != 0? (pUser) cmp.ne.unc p8,p0=r18,r0 // current->sigpending != 0? @@ -550,7 +543,7 @@ adds r2=PT(R8)+16,r12 adds r3=PT(R9)+16,r12 #ifdef CONFIG_PERFMON -(p9) br.call.spnt.many b7=pfm_overflow_notify +(p9) br.call.spnt.many b7=pfm_block_on_overflow #endif #if __GNUC__ < 3 (p7) br.call.spnt.many b7=invoke_schedule @@ -650,13 +643,13 @@ movl r17=PERCPU_ADDR+IA64_CPU_PHYS_STACKED_SIZE_P8_OFFSET ;; ld4 r17=[r17] // r17 = cpu_data->phys_stacked_size_p8 -(pKern) br.cond.dpnt.few skip_rbs_switch +(pKern) br.cond.dpnt skip_rbs_switch /* * Restore user backing store. * * NOTE: alloc, loadrs, and cover can't be predicated. */ -(pNonSys) br.cond.dpnt.few dont_preserve_current_frame +(pNonSys) br.cond.dpnt dont_preserve_current_frame cover // add current frame into dirty partition ;; mov r19=ar.bsp // get new backing store pointer @@ -687,7 +680,7 @@ shladd in0=loc1,3,r17 mov in1=0 ;; - .align 32 +// .align 32 // gas-2.11.90 is unable to generate a stop bit after .align rse_clear_invalid: // cycle 0 { .mii @@ -706,7 +699,7 @@ }{ .mib mov loc3=0 mov loc4=0 -(pRecurse) br.call.sptk.few b6=rse_clear_invalid +(pRecurse) br.call.sptk.many b6=rse_clear_invalid }{ .mfi // cycle 2 mov loc5=0 @@ -715,7 +708,7 @@ }{ .mib mov loc6=0 mov loc7=0 -(pReturn) br.ret.sptk.few b6 +(pReturn) br.ret.sptk.many b6 } # undef pRecurse # undef pReturn @@ -761,24 +754,24 @@ ;; .mem.offset 0,0; st8.spill [r2]=r9 // store errno in pt_regs.r8 and set unat bit .mem.offset 8,0; st8.spill [r3]=r10 // store error indication in pt_regs.r10 and set unat bit - br.cond.sptk.many ia64_leave_kernel + br.cond.sptk ia64_leave_kernel END(handle_syscall_error) /* * Invoke schedule_tail(task) while preserving in0-in7, which may be needed * in case a system call gets restarted. */ -ENTRY(invoke_schedule_tail) +GLOBAL_ENTRY(ia64_invoke_schedule_tail) .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(8) alloc loc1=ar.pfs,8,2,1,0 mov loc0=rp mov out0=r8 // Address of previous task ;; - br.call.sptk.few rp=schedule_tail + br.call.sptk.many rp=schedule_tail .ret11: mov ar.pfs=loc1 mov rp=loc0 br.ret.sptk.many rp -END(invoke_schedule_tail) +END(ia64_invoke_schedule_tail) #if __GNUC__ < 3 @@ -797,7 +790,7 @@ mov loc0=rp ;; .body - br.call.sptk.few rp=schedule + br.call.sptk.many rp=schedule .ret14: mov ar.pfs=loc1 mov rp=loc0 br.ret.sptk.many rp @@ -824,7 +817,7 @@ .spillpsp ar.unat, 16 // (note that offset is relative to psp+0x10!) st8 [sp]=r9,-16 // allocate space for ar.unat and save it .body - br.call.sptk.few rp=ia64_do_signal + br.call.sptk.many rp=ia64_do_signal .ret15: .restore sp adds sp=16,sp // pop scratch stack space ;; @@ -849,7 +842,7 @@ .spillpsp ar.unat, 16 // (note that offset is relative to psp+0x10!) st8 [sp]=r9,-16 // allocate space for ar.unat and save it .body - br.call.sptk.few rp=ia64_rt_sigsuspend + br.call.sptk.many rp=ia64_rt_sigsuspend .ret17: .restore sp adds sp=16,sp // pop scratch stack space ;; @@ -871,15 +864,15 @@ cmp.eq pNonSys,pSys=r0,r0 // sigreturn isn't a normal syscall... ;; adds out0=16,sp // out0 = &sigscratch - br.call.sptk.few rp=ia64_rt_sigreturn + br.call.sptk.many rp=ia64_rt_sigreturn .ret19: .restore sp 0 adds sp=16,sp ;; ld8 r9=[sp] // load new ar.unat - MOVBR(.sptk,b7,r8,ia64_leave_kernel) + mov.sptk b7=r8,ia64_leave_kernel ;; mov ar.unat=r9 - br b7 + br.many b7 END(sys_rt_sigreturn) GLOBAL_ENTRY(ia64_prepare_handle_unaligned) @@ -890,7 +883,7 @@ mov r16=r0 .prologue DO_SAVE_SWITCH_STACK - br.call.sptk.few rp=ia64_handle_unaligned // stack frame setup in ivt + br.call.sptk.many rp=ia64_handle_unaligned // stack frame setup in ivt .ret21: .body DO_LOAD_SWITCH_STACK br.cond.sptk.many rp // goes to ia64_leave_kernel @@ -920,14 +913,14 @@ adds out0=16,sp // &info mov out1=r13 // current adds out2=16+EXTRA_FRAME_SIZE,sp // &switch_stack - br.call.sptk.few rp=unw_init_frame_info + br.call.sptk.many rp=unw_init_frame_info 1: adds out0=16,sp // &info mov b6=loc2 mov loc2=gp // save gp across indirect function call ;; ld8 gp=[in0] mov out1=in1 // arg - br.call.sptk.few rp=b6 // invoke the callback function + br.call.sptk.many rp=b6 // invoke the callback function 1: mov gp=loc2 // restore gp // For now, we don't allow changing registers from within diff -urN linux-2.4.10/arch/ia64/kernel/entry.h linux-2.4.10-lia/arch/ia64/kernel/entry.h --- linux-2.4.10/arch/ia64/kernel/entry.h Tue Jul 31 10:30:08 2001 +++ linux-2.4.10-lia/arch/ia64/kernel/entry.h Mon Aug 13 23:52:30 2001 @@ -1,12 +1,5 @@ #include -/* XXX fixme */ -#if defined(CONFIG_ITANIUM_B1_SPECIFIC) -# define MOVBR(type,br,gr,lbl) mov br=gr -#else -# define MOVBR(type,br,gr,lbl) mov##type br=gr,lbl -#endif - /* * Preserved registers that are shared between code in ivt.S and entry.S. Be * careful not to step on these! @@ -62,7 +55,7 @@ ;; \ .fframe IA64_SWITCH_STACK_SIZE; \ adds sp=-IA64_SWITCH_STACK_SIZE,sp; \ - MOVBR(.ret.sptk,b7,r28,1f); \ + mov.ret.sptk b7=r28,1f; \ SWITCH_STACK_SAVES(0); \ br.cond.sptk.many save_switch_stack; \ 1: @@ -71,7 +64,7 @@ movl r28=1f; \ ;; \ invala; \ - MOVBR(.ret.sptk,b7,r28,1f); \ + mov.ret.sptk b7=r28,1f; \ br.cond.sptk.many load_switch_stack; \ 1: .restore sp; \ adds sp=IA64_SWITCH_STACK_SIZE,sp diff -urN linux-2.4.10/arch/ia64/kernel/fw-emu.c linux-2.4.10-lia/arch/ia64/kernel/fw-emu.c --- linux-2.4.10/arch/ia64/kernel/fw-emu.c Tue Jul 31 10:30:08 2001 +++ linux-2.4.10-lia/arch/ia64/kernel/fw-emu.c Mon Sep 24 21:46:40 2001 @@ -416,11 +416,6 @@ strcpy(sal_systab->product_id, "SDV"); #endif -#ifdef CONFIG_IA64_SGI_SN1_SIM - strcpy(sal_systab->oem_id, "SGI"); - strcpy(sal_systab->product_id, "SN1"); -#endif - /* fill in an entry point: */ sal_ed->type = SAL_DESC_ENTRY_POINT; sal_ed->pal_proc = __pa(pal_desc[0]); diff -urN linux-2.4.10/arch/ia64/kernel/gate.S linux-2.4.10-lia/arch/ia64/kernel/gate.S --- linux-2.4.10/arch/ia64/kernel/gate.S Tue Jul 31 10:30:08 2001 +++ linux-2.4.10-lia/arch/ia64/kernel/gate.S Mon Sep 24 21:46:49 2001 @@ -3,7 +3,7 @@ * region. For now, it contains the signal trampoline code only. * * Copyright (C) 1999-2001 Hewlett-Packard Co - * Copyright (C) 1999-2001 David Mosberger-Tang + * David Mosberger-Tang */ #include @@ -18,7 +18,6 @@ # define ARG0_OFF (16 + IA64_SIGFRAME_ARG0_OFFSET) # define ARG1_OFF (16 + IA64_SIGFRAME_ARG1_OFFSET) # define ARG2_OFF (16 + IA64_SIGFRAME_ARG2_OFFSET) -# define RBS_BASE_OFF (16 + IA64_SIGFRAME_RBS_BASE_OFFSET) # define SIGHANDLER_OFF (16 + IA64_SIGFRAME_HANDLER_OFFSET) # define SIGCONTEXT_OFF (16 + IA64_SIGFRAME_SIGCONTEXT_OFFSET) @@ -32,6 +31,8 @@ # define PR_OFF IA64_SIGCONTEXT_PR_OFFSET # define RP_OFF IA64_SIGCONTEXT_B0_OFFSET # define SP_OFF IA64_SIGCONTEXT_R12_OFFSET +# define RBS_BASE_OFF IA64_SIGCONTEXT_RBS_BASE_OFFSET +# define LOADRS_OFF IA64_SIGCONTEXT_LOADRS_OFFSET # define base0 r2 # define base1 r3 /* @@ -73,34 +74,37 @@ .vframesp SP_OFF+SIGCONTEXT_OFF .body - .prologue + .label_state 1 + adds base0=SIGHANDLER_OFF,sp - adds base1=RBS_BASE_OFF,sp + adds base1=RBS_BASE_OFF+SIGCONTEXT_OFF,sp br.call.sptk.many rp=1f 1: ld8 r17=[base0],(ARG0_OFF-SIGHANDLER_OFF) // get pointer to signal handler's plabel - ld8 r15=[base1],(ARG1_OFF-RBS_BASE_OFF) // get address of new RBS base (or NULL) + ld8 r15=[base1] // get address of new RBS base (or NULL) cover // push args in interrupted frame onto backing store ;; + cmp.ne p8,p0=r15,r0 // do we need to switch the rbs? + mov.m r9=ar.bsp // fetch ar.bsp + .spillsp.p p8, ar.rnat, RNAT_OFF+SIGCONTEXT_OFF +(p8) br.cond.spnt setup_rbs // yup -> (clobbers r14, r15, and r16) +back_from_setup_rbs: + .save ar.pfs, r8 alloc r8=ar.pfs,0,0,3,0 // get CFM0, EC0, and CPL0 into r8 ld8 out0=[base0],16 // load arg0 (signum) + adds base1=(ARG1_OFF-(RBS_BASE_OFF+SIGCONTEXT_OFF)),base1 ;; ld8 out1=[base1] // load arg1 (siginfop) ld8 r10=[r17],8 // get signal handler entry point ;; ld8 out2=[base0] // load arg2 (sigcontextp) ld8 gp=[r17] // get signal handler's global pointer - cmp.ne p8,p0=r15,r0 // do we need to switch the rbs? - mov.m r17=ar.bsp // fetch ar.bsp - .spillsp.p p8, ar.rnat, RNAT_OFF+SIGCONTEXT_OFF -(p8) br.cond.spnt.few setup_rbs // yup -> (clobbers r14 and r16) -back_from_setup_rbs: adds base0=(BSP_OFF+SIGCONTEXT_OFF),sp ;; .spillsp ar.bsp, BSP_OFF+SIGCONTEXT_OFF - st8 [base0]=r17,(CFM_OFF-BSP_OFF) // save sc_ar_bsp + st8 [base0]=r9,(CFM_OFF-BSP_OFF) // save sc_ar_bsp dep r8=0,r8,38,26 // clear EC0, CPL0 and reserved bits adds base1=(FR6_OFF+16+SIGCONTEXT_OFF),sp ;; @@ -123,7 +127,7 @@ ;; stf.spill [base0]=f14,32 stf.spill [base1]=f15,32 - br.call.sptk.few rp=b6 // call the signal handler + br.call.sptk.many rp=b6 // call the signal handler .ret0: adds base0=(BSP_OFF+SIGCONTEXT_OFF),sp ;; ld8 r15=[base0],(CFM_OFF-BSP_OFF) // fetch sc_ar_bsp and advance to CFM_OFF @@ -131,7 +135,7 @@ ;; ld8 r8=[base0] // restore (perhaps modified) CFM0, EC0, and CPL0 cmp.ne p8,p0=r14,r15 // do we need to restore the rbs? -(p8) br.cond.spnt.few restore_rbs // yup -> (clobbers r14 and r16) +(p8) br.cond.spnt restore_rbs // yup -> (clobbers r14 and r16) ;; back_from_restore_rbs: adds base0=(FR6_OFF+SIGCONTEXT_OFF),sp @@ -154,30 +158,52 @@ mov r15=__NR_rt_sigreturn break __BREAK_SYSCALL + .body + .copy_state 1 setup_rbs: - flushrs // must be first in insn mov ar.rsc=0 // put RSE into enforced lazy mode - adds r16=(RNAT_OFF+SIGCONTEXT_OFF),sp ;; - mov r14=ar.rnat // get rnat as updated by flushrs - mov ar.bspstore=r15 // set new register backing store area + .save ar.rnat, r16 + mov r16=ar.rnat // save RNaT before switching backing store area + adds r14=(RNAT_OFF+SIGCONTEXT_OFF),sp + + mov ar.bspstore=r15 // switch over to new register backing store area ;; .spillsp ar.rnat, RNAT_OFF+SIGCONTEXT_OFF - st8 [r16]=r14 // save sc_ar_rnat + st8 [r14]=r16 // save sc_ar_rnat + adds r14=(LOADRS_OFF+SIGCONTEXT_OFF),sp + + mov.m r16=ar.bsp // sc_loadrs <- (new bsp - new bspstore) << 16 + ;; + invala + sub r15=r16,r15 + ;; + shl r15=r15,16 + ;; + st8 [r14]=r15 // save sc_loadrs mov ar.rsc=0xf // set RSE into eager mode, pl 3 - invala // invalidate ALAT - br.cond.sptk.many back_from_setup_rbs + br.cond.sptk back_from_setup_rbs + .prologue + .copy_state 1 + .spillsp ar.rnat, RNAT_OFF+SIGCONTEXT_OFF + .body restore_rbs: - flushrs - mov ar.rsc=0 // put RSE into enforced lazy mode + alloc r2=ar.pfs,0,0,0,0 // alloc null frame + adds r16=(LOADRS_OFF+SIGCONTEXT_OFF),sp + ;; + ld8 r14=[r16] adds r16=(RNAT_OFF+SIGCONTEXT_OFF),sp ;; + mov ar.rsc=r14 // put RSE into enforced lazy mode ld8 r14=[r16] // get new rnat - mov ar.bspstore=r15 // set old register backing store area ;; - mov ar.rnat=r14 // establish new rnat + loadrs // restore dirty partition + ;; + mov ar.bspstore=r15 // switch back to old register backing store area + ;; + mov ar.rnat=r14 // restore RNaT mov ar.rsc=0xf // (will be restored later on from sc_ar_rsc) // invala not necessary as that will happen when returning to user-mode - br.cond.sptk.many back_from_restore_rbs + br.cond.sptk back_from_restore_rbs END(ia64_sigtramp) diff -urN linux-2.4.10/arch/ia64/kernel/head.S linux-2.4.10-lia/arch/ia64/kernel/head.S --- linux-2.4.10/arch/ia64/kernel/head.S Tue Jul 31 10:30:08 2001 +++ linux-2.4.10-lia/arch/ia64/kernel/head.S Mon Sep 24 21:47:23 2001 @@ -6,8 +6,8 @@ * entry point. * * Copyright (C) 1998-2001 Hewlett-Packard Co - * Copyright (C) 1998-2001 David Mosberger-Tang - * Copyright (C) 2001 Stephane Eranian + * David Mosberger-Tang + * Stephane Eranian * Copyright (C) 1999 VA Linux Systems * Copyright (C) 1999 Walt Drummond * Copyright (C) 1999 Intel Corp. @@ -86,7 +86,8 @@ /* * Switch into virtual mode: */ - movl r16=(IA64_PSR_IT|IA64_PSR_IC|IA64_PSR_DT|IA64_PSR_RT|IA64_PSR_DFH|IA64_PSR_BN) + movl r16=(IA64_PSR_IT|IA64_PSR_IC|IA64_PSR_DT|IA64_PSR_RT|IA64_PSR_DFH|IA64_PSR_BN \ + |IA64_PSR_DI) ;; mov cr.ipsr=r16 movl r17=1f @@ -183,31 +184,31 @@ alloc r2=ar.pfs,0,0,2,0 movl out0=alive_msg ;; - br.call.sptk.few rp=early_printk + br.call.sptk.many rp=early_printk 1: // force new bundle #endif /* CONFIG_IA64_EARLY_PRINTK */ #ifdef CONFIG_SMP -(isAP) br.call.sptk.few rp=start_secondary +(isAP) br.call.sptk.many rp=start_secondary .ret0: -(isAP) br.cond.sptk.few self +(isAP) br.cond.sptk self #endif // This is executed by the bootstrap processor (bsp) only: #ifdef CONFIG_IA64_FW_EMU // initialize PAL & SAL emulator: - br.call.sptk.few rp=sys_fw_init + br.call.sptk.many rp=sys_fw_init .ret1: #endif - br.call.sptk.few rp=start_kernel + br.call.sptk.many rp=start_kernel .ret2: addl r3=@ltoff(halt_msg),gp ;; alloc r2=ar.pfs,8,0,2,0 ;; ld8 out0=[r3] - br.call.sptk.few b0=console_print -self: br.sptk.few self // endless loop + br.call.sptk.many b0=console_print +self: br.sptk.many self // endless loop END(_start) GLOBAL_ENTRY(ia64_save_debug_regs) @@ -218,7 +219,7 @@ add r19=IA64_NUM_DBG_REGS*8,in0 ;; 1: mov r16=dbr[r18] -#if defined(CONFIG_ITANIUM_C0_SPECIFIC) +#ifdef CONFIG_ITANIUM ;; srlz.d #endif @@ -227,17 +228,15 @@ ;; st8.nta [in0]=r16,8 st8.nta [r19]=r17,8 - br.cloop.sptk.few 1b + br.cloop.sptk.many 1b ;; mov ar.lc=r20 // restore ar.lc - br.ret.sptk.few rp + br.ret.sptk.many rp END(ia64_save_debug_regs) GLOBAL_ENTRY(ia64_load_debug_regs) alloc r16=ar.pfs,1,0,0,0 -#if !(defined(CONFIG_ITANIUM_B0_SPECIFIC) || defined(CONFIG_ITANIUM_B1_SPECIFIC)) lfetch.nta [in0] -#endif mov r20=ar.lc // preserve ar.lc add r19=IA64_NUM_DBG_REGS*8,in0 mov ar.lc=IA64_NUM_DBG_REGS-1 @@ -248,15 +247,15 @@ add r18=1,r18 ;; mov dbr[r18]=r16 -#if defined(CONFIG_ITANIUM_BSTEP_SPECIFIC) || defined(CONFIG_ITANIUM_C0_SPECIFIC) +#ifdef CONFIG_ITANIUM ;; - srlz.d + srlz.d // Errata 132 (NoFix status) #endif mov ibr[r18]=r17 - br.cloop.sptk.few 1b + br.cloop.sptk.many 1b ;; mov ar.lc=r20 // restore ar.lc - br.ret.sptk.few rp + br.ret.sptk.many rp END(ia64_load_debug_regs) GLOBAL_ENTRY(__ia64_save_fpu) @@ -406,7 +405,7 @@ ;; stf.spill.nta [in0]=f126,32 stf.spill.nta [ r3]=f127,32 - br.ret.sptk.few rp + br.ret.sptk.many rp END(__ia64_save_fpu) GLOBAL_ENTRY(__ia64_load_fpu) @@ -556,7 +555,7 @@ ;; ldf.fill.nta f126=[in0],32 ldf.fill.nta f127=[ r3],32 - br.ret.sptk.few rp + br.ret.sptk.many rp END(__ia64_load_fpu) GLOBAL_ENTRY(__ia64_init_fpu) @@ -690,7 +689,7 @@ ;; ldf.fill f126=[sp] mov f127=f0 - br.ret.sptk.few rp + br.ret.sptk.many rp END(__ia64_init_fpu) /* @@ -738,7 +737,7 @@ rfi // must be last insn in group ;; 1: mov rp=r14 - br.ret.sptk.few rp + br.ret.sptk.many rp END(ia64_switch_mode) #ifdef CONFIG_IA64_BRL_EMU @@ -752,7 +751,7 @@ alloc r16=ar.pfs,1,0,0,0; \ mov reg=r32; \ ;; \ - br.ret.sptk rp; \ + br.ret.sptk.many rp; \ END(ia64_set_##reg) SET_REG(b1); @@ -816,12 +815,11 @@ ;; cmp.ne p15,p0=tmp,r0 mov tmp=ar.itc -(p15) br.cond.sptk.few .retry // lock is still busy +(p15) br.cond.sptk .retry // lock is still busy ;; // try acquiring lock (we know ar.ccv is still zero!): mov tmp=1 ;; - IA64_SEMFIX_INSN cmpxchg4.acq tmp=[r31],tmp,ar.ccv ;; cmp.eq p15,p0=tmp,r0 diff -urN linux-2.4.10/arch/ia64/kernel/ia64_ksyms.c linux-2.4.10-lia/arch/ia64/kernel/ia64_ksyms.c --- linux-2.4.10/arch/ia64/kernel/ia64_ksyms.c Tue Jul 31 10:30:08 2001 +++ linux-2.4.10-lia/arch/ia64/kernel/ia64_ksyms.c Mon Sep 24 21:47:44 2001 @@ -145,4 +145,3 @@ #include extern struct proc_dir_entry *efi_dir; EXPORT_SYMBOL(efi_dir); - diff -urN linux-2.4.10/arch/ia64/kernel/iosapic.c linux-2.4.10-lia/arch/ia64/kernel/iosapic.c --- linux-2.4.10/arch/ia64/kernel/iosapic.c Tue Jul 31 10:30:08 2001 +++ linux-2.4.10-lia/arch/ia64/kernel/iosapic.c Mon Sep 24 21:47:52 2001 @@ -53,6 +53,7 @@ #include #include #include +#include #include #include #include @@ -325,7 +326,7 @@ set_affinity: iosapic_set_affinity }; -static unsigned int +unsigned int iosapic_version (char *addr) { /* @@ -342,6 +343,113 @@ } /* + * ACPI can describe IOSAPIC interrupts via static tables and namespace + * methods. This provides an interface to register those interrupts and + * program the IOSAPIC RTE. + */ +int +iosapic_register_irq (u32 global_vector, unsigned long polarity, unsigned long + edge_triggered, u32 base_irq, char *iosapic_address) +{ + irq_desc_t *idesc; + struct hw_interrupt_type *irq_type; + int vector; + + vector = iosapic_irq_to_vector(global_vector); + if (vector < 0) + vector = ia64_alloc_irq(); + + /* fill in information from this vector's IOSAPIC */ + iosapic_irq[vector].addr = iosapic_address; + iosapic_irq[vector].base_irq = base_irq; + iosapic_irq[vector].pin = global_vector - iosapic_irq[vector].base_irq; + iosapic_irq[vector].polarity = polarity ? IOSAPIC_POL_HIGH : IOSAPIC_POL_LOW; + iosapic_irq[vector].dmode = IOSAPIC_LOWEST_PRIORITY; + + if (edge_triggered) { + iosapic_irq[vector].trigger = IOSAPIC_EDGE; + irq_type = &irq_type_iosapic_edge; + } else { + iosapic_irq[vector].trigger = IOSAPIC_LEVEL; + irq_type = &irq_type_iosapic_level; + } + + idesc = irq_desc(vector); + if (idesc->handler != irq_type) { + if (idesc->handler != &no_irq_type) + printk("iosapic_register_irq(): changing vector 0x%02x from" + "%s to %s\n", vector, idesc->handler->typename, irq_type->typename); + idesc->handler = irq_type; + } + + printk("IOSAPIC %x(%s,%s) -> Vector %x\n", global_vector, + (polarity ? "high" : "low"), (edge_triggered ? "edge" : "level"), vector); + + /* program the IOSAPIC routing table */ + set_rte(vector, (ia64_get_lid() >> 16) & 0xffff); + return vector; +} + +/* + * ACPI calls this when it finds an entry for a platform interrupt. + * Note that the irq_base and IOSAPIC address must be set in iosapic_init(). + */ +int +iosapic_register_platform_irq (u32 int_type, u32 global_vector, u32 iosapic_vector, + u16 eid, u16 id, unsigned long polarity, + unsigned long edge_triggered, u32 base_irq, char *iosapic_address) +{ + struct hw_interrupt_type *irq_type; + irq_desc_t *idesc; + int vector; + + switch (int_type) { + case ACPI20_ENTRY_PIS_CPEI: + vector = IA64_PCE_VECTOR; + iosapic_irq[vector].dmode = IOSAPIC_LOWEST_PRIORITY; + break; + case ACPI20_ENTRY_PIS_INIT: + vector = ia64_alloc_irq(); + iosapic_irq[vector].dmode = IOSAPIC_INIT; + break; + default: + printk("iosapic_register_platform_irq(): invalid int type\n"); + return -1; + } + + /* fill in information from this vector's IOSAPIC */ + iosapic_irq[vector].addr = iosapic_address; + iosapic_irq[vector].base_irq = base_irq; + iosapic_irq[vector].pin = global_vector - iosapic_irq[vector].base_irq; + iosapic_irq[vector].polarity = polarity ? IOSAPIC_POL_HIGH : IOSAPIC_POL_LOW; + + if (edge_triggered) { + iosapic_irq[vector].trigger = IOSAPIC_EDGE; + irq_type = &irq_type_iosapic_edge; + } else { + iosapic_irq[vector].trigger = IOSAPIC_LEVEL; + irq_type = &irq_type_iosapic_level; + } + + idesc = irq_desc(vector); + if (idesc->handler != irq_type) { + if (idesc->handler != &no_irq_type) + printk("iosapic_register_platform_irq(): changing vector 0x%02x from" + "%s to %s\n", vector, idesc->handler->typename, irq_type->typename); + idesc->handler = irq_type; + } + + printk("PLATFORM int %x: IOSAPIC %x(%s,%s) -> Vector %x CPU %.02u:%.02u\n", + int_type, global_vector, (polarity ? "high" : "low"), + (edge_triggered ? "edge" : "level"), vector, eid, id); + + /* program the IOSAPIC routing table */ + set_rte(vector, ((id << 8) | eid) & 0xffff); + return vector; +} + + +/* * ACPI calls this when it finds an entry for a legacy ISA interrupt. Note that the * irq_base and IOSAPIC address must be set in iosapic_init(). */ @@ -436,7 +544,7 @@ /* the interrupt route is for another controller... */ continue; - if (irq < 16) + if (pcat_compat && (irq < 16)) vector = isa_irq_to_vector(irq); else { vector = iosapic_irq_to_vector(irq); @@ -515,6 +623,23 @@ printk("PCI->APIC IRQ transform: (B%d,I%d,P%d) -> 0x%02x\n", dev->bus->number, PCI_SLOT(dev->devfn), pin, vector); dev->irq = vector; + +#ifdef CONFIG_SMP + /* + * For platforms that do not support interrupt redirect + * via the XTP interface, we can round-robin the PCI + * device interrupts to the processors + */ + if (!(smp_int_redirect & SMP_IRQ_REDIRECTION)) { + static int cpu_index = 0; + + set_rte(vector, cpu_physical_id(cpu_index) & 0xffff); + + cpu_index++; + if (cpu_index >= smp_num_cpus) + cpu_index = 0; + } +#endif } } /* diff -urN linux-2.4.10/arch/ia64/kernel/irq.c linux-2.4.10-lia/arch/ia64/kernel/irq.c --- linux-2.4.10/arch/ia64/kernel/irq.c Tue Jul 31 10:30:08 2001 +++ linux-2.4.10-lia/arch/ia64/kernel/irq.c Mon Sep 24 21:48:11 2001 @@ -33,6 +33,7 @@ #include #include +#include #include #include #include @@ -121,7 +122,10 @@ end_none }; -volatile unsigned long irq_err_count; +atomic_t irq_err_count; +#if defined(CONFIG_X86) && defined(CONFIG_X86_IO_APIC) && defined(APIC_MISMATCH_DEBUG) +atomic_t irq_mis_count; +#endif /* * Generic, controller-independent functions: @@ -164,14 +168,17 @@ p += sprintf(p, "%10u ", nmi_count(cpu_logical_map(j))); p += sprintf(p, "\n"); -#if defined(CONFIG_SMP) && defined(__i386__) +#if defined(CONFIG_SMP) && defined(CONFIG_X86) p += sprintf(p, "LOC: "); for (j = 0; j < smp_num_cpus; j++) p += sprintf(p, "%10u ", apic_timer_irqs[cpu_logical_map(j)]); p += sprintf(p, "\n"); #endif - p += sprintf(p, "ERR: %10lu\n", irq_err_count); + p += sprintf(p, "ERR: %10u\n", atomic_read(&irq_err_count)); +#if defined(CONFIG_X86) && defined(CONFIG_X86_IO_APIC) && defined(APIC_MISMATCH_DEBUG) + p += sprintf(p, "MIS: %10u\n", atomic_read(&irq_mis_count)); +#endif return p - buf; } @@ -183,7 +190,7 @@ #ifdef CONFIG_SMP unsigned int global_irq_holder = NO_PROC_ID; -volatile unsigned long global_irq_lock; /* long for set_bit --RR */ +unsigned volatile long global_irq_lock; /* pedantic: long for set_bit --RR */ extern void show_stack(unsigned long* esp); @@ -201,14 +208,14 @@ printk(" %d",bh_count(i)); printk(" ]\nStack dumps:"); -#if defined(__ia64__) +#if defined(CONFIG_IA64) /* * We can't unwind the stack of another CPU without access to * the registers of that CPU. And sending an IPI when we're * in a potentially wedged state doesn't sound like a smart * idea. */ -#elif defined(__i386__) +#elif defined(CONFIG_X86) for(i=0;i< smp_num_cpus;i++) { unsigned long esp; if(i==cpu) @@ -261,7 +268,7 @@ /* * We have to allow irqs to arrive between __sti and __cli */ -# ifdef __ia64__ +# ifdef CONFIG_IA64 # define SYNC_OTHER_CORES(x) __asm__ __volatile__ ("nop 0") # else # define SYNC_OTHER_CORES(x) __asm__ __volatile__ ("nop") @@ -331,6 +338,9 @@ /* Uhhuh.. Somebody else got it. Wait.. */ do { do { +#ifdef CONFIG_X86 + rep_nop(); +#endif } while (test_bit(0,&global_irq_lock)); } while (test_and_set_bit(0,&global_irq_lock)); } @@ -364,7 +374,7 @@ { unsigned int flags; -#ifdef __ia64__ +#ifdef CONFIG_IA64 __save_flags(flags); if (flags & IA64_PSR_I) { __cli(); @@ -403,7 +413,7 @@ int cpu = smp_processor_id(); __save_flags(flags); -#ifdef __ia64__ +#ifdef CONFIG_IA64 local_enabled = (flags & IA64_PSR_I) != 0; #else local_enabled = (flags >> EFLAGS_IF_SHIFT) & 1; @@ -476,13 +486,19 @@ return status; } -/* - * Generic enable/disable code: this just calls - * down into the PIC-specific version for the actual - * hardware disable after having gotten the irq - * controller lock. +/** + * disable_irq_nosync - disable an irq without waiting + * @irq: Interrupt to disable + * + * Disable the selected interrupt line. Disables and Enables are + * nested. + * Unlike disable_irq(), this function does not ensure existing + * instances of the IRQ handler have completed before returning. + * + * This function may be called from IRQ context. */ -void inline disable_irq_nosync(unsigned int irq) + +inline void disable_irq_nosync(unsigned int irq) { irq_desc_t *desc = irq_desc(irq); unsigned long flags; @@ -495,10 +511,19 @@ spin_unlock_irqrestore(&desc->lock, flags); } -/* - * Synchronous version of the above, making sure the IRQ is - * no longer running on any other IRQ.. +/** + * disable_irq - disable an irq and wait for completion + * @irq: Interrupt to disable + * + * Disable the selected interrupt line. Enables and Disables are + * nested. + * This function waits for any pending IRQ handlers for this interrupt + * to complete before returning. If you use this function while + * holding a resource the IRQ handler may need you will deadlock. + * + * This function may be called - with care - from IRQ context. */ + void disable_irq(unsigned int irq) { disable_irq_nosync(irq); @@ -512,6 +537,17 @@ #endif } +/** + * enable_irq - enable handling of an irq + * @irq: Interrupt to enable + * + * Undoes the effect of one call to disable_irq(). If this + * matches the last disable, processing of interrupts on this + * IRQ line is re-enabled. + * + * This function may be called from IRQ context. + */ + void enable_irq(unsigned int irq) { irq_desc_t *desc = irq_desc(irq); @@ -533,7 +569,8 @@ desc->depth--; break; case 0: - printk("enable_irq() unbalanced from %p\n", (void *) __builtin_return_address(0)); + printk("enable_irq(%u) unbalanced from %p\n", + irq, (void *) __builtin_return_address(0)); } spin_unlock_irqrestore(&desc->lock, flags); } @@ -626,11 +663,41 @@ desc->handler->end(irq); spin_unlock(&desc->lock); } - if (local_softirq_pending()) - do_softirq(); return 1; } +/** + * request_irq - allocate an interrupt line + * @irq: Interrupt line to allocate + * @handler: Function to be called when the IRQ occurs + * @irqflags: Interrupt type flags + * @devname: An ascii name for the claiming device + * @dev_id: A cookie passed back to the handler function + * + * This call allocates interrupt resources and enables the + * interrupt line and IRQ handling. From the point this + * call is made your handler function may be invoked. Since + * your handler function must clear any interrupt the board + * raises, you must take care both to initialise your hardware + * and to set up the interrupt handler in the right order. + * + * Dev_id must be globally unique. Normally the address of the + * device data structure is used as the cookie. Since the handler + * receives this value it makes sense to use it. + * + * If your interrupt is shared you must pass a non NULL dev_id + * as this is required when freeing the interrupt. + * + * Flags: + * + * SA_SHIRQ Interrupt is shared + * + * SA_INTERRUPT Disable local interrupts while processing + * + * SA_SAMPLE_RANDOM The interrupt can be used for entropy + * + */ + int request_irq(unsigned int irq, void (*handler)(int, void *, struct pt_regs *), unsigned long irqflags, @@ -676,6 +743,24 @@ return retval; } +/** + * free_irq - free an interrupt + * @irq: Interrupt line to free + * @dev_id: Device identity to free + * + * Remove an interrupt handler. The handler is removed and if the + * interrupt line is no longer in use by any driver it is disabled. + * On a shared IRQ the caller must ensure the interrupt is disabled + * on the card it drives before calling this function. The function + * does not return until any executing interrupts for this IRQ + * have completed. + * + * This function may be called from interrupt context. + * + * Bugs: Attempting to free an irq in a handler for the same irq hangs + * the machine. + */ + void free_irq(unsigned int irq, void *dev_id) { irq_desc_t *desc; @@ -726,6 +811,17 @@ * with "IRQ_WAITING" cleared and the interrupt * disabled. */ + +static DECLARE_MUTEX(probe_sem); + +/** + * probe_irq_on - begin an interrupt autodetect + * + * Commence probing for an interrupt. The interrupts are scanned + * and a mask of potential interrupt lines is returned. + * + */ + unsigned long probe_irq_on(void) { unsigned int i; @@ -733,6 +829,7 @@ unsigned long val; unsigned long delay; + down(&probe_sem); /* * something may have generated an irq long ago and we want to * flush such a longstanding irq before considering it as spurious. @@ -799,10 +896,19 @@ return val; } -/* - * Return a mask of triggered interrupts (this - * can handle only legacy ISA interrupts). +/** + * probe_irq_mask - scan a bitmap of interrupt lines + * @val: mask of interrupts to consider + * + * Scan the ISA bus interrupt lines and return a bitmap of + * active interrupts. The interrupt probe logic state is then + * returned to its previous value. + * + * Note: we need to scan all the irq's even though we will + * only return ISA irq numbers - just so that we reset them + * all to a known state. */ + unsigned int probe_irq_mask(unsigned long val) { int i; @@ -825,14 +931,29 @@ } spin_unlock_irq(&desc->lock); } + up(&probe_sem); return mask & val; } -/* - * Return the one interrupt that triggered (this can - * handle any interrupt source) +/** + * probe_irq_off - end an interrupt autodetect + * @val: mask of potential interrupts (unused) + * + * Scans the unused interrupt lines and returns the line which + * appears to have triggered the interrupt. If no interrupt was + * found then zero is returned. If more than one interrupt is + * found then minus the first candidate is returned to indicate + * their is doubt. + * + * The interrupt probe logic state is returned to its previous + * value. + * + * BUGS: When used in a module (which arguably shouldnt happen) + * nothing prevents two IRQ probe callers from overlapping. The + * results of this are non-optimal. */ + int probe_irq_off(unsigned long val) { int i, irq_found, nr_irqs; @@ -857,6 +978,7 @@ } spin_unlock_irq(&desc->lock); } + up(&probe_sem); if (nr_irqs > 1) irq_found = -irq_found; @@ -911,7 +1033,7 @@ if (!shared) { desc->depth = 0; - desc->status &= ~IRQ_DISABLED; + desc->status &= ~(IRQ_DISABLED | IRQ_AUTODETECT | IRQ_WAITING); desc->handler->startup(irq); } spin_unlock_irqrestore(&desc->lock,flags); @@ -922,20 +1044,9 @@ static struct proc_dir_entry * root_irq_dir; static struct proc_dir_entry * irq_dir [NR_IRQS]; -static struct proc_dir_entry * smp_affinity_entry [NR_IRQS]; - -static unsigned long irq_affinity [NR_IRQS] = { [0 ... NR_IRQS-1] = ~0UL }; #define HEX_DIGITS 8 -static int irq_affinity_read_proc (char *page, char **start, off_t off, - int count, int *eof, void *data) -{ - if (count < HEX_DIGITS+1) - return -EINVAL; - return sprintf (page, "%08lx\n", irq_affinity[(long)data]); -} - static unsigned int parse_hex_value (const char *buffer, unsigned long count, unsigned long *ret) { @@ -973,6 +1084,20 @@ return 0; } +#if CONFIG_SMP + +static struct proc_dir_entry * smp_affinity_entry [NR_IRQS]; + +static unsigned long irq_affinity [NR_IRQS] = { [0 ... NR_IRQS-1] = ~0UL }; + +static int irq_affinity_read_proc (char *page, char **start, off_t off, + int count, int *eof, void *data) +{ + if (count < HEX_DIGITS+1) + return -EINVAL; + return sprintf (page, "%08lx\n", irq_affinity[(long)data]); +} + static int irq_affinity_write_proc (struct file *file, const char *buffer, unsigned long count, void *data) { @@ -984,7 +1109,6 @@ err = parse_hex_value(buffer, count, &new_value); -#if CONFIG_SMP /* * Do not allow disabling IRQs completely - it's a too easy * way to make the system unusable accidentally :-) At least @@ -992,7 +1116,6 @@ */ if (!(new_value & cpu_online_map)) return -EINVAL; -#endif irq_affinity[irq] = new_value; irq_desc(irq)->handler->set_affinity(irq, new_value); @@ -1000,6 +1123,8 @@ return full_count; } +#endif /* CONFIG_SMP */ + static int prof_cpu_mask_read_proc (char *page, char **start, off_t off, int count, int *eof, void *data) { @@ -1027,7 +1152,6 @@ static void register_irq_proc (unsigned int irq) { - struct proc_dir_entry *entry; char name [MAX_NAMELEN]; if (!root_irq_dir || (irq_desc(irq)->handler == &no_irq_type)) @@ -1039,15 +1163,22 @@ /* create /proc/irq/1234 */ irq_dir[irq] = proc_mkdir(name, root_irq_dir); - /* create /proc/irq/1234/smp_affinity */ - entry = create_proc_entry("smp_affinity", 0600, irq_dir[irq]); - - entry->nlink = 1; - entry->data = (void *)(long)irq; - entry->read_proc = irq_affinity_read_proc; - entry->write_proc = irq_affinity_write_proc; +#if CONFIG_SMP + { + struct proc_dir_entry *entry; + /* create /proc/irq/1234/smp_affinity */ + entry = create_proc_entry("smp_affinity", 0600, irq_dir[irq]); + + if (entry) { + entry->nlink = 1; + entry->data = (void *)(long)irq; + entry->read_proc = irq_affinity_read_proc; + entry->write_proc = irq_affinity_write_proc; + } - smp_affinity_entry[irq] = entry; + smp_affinity_entry[irq] = entry; + } +#endif } unsigned long prof_cpu_mask = -1; @@ -1062,6 +1193,9 @@ /* create /proc/irq/prof_cpu_mask */ entry = create_proc_entry("prof_cpu_mask", 0600, root_irq_dir); + + if (!entry) + return; entry->nlink = 1; entry->data = (void *)&prof_cpu_mask; diff -urN linux-2.4.10/arch/ia64/kernel/irq_ia64.c linux-2.4.10-lia/arch/ia64/kernel/irq_ia64.c --- linux-2.4.10/arch/ia64/kernel/irq_ia64.c Tue Jul 31 10:30:08 2001 +++ linux-2.4.10-lia/arch/ia64/kernel/irq_ia64.c Mon Sep 24 21:48:36 2001 @@ -1,9 +1,9 @@ /* * linux/arch/ia64/kernel/irq.c * - * Copyright (C) 1998-2000 Hewlett-Packard Co - * Copyright (C) 1998, 1999 Stephane Eranian - * Copyright (C) 1999-2000 David Mosberger-Tang + * Copyright (C) 1998-2001 Hewlett-Packard Co + * Stephane Eranian + * David Mosberger-Tang * * 6/10/99: Updated to bring in sync with x86 version to facilitate * support for SMP and different interrupt controllers. @@ -131,6 +131,13 @@ ia64_eoi(); vector = ia64_get_ivr(); } + /* + * This must be done *after* the ia64_eoi(). For example, the keyboard softirq + * handler needs to be able to wait for further keyboard interrupts, which can't + * come through until ia64_eoi() has been done. + */ + if (local_softirq_pending()) + do_softirq(); } #ifdef CONFIG_SMP diff -urN linux-2.4.10/arch/ia64/kernel/ivt.S linux-2.4.10-lia/arch/ia64/kernel/ivt.S --- linux-2.4.10/arch/ia64/kernel/ivt.S Tue Jul 31 10:30:08 2001 +++ linux-2.4.10-lia/arch/ia64/kernel/ivt.S Mon Sep 24 21:48:47 2001 @@ -2,8 +2,8 @@ * arch/ia64/kernel/ivt.S * * Copyright (C) 1998-2001 Hewlett-Packard Co - * Copyright (C) 1998, 1999 Stephane Eranian - * Copyright (C) 1998-2001 David Mosberger + * Stephane Eranian + * David Mosberger * * 00/08/23 Asit Mallick TLB handling for SMP * 00/12/20 David Mosberger-Tang DTLB/ITLB handler now uses virtual PT. @@ -157,7 +157,7 @@ ;; (p10) itc.i r18 // insert the instruction TLB entry (p11) itc.d r18 // insert the data TLB entry -(p6) br.spnt.many page_fault // handle bad address/page not present (page fault) +(p6) br.cond.spnt.many page_fault // handle bad address/page not present (page fault) mov cr.ifa=r22 /* @@ -213,7 +213,7 @@ ;; mov b0=r29 tbit.z p6,p0=r18,_PAGE_P_BIT // page present bit cleared? -(p6) br.cond.spnt.many page_fault +(p6) br.cond.spnt page_fault ;; itc.i r18 ;; @@ -251,7 +251,7 @@ ;; mov b0=r29 tbit.z p6,p0=r18,_PAGE_P_BIT // page present bit cleared? -(p6) br.cond.spnt.many page_fault +(p6) br.cond.spnt page_fault ;; itc.d r18 ;; @@ -286,7 +286,7 @@ ;; (p8) mov cr.iha=r17 (p8) mov r29=b0 // save b0 -(p8) br.cond.dptk.many itlb_fault +(p8) br.cond.dptk itlb_fault #endif extr.u r23=r21,IA64_PSR_CPL0_BIT,2 // extract psr.cpl shr.u r18=r16,57 // move address bit 61 to bit 4 @@ -297,7 +297,7 @@ dep r19=r17,r19,0,12 // insert PTE control bits into r19 ;; or r19=r19,r18 // set bit 4 (uncached) if the access was to region 6 -(p8) br.cond.spnt.many page_fault +(p8) br.cond.spnt page_fault ;; itc.i r19 // insert the TLB entry mov pr=r31,-1 @@ -324,7 +324,7 @@ ;; (p8) mov cr.iha=r17 (p8) mov r29=b0 // save b0 -(p8) br.cond.dptk.many dtlb_fault +(p8) br.cond.dptk dtlb_fault #endif extr.u r23=r21,IA64_PSR_CPL0_BIT,2 // extract psr.cpl tbit.nz p6,p7=r20,IA64_ISR_SP_BIT // is speculation bit on? @@ -333,7 +333,7 @@ ;; andcm r18=0x10,r18 // bit 4=~address-bit(61) cmp.ne p8,p0=r0,r23 -(p8) br.cond.spnt.many page_fault +(p8) br.cond.spnt page_fault dep r21=-1,r21,IA64_PSR_ED_BIT,1 dep r19=r17,r19,0,12 // insert PTE control bits into r19 @@ -429,7 +429,7 @@ ;; (p7) cmp.eq.or.andcm p6,p7=r17,r0 // was L2 entry NULL? dep r17=r19,r17,3,(PAGE_SHIFT-3) // compute address of L3 page table entry -(p6) br.cond.spnt.many page_fault +(p6) br.cond.spnt page_fault mov b0=r30 br.sptk.many b0 // return to continuation point END(nested_dtlb_miss) @@ -534,15 +534,6 @@ ;; 1: ld8 r18=[r17] ;; -# if defined(CONFIG_IA32_SUPPORT) && defined(CONFIG_ITANIUM_B0_SPECIFIC) - /* - * Erratum 85 (Access bit fault could be reported before page not present fault) - * If the PTE is indicates the page is not present, then just turn this into a - * page fault. - */ - tbit.z p6,p0=r18,_PAGE_P_BIT // page present bit cleared? -(p6) br.sptk page_fault // page wasn't present -# endif mov ar.ccv=r18 // set compare value for cmpxchg or r25=_PAGE_A,r18 // set the accessed bit ;; @@ -564,15 +555,6 @@ ;; 1: ld8 r18=[r17] ;; -# if defined(CONFIG_IA32_SUPPORT) && defined(CONFIG_ITANIUM_B0_SPECIFIC) - /* - * Erratum 85 (Access bit fault could be reported before page not present fault) - * If the PTE is indicates the page is not present, then just turn this into a - * page fault. - */ - tbit.z p6,p0=r18,_PAGE_P_BIT // page present bit cleared? -(p6) br.sptk page_fault // page wasn't present -# endif or r18=_PAGE_A,r18 // set the accessed bit mov b0=r29 // restore b0 ;; @@ -640,7 +622,7 @@ mov r31=pr // prepare to save predicates ;; cmp.eq p0,p7=r16,r17 // is this a system call? (p7 <- false, if so) -(p7) br.cond.spnt.many non_syscall +(p7) br.cond.spnt non_syscall SAVE_MIN // uses r31; defines r2: @@ -656,7 +638,7 @@ adds r3=8,r2 // set up second base pointer for SAVE_REST ;; SAVE_REST - br.call.sptk rp=demine_args // clear NaT bits in (potential) syscall args + br.call.sptk.many rp=demine_args // clear NaT bits in (potential) syscall args mov r3=255 adds r15=-1024,r15 // r15 contains the syscall number---subtract 1024 @@ -698,7 +680,7 @@ st8 [r16]=r18 // store new value for cr.isr (p8) br.call.sptk.many b6=b6 // ignore this return addr - br.cond.sptk.many ia64_trace_syscall + br.cond.sptk ia64_trace_syscall // NOT REACHED END(break_fault) @@ -811,8 +793,8 @@ mov b6=r8 ;; cmp.ne p6,p0=0,r8 -(p6) br.call.dpnt b6=b6 // call returns to ia64_leave_kernel - br.sptk ia64_leave_kernel +(p6) br.call.dpnt.many b6=b6 // call returns to ia64_leave_kernel + br.sptk.many ia64_leave_kernel END(dispatch_illegal_op_fault) .align 1024 @@ -855,12 +837,12 @@ adds r15=IA64_PT_REGS_R1_OFFSET + 16,sp ;; cmp.eq pSys,pNonSys=r0,r0 // set pSys=1, pNonSys=0 - st8 [r15]=r8 // save orignal EAX in r1 (IA32 procs don't use the GP) + st8 [r15]=r8 // save original EAX in r1 (IA32 procs don't use the GP) ;; alloc r15=ar.pfs,0,0,6,0 // must first in an insn group ;; ld4 r8=[r14],8 // r8 == EAX (syscall number) - mov r15=222 // sys_vfork - last implemented system call + mov r15=222 // last entry in system call table ;; cmp.leu.unc p6,p7=r8,r15 ld4 out1=[r14],8 // r9 == ecx @@ -889,7 +871,7 @@ ;; mov rp=r15 (p8) br.call.sptk.many b6=b6 - br.cond.sptk.many ia32_trace_syscall + br.cond.sptk ia32_trace_syscall non_ia32_syscall: alloc r15=ar.pfs,0,0,2,0 @@ -1085,7 +1067,7 @@ mov r31=pr ;; cmp4.eq p6,p0=0,r16 -(p6) br.sptk dispatch_illegal_op_fault +(p6) br.sptk.many dispatch_illegal_op_fault ;; mov r19=24 // fault number br.sptk.many dispatch_to_fault_handler diff -urN linux-2.4.10/arch/ia64/kernel/mca.c linux-2.4.10-lia/arch/ia64/kernel/mca.c --- linux-2.4.10/arch/ia64/kernel/mca.c Tue Jul 31 10:30:08 2001 +++ linux-2.4.10-lia/arch/ia64/kernel/mca.c Mon Sep 24 21:49:34 2001 @@ -3,12 +3,20 @@ * Purpose: Generic MCA handling layer * * Updated for latest kernel + * Copyright (C) 2001 Intel + * Copyright (C) Fred Lewis (frederick.v.lewis@intel.com) + * * Copyright (C) 2000 Intel * Copyright (C) Chuck Fleckenstein (cfleck@co.intel.com) * * Copyright (C) 1999 Silicon Graphics, Inc. * Copyright (C) Vijay Chander(vijay@engr.sgi.com) * + * 01/01/03 F. Lewis Added setup of CMCI and CPEI IRQs, logging of corrected + * platform errors, completed code for logging of + * corrected & uncorrected machine check errors, and + * updated for conformance with Nov. 2000 revision of the + * SAL 3.0 spec. * 00/03/29 C. Fleckenstein Fixed PAL/SAL update issues, began MCA bug fixes, logging issues, * added min save state dump, added INIT handler. */ @@ -16,6 +24,7 @@ #include #include #include +#include #include #include @@ -27,8 +36,10 @@ #include #include -#include +#include +#include +#define MCA_PRT_XTRA_DATA // Uncomment to printer headers and dumps typedef struct ia64_fptr { unsigned long fp; @@ -38,22 +49,67 @@ ia64_mc_info_t ia64_mc_info; ia64_mca_sal_to_os_state_t ia64_sal_to_os_handoff_state; ia64_mca_os_to_sal_state_t ia64_os_to_sal_handoff_state; -u64 ia64_mca_proc_state_dump[256]; +u64 ia64_mca_proc_state_dump[512]; u64 ia64_mca_stack[1024]; u64 ia64_mca_stackframe[32]; u64 ia64_mca_bspstore[1024]; u64 ia64_init_stack[INIT_TASK_SIZE] __attribute__((aligned(16))); -static void ia64_mca_cmc_vector_setup(int enable, - int_vector_t cmc_vector); static void ia64_mca_wakeup_ipi_wait(void); static void ia64_mca_wakeup(int cpu); static void ia64_mca_wakeup_all(void); -static void ia64_log_init(int,int); -static void ia64_log_get(int,int, prfunc_t); -static void ia64_log_clear(int,int,int, prfunc_t); +static void ia64_log_init(int); extern void ia64_monarch_init_handler (void); extern void ia64_slave_init_handler (void); +extern struct hw_interrupt_type irq_type_iosapic_level; + +static struct irqaction cmci_irqaction = { + handler: ia64_mca_cmc_int_handler, + flags: SA_INTERRUPT, + name: "cmc_hndlr" +}; + +static struct irqaction mca_rdzv_irqaction = { + handler: ia64_mca_rendez_int_handler, + flags: SA_INTERRUPT, + name: "mca_rdzv" +}; + +static struct irqaction mca_wkup_irqaction = { + handler: ia64_mca_wakeup_int_handler, + flags: SA_INTERRUPT, + name: "mca_wkup" +}; + +static struct irqaction mca_cpe_irqaction = { + handler: ia64_mca_cpe_int_handler, + flags: SA_INTERRUPT, + name: "cpe_hndlr" +}; + +/* + * ia64_mca_log_sal_error_record + * + * This function retrieves a specified error record type from SAL, sends it to + * the system log, and notifies SALs to clear the record from its non-volatile + * memory. + * + * Inputs : sal_info_type (Type of error record MCA/CMC/CPE/INIT) + * Outputs : None + */ +void +ia64_mca_log_sal_error_record(int sal_info_type) +{ + /* Get the MCA error record */ + if (!ia64_log_get(sal_info_type, (prfunc_t)printk)) + return; // no record retrieved + + /* Log the error record */ + ia64_log_print(sal_info_type, (prfunc_t)printk); + + /* Clear the CMC SAL logs now that they have been logged */ + ia64_sal_clear_state_info(sal_info_type); +} /* * hack for now, add platform dependent handlers @@ -67,10 +123,14 @@ } void -cmci_handler_platform (int cmc_irq, void *arg, struct pt_regs *ptregs) +ia64_mca_cpe_int_handler (int cpe_irq, void *arg, struct pt_regs *ptregs) { + IA64_MCA_DEBUG("ia64_mca_cpe_int_handler: received interrupt. vector = %#x\n", cpe_irq); + /* Get the CMC error record and log it */ + ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CPE); } + /* * This routine will be used to deal with platform specific handling * of the init, i.e. drop into the kernel debugger on server machine, @@ -81,17 +141,72 @@ init_handler_platform (struct pt_regs *regs) { /* if a kernel debugger is available call it here else just dump the registers */ + show_regs(regs); /* dump the state info */ + while (1); /* hang city if no debugger */ } +/* + * ia64_mca_init_platform + * + * External entry for platform specific MCA initialization. + * + * Inputs + * None + * + * Outputs + * None + */ void -log_print_platform ( void *cur_buff_ptr, prfunc_t prfunc) +ia64_mca_init_platform (void) { + } +/* + * ia64_mca_check_errors + * + * External entry to check for error records which may have been posted by SAL + * for a prior failure which resulted in a machine shutdown before an the + * error could be logged. This function must be called after the filesystem + * is initialized. + * + * Inputs : None + * + * Outputs : None + */ void -ia64_mca_init_platform (void) +ia64_mca_check_errors (void) { + /* + * If there is an MCA error record pending, get it and log it. + */ + ia64_mca_log_sal_error_record(SAL_INFO_TYPE_MCA); +} + +/* + * ia64_mca_register_cpev + * + * Register the corrected platform error vector with SAL. + * + * Inputs + * cpev Corrected Platform Error Vector number + * + * Outputs + * None + */ +static void +ia64_mca_register_cpev (int cpev) +{ + /* Register the CPE interrupt vector with SAL */ + if (ia64_sal_mc_set_params(SAL_MC_PARAM_CPE_INT, SAL_MC_PARAM_MECHANISM_INT, cpev, 0, 0)) { + printk("ia64_mca_platform_init: failed to register Corrected " + "Platform Error interrupt vector with SAL.\n"); + return; + } + + IA64_MCA_DEBUG("ia64_mca_platform_init: corrected platform error " + "vector %#x setup and enabled\n", cpev); } #endif /* PLATFORM_MCA_HANDLERS */ @@ -140,30 +255,36 @@ && !ia64_pmss_dump_bank0)) printk("\n"); } - /* hang city for now, until we include debugger or copy to ptregs to show: */ - while (1); } /* * ia64_mca_cmc_vector_setup - * Setup the correctable machine check vector register in the processor + * + * Setup the corrected machine check vector register in the processor and + * unmask interrupt. This function is invoked on a per-processor basis. + * * Inputs - * Enable (1 - enable cmc interrupt , 0 - disable) - * CMC handler entry point (if enabled) + * None * * Outputs * None */ -static void -ia64_mca_cmc_vector_setup(int enable, - int_vector_t cmc_vector) +void +ia64_mca_cmc_vector_setup (void) { cmcv_reg_t cmcv; cmcv.cmcv_regval = 0; - cmcv.cmcv_mask = enable; - cmcv.cmcv_vector = cmc_vector; + cmcv.cmcv_mask = 0; /* Unmask/enable interrupt */ + cmcv.cmcv_vector = IA64_CMC_VECTOR; ia64_set_cmcv(cmcv.cmcv_regval); + + IA64_MCA_DEBUG("ia64_mca_platform_init: CPU %d corrected " + "machine check vector %#x setup and enabled.\n", + smp_processor_id(), IA64_CMC_VECTOR); + + IA64_MCA_DEBUG("ia64_mca_platform_init: CPU %d CMCV = %#016lx\n", + smp_processor_id(), ia64_get_cmcv()); } @@ -174,26 +295,58 @@ void mca_test(void) { - slpi_buf.slpi_valid.slpi_psi = 1; - slpi_buf.slpi_valid.slpi_cache_check = 1; - slpi_buf.slpi_valid.slpi_tlb_check = 1; - slpi_buf.slpi_valid.slpi_bus_check = 1; - slpi_buf.slpi_valid.slpi_minstate = 1; - slpi_buf.slpi_valid.slpi_bank1_gr = 1; - slpi_buf.slpi_valid.slpi_br = 1; - slpi_buf.slpi_valid.slpi_cr = 1; - slpi_buf.slpi_valid.slpi_ar = 1; - slpi_buf.slpi_valid.slpi_rr = 1; - slpi_buf.slpi_valid.slpi_fr = 1; + slpi_buf.valid.psi_static_struct = 1; + slpi_buf.valid.num_cache_check = 1; + slpi_buf.valid.num_tlb_check = 1; + slpi_buf.valid.num_bus_check = 1; + slpi_buf.valid.processor_static_info.minstate = 1; + slpi_buf.valid.processor_static_info.br = 1; + slpi_buf.valid.processor_static_info.cr = 1; + slpi_buf.valid.processor_static_info.ar = 1; + slpi_buf.valid.processor_static_info.rr = 1; + slpi_buf.valid.processor_static_info.fr = 1; ia64_os_mca_dispatch(); } #endif /* #if defined(MCA_TEST) */ + +/* + * verify_guid + * + * Compares a test guid to a target guid and returns result. + * + * Inputs + * test_guid * (ptr to guid to be verified) + * target_guid * (ptr to standard guid to be verified against) + * + * Outputs + * 0 (test verifies against target) + * non-zero (test guid does not verify) + */ +static int +verify_guid (efi_guid_t *test, efi_guid_t *target) +{ + int rc; + + if ((rc = memcmp((void *)test, (void *)target, sizeof(efi_guid_t)))) { + IA64_MCA_DEBUG("ia64_mca_print: invalid guid = " + "{ %08x, %04x, %04x, { %#02x, %#02x, %#02x, %#02x, " + "%#02x, %#02x, %#02x, %#02x, } } \n ", + test->data1, test->data2, test->data3, test->data4[0], + test->data4[1], test->data4[2], test->data4[3], + test->data4[4], test->data4[5], test->data4[6], + test->data4[7]); + } + + return rc; +} + /* * ia64_mca_init - * Do all the mca specific initialization on a per-processor basis. + * + * Do all the system level mca specific initialization. * * 1. Register spinloop and wakeup request interrupt vectors * @@ -201,77 +354,80 @@ * * 3. Register OS_INIT handler entry point * - * 4. Initialize CMCV register to enable/disable CMC interrupt on the - * processor and hook a handler in the platform-specific ia64_mca_init. + * 4. Initialize MCA/CMC/INIT related log buffers maintained by the OS. * - * 5. Initialize MCA/CMC/INIT related log buffers maintained by the OS. + * Note that this initialization is done very early before some kernel + * services are available. * - * Inputs - * None - * Outputs - * None + * Inputs : None + * + * Outputs : None */ void __init ia64_mca_init(void) { ia64_fptr_t *mon_init_ptr = (ia64_fptr_t *)ia64_monarch_init_handler; ia64_fptr_t *slave_init_ptr = (ia64_fptr_t *)ia64_slave_init_handler; + ia64_fptr_t *mca_hldlr_ptr = (ia64_fptr_t *)ia64_os_mca_dispatch; int i; + s64 rc; - IA64_MCA_DEBUG("ia64_mca_init : begin\n"); + IA64_MCA_DEBUG("ia64_mca_init: begin\n"); /* Clear the Rendez checkin flag for all cpus */ - for(i = 0 ; i < IA64_MAXCPUS; i++) + for(i = 0 ; i < NR_CPUS; i++) ia64_mc_info.imi_rendez_checkin[i] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE; - /* NOTE : The actual irqs for the rendez, wakeup and - * cmc interrupts are requested in the platform-specific - * mca initialization code. - */ /* * Register the rendezvous spinloop and wakeup mechanism with SAL */ /* Register the rendezvous interrupt vector with SAL */ - if (ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_INT, - SAL_MC_PARAM_MECHANISM_INT, - IA64_MCA_RENDEZ_VECTOR, - IA64_MCA_RENDEZ_TIMEOUT, - 0)) + if ((rc = ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_INT, + SAL_MC_PARAM_MECHANISM_INT, + IA64_MCA_RENDEZ_VECTOR, + IA64_MCA_RENDEZ_TIMEOUT, + 0))) + { + printk("ia64_mca_init: Failed to register rendezvous interrupt " + "with SAL. rc = %ld\n", rc); return; + } /* Register the wakeup interrupt vector with SAL */ - if (ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_WAKEUP, - SAL_MC_PARAM_MECHANISM_INT, - IA64_MCA_WAKEUP_VECTOR, - 0, - 0)) + if ((rc = ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_WAKEUP, + SAL_MC_PARAM_MECHANISM_INT, + IA64_MCA_WAKEUP_VECTOR, + 0, 0))) + { + printk("ia64_mca_init: Failed to register wakeup interrupt with SAL. rc = %ld\n", + rc); return; + } - IA64_MCA_DEBUG("ia64_mca_init : registered mca rendezvous spinloop and wakeup mech.\n"); - /* - * Setup the correctable machine check vector - */ - ia64_mca_cmc_vector_setup(IA64_CMC_INT_ENABLE, IA64_CMC_VECTOR); - - IA64_MCA_DEBUG("ia64_mca_init : correctable mca vector setup done\n"); + IA64_MCA_DEBUG("ia64_mca_init: registered mca rendezvous spinloop and wakeup mech.\n"); - ia64_mc_info.imi_mca_handler = __pa(ia64_os_mca_dispatch); + ia64_mc_info.imi_mca_handler = __pa(mca_hldlr_ptr->fp); /* * XXX - disable SAL checksum by setting size to 0; should be * __pa(ia64_os_mca_dispatch_end) - __pa(ia64_os_mca_dispatch); */ ia64_mc_info.imi_mca_handler_size = 0; - /* Register the os mca handler with SAL */ - if (ia64_sal_set_vectors(SAL_VECTOR_OS_MCA, - ia64_mc_info.imi_mca_handler, - __pa(ia64_get_gp()), - ia64_mc_info.imi_mca_handler_size, - 0,0,0)) + /* Register the os mca handler with SAL */ + if ((rc = ia64_sal_set_vectors(SAL_VECTOR_OS_MCA, + ia64_mc_info.imi_mca_handler, + mca_hldlr_ptr->gp, + ia64_mc_info.imi_mca_handler_size, + 0, 0, 0))) + { + printk("ia64_mca_init: Failed to register os mca handler with SAL. rc = %ld\n", + rc); return; + } - IA64_MCA_DEBUG("ia64_mca_init : registered os mca handler with SAL\n"); + IA64_MCA_DEBUG("ia64_mca_init: registered os mca handler with SAL at 0x%lx, gp = 0x%lx\n", + ia64_mc_info.imi_mca_handler, mca_hldlr_ptr->gp); /* * XXX - disable SAL checksum by setting size to 0, should be @@ -282,53 +438,87 @@ ia64_mc_info.imi_slave_init_handler = __pa(slave_init_ptr->fp); ia64_mc_info.imi_slave_init_handler_size = 0; - IA64_MCA_DEBUG("ia64_mca_init : os init handler at %lx\n",ia64_mc_info.imi_monarch_init_handler); + IA64_MCA_DEBUG("ia64_mca_init: os init handler at %lx\n", + ia64_mc_info.imi_monarch_init_handler); /* Register the os init handler with SAL */ - if (ia64_sal_set_vectors(SAL_VECTOR_OS_INIT, - ia64_mc_info.imi_monarch_init_handler, - __pa(ia64_get_gp()), - ia64_mc_info.imi_monarch_init_handler_size, - ia64_mc_info.imi_slave_init_handler, - __pa(ia64_get_gp()), - ia64_mc_info.imi_slave_init_handler_size)) + if ((rc = ia64_sal_set_vectors(SAL_VECTOR_OS_INIT, + ia64_mc_info.imi_monarch_init_handler, + __pa(ia64_get_gp()), + ia64_mc_info.imi_monarch_init_handler_size, + ia64_mc_info.imi_slave_init_handler, + __pa(ia64_get_gp()), + ia64_mc_info.imi_slave_init_handler_size))) + { + printk("ia64_mca_init: Failed to register m/s init handlers with SAL. rc = %ld\n", + rc); + return; + } + IA64_MCA_DEBUG("ia64_mca_init: registered os init handler with SAL\n"); - return; + /* + * Configure the CMCI vector and handler. Interrupts for CMC are + * per-processor, so AP CMC interrupts are setup in smp_callin() (smp.c). + */ + register_percpu_irq(IA64_CMC_VECTOR, &cmci_irqaction); + ia64_mca_cmc_vector_setup(); /* Setup vector on BSP & enable */ - IA64_MCA_DEBUG("ia64_mca_init : registered os init handler with SAL\n"); + /* Setup the MCA rendezvous interrupt vector */ + register_percpu_irq(IA64_MCA_RENDEZ_VECTOR, &mca_rdzv_irqaction); + + /* Setup the MCA wakeup interrupt vector */ + register_percpu_irq(IA64_MCA_WAKEUP_VECTOR, &mca_wkup_irqaction); + + /* Setup the CPE interrupt vector */ + { + irq_desc_t *desc; + unsigned int irq; + int cpev = acpi_request_vector(ACPI20_ENTRY_PIS_CPEI); + + if (cpev >= 0) { + for (irq = 0; irq < NR_IRQS; ++irq) + if (irq_to_vector(irq) == cpev) { + desc = irq_desc(irq); + desc->status |= IRQ_PER_CPU; + desc->handler = &irq_type_iosapic_level; + setup_irq(irq, &mca_cpe_irqaction); + } + ia64_mca_register_cpev(cpev); + } else + printk("ia64_mca_init: Failed to get routed CPEI vector from ACPI.\n"); + } /* Initialize the areas set aside by the OS to buffer the * platform/processor error states for MCA/INIT/CMC * handling. */ - ia64_log_init(SAL_INFO_TYPE_MCA, SAL_SUB_INFO_TYPE_PROCESSOR); - ia64_log_init(SAL_INFO_TYPE_MCA, SAL_SUB_INFO_TYPE_PLATFORM); - ia64_log_init(SAL_INFO_TYPE_INIT, SAL_SUB_INFO_TYPE_PROCESSOR); - ia64_log_init(SAL_INFO_TYPE_INIT, SAL_SUB_INFO_TYPE_PLATFORM); - ia64_log_init(SAL_INFO_TYPE_CMC, SAL_SUB_INFO_TYPE_PROCESSOR); - ia64_log_init(SAL_INFO_TYPE_CMC, SAL_SUB_INFO_TYPE_PLATFORM); - - ia64_mca_init_platform(); - - IA64_MCA_DEBUG("ia64_mca_init : platform-specific mca handling setup done\n"); + ia64_log_init(SAL_INFO_TYPE_MCA); + ia64_log_init(SAL_INFO_TYPE_INIT); + ia64_log_init(SAL_INFO_TYPE_CMC); + ia64_log_init(SAL_INFO_TYPE_CPE); #if defined(MCA_TEST) mca_test(); #endif /* #if defined(MCA_TEST) */ printk("Mca related initialization done\n"); + +#if 0 // Too early in initialization -- error log is lost + /* Do post-failure MCA error logging */ + ia64_mca_check_errors(); +#endif // Too early in initialization -- error log is lost } /* * ia64_mca_wakeup_ipi_wait + * * Wait for the inter-cpu interrupt to be sent by the * monarch processor once it is done with handling the * MCA. - * Inputs - * None - * Outputs - * None + * + * Inputs : None + * Outputs : None */ void ia64_mca_wakeup_ipi_wait(void) @@ -339,16 +529,16 @@ do { switch(irr_num) { - case 0: + case 0: irr = ia64_get_irr0(); break; - case 1: + case 1: irr = ia64_get_irr1(); break; - case 2: + case 2: irr = ia64_get_irr2(); break; - case 3: + case 3: irr = ia64_get_irr3(); break; } @@ -357,26 +547,28 @@ /* * ia64_mca_wakeup + * * Send an inter-cpu interrupt to wake-up a particular cpu * and mark that cpu to be out of rendez. - * Inputs - * cpuid - * Outputs - * None + * + * Inputs : cpuid + * Outputs : None */ void ia64_mca_wakeup(int cpu) { platform_send_ipi(cpu, IA64_MCA_WAKEUP_VECTOR, IA64_IPI_DM_INT, 0); ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE; + } + /* * ia64_mca_wakeup_all + * * Wakeup all the cpus which have rendez'ed previously. - * Inputs - * None - * Outputs - * None + * + * Inputs : None + * Outputs : None */ void ia64_mca_wakeup_all(void) @@ -389,15 +581,16 @@ ia64_mca_wakeup(cpu); } + /* * ia64_mca_rendez_interrupt_handler + * * This is handler used to put slave processors into spinloop * while the monarch processor does the mca handling and later * wake each slave up once the monarch is done. - * Inputs - * None - * Outputs - * None + * + * Inputs : None + * Outputs : None */ void ia64_mca_rendez_int_handler(int rendez_irq, void *arg, struct pt_regs *ptregs) @@ -423,23 +616,22 @@ /* Enable all interrupts */ restore_flags(flags); - - } /* * ia64_mca_wakeup_int_handler + * * The interrupt handler for processing the inter-cpu interrupt to the * slave cpu which was spinning in the rendez loop. * Since this spinning is done by turning off the interrupts and * polling on the wakeup-interrupt bit in the IRR, there is * nothing useful to be done in the handler. - * Inputs - * wakeup_irq (Wakeup-interrupt bit) + * + * Inputs : wakeup_irq (Wakeup-interrupt bit) * arg (Interrupt handler specific argument) * ptregs (Exception frame at the time of the interrupt) - * Outputs + * Outputs : None * */ void @@ -450,16 +642,16 @@ /* * ia64_return_to_sal_check + * * This is function called before going back from the OS_MCA handler * to the OS_MCA dispatch code which finally takes the control back * to the SAL. * The main purpose of this routine is to setup the OS_MCA to SAL * return state which can be used by the OS_MCA dispatch code * just before going back to SAL. - * Inputs - * None - * Outputs - * None + * + * Inputs : None + * Outputs : None */ void @@ -474,11 +666,13 @@ ia64_os_to_sal_handoff_state.imots_sal_check_ra = ia64_sal_to_os_handoff_state.imsto_sal_check_ra; - /* For now ignore the MCA */ - ia64_os_to_sal_handoff_state.imots_os_status = IA64_MCA_CORRECTED; + /* Cold Boot for uncorrectable MCA */ + ia64_os_to_sal_handoff_state.imots_os_status = IA64_MCA_COLD_BOOT; } + /* * ia64_mca_ucmc_handler + * * This is uncorrectable machine check handler called from OS_MCA * dispatch code which is in turn called from SAL_CHECK(). * This is the place where the core of OS MCA handling is done. @@ -487,93 +681,92 @@ * monarch processor. Once the monarch is done with MCA handling * further MCA logging is enabled by clearing logs. * Monarch also has the duty of sending wakeup-IPIs to pull the - * slave processors out of rendez. spinloop. - * Inputs - * None - * Outputs - * None + * slave processors out of rendezvous spinloop. + * + * Inputs : None + * Outputs : None */ void ia64_mca_ucmc_handler(void) { +#if 0 /* stubbed out @FVL */ + /* + * Attempting to log a DBE error Causes "reserved register/field panic" + * in printk. + */ - /* Get the MCA processor log */ - ia64_log_get(SAL_INFO_TYPE_MCA, SAL_SUB_INFO_TYPE_PROCESSOR, (prfunc_t)printk); - /* Get the MCA platform log */ - ia64_log_get(SAL_INFO_TYPE_MCA, SAL_SUB_INFO_TYPE_PLATFORM, (prfunc_t)printk); - - ia64_log_print(SAL_INFO_TYPE_MCA, SAL_SUB_INFO_TYPE_PROCESSOR, (prfunc_t)printk); + /* Get the MCA error record and log it */ + ia64_mca_log_sal_error_record(SAL_INFO_TYPE_MCA); +#endif /* stubbed out @FVL */ /* - * Do some error handling - Platform-specific mca handler is called at this point + * Do Platform-specific mca error handling if required. */ - mca_handler_platform() ; - /* Clear the SAL MCA logs */ - ia64_log_clear(SAL_INFO_TYPE_MCA, SAL_SUB_INFO_TYPE_PROCESSOR, 1, printk); - ia64_log_clear(SAL_INFO_TYPE_MCA, SAL_SUB_INFO_TYPE_PLATFORM, 1, printk); - - /* Wakeup all the processors which are spinning in the rendezvous - * loop. + /* + * Wakeup all the processors which are spinning in the rendezvous + * loop. */ ia64_mca_wakeup_all(); + + /* Return to SAL */ ia64_return_to_sal_check(); } /* * ia64_mca_cmc_int_handler - * This is correctable machine check interrupt handler. + * + * This is corrected machine check interrupt handler. * Right now the logs are extracted and displayed in a well-defined * format. + * * Inputs - * None + * interrupt number + * client data arg ptr + * saved registers ptr + * * Outputs * None */ void ia64_mca_cmc_int_handler(int cmc_irq, void *arg, struct pt_regs *ptregs) { - /* Get the CMC processor log */ - ia64_log_get(SAL_INFO_TYPE_CMC, SAL_SUB_INFO_TYPE_PROCESSOR, (prfunc_t)printk); - /* Get the CMC platform log */ - ia64_log_get(SAL_INFO_TYPE_CMC, SAL_SUB_INFO_TYPE_PLATFORM, (prfunc_t)printk); - - - ia64_log_print(SAL_INFO_TYPE_CMC, SAL_SUB_INFO_TYPE_PROCESSOR, (prfunc_t)printk); - cmci_handler_platform(cmc_irq, arg, ptregs); + IA64_MCA_DEBUG("ia64_mca_cmc_int_handler: received interrupt vector = %#x on CPU %d\n", + cmc_irq, smp_processor_id()); - /* Clear the CMC SAL logs now that they have been saved in the OS buffer */ - ia64_sal_clear_state_info(SAL_INFO_TYPE_CMC); + /* Get the CMC error record and log it */ + ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CMC); } /* * IA64_MCA log support */ #define IA64_MAX_LOGS 2 /* Double-buffering for nested MCAs */ -#define IA64_MAX_LOG_TYPES 3 /* MCA, CMC, INIT */ -#define IA64_MAX_LOG_SUBTYPES 2 /* Processor, Platform */ +#define IA64_MAX_LOG_TYPES 4 /* MCA, INIT, CMC, CPE */ -typedef struct ia64_state_log_s { +typedef struct ia64_state_log_s +{ spinlock_t isl_lock; int isl_index; - ia64_psilog_t isl_log[IA64_MAX_LOGS]; /* need space to store header + error log */ + ia64_err_rec_t isl_log[IA64_MAX_LOGS]; /* need space to store header + error log */ } ia64_state_log_t; -static ia64_state_log_t ia64_state_log[IA64_MAX_LOG_TYPES][IA64_MAX_LOG_SUBTYPES]; +static ia64_state_log_t ia64_state_log[IA64_MAX_LOG_TYPES]; -#define IA64_LOG_LOCK_INIT(it, sit) spin_lock_init(&ia64_state_log[it][sit].isl_lock) -#define IA64_LOG_LOCK(it, sit) spin_lock_irqsave(&ia64_state_log[it][sit].isl_lock, s) -#define IA64_LOG_UNLOCK(it, sit) spin_unlock_irqrestore(&ia64_state_log[it][sit].isl_lock,\ - s) -#define IA64_LOG_NEXT_INDEX(it, sit) ia64_state_log[it][sit].isl_index -#define IA64_LOG_CURR_INDEX(it, sit) 1 - ia64_state_log[it][sit].isl_index -#define IA64_LOG_INDEX_INC(it, sit) \ - ia64_state_log[it][sit].isl_index = 1 - ia64_state_log[it][sit].isl_index -#define IA64_LOG_INDEX_DEC(it, sit) \ - ia64_state_log[it][sit].isl_index = 1 - ia64_state_log[it][sit].isl_index -#define IA64_LOG_NEXT_BUFFER(it, sit) (void *)(&(ia64_state_log[it][sit].isl_log[IA64_LOG_NEXT_INDEX(it,sit)])) -#define IA64_LOG_CURR_BUFFER(it, sit) (void *)(&(ia64_state_log[it][sit].isl_log[IA64_LOG_CURR_INDEX(it,sit)])) +/* Note: Some of these macros assume IA64_MAX_LOGS is always 2. Should be */ +/* fixed. @FVL */ +#define IA64_LOG_LOCK_INIT(it) spin_lock_init(&ia64_state_log[it].isl_lock) +#define IA64_LOG_LOCK(it) spin_lock_irqsave(&ia64_state_log[it].isl_lock, s) +#define IA64_LOG_UNLOCK(it) spin_unlock_irqrestore(&ia64_state_log[it].isl_lock,s) +#define IA64_LOG_NEXT_INDEX(it) ia64_state_log[it].isl_index +#define IA64_LOG_CURR_INDEX(it) 1 - ia64_state_log[it].isl_index +#define IA64_LOG_INDEX_INC(it) \ + ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index +#define IA64_LOG_INDEX_DEC(it) \ + ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index +#define IA64_LOG_NEXT_BUFFER(it) (void *)(&(ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)])) +#define IA64_LOG_CURR_BUFFER(it) (void *)(&(ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)])) /* * C portion of the OS INIT handler @@ -584,123 +777,216 @@ * * Returns: * 0 if SAL must warm boot the System - * 1 if SAL must retrun to interrupted context using PAL_MC_RESUME + * 1 if SAL must return to interrupted context using PAL_MC_RESUME * */ - void ia64_init_handler (struct pt_regs *regs) { sal_log_processor_info_t *proc_ptr; - ia64_psilog_t *plog_ptr; + ia64_err_rec_t *plog_ptr; printk("Entered OS INIT handler\n"); /* Get the INIT processor log */ - ia64_log_get(SAL_INFO_TYPE_INIT, SAL_SUB_INFO_TYPE_PROCESSOR, (prfunc_t)printk); - /* Get the INIT platform log */ - ia64_log_get(SAL_INFO_TYPE_INIT, SAL_SUB_INFO_TYPE_PLATFORM, (prfunc_t)printk); + if (!ia64_log_get(SAL_INFO_TYPE_INIT, (prfunc_t)printk)) + return; // no record retrieved #ifdef IA64_DUMP_ALL_PROC_INFO - ia64_log_print(SAL_INFO_TYPE_INIT, SAL_SUB_INFO_TYPE_PROCESSOR, (prfunc_t)printk); + ia64_log_print(SAL_INFO_TYPE_INIT, (prfunc_t)printk); #endif /* * get pointer to min state save area * */ - plog_ptr=(ia64_psilog_t *)IA64_LOG_CURR_BUFFER(SAL_INFO_TYPE_INIT, - SAL_SUB_INFO_TYPE_PROCESSOR); - proc_ptr = &plog_ptr->devlog.proclog; + plog_ptr=(ia64_err_rec_t *)IA64_LOG_CURR_BUFFER(SAL_INFO_TYPE_INIT); + proc_ptr = &plog_ptr->proc_err; - ia64_process_min_state_save(&proc_ptr->slpi_min_state_area,regs); - - init_handler_platform(regs); /* call platform specific routines */ + ia64_process_min_state_save(&proc_ptr->processor_static_info.min_state_area, + regs); /* Clear the INIT SAL logs now that they have been saved in the OS buffer */ ia64_sal_clear_state_info(SAL_INFO_TYPE_INIT); + + init_handler_platform(regs); /* call platform specific routines */ } /* + * ia64_log_prt_guid + * + * Print a formatted GUID. + * + * Inputs : p_guid (ptr to the GUID) + * prfunc (print function) + * Outputs : None + * + */ +void +ia64_log_prt_guid (efi_guid_t *p_guid, prfunc_t prfunc) +{ + printk("GUID = { %08x, %04x, %04x, { %#02x, %#02x, %#02x, %#02x, " + "%#02x, %#02x, %#02x, %#02x, } } \n ", p_guid->data1, + p_guid->data2, p_guid->data3, p_guid->data4[0], p_guid->data4[1], + p_guid->data4[2], p_guid->data4[3], p_guid->data4[4], + p_guid->data4[5], p_guid->data4[6], p_guid->data4[7]); +} + +#ifdef MCA_PRT_XTRA_DATA // for test only @FVL +static void +ia64_log_hexdump(unsigned char *p, unsigned long n_ch, prfunc_t prfunc) +{ + int i, j; + + if (!p) + return; + + for (i = 0; i < n_ch;) { + prfunc("%p ", (void *)p); + for (j = 0; (j < 16) && (i < n_ch); i++, j++, p++) { + prfunc("%02x ", *p); + } + prfunc("\n"); + } +} + +static void +ia64_log_prt_record_header (sal_log_record_header_t *rh, prfunc_t prfunc) +{ + prfunc("SAL RECORD HEADER: Record buffer = %p, header size = %ld\n", + (void *)rh, sizeof(sal_log_record_header_t)); + ia64_log_hexdump((unsigned char *)rh, sizeof(sal_log_record_header_t), + (prfunc_t)prfunc); + prfunc("Total record length = %d\n", rh->len); + ia64_log_prt_guid(&rh->platform_guid, prfunc); + prfunc("End of SAL RECORD HEADER\n"); +} + +static void +ia64_log_prt_section_header (sal_log_section_hdr_t *sh, prfunc_t prfunc) +{ + prfunc("SAL SECTION HEADER: Record buffer = %p, header size = %ld\n", + (void *)sh, sizeof(sal_log_section_hdr_t)); + ia64_log_hexdump((unsigned char *)sh, sizeof(sal_log_section_hdr_t), + (prfunc_t)prfunc); + prfunc("Length of section & header = %d\n", sh->len); + ia64_log_prt_guid(&sh->guid, prfunc); + prfunc("End of SAL SECTION HEADER\n"); +} +#endif // MCA_PRT_XTRA_DATA for test only @FVL + +/* * ia64_log_init * Reset the OS ia64 log buffer - * Inputs : info_type (SAL_INFO_TYPE_{MCA,INIT,CMC}) - * sub_info_type (SAL_SUB_INFO_TYPE_{PROCESSOR,PLATFORM}) + * Inputs : info_type (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE}) * Outputs : None */ void -ia64_log_init(int sal_info_type, int sal_sub_info_type) +ia64_log_init(int sal_info_type) { - IA64_LOG_LOCK_INIT(sal_info_type, sal_sub_info_type); - IA64_LOG_NEXT_INDEX(sal_info_type, sal_sub_info_type) = 0; - memset(IA64_LOG_NEXT_BUFFER(sal_info_type, sal_sub_info_type), 0, - sizeof(ia64_psilog_t) * IA64_MAX_LOGS); + IA64_LOG_LOCK_INIT(sal_info_type); + IA64_LOG_NEXT_INDEX(sal_info_type) = 0; + memset(IA64_LOG_NEXT_BUFFER(sal_info_type), 0, + sizeof(ia64_err_rec_t) * IA64_MAX_LOGS); } /* * ia64_log_get + * * Get the current MCA log from SAL and copy it into the OS log buffer. - * Inputs : info_type (SAL_INFO_TYPE_{MCA,INIT,CMC}) - * sub_info_type (SAL_SUB_INFO_TYPE_{PROCESSOR,PLATFORM}) - * Outputs : None + * + * Inputs : info_type (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE}) + * prfunc (fn ptr of log output function) + * Outputs : size (total record length) * */ -void -ia64_log_get(int sal_info_type, int sal_sub_info_type, prfunc_t prfunc) +u64 +ia64_log_get(int sal_info_type, prfunc_t prfunc) { - sal_log_header_t *log_buffer; - int s,total_len=0; - - IA64_LOG_LOCK(sal_info_type, sal_sub_info_type); + sal_log_record_header_t *log_buffer; + u64 total_len = 0; + int s; + IA64_LOG_LOCK(sal_info_type); /* Get the process state information */ - log_buffer = IA64_LOG_NEXT_BUFFER(sal_info_type, sal_sub_info_type); - - if (!(total_len=ia64_sal_get_state_info(sal_info_type,(u64 *)log_buffer))) - prfunc("ia64_mca_log_get : Getting processor log failed\n"); - - IA64_MCA_DEBUG("ia64_log_get: retrieved %d bytes of error information\n",total_len); - - IA64_LOG_INDEX_INC(sal_info_type, sal_sub_info_type); + log_buffer = IA64_LOG_NEXT_BUFFER(sal_info_type); - IA64_LOG_UNLOCK(sal_info_type, sal_sub_info_type); + total_len = ia64_sal_get_state_info(sal_info_type, (u64 *)log_buffer); + if (total_len) { + IA64_LOG_INDEX_INC(sal_info_type); + IA64_LOG_UNLOCK(sal_info_type); + IA64_MCA_DEBUG("ia64_log_get: SAL error record type %d retrieved. " + "Record length = %ld\n", sal_info_type, total_len); + return total_len; + } else { + IA64_LOG_UNLOCK(sal_info_type); + prfunc("ia64_log_get: Failed to retrieve SAL error record type %d\n", + sal_info_type); + return 0; + } } /* - * ia64_log_clear - * Clear the current MCA log from SAL and dpending on the clear_os_buffer flags - * clear the OS log buffer also - * Inputs : info_type (SAL_INFO_TYPE_{MCA,INIT,CMC}) - * sub_info_type (SAL_SUB_INFO_TYPE_{PROCESSOR,PLATFORM}) - * clear_os_buffer + * ia64_log_prt_oem_data + * + * Print OEM specific data if included. + * + * Inputs : header_len (length passed in section header) + * sect_len (default length of section type) + * p_data (ptr to data) * prfunc (print function) * Outputs : None * */ void -ia64_log_clear(int sal_info_type, int sal_sub_info_type, int clear_os_buffer, prfunc_t prfunc) +ia64_log_prt_oem_data (int header_len, int sect_len, u8 *p_data, prfunc_t prfunc) { - if (ia64_sal_clear_state_info(sal_info_type)) - prfunc("ia64_mca_log_get : Clearing processor log failed\n"); - - if (clear_os_buffer) { - sal_log_header_t *log_buffer; - int s; - - IA64_LOG_LOCK(sal_info_type, sal_sub_info_type); - - /* Get the process state information */ - log_buffer = IA64_LOG_CURR_BUFFER(sal_info_type, sal_sub_info_type); + int oem_data_len, i; - memset(log_buffer, 0, sizeof(ia64_psilog_t)); - - IA64_LOG_INDEX_DEC(sal_info_type, sal_sub_info_type); - - IA64_LOG_UNLOCK(sal_info_type, sal_sub_info_type); + if ((oem_data_len = header_len - sect_len) > 0) { + prfunc(" OEM Specific Data:"); + for (i = 0; i < oem_data_len; i++, p_data++) + prfunc(" %02x", *p_data); } + prfunc("\n"); +} +/* + * ia64_log_rec_header_print + * + * Log info from the SAL error record header. + * + * Inputs : lh * (ptr to SAL log error record header) + * prfunc (fn ptr of log output function to use) + * Outputs : None + */ +void +ia64_log_rec_header_print (sal_log_record_header_t *lh, prfunc_t prfunc) +{ + char str_buf[32]; + + sprintf(str_buf, "%2d.%02d", + (lh->revision.major >> 4) * 10 + (lh->revision.major & 0xf), + (lh->revision.minor >> 4) * 10 + (lh->revision.minor & 0xf)); + prfunc("+Err Record ID: %d SAL Rev: %s\n", lh->id, str_buf); + sprintf(str_buf, "%02d/%02d/%04d/ %02d:%02d:%02d", + (lh->timestamp.slh_month >> 4) * 10 + + (lh->timestamp.slh_month & 0xf), + (lh->timestamp.slh_day >> 4) * 10 + + (lh->timestamp.slh_day & 0xf), + (lh->timestamp.slh_century >> 4) * 1000 + + (lh->timestamp.slh_century & 0xf) * 100 + + (lh->timestamp.slh_year >> 4) * 10 + + (lh->timestamp.slh_year & 0xf), + (lh->timestamp.slh_hour >> 4) * 10 + + (lh->timestamp.slh_hour & 0xf), + (lh->timestamp.slh_minute >> 4) * 10 + + (lh->timestamp.slh_minute & 0xf), + (lh->timestamp.slh_second >> 4) * 10 + + (lh->timestamp.slh_second & 0xf)); + prfunc("+Time: %s Severity %d\n", str_buf, lh->severity); } /* @@ -729,6 +1015,33 @@ prfunc("+ %s[%d] 0x%lx\n", reg_prefix, i, regs[i]); } +/* + * ia64_log_processor_fp_regs_print + * Print the contents of the saved floating page register(s) in the format + * [] + * + * Inputs: ia64_fpreg (Register save buffer) + * reg_num (# of registers) + * reg_class (application/banked/control/bank1_general) + * reg_prefix (ar/br/cr/b1_gr) + * Outputs: None + * + */ +void +ia64_log_processor_fp_regs_print (struct ia64_fpreg *regs, + int reg_num, + char *reg_class, + char *reg_prefix, + prfunc_t prfunc) +{ + int i; + + prfunc("+%s Registers\n", reg_class); + for (i = 0; i < reg_num; i++) + prfunc("+ %s[%d] 0x%lx%016lx\n", reg_prefix, i, regs[i].u.bits[1], + regs[i].u.bits[0]); +} + static char *pal_mesi_state[] = { "Invalid", "Shared", @@ -754,69 +1067,91 @@ /* * ia64_log_cache_check_info_print * Display the machine check information related to cache error(s). - * Inputs : i (Multiple errors are logged, i - index of logged error) - * info (Machine check info logged by the PAL and later + * Inputs: i (Multiple errors are logged, i - index of logged error) + * cc_info * (Ptr to cache check info logged by the PAL and later * captured by the SAL) - * target_addr (Address which caused the cache error) - * Outputs : None + * prfunc (fn ptr of print function to be used for output) + * Outputs: None */ void -ia64_log_cache_check_info_print(int i, - pal_cache_check_info_t info, - u64 target_addr, - prfunc_t prfunc) +ia64_log_cache_check_info_print (int i, + sal_log_mod_error_info_t *cache_check_info, + prfunc_t prfunc) { + pal_cache_check_info_t *info; + u64 target_addr; + + if (!cache_check_info->valid.check_info) { + IA64_MCA_DEBUG("ia64_mca_log_print: invalid cache_check_info[%d]\n",i); + return; /* If check info data not valid, skip it */ + } + + info = (pal_cache_check_info_t *)&cache_check_info->check_info; + target_addr = cache_check_info->target_identifier; + prfunc("+ Cache check info[%d]\n+", i); - prfunc(" Level: L%d",info.level); - if (info.mv) - prfunc(" ,Mesi: %s",pal_mesi_state[info.mesi]); - prfunc(" ,Index: %d,", info.index); - if (info.ic) - prfunc(" ,Cache: Instruction"); - if (info.dc) - prfunc(" ,Cache: Data"); - if (info.tl) - prfunc(" ,Line: Tag"); - if (info.dl) - prfunc(" ,Line: Data"); - prfunc(" ,Operation: %s,", pal_cache_op[info.op]); - if (info.wv) - prfunc(" ,Way: %d,", info.way); - if (info.tv) - prfunc(" ,Target Addr: 0x%lx", target_addr); - if (info.mc) - prfunc(" ,MC: Corrected"); + prfunc(" Level: L%d,",info->level); + if (info->mv) + prfunc(" Mesi: %s,",pal_mesi_state[info->mesi]); + prfunc(" Index: %d,", info->index); + if (info->ic) + prfunc(" Cache: Instruction,"); + if (info->dc) + prfunc(" Cache: Data,"); + if (info->tl) + prfunc(" Line: Tag,"); + if (info->dl) + prfunc(" Line: Data,"); + prfunc(" Operation: %s,", pal_cache_op[info->op]); + if (info->wv) + prfunc(" Way: %d,", info->way); + if (cache_check_info->valid.target_identifier) + /* Hope target address is saved in target_identifier */ + if (info->tv) + prfunc(" Target Addr: 0x%lx,", target_addr); + if (info->mc) + prfunc(" MC: Corrected"); prfunc("\n"); } /* * ia64_log_tlb_check_info_print * Display the machine check information related to tlb error(s). - * Inputs : i (Multiple errors are logged, i - index of logged error) - * info (Machine check info logged by the PAL and later + * Inputs: i (Multiple errors are logged, i - index of logged error) + * tlb_info * (Ptr to machine check info logged by the PAL and later * captured by the SAL) - * Outputs : None + * prfunc (fn ptr of print function to be used for output) + * Outputs: None */ - void -ia64_log_tlb_check_info_print(int i, - pal_tlb_check_info_t info, - prfunc_t prfunc) +ia64_log_tlb_check_info_print (int i, + sal_log_mod_error_info_t *tlb_check_info, + prfunc_t prfunc) + { + pal_tlb_check_info_t *info; + + if (!tlb_check_info->valid.check_info) { + IA64_MCA_DEBUG("ia64_mca_log_print: invalid tlb_check_info[%d]\n", i); + return; /* If check info data not valid, skip it */ + } + + info = (pal_tlb_check_info_t *)&tlb_check_info->check_info; + prfunc("+ TLB Check Info [%d]\n+", i); - if (info.itc) + if (info->itc) prfunc(" Failure: Instruction Translation Cache"); - if (info.dtc) + if (info->dtc) prfunc(" Failure: Data Translation Cache"); - if (info.itr) { + if (info->itr) { prfunc(" Failure: Instruction Translation Register"); - prfunc(" ,Slot: %d", info.tr_slot); + prfunc(" ,Slot: %d", info->tr_slot); } - if (info.dtr) { + if (info->dtr) { prfunc(" Failure: Data Translation Register"); - prfunc(" ,Slot: %d", info.tr_slot); + prfunc(" ,Slot: %d", info->tr_slot); } - if (info.mc) + if (info->mc) prfunc(" ,MC: Corrected"); prfunc("\n"); } @@ -824,159 +1159,719 @@ /* * ia64_log_bus_check_info_print * Display the machine check information related to bus error(s). - * Inputs : i (Multiple errors are logged, i - index of logged error) - * info (Machine check info logged by the PAL and later + * Inputs: i (Multiple errors are logged, i - index of logged error) + * bus_info * (Ptr to machine check info logged by the PAL and later * captured by the SAL) - * req_addr (Address of the requestor of the transaction) - * resp_addr (Address of the responder of the transaction) - * target_addr (Address where the data was to be delivered to or - * obtained from) - * Outputs : None + * prfunc (fn ptr of print function to be used for output) + * Outputs: None */ void -ia64_log_bus_check_info_print(int i, - pal_bus_check_info_t info, - u64 req_addr, - u64 resp_addr, - u64 targ_addr, - prfunc_t prfunc) -{ +ia64_log_bus_check_info_print (int i, + sal_log_mod_error_info_t *bus_check_info, + prfunc_t prfunc) +{ + pal_bus_check_info_t *info; + u64 req_addr; /* Address of the requestor of the transaction */ + u64 resp_addr; /* Address of the responder of the transaction */ + u64 targ_addr; /* Address where the data was to be delivered to */ + /* or obtained from */ + + if (!bus_check_info->valid.check_info) { + IA64_MCA_DEBUG("ia64_mca_log_print: invalid bus_check_info[%d]\n", i); + return; /* If check info data not valid, skip it */ + } + + info = (pal_bus_check_info_t *)&bus_check_info->check_info; + req_addr = bus_check_info->requestor_identifier; + resp_addr = bus_check_info->responder_identifier; + targ_addr = bus_check_info->target_identifier; + prfunc("+ BUS Check Info [%d]\n+", i); - prfunc(" Status Info: %d", info.bsi); - prfunc(" ,Severity: %d", info.sev); - prfunc(" ,Transaction Type: %d", info.type); - prfunc(" ,Transaction Size: %d", info.size); - if (info.cc) + prfunc(" Status Info: %d", info->bsi); + prfunc(" ,Severity: %d", info->sev); + prfunc(" ,Transaction Type: %d", info->type); + prfunc(" ,Transaction Size: %d", info->size); + if (info->cc) prfunc(" ,Cache-cache-transfer"); - if (info.ib) + if (info->ib) prfunc(" ,Error: Internal"); - if (info.eb) + if (info->eb) prfunc(" ,Error: External"); - if (info.mc) + if (info->mc) prfunc(" ,MC: Corrected"); - if (info.tv) + if (info->tv) prfunc(" ,Target Address: 0x%lx", targ_addr); - if (info.rq) + if (info->rq) prfunc(" ,Requestor Address: 0x%lx", req_addr); - if (info.tv) + if (info->tv) prfunc(" ,Responder Address: 0x%lx", resp_addr); prfunc("\n"); } /* + * ia64_log_mem_dev_err_info_print + * + * Format and log the platform memory device error record section data. + * + * Inputs: mem_dev_err_info * (Ptr to memory device error record section + * returned by SAL) + * prfunc (fn ptr of print function to be used for output) + * Outputs: None + */ +void +ia64_log_mem_dev_err_info_print (sal_log_mem_dev_err_info_t *mdei, + prfunc_t prfunc) +{ + prfunc("+ Mem Error Detail: "); + + if (mdei->valid.error_status) + prfunc(" Error Status: %#lx,", mdei->error_status); + if (mdei->valid.physical_addr) + prfunc(" Physical Address: %#lx,", mdei->physical_addr); + if (mdei->valid.addr_mask) + prfunc(" Address Mask: %#lx,", mdei->addr_mask); + if (mdei->valid.node) + prfunc(" Node: %d,", mdei->node); + if (mdei->valid.card) + prfunc(" Card: %d,", mdei->card); + if (mdei->valid.module) + prfunc(" Module: %d,", mdei->module); + if (mdei->valid.bank) + prfunc(" Bank: %d,", mdei->bank); + if (mdei->valid.device) + prfunc(" Device: %d,", mdei->device); + if (mdei->valid.row) + prfunc(" Row: %d,", mdei->row); + if (mdei->valid.column) + prfunc(" Column: %d,", mdei->column); + if (mdei->valid.bit_position) + prfunc(" Bit Position: %d,", mdei->bit_position); + if (mdei->valid.target_id) + prfunc(" ,Target Address: %#lx,", mdei->target_id); + if (mdei->valid.requestor_id) + prfunc(" ,Requestor Address: %#lx,", mdei->requestor_id); + if (mdei->valid.responder_id) + prfunc(" ,Responder Address: %#lx,", mdei->responder_id); + if (mdei->valid.bus_spec_data) + prfunc(" Bus Specific Data: %#lx,", mdei->bus_spec_data); + prfunc("\n"); + + if (mdei->valid.oem_id) { + u8 *p_data = &(mdei->oem_id[0]); + int i; + + prfunc(" OEM Memory Controller ID:"); + for (i = 0; i < 16; i++, p_data++) + prfunc(" %02x", *p_data); + prfunc("\n"); + } + + if (mdei->valid.oem_data) { + ia64_log_prt_oem_data((int)mdei->header.len, + (int)sizeof(sal_log_mem_dev_err_info_t) - 1, + &(mdei->oem_data[0]), prfunc); + } +} + +/* + * ia64_log_sel_dev_err_info_print + * + * Format and log the platform SEL device error record section data. + * + * Inputs: sel_dev_err_info * (Ptr to the SEL device error record section + * returned by SAL) + * prfunc (fn ptr of print function to be used for output) + * Outputs: None + */ +void +ia64_log_sel_dev_err_info_print (sal_log_sel_dev_err_info_t *sdei, + prfunc_t prfunc) +{ + int i; + + prfunc("+ SEL Device Error Detail: "); + + if (sdei->valid.record_id) + prfunc(" Record ID: %#x", sdei->record_id); + if (sdei->valid.record_type) + prfunc(" Record Type: %#x", sdei->record_type); + prfunc(" Time Stamp: "); + for (i = 0; i < 4; i++) + prfunc("%1d", sdei->timestamp[i]); + if (sdei->valid.generator_id) + prfunc(" Generator ID: %#x", sdei->generator_id); + if (sdei->valid.evm_rev) + prfunc(" Message Format Version: %#x", sdei->evm_rev); + if (sdei->valid.sensor_type) + prfunc(" Sensor Type: %#x", sdei->sensor_type); + if (sdei->valid.sensor_num) + prfunc(" Sensor Number: %#x", sdei->sensor_num); + if (sdei->valid.event_dir) + prfunc(" Event Direction Type: %#x", sdei->event_dir); + if (sdei->valid.event_data1) + prfunc(" Data1: %#x", sdei->event_data1); + if (sdei->valid.event_data2) + prfunc(" Data2: %#x", sdei->event_data2); + if (sdei->valid.event_data3) + prfunc(" Data3: %#x", sdei->event_data3); + prfunc("\n"); + +} + +/* + * ia64_log_pci_bus_err_info_print + * + * Format and log the platform PCI bus error record section data. + * + * Inputs: pci_bus_err_info * (Ptr to the PCI bus error record section + * returned by SAL) + * prfunc (fn ptr of print function to be used for output) + * Outputs: None + */ +void +ia64_log_pci_bus_err_info_print (sal_log_pci_bus_err_info_t *pbei, + prfunc_t prfunc) +{ + prfunc("+ PCI Bus Error Detail: "); + + if (pbei->valid.err_status) + prfunc(" Error Status: %#lx", pbei->err_status); + if (pbei->valid.err_type) + prfunc(" Error Type: %#x", pbei->err_type); + if (pbei->valid.bus_id) + prfunc(" Bus ID: %#x", pbei->bus_id); + if (pbei->valid.bus_address) + prfunc(" Bus Address: %#lx", pbei->bus_address); + if (pbei->valid.bus_data) + prfunc(" Bus Data: %#lx", pbei->bus_data); + if (pbei->valid.bus_cmd) + prfunc(" Bus Command: %#lx", pbei->bus_cmd); + if (pbei->valid.requestor_id) + prfunc(" Requestor ID: %#lx", pbei->requestor_id); + if (pbei->valid.responder_id) + prfunc(" Responder ID: %#lx", pbei->responder_id); + if (pbei->valid.target_id) + prfunc(" Target ID: %#lx", pbei->target_id); + if (pbei->valid.oem_data) + prfunc("\n"); + + if (pbei->valid.oem_data) { + ia64_log_prt_oem_data((int)pbei->header.len, + (int)sizeof(sal_log_pci_bus_err_info_t) - 1, + &(pbei->oem_data[0]), prfunc); + } +} + +/* + * ia64_log_smbios_dev_err_info_print + * + * Format and log the platform SMBIOS device error record section data. + * + * Inputs: smbios_dev_err_info * (Ptr to the SMBIOS device error record + * section returned by SAL) + * prfunc (fn ptr of print function to be used for output) + * Outputs: None + */ +void +ia64_log_smbios_dev_err_info_print (sal_log_smbios_dev_err_info_t *sdei, + prfunc_t prfunc) +{ + u8 i; + + prfunc("+ SMBIOS Device Error Detail: "); + + if (sdei->valid.event_type) + prfunc(" Event Type: %#x", sdei->event_type); + if (sdei->valid.time_stamp) { + prfunc(" Time Stamp: "); + for (i = 0; i < 6; i++) + prfunc("%d", sdei->time_stamp[i]); + } + if ((sdei->valid.data) && (sdei->valid.length)) { + prfunc(" Data: "); + for (i = 0; i < sdei->length; i++) + prfunc(" %02x", sdei->data[i]); + } + prfunc("\n"); +} + +/* + * ia64_log_pci_comp_err_info_print + * + * Format and log the platform PCI component error record section data. + * + * Inputs: pci_comp_err_info * (Ptr to the PCI component error record section + * returned by SAL) + * prfunc (fn ptr of print function to be used for output) + * Outputs: None + */ +void +ia64_log_pci_comp_err_info_print(sal_log_pci_comp_err_info_t *pcei, + prfunc_t prfunc) +{ + u32 n_mem_regs, n_io_regs; + u64 i, n_pci_data; + u64 *p_reg_data; + u8 *p_oem_data; + + prfunc("+ PCI Component Error Detail: "); + + if (pcei->valid.err_status) + prfunc(" Error Status: %#lx\n", pcei->err_status); + if (pcei->valid.comp_info) + prfunc(" Component Info: Vendor Id = %#x, Device Id = %#x," + " Class Code = %#x, Seg/Bus/Dev/Func = %d/%d/%d/%d\n", + pcei->comp_info.vendor_id, pcei->comp_info.device_id, + pcei->comp_info.class_code, pcei->comp_info.seg_num, + pcei->comp_info.bus_num, pcei->comp_info.dev_num, + pcei->comp_info.func_num); + + n_mem_regs = (pcei->valid.num_mem_regs) ? pcei->num_mem_regs : 0; + n_io_regs = (pcei->valid.num_io_regs) ? pcei->num_io_regs : 0; + p_reg_data = &(pcei->reg_data_pairs[0]); + p_oem_data = (u8 *)p_reg_data + + (n_mem_regs + n_io_regs) * 2 * sizeof(u64); + n_pci_data = p_oem_data - (u8 *)pcei; + + if (n_pci_data > pcei->header.len) { + prfunc(" Invalid PCI Component Error Record format: length = %ld, " + " Size PCI Data = %d, Num Mem-Map/IO-Map Regs = %ld/%ld\n", + pcei->header.len, n_pci_data, n_mem_regs, n_io_regs); + return; + } + + if (n_mem_regs) { + prfunc(" Memory Mapped Registers\n Address \tValue\n"); + for (i = 0; i < pcei->num_mem_regs; i++) { + prfunc(" %#lx %#lx\n", p_reg_data[0], p_reg_data[1]); + p_reg_data += 2; + } + } + if (n_io_regs) { + prfunc(" I/O Mapped Registers\n Address \tValue\n"); + for (i = 0; i < pcei->num_io_regs; i++) { + prfunc(" %#lx %#lx\n", p_reg_data[0], p_reg_data[1]); + p_reg_data += 2; + } + } + if (pcei->valid.oem_data) { + ia64_log_prt_oem_data((int)pcei->header.len, n_pci_data, + p_oem_data, prfunc); + prfunc("\n"); + } +} + +/* + * ia64_log_plat_specific_err_info_print + * + * Format and log the platform specifie error record section data. + * + * Inputs: sel_dev_err_info * (Ptr to the platform specific error record + * section returned by SAL) + * prfunc (fn ptr of print function to be used for output) + * Outputs: None + */ +void +ia64_log_plat_specific_err_info_print (sal_log_plat_specific_err_info_t *psei, + prfunc_t prfunc) +{ + prfunc("+ Platform Specific Error Detail: "); + + if (psei->valid.err_status) + prfunc(" Error Status: %#lx", psei->err_status); + if (psei->valid.guid) { + prfunc(" GUID: "); + ia64_log_prt_guid(&psei->guid, prfunc); + } + if (psei->valid.oem_data) { + ia64_log_prt_oem_data((int)psei->header.len, + (int)sizeof(sal_log_plat_specific_err_info_t) - 1, + &(psei->oem_data[0]), prfunc); + } + prfunc("\n"); +} + +/* + * ia64_log_host_ctlr_err_info_print + * + * Format and log the platform host controller error record section data. + * + * Inputs: host_ctlr_err_info * (Ptr to the host controller error record + * section returned by SAL) + * prfunc (fn ptr of print function to be used for output) + * Outputs: None + */ +void +ia64_log_host_ctlr_err_info_print (sal_log_host_ctlr_err_info_t *hcei, + prfunc_t prfunc) +{ + prfunc("+ Host Controller Error Detail: "); + + if (hcei->valid.err_status) + prfunc(" Error Status: %#lx", hcei->err_status); + if (hcei->valid.requestor_id) + prfunc(" Requestor ID: %#lx", hcei->requestor_id); + if (hcei->valid.responder_id) + prfunc(" Responder ID: %#lx", hcei->responder_id); + if (hcei->valid.target_id) + prfunc(" Target ID: %#lx", hcei->target_id); + if (hcei->valid.bus_spec_data) + prfunc(" Bus Specific Data: %#lx", hcei->bus_spec_data); + if (hcei->valid.oem_data) { + ia64_log_prt_oem_data((int)hcei->header.len, + (int)sizeof(sal_log_host_ctlr_err_info_t) - 1, + &(hcei->oem_data[0]), prfunc); + } + prfunc("\n"); +} + +/* + * ia64_log_plat_bus_err_info_print + * + * Format and log the platform bus error record section data. + * + * Inputs: plat_bus_err_info * (Ptr to the platform bus error record section + * returned by SAL) + * prfunc (fn ptr of print function to be used for output) + * Outputs: None + */ +void +ia64_log_plat_bus_err_info_print (sal_log_plat_bus_err_info_t *pbei, + prfunc_t prfunc) +{ + prfunc("+ Platform Bus Error Detail: "); + + if (pbei->valid.err_status) + prfunc(" Error Status: %#lx", pbei->err_status); + if (pbei->valid.requestor_id) + prfunc(" Requestor ID: %#lx", pbei->requestor_id); + if (pbei->valid.responder_id) + prfunc(" Responder ID: %#lx", pbei->responder_id); + if (pbei->valid.target_id) + prfunc(" Target ID: %#lx", pbei->target_id); + if (pbei->valid.bus_spec_data) + prfunc(" Bus Specific Data: %#lx", pbei->bus_spec_data); + if (pbei->valid.oem_data) { + ia64_log_prt_oem_data((int)pbei->header.len, + (int)sizeof(sal_log_plat_bus_err_info_t) - 1, + &(pbei->oem_data[0]), prfunc); + } + prfunc("\n"); +} + +/* + * ia64_log_proc_dev_err_info_print + * + * Display the processor device error record. + * + * Inputs: sal_log_processor_info_t * (Ptr to processor device error record + * section body). + * prfunc (fn ptr of print function to be used + * for output). + * Outputs: None + */ +void +ia64_log_proc_dev_err_info_print (sal_log_processor_info_t *slpi, + prfunc_t prfunc) +{ + size_t d_len = slpi->header.len - sizeof(sal_log_section_hdr_t); + sal_processor_static_info_t *spsi; + int i; + sal_log_mod_error_info_t *p_data; + + prfunc("+Processor Device Error Info Section\n"); + +#ifdef MCA_PRT_XTRA_DATA // for test only @FVL + { + char *p_data = (char *)&slpi->valid; + + prfunc("SAL_PROC_DEV_ERR SECTION DATA: Data buffer = %p, " + "Data size = %ld\n", (void *)p_data, d_len); + ia64_log_hexdump(p_data, d_len, prfunc); + prfunc("End of SAL_PROC_DEV_ERR SECTION DATA\n"); + } +#endif // MCA_PRT_XTRA_DATA for test only @FVL + + if (slpi->valid.proc_error_map) + prfunc(" Processor Error Map: %#lx\n", slpi->proc_error_map); + + if (slpi->valid.proc_state_param) + prfunc(" Processor State Param: %#lx\n", slpi->proc_state_parameter); + + if (slpi->valid.proc_cr_lid) + prfunc(" Processor LID: %#lx\n", slpi->proc_cr_lid); + + /* + * Note: March 2001 SAL spec states that if the number of elements in any + * of the MOD_ERROR_INFO_STRUCT arrays is zero, the entire array is + * absent. Also, current implementations only allocate space for number of + * elements used. So we walk the data pointer from here on. + */ + p_data = &slpi->cache_check_info[0]; + + /* Print the cache check information if any*/ + for (i = 0 ; i < slpi->valid.num_cache_check; i++, p_data++) + ia64_log_cache_check_info_print(i, p_data, prfunc); + + /* Print the tlb check information if any*/ + for (i = 0 ; i < slpi->valid.num_tlb_check; i++, p_data++) + ia64_log_tlb_check_info_print(i, p_data, prfunc); + + /* Print the bus check information if any*/ + for (i = 0 ; i < slpi->valid.num_bus_check; i++, p_data++) + ia64_log_bus_check_info_print(i, p_data, prfunc); + + /* Print the reg file check information if any*/ + for (i = 0 ; i < slpi->valid.num_reg_file_check; i++, p_data++) + ia64_log_hexdump((u8 *)p_data, sizeof(sal_log_mod_error_info_t), + prfunc); /* Just hex dump for now */ + + /* Print the ms check information if any*/ + for (i = 0 ; i < slpi->valid.num_ms_check; i++, p_data++) + ia64_log_hexdump((u8 *)p_data, sizeof(sal_log_mod_error_info_t), + prfunc); /* Just hex dump for now */ + + /* Print CPUID registers if any*/ + if (slpi->valid.cpuid_info) { + u64 *p = (u64 *)p_data; + + prfunc(" CPUID Regs: %#lx %#lx %#lx %#lx\n", p[0], p[1], p[2], p[3]); + p_data++; + } + + /* Print processor static info if any */ + if (slpi->valid.psi_static_struct) { + spsi = (sal_processor_static_info_t *)p_data; + + /* Print branch register contents if valid */ + if (spsi->valid.br) + ia64_log_processor_regs_print(spsi->br, 8, "Branch", "br", + prfunc); + + /* Print control register contents if valid */ + if (spsi->valid.cr) + ia64_log_processor_regs_print(spsi->cr, 128, "Control", "cr", + prfunc); + + /* Print application register contents if valid */ + if (spsi->valid.ar) + ia64_log_processor_regs_print(spsi->ar, 128, "Application", + "ar", prfunc); + + /* Print region register contents if valid */ + if (spsi->valid.rr) + ia64_log_processor_regs_print(spsi->rr, 8, "Region", "rr", + prfunc); + + /* Print floating-point register contents if valid */ + if (spsi->valid.fr) + ia64_log_processor_fp_regs_print(spsi->fr, 128, "Floating-point", "fr", + prfunc); + } +} + +/* * ia64_log_processor_info_print + * * Display the processor-specific information logged by PAL as a part * of MCA or INIT or CMC. - * Inputs : lh (Pointer of the sal log header which specifies the format - * of SAL state info as specified by the SAL spec). + * + * Inputs : lh (Pointer of the sal log header which specifies the + * format of SAL state info as specified by the SAL spec). + * prfunc (fn ptr of print function to be used for output). * Outputs : None */ void -ia64_log_processor_info_print(sal_log_header_t *lh, prfunc_t prfunc) +ia64_log_processor_info_print(sal_log_record_header_t *lh, prfunc_t prfunc) { - sal_log_processor_info_t *slpi; - int i; + sal_log_section_hdr_t *slsh; + int n_sects; + int ercd_pos; if (!lh) return; - if (lh->slh_log_type != SAL_SUB_INFO_TYPE_PROCESSOR) +#ifdef MCA_PRT_XTRA_DATA // for test only @FVL + ia64_log_prt_record_header(lh, prfunc); +#endif // MCA_PRT_XTRA_DATA for test only @FVL + + if ((ercd_pos = sizeof(sal_log_record_header_t)) >= lh->len) { + IA64_MCA_DEBUG("ia64_mca_log_print: " + "truncated SAL CMC error record. len = %d\n", + lh->len); return; + } - slpi = (sal_log_processor_info_t *)((char *)lh+sizeof(sal_log_header_t)); /* point to proc info */ + /* Print record header info */ + ia64_log_rec_header_print(lh, prfunc); - if (!slpi) { - prfunc("No Processor Error Log found\n"); - return; + for (n_sects = 0; (ercd_pos < lh->len); n_sects++, ercd_pos += slsh->len) { + /* point to next section header */ + slsh = (sal_log_section_hdr_t *)((char *)lh + ercd_pos); + +#ifdef MCA_PRT_XTRA_DATA // for test only @FVL + ia64_log_prt_section_header(slsh, prfunc); +#endif // MCA_PRT_XTRA_DATA for test only @FVL + + if (verify_guid((void *)&slsh->guid, (void *)&(SAL_PROC_DEV_ERR_SECT_GUID))) { + IA64_MCA_DEBUG("ia64_mca_log_print: unsupported record section\n"); + continue; + } + + /* + * Now process processor device error record section + */ + ia64_log_proc_dev_err_info_print((sal_log_processor_info_t *)slsh, + printk); } - /* Print branch register contents if valid */ - if (slpi->slpi_valid.slpi_br) - ia64_log_processor_regs_print(slpi->slpi_br, 8, "Branch", "br", prfunc); + IA64_MCA_DEBUG("ia64_mca_log_print: " + "found %d sections in SAL CMC error record. len = %d\n", + n_sects, lh->len); + if (!n_sects) { + prfunc("No Processor Device Error Info Section found\n"); + return; + } +} - /* Print control register contents if valid */ - if (slpi->slpi_valid.slpi_cr) - ia64_log_processor_regs_print(slpi->slpi_cr, 128, "Control", "cr", prfunc); +/* + * ia64_log_platform_info_print + * + * Format and Log the SAL Platform Error Record. + * + * Inputs : lh (Pointer to the sal error record header with format + * specified by the SAL spec). + * prfunc (fn ptr of log output function to use) + * Outputs : None + */ +void +ia64_log_platform_info_print (sal_log_record_header_t *lh, prfunc_t prfunc) +{ + sal_log_section_hdr_t *slsh; + int n_sects; + int ercd_pos; - /* Print application register contents if valid */ - if (slpi->slpi_valid.slpi_ar) - ia64_log_processor_regs_print(slpi->slpi_br, 128, "Application", "ar", prfunc); + if (!lh) + return; - /* Print region register contents if valid */ - if (slpi->slpi_valid.slpi_rr) - ia64_log_processor_regs_print(slpi->slpi_rr, 8, "Region", "rr", prfunc); +#ifdef MCA_PRT_XTRA_DATA // for test only @FVL + ia64_log_prt_record_header(lh, prfunc); +#endif // MCA_PRT_XTRA_DATA for test only @FVL + + if ((ercd_pos = sizeof(sal_log_record_header_t)) >= lh->len) { + IA64_MCA_DEBUG("ia64_mca_log_print: " + "truncated SAL error record. len = %d\n", + lh->len); + return; + } - /* Print floating-point register contents if valid */ - if (slpi->slpi_valid.slpi_fr) - ia64_log_processor_regs_print(slpi->slpi_fr, 128, "Floating-point", "fr", - prfunc); + /* Print record header info */ + ia64_log_rec_header_print(lh, prfunc); - /* Print the cache check information if any*/ - for (i = 0 ; i < MAX_CACHE_ERRORS; i++) - ia64_log_cache_check_info_print(i, - slpi->slpi_cache_check_info[i].slpi_cache_check, - slpi->slpi_cache_check_info[i].slpi_target_address, - prfunc); - /* Print the tlb check information if any*/ - for (i = 0 ; i < MAX_TLB_ERRORS; i++) - ia64_log_tlb_check_info_print(i,slpi->slpi_tlb_check_info[i], prfunc); + for (n_sects = 0; (ercd_pos < lh->len); n_sects++, ercd_pos += slsh->len) { + /* point to next section header */ + slsh = (sal_log_section_hdr_t *)((char *)lh + ercd_pos); + +#ifdef MCA_PRT_XTRA_DATA // for test only @FVL + ia64_log_prt_section_header(slsh, prfunc); + + if (efi_guidcmp(slsh->guid, SAL_PROC_DEV_ERR_SECT_GUID) != 0) { + size_t d_len = slsh->len - sizeof(sal_log_section_hdr_t); + char *p_data = (char *)&((sal_log_mem_dev_err_info_t *)slsh)->valid; + + prfunc("Start of Platform Err Data Section: Data buffer = %p, " + "Data size = %ld\n", (void *)p_data, d_len); + ia64_log_hexdump(p_data, d_len, prfunc); + prfunc("End of Platform Err Data Section\n"); + } +#endif // MCA_PRT_XTRA_DATA for test only @FVL - /* Print the bus check information if any*/ - for (i = 0 ; i < MAX_BUS_ERRORS; i++) - ia64_log_bus_check_info_print(i, - slpi->slpi_bus_check_info[i].slpi_bus_check, - slpi->slpi_bus_check_info[i].slpi_requestor_addr, - slpi->slpi_bus_check_info[i].slpi_responder_addr, - slpi->slpi_bus_check_info[i].slpi_target_addr, - prfunc); + /* + * Now process CPE error record section + */ + if (efi_guidcmp(slsh->guid, SAL_PROC_DEV_ERR_SECT_GUID) == 0) { + ia64_log_proc_dev_err_info_print((sal_log_processor_info_t *)slsh, + prfunc); + } else if (efi_guidcmp(slsh->guid, SAL_PLAT_MEM_DEV_ERR_SECT_GUID) == 0) { + prfunc("+Platform Memory Device Error Info Section\n"); + ia64_log_mem_dev_err_info_print((sal_log_mem_dev_err_info_t *)slsh, + prfunc); + } else if (efi_guidcmp(slsh->guid, SAL_PLAT_SEL_DEV_ERR_SECT_GUID) == 0) { + prfunc("+Platform SEL Device Error Info Section\n"); + ia64_log_sel_dev_err_info_print((sal_log_sel_dev_err_info_t *)slsh, + prfunc); + } else if (efi_guidcmp(slsh->guid, SAL_PLAT_PCI_BUS_ERR_SECT_GUID) == 0) { + prfunc("+Platform PCI Bus Error Info Section\n"); + ia64_log_pci_bus_err_info_print((sal_log_pci_bus_err_info_t *)slsh, + prfunc); + } else if (efi_guidcmp(slsh->guid, SAL_PLAT_SMBIOS_DEV_ERR_SECT_GUID) == 0) { + prfunc("+Platform SMBIOS Device Error Info Section\n"); + ia64_log_smbios_dev_err_info_print((sal_log_smbios_dev_err_info_t *)slsh, + prfunc); + } else if (efi_guidcmp(slsh->guid, SAL_PLAT_PCI_COMP_ERR_SECT_GUID) == 0) { + prfunc("+Platform PCI Component Error Info Section\n"); + ia64_log_pci_comp_err_info_print((sal_log_pci_comp_err_info_t *)slsh, + prfunc); + } else if (efi_guidcmp(slsh->guid, SAL_PLAT_SPECIFIC_ERR_SECT_GUID) == 0) { + prfunc("+Platform Specific Error Info Section\n"); + ia64_log_plat_specific_err_info_print((sal_log_plat_specific_err_info_t *) + slsh, + prfunc); + } else if (efi_guidcmp(slsh->guid, SAL_PLAT_HOST_CTLR_ERR_SECT_GUID) == 0) { + prfunc("+Platform Host Controller Error Info Section\n"); + ia64_log_host_ctlr_err_info_print((sal_log_host_ctlr_err_info_t *)slsh, + prfunc); + } else if (efi_guidcmp(slsh->guid, SAL_PLAT_BUS_ERR_SECT_GUID) == 0) { + prfunc("+Platform Bus Error Info Section\n"); + ia64_log_plat_bus_err_info_print((sal_log_plat_bus_err_info_t *)slsh, + prfunc); + } else { + IA64_MCA_DEBUG("ia64_mca_log_print: unsupported record section\n"); + continue; + } + } + IA64_MCA_DEBUG("ia64_mca_log_print: found %d sections in SAL error record. len = %d\n", + n_sects, lh->len); + if (!n_sects) { + prfunc("No Platform Error Info Sections found\n"); + return; + } } /* * ia64_log_print - * Display the contents of the OS error log information - * Inputs : info_type (SAL_INFO_TYPE_{MCA,INIT,CMC}) - * sub_info_type (SAL_SUB_INFO_TYPE_{PROCESSOR,PLATFORM}) + * + * Displays the contents of the OS error log information + * + * Inputs : info_type (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE}) + * prfunc (fn ptr of log output function to use) * Outputs : None */ void -ia64_log_print(int sal_info_type, int sal_sub_info_type, prfunc_t prfunc) +ia64_log_print(int sal_info_type, prfunc_t prfunc) { - char *info_type, *sub_info_type; - switch(sal_info_type) { - case SAL_INFO_TYPE_MCA: - info_type = "MCA"; + case SAL_INFO_TYPE_MCA: + prfunc("+BEGIN HARDWARE ERROR STATE AT MCA\n"); + ia64_log_platform_info_print(IA64_LOG_CURR_BUFFER(sal_info_type), prfunc); + prfunc("+END HARDWARE ERROR STATE AT MCA\n"); break; - case SAL_INFO_TYPE_INIT: - info_type = "INIT"; + case SAL_INFO_TYPE_INIT: + prfunc("+MCA INIT ERROR LOG (UNIMPLEMENTED)\n"); break; - case SAL_INFO_TYPE_CMC: - info_type = "CMC"; + case SAL_INFO_TYPE_CMC: + prfunc("+BEGIN HARDWARE ERROR STATE AT CMC\n"); + ia64_log_processor_info_print(IA64_LOG_CURR_BUFFER(sal_info_type), prfunc); + prfunc("+END HARDWARE ERROR STATE AT CMC\n"); break; - default: - info_type = "UNKNOWN"; + case SAL_INFO_TYPE_CPE: + prfunc("+BEGIN HARDWARE ERROR STATE AT CPE\n"); + ia64_log_platform_info_print(IA64_LOG_CURR_BUFFER(sal_info_type), prfunc); + prfunc("+END HARDWARE ERROR STATE AT CPE\n"); break; - } - - switch(sal_sub_info_type) { - case SAL_SUB_INFO_TYPE_PROCESSOR: - sub_info_type = "PROCESSOR"; - break; - case SAL_SUB_INFO_TYPE_PLATFORM: - sub_info_type = "PLATFORM"; - break; - default: - sub_info_type = "UNKNOWN"; + default: + prfunc("+MCA UNKNOWN ERROR LOG (UNIMPLEMENTED)\n"); break; } - - prfunc("+BEGIN HARDWARE ERROR STATE [%s %s]\n", info_type, sub_info_type); - if (sal_sub_info_type == SAL_SUB_INFO_TYPE_PROCESSOR) - ia64_log_processor_info_print( - IA64_LOG_CURR_BUFFER(sal_info_type, sal_sub_info_type), - prfunc); - else - log_print_platform(IA64_LOG_CURR_BUFFER(sal_info_type, sal_sub_info_type),prfunc); - prfunc("+END HARDWARE ERROR STATE [%s %s]\n", info_type, sub_info_type); } diff -urN linux-2.4.10/arch/ia64/kernel/mca_asm.S linux-2.4.10-lia/arch/ia64/kernel/mca_asm.S --- linux-2.4.10/arch/ia64/kernel/mca_asm.S Tue Jul 31 10:30:08 2001 +++ linux-2.4.10-lia/arch/ia64/kernel/mca_asm.S Mon Sep 24 21:49:52 2001 @@ -9,6 +9,7 @@ // #include +#include #include #include #include @@ -23,7 +24,7 @@ #include "minstate.h" /* - * SAL_TO_OS_MCA_HANDOFF_STATE + * SAL_TO_OS_MCA_HANDOFF_STATE (SAL 3.0 spec) * 1. GR1 = OS GP * 2. GR8 = PAL_PROC physical address * 3. GR9 = SAL_PROC physical address @@ -33,6 +34,7 @@ */ #define SAL_TO_OS_MCA_HANDOFF_STATE_SAVE(_tmp) \ movl _tmp=ia64_sal_to_os_handoff_state;; \ + DATA_VA_TO_PA(_tmp);; \ st8 [_tmp]=r1,0x08;; \ st8 [_tmp]=r8,0x08;; \ st8 [_tmp]=r9,0x08;; \ @@ -41,47 +43,29 @@ st8 [_tmp]=r12,0x08;; /* - * OS_MCA_TO_SAL_HANDOFF_STATE - * 1. GR8 = OS_MCA status - * 2. GR9 = SAL GP (physical) - * 3. GR22 = New min state save area pointer + * OS_MCA_TO_SAL_HANDOFF_STATE (SAL 3.0 spec) + * 1. GR8 = OS_MCA return status + * 2. GR9 = SAL GP (physical) + * 3. GR10 = 0/1 returning same/new context + * 4. GR22 = New min state save area pointer + * returns ptr to SAL rtn save loc in _tmp */ -#define OS_MCA_TO_SAL_HANDOFF_STATE_RESTORE(_tmp) \ - movl _tmp=ia64_os_to_sal_handoff_state;; \ - DATA_VA_TO_PA(_tmp);; \ - ld8 r8=[_tmp],0x08;; \ - ld8 r9=[_tmp],0x08;; \ - ld8 r22=[_tmp],0x08;; - -/* - * BRANCH - * Jump to the instruction referenced by - * "to_label". - * Branch is taken only if the predicate - * register "p" is true. - * "ip" is the address of the instruction - * located at "from_label". - * "temp" is a scratch register like r2 - * "adjust" needed for HP compiler. - * A screwup somewhere with constant arithmetic. - */ -#define BRANCH(to_label, temp, p, adjust) \ -100: (p) mov temp=ip; \ - ;; \ - (p) adds temp=to_label-100b,temp;\ - ;; \ - (p) adds temp=adjust,temp; \ - ;; \ - (p) mov b1=temp ; \ - (p) br b1 +#define OS_MCA_TO_SAL_HANDOFF_STATE_RESTORE(_tmp) \ + movl _tmp=ia64_os_to_sal_handoff_state;; \ + DATA_VA_TO_PA(_tmp);; \ + ld8 r8=[_tmp],0x08;; \ + ld8 r9=[_tmp],0x08;; \ + ld8 r10=[_tmp],0x08;; \ + ld8 r22=[_tmp],0x08;; \ + movl _tmp=ia64_sal_to_os_handoff_state;; \ + DATA_VA_TO_PA(_tmp);; \ + add _tmp=0x28,_tmp;; // point to SAL rtn save location .global ia64_os_mca_dispatch .global ia64_os_mca_dispatch_end .global ia64_sal_to_os_handoff_state .global ia64_os_to_sal_handoff_state - .global ia64_os_mca_ucmc_handler .global ia64_mca_proc_state_dump - .global ia64_mca_proc_state_restore .global ia64_mca_stack .global ia64_mca_stackframe .global ia64_mca_bspstore @@ -100,7 +84,7 @@ #endif /* #if defined(MCA_TEST) */ // Save the SAL to OS MCA handoff state as defined - // by SAL SPEC 2.5 + // by SAL SPEC 3.0 // NOTE : The order in which the state gets saved // is dependent on the way the C-structure // for ia64_mca_sal_to_os_state_t has been @@ -110,15 +94,20 @@ // LOG PROCESSOR STATE INFO FROM HERE ON.. ;; begin_os_mca_dump: - BRANCH(ia64_os_mca_proc_state_dump, r2, p0, 0x0) - ;; + br ia64_os_mca_proc_state_dump;; + ia64_os_mca_done_dump: // Setup new stack frame for OS_MCA handling - movl r2=ia64_mca_bspstore // local bspstore area location in r2 - movl r3=ia64_mca_stackframe // save stack frame to memory in r3 + movl r2=ia64_mca_bspstore;; // local bspstore area location in r2 + DATA_VA_TO_PA(r2);; + movl r3=ia64_mca_stackframe;; // save stack frame to memory in r3 + DATA_VA_TO_PA(r3);; rse_switch_context(r6,r3,r2);; // RSC management in this new context movl r12=ia64_mca_stack;; + mov r2=8*1024;; // stack size must be same as c array + add r12=r2,r12;; // stack base @ bottom of array + DATA_VA_TO_PA(r12);; // Enter virtual mode from physical mode VIRTUAL_MODE_ENTER(r2, r3, ia64_os_mca_virtual_begin, r4) @@ -127,7 +116,7 @@ // call our handler movl r2=ia64_mca_ucmc_handler;; mov b6=r2;; - br.call.sptk.few b0=b6 + br.call.sptk.many b0=b6;; .ret0: // Revert back to physical mode before going back to SAL PHYSICAL_MODE_ENTER(r2, r3, ia64_os_mca_virtual_end, r4) @@ -135,9 +124,9 @@ #if defined(MCA_TEST) // Pretend that we are in interrupt context - mov r2=psr - dep r2=0, r2, PSR_IC, 2; - mov psr.l = r2 + mov r2=psr;; + dep r2=0, r2, PSR_IC, 2;; + mov psr.l = r2;; #endif /* #if defined(MCA_TEST) */ // restore the original stack frame here @@ -152,15 +141,14 @@ mov r8=gp ;; begin_os_mca_restore: - BRANCH(ia64_os_mca_proc_state_restore, r2, p0, 0x0) - ;; + br ia64_os_mca_proc_state_restore;; ia64_os_mca_done_restore: ;; // branch back to SALE_CHECK OS_MCA_TO_SAL_HANDOFF_STATE_RESTORE(r2) ld8 r3=[r2];; - mov b0=r3 // SAL_CHECK return address + mov b0=r3;; // SAL_CHECK return address br b0 ;; ia64_os_mca_dispatch_end: @@ -178,8 +166,10 @@ //-- ia64_os_mca_proc_state_dump: -// Get and save GR0-31 from Proc. Min. State Save Area to SAL PSI +// Save bank 1 GRs 16-31 which will be used by c-language code when we switch +// to virtual addressing mode. movl r2=ia64_mca_proc_state_dump;; // Os state dump area + DATA_VA_TO_PA(r2) // convert to to physical address // save ar.NaT mov r5=ar.unat // ar.unat @@ -250,16 +240,16 @@ // if PSR.ic=0, reading interruption registers causes an illegal operation fault mov r3=psr;; tbit.nz.unc p6,p0=r3,PSR_IC;; // PSI Valid Log bit pos. test -(p6) st8 [r2]=r0,9*8+160 // increment by 168 byte inc. +(p6) st8 [r2]=r0,9*8+160 // increment by 232 byte inc. begin_skip_intr_regs: - BRANCH(SkipIntrRegs, r9, p6, 0x0) - ;; +(p6) br SkipIntrRegs;; + add r4=8,r2 // duplicate r2 in r4 add r6=2*8,r2 // duplicate r2 in r6 mov r3=cr16 // cr.ipsr mov r5=cr17 // cr.isr - mov r7=r0;; // cr.ida => cr18 + mov r7=r0;; // cr.ida => cr18 (reserved) st8 [r2]=r3,3*8 st8 [r4]=r5,3*8 st8 [r6]=r7,3*8;; @@ -394,8 +384,7 @@ br.cloop.sptk.few cStRR ;; end_os_mca_dump: - BRANCH(ia64_os_mca_done_dump, r2, p0, -0x10) - ;; + br ia64_os_mca_done_dump;; //EndStub////////////////////////////////////////////////////////////////////// @@ -484,11 +473,10 @@ // if PSR.ic=1, reading interruption registers causes an illegal operation fault mov r3=psr;; tbit.nz.unc p6,p0=r3,PSR_IC;; // PSI Valid Log bit pos. test -(p6) st8 [r2]=r0,9*8+160 // increment by 160 byte inc. +(p6) st8 [r2]=r0,9*8+160 // increment by 232 byte inc. begin_rskip_intr_regs: - BRANCH(rSkipIntrRegs, r9, p6, 0x0) - ;; +(p6) br rSkipIntrRegs;; add r4=8,r2 // duplicate r2 in r4 add r6=2*8,r2;; // duplicate r2 in r4 @@ -498,7 +486,7 @@ ld8 r7=[r6],3*8;; mov cr16=r3 // cr.ipsr mov cr17=r5 // cr.isr is read only -// mov cr18=r7;; // cr.ida +// mov cr18=r7;; // cr.ida (reserved - don't restore) ld8 r3=[r2],3*8 ld8 r5=[r4],3*8 @@ -629,8 +617,8 @@ mov ar.lc=r5 ;; end_os_mca_restore: - BRANCH(ia64_os_mca_done_restore, r2, p0, -0x20) - ;; + br ia64_os_mca_done_restore;; + //EndStub////////////////////////////////////////////////////////////////////// // ok, the issue here is that we need to save state information so @@ -660,12 +648,7 @@ // 6. GR12 = Return address to location within SAL_INIT procedure - .text - .align 16 -.global ia64_monarch_init_handler -.proc ia64_monarch_init_handler -ia64_monarch_init_handler: - +GLOBAL_ENTRY(ia64_monarch_init_handler) #if defined(CONFIG_SMP) && defined(SAL_MPINIT_WORKAROUND) // // work around SAL bug that sends all processors to monarch entry @@ -741,13 +724,12 @@ adds out0=16,sp // out0 = pointer to pt_regs ;; - br.call.sptk.few rp=ia64_init_handler + br.call.sptk.many rp=ia64_init_handler .ret1: return_from_init: br.sptk return_from_init - - .endp +END(ia64_monarch_init_handler) // // SAL to OS entry point for INIT on the slave processor @@ -755,14 +737,6 @@ // as a part of ia64_mca_init. // - .text - .align 16 -.global ia64_slave_init_handler -.proc ia64_slave_init_handler -ia64_slave_init_handler: - - -slave_init_spin_me: - br.sptk slave_init_spin_me - ;; - .endp +GLOBAL_ENTRY(ia64_slave_init_handler) +1: br.sptk 1b +END(ia64_slave_init_handler) diff -urN linux-2.4.10/arch/ia64/kernel/pal.S linux-2.4.10-lia/arch/ia64/kernel/pal.S --- linux-2.4.10/arch/ia64/kernel/pal.S Thu Apr 5 12:51:47 2001 +++ linux-2.4.10-lia/arch/ia64/kernel/pal.S Mon Sep 24 21:50:01 2001 @@ -4,8 +4,9 @@ * * Copyright (C) 1999 Don Dugger * Copyright (C) 1999 Walt Drummond - * Copyright (C) 1999-2000 David Mosberger - * Copyright (C) 2000 Stephane Eranian + * Copyright (C) 1999-2001 Hewlett-Packard Co + * David Mosberger + * Stephane Eranian * * 05/22/2000 eranian Added support for stacked register calls * 05/24/2000 eranian Added support for physical mode static calls @@ -31,7 +32,7 @@ movl r2=pal_entry_point ;; st8 [r2]=in0 - br.ret.sptk.few rp + br.ret.sptk.many rp END(ia64_pal_handler_init) /* @@ -41,7 +42,7 @@ */ GLOBAL_ENTRY(ia64_pal_default_handler) mov r8=-1 - br.cond.sptk.few rp + br.cond.sptk.many rp END(ia64_pal_default_handler) /* @@ -79,13 +80,13 @@ ;; (p6) srlz.i mov rp = r8 - br.cond.sptk.few b7 + br.cond.sptk.many b7 1: mov psr.l = loc3 mov ar.pfs = loc1 mov rp = loc0 ;; srlz.d // seralize restoration of psr.l - br.ret.sptk.few b0 + br.ret.sptk.many b0 END(ia64_pal_call_static) /* @@ -120,7 +121,7 @@ mov rp = loc0 ;; srlz.d // serialize restoration of psr.l - br.ret.sptk.few b0 + br.ret.sptk.many b0 END(ia64_pal_call_stacked) /* @@ -173,13 +174,13 @@ or loc3=loc3,r17 // add in psr the bits to set ;; andcm r16=loc3,r16 // removes bits to clear from psr - br.call.sptk.few rp=ia64_switch_mode + br.call.sptk.many rp=ia64_switch_mode .ret1: mov rp = r8 // install return address (physical) - br.cond.sptk.few b7 + br.cond.sptk.many b7 1: mov ar.rsc=0 // put RSE in enforced lazy, LE mode mov r16=loc3 // r16= original psr - br.call.sptk.few rp=ia64_switch_mode // return to virtual mode + br.call.sptk.many rp=ia64_switch_mode // return to virtual mode .ret2: mov psr.l = loc3 // restore init PSR @@ -188,7 +189,7 @@ ;; mov ar.rsc=loc4 // restore RSE configuration srlz.d // seralize restoration of psr.l - br.ret.sptk.few b0 + br.ret.sptk.many b0 END(ia64_pal_call_phys_static) /* @@ -227,13 +228,13 @@ mov b7 = loc2 // install target to branch reg ;; andcm r16=loc3,r16 // removes bits to clear from psr - br.call.sptk.few rp=ia64_switch_mode + br.call.sptk.many rp=ia64_switch_mode .ret6: br.call.sptk.many rp=b7 // now make the call .ret7: mov ar.rsc=0 // put RSE in enforced lazy, LE mode mov r16=loc3 // r16= original psr - br.call.sptk.few rp=ia64_switch_mode // return to virtual mode + br.call.sptk.many rp=ia64_switch_mode // return to virtual mode .ret8: mov psr.l = loc3 // restore init PSR mov ar.pfs = loc1 @@ -241,6 +242,6 @@ ;; mov ar.rsc=loc4 // restore RSE configuration srlz.d // seralize restoration of psr.l - br.ret.sptk.few b0 + br.ret.sptk.many b0 END(ia64_pal_call_phys_stacked) diff -urN linux-2.4.10/arch/ia64/kernel/pci.c linux-2.4.10-lia/arch/ia64/kernel/pci.c --- linux-2.4.10/arch/ia64/kernel/pci.c Tue Jul 31 10:30:08 2001 +++ linux-2.4.10-lia/arch/ia64/kernel/pci.c Mon Aug 13 23:53:49 2001 @@ -38,6 +38,10 @@ #define DBG(x...) #endif +#ifdef CONFIG_IA64_MCA +extern void ia64_mca_check_errors( void ); +#endif + /* * This interrupt-safe spinlock protects all accesses to PCI * configuration space. @@ -122,6 +126,10 @@ # define PCI_BUSES_TO_SCAN 255 int i; +#ifdef CONFIG_IA64_MCA + ia64_mca_check_errors(); /* For post-failure MCA error logging */ +#endif + platform_pci_fixup(0); /* phase 0 initialization (before PCI bus has been scanned) */ printk("PCI: Probing PCI hardware\n"); @@ -194,4 +202,40 @@ pcibios_setup (char *str) { return NULL; +} + +int +pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma, + enum pci_mmap_state mmap_state, int write_combine) +{ + /* + * I/O space cannot be accessed via normal processor loads and stores on this + * platform. + */ + if (mmap_state == pci_mmap_io) + /* + * XXX we could relax this for I/O spaces for which ACPI indicates that + * the space is 1-to-1 mapped. But at the moment, we don't support + * multiple PCI address spaces and the legacy I/O space is not 1-to-1 + * mapped, so this is moot. + */ + return -EINVAL; + + /* + * Leave vm_pgoff as-is, the PCI space address is the physical address on this + * platform. + */ + vma->vm_flags |= (VM_SHM | VM_LOCKED | VM_IO); + + if (write_combine) + vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); + else + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); + + if (remap_page_range(vma->vm_start, vma->vm_pgoff << PAGE_SHIFT, + vma->vm_end - vma->vm_start, + vma->vm_page_prot)) + return -EAGAIN; + + return 0; } diff -urN linux-2.4.10/arch/ia64/kernel/perfmon.c linux-2.4.10-lia/arch/ia64/kernel/perfmon.c --- linux-2.4.10/arch/ia64/kernel/perfmon.c Tue Jul 31 10:30:08 2001 +++ linux-2.4.10-lia/arch/ia64/kernel/perfmon.c Mon Sep 24 21:50:18 2001 @@ -38,7 +38,7 @@ #ifdef CONFIG_PERFMON -#define PFM_VERSION "0.2" +#define PFM_VERSION "0.3" #define PFM_SMPL_HDR_VERSION 1 #define PMU_FIRST_COUNTER 4 /* first generic counter */ @@ -52,6 +52,7 @@ #define PFM_DISABLE 0xa6 /* freeze only */ #define PFM_RESTART 0xcf #define PFM_CREATE_CONTEXT 0xa7 +#define PFM_DESTROY_CONTEXT 0xa8 /* * Those 2 are just meant for debugging. I considered using sysctl() for * that but it is a little bit too pervasive. This solution is at least @@ -60,6 +61,8 @@ #define PFM_DEBUG_ON 0xe0 #define PFM_DEBUG_OFF 0xe1 +#define PFM_DEBUG_BASE PFM_DEBUG_ON + /* * perfmon API flags @@ -68,7 +71,8 @@ #define PFM_FL_INHERIT_ONCE 0x01 /* clone pfm_context only once across fork() */ #define PFM_FL_INHERIT_ALL 0x02 /* always clone pfm_context across fork() */ #define PFM_FL_SMPL_OVFL_NOBLOCK 0x04 /* do not block on sampling buffer overflow */ -#define PFM_FL_SYSTEMWIDE 0x08 /* create a systemwide context */ +#define PFM_FL_SYSTEM_WIDE 0x08 /* create a system wide context */ +#define PFM_FL_EXCL_INTR 0x10 /* exclude interrupt from system wide monitoring */ /* * PMC API flags @@ -87,7 +91,7 @@ #endif #define PMC_IS_IMPL(i) (i < pmu_conf.num_pmcs && pmu_conf.impl_regs[i>>6] & (1<< (i&~(64-1)))) -#define PMD_IS_IMPL(i) (i < pmu_conf.num_pmds && pmu_conf.impl_regs[4+(i>>6)] & (1<< (i&~(64-1)))) +#define PMD_IS_IMPL(i) (i < pmu_conf.num_pmds && pmu_conf.impl_regs[4+(i>>6)] & (1<< (i&~(64-1)))) #define PMD_IS_COUNTER(i) (i>=PMU_FIRST_COUNTER && i < (PMU_FIRST_COUNTER+pmu_conf.max_counters)) #define PMC_IS_COUNTER(i) (i>=PMU_FIRST_COUNTER && i < (PMU_FIRST_COUNTER+pmu_conf.max_counters)) @@ -197,7 +201,8 @@ unsigned int noblock:1; /* block/don't block on overflow with notification */ unsigned int system:1; /* do system wide monitoring */ unsigned int frozen:1; /* pmu must be kept frozen on ctxsw in */ - unsigned int reserved:27; + unsigned int exclintr:1;/* exlcude interrupts from system wide monitoring */ + unsigned int reserved:26; } pfm_context_flags_t; typedef struct pfm_context { @@ -207,26 +212,33 @@ unsigned long ctx_iear_counter; /* which PMD holds I-EAR */ unsigned long ctx_btb_counter; /* which PMD holds BTB */ - pid_t ctx_notify_pid; /* who to notify on overflow */ - int ctx_notify_sig; /* XXX: SIGPROF or other */ - pfm_context_flags_t ctx_flags; /* block/noblock */ - pid_t ctx_creator; /* pid of creator (debug) */ - unsigned long ctx_ovfl_regs; /* which registers just overflowed (notification) */ - unsigned long ctx_smpl_regs; /* which registers to record on overflow */ + spinlock_t ctx_notify_lock; + pfm_context_flags_t ctx_flags; /* block/noblock */ + int ctx_notify_sig; /* XXX: SIGPROF or other */ + struct task_struct *ctx_notify_task; /* who to notify on overflow */ + struct task_struct *ctx_creator; /* pid of creator (debug) */ + + unsigned long ctx_ovfl_regs; /* which registers just overflowed (notification) */ + unsigned long ctx_smpl_regs; /* which registers to record on overflow */ + + struct semaphore ctx_restart_sem; /* use for blocking notification mode */ - struct semaphore ctx_restart_sem; /* use for blocking notification mode */ + unsigned long ctx_used_pmds[4]; /* bitmask of used PMD (speedup ctxsw) */ + unsigned long ctx_used_pmcs[4]; /* bitmask of used PMC (speedup ctxsw) */ pfm_counter_t ctx_pmds[IA64_NUM_PMD_COUNTERS]; /* XXX: size should be dynamic */ + } pfm_context_t; +#define CTX_USED_PMD(ctx,n) (ctx)->ctx_used_pmds[(n)>>6] |= 1<< ((n) % 64) +#define CTX_USED_PMC(ctx,n) (ctx)->ctx_used_pmcs[(n)>>6] |= 1<< ((n) % 64) + #define ctx_fl_inherit ctx_flags.inherit #define ctx_fl_noblock ctx_flags.noblock #define ctx_fl_system ctx_flags.system #define ctx_fl_frozen ctx_flags.frozen +#define ctx_fl_exclintr ctx_flags.exclintr -#define CTX_IS_DEAR(c,n) ((c)->ctx_dear_counter == (n)) -#define CTX_IS_IEAR(c,n) ((c)->ctx_iear_counter == (n)) -#define CTX_IS_BTB(c,n) ((c)->ctx_btb_counter == (n)) #define CTX_OVFL_NOBLOCK(c) ((c)->ctx_fl_noblock == 1) #define CTX_INHERIT_MODE(c) ((c)->ctx_fl_inherit) #define CTX_HAS_SMPL(c) ((c)->ctx_smpl_buf != NULL) @@ -234,17 +246,15 @@ static pmu_config_t pmu_conf; /* for debug only */ -static unsigned long pfm_debug=0; /* 0= nodebug, >0= debug output on */ +static int pfm_debug=0; /* 0= nodebug, >0= debug output on */ + #define DBprintk(a) \ do { \ - if (pfm_debug >0) { printk(__FUNCTION__" "); printk a; } \ + if (pfm_debug >0) { printk(__FUNCTION__" %d: ", __LINE__); printk a; } \ } while (0); -static void perfmon_softint(unsigned long ignored); static void ia64_reset_pmu(void); -DECLARE_TASKLET(pfm_tasklet, perfmon_softint, 0); - /* * structure used to pass information between the interrupt handler * and the tasklet. @@ -256,26 +266,42 @@ unsigned long bitvect; /* which counters have overflowed */ } notification_info_t; -#define notification_is_invalid(i) (i->to_pid < 2) -/* will need to be cache line padded */ -static notification_info_t notify_info[NR_CPUS]; +typedef struct { + unsigned long pfs_proc_sessions; + unsigned long pfs_sys_session; /* can only be 0/1 */ + unsigned long pfs_dfl_dcr; /* XXX: hack */ + unsigned int pfs_pp; +} pfm_session_t; -/* - * We force cache line alignment to avoid false sharing - * given that we have one entry per CPU. - */ -static struct { +struct { struct task_struct *owner; } ____cacheline_aligned pmu_owners[NR_CPUS]; -/* helper macros */ + + +/* + * helper macros + */ #define SET_PMU_OWNER(t) do { pmu_owners[smp_processor_id()].owner = (t); } while(0); #define PMU_OWNER() pmu_owners[smp_processor_id()].owner +#ifdef CONFIG_SMP +#define PFM_CAN_DO_LAZY() (smp_num_cpus==1 && pfs_info.pfs_sys_session==0) +#else +#define PFM_CAN_DO_LAZY() (pfs_info.pfs_sys_session==0) +#endif + +static void pfm_lazy_save_regs (struct task_struct *ta); + /* for debug only */ static struct proc_dir_entry *perfmon_dir; /* + * XXX: hack to indicate that a system wide monitoring session is active + */ +static pfm_session_t pfs_info; + +/* * finds the number of PM(C|D) registers given * the bitvector returned by PAL */ @@ -339,8 +365,7 @@ static inline unsigned long kvirt_to_pa(unsigned long adr) { - __u64 pa; - __asm__ __volatile__ ("tpa %0 = %1" : "=r"(pa) : "r"(adr) : "memory"); + __u64 pa = ia64_tpa(adr); DBprintk(("kv2pa(%lx-->%lx)\n", adr, pa)); return pa; } @@ -568,25 +593,44 @@ static int pfx_is_sane(pfreq_context_t *pfx) { + int ctx_flags; + /* valid signal */ - if (pfx->notify_sig < 1 || pfx->notify_sig >= _NSIG) return 0; + //if (pfx->notify_sig < 1 || pfx->notify_sig >= _NSIG) return -EINVAL; + if (pfx->notify_sig !=0 && pfx->notify_sig != SIGPROF) return -EINVAL; /* cannot send to process 1, 0 means do not notify */ - if (pfx->notify_pid < 0 || pfx->notify_pid == 1) return 0; + if (pfx->notify_pid < 0 || pfx->notify_pid == 1) return -EINVAL; + + ctx_flags = pfx->flags; + if (ctx_flags & PFM_FL_SYSTEM_WIDE) { +#ifdef CONFIG_SMP + if (smp_num_cpus > 1) { + printk("perfmon: system wide monitoring on SMP not yet supported\n"); + return -EINVAL; + } +#endif + if ((ctx_flags & PFM_FL_SMPL_OVFL_NOBLOCK) == 0) { + printk("perfmon: system wide monitoring cannot use blocking notification mode\n"); + return -EINVAL; + } + } /* probably more to add here */ - return 1; + return 0; } static int -pfm_context_create(struct task_struct *task, int flags, perfmon_req_t *req) +pfm_context_create(int flags, perfmon_req_t *req) { pfm_context_t *ctx; + struct task_struct *task = NULL; perfmon_req_t tmp; void *uaddr = NULL; - int ret = -EFAULT; + int ret; int ctx_flags; + pid_t pid; /* to go away */ if (flags) { @@ -595,48 +639,156 @@ if (copy_from_user(&tmp, req, sizeof(tmp))) return -EFAULT; + ret = pfx_is_sane(&tmp.pfr_ctx); + if (ret < 0) return ret; + ctx_flags = tmp.pfr_ctx.flags; - /* not yet supported */ - if (ctx_flags & PFM_FL_SYSTEMWIDE) return -EINVAL; + if (ctx_flags & PFM_FL_SYSTEM_WIDE) { + /* + * XXX: This is not AT ALL SMP safe + */ + if (pfs_info.pfs_proc_sessions > 0) return -EBUSY; + if (pfs_info.pfs_sys_session > 0) return -EBUSY; + + pfs_info.pfs_sys_session = 1; - if (!pfx_is_sane(&tmp.pfr_ctx)) return -EINVAL; + } else if (pfs_info.pfs_sys_session >0) { + /* no per-process monitoring while there is a system wide session */ + return -EBUSY; + } else + pfs_info.pfs_proc_sessions++; ctx = pfm_context_alloc(); - if (!ctx) return -ENOMEM; + if (!ctx) goto error; + + /* record the creator (debug only) */ + ctx->ctx_creator = current; + + pid = tmp.pfr_ctx.notify_pid; + + spin_lock_init(&ctx->ctx_notify_lock); + + if (pid == current->pid) { + ctx->ctx_notify_task = task = current; + current->thread.pfm_context = ctx; + + atomic_set(¤t->thread.pfm_notifiers_check, 1); + + } else if (pid!=0) { + read_lock(&tasklist_lock); + + task = find_task_by_pid(pid); + if (task) { + /* + * record who to notify + */ + ctx->ctx_notify_task = task; + + /* + * make visible + * must be done inside critical section + * + * if the initialization does not go through it is still + * okay because child will do the scan for nothing which + * won't hurt. + */ + current->thread.pfm_context = ctx; + + /* + * will cause task to check on exit for monitored + * processes that would notify it. see release_thread() + * Note: the scan MUST be done in release thread, once the + * task has been detached from the tasklist otherwise you are + * exposed to race conditions. + */ + atomic_add(1, &task->thread.pfm_notifiers_check); + } + read_unlock(&tasklist_lock); + } - /* record who the creator is (for debug) */ - ctx->ctx_creator = task->pid; + /* + * notification process does not exist + */ + if (pid != 0 && task == NULL) { + ret = -EINVAL; + goto buffer_error; + } - ctx->ctx_notify_pid = tmp.pfr_ctx.notify_pid; ctx->ctx_notify_sig = SIGPROF; /* siginfo imposes a fixed signal */ if (tmp.pfr_ctx.smpl_entries) { DBprintk((" sampling entries=%ld\n",tmp.pfr_ctx.smpl_entries)); - if ((ret=pfm_smpl_buffer_alloc(ctx, tmp.pfr_ctx.smpl_regs, tmp.pfr_ctx.smpl_entries, &uaddr)) ) goto buffer_error; + + ret = pfm_smpl_buffer_alloc(ctx, tmp.pfr_ctx.smpl_regs, + tmp.pfr_ctx.smpl_entries, &uaddr); + if (ret<0) goto buffer_error; + tmp.pfr_ctx.smpl_vaddr = uaddr; } /* initialization of context's flags */ - ctx->ctx_fl_inherit = ctx_flags & PFM_FL_INHERIT_MASK; - ctx->ctx_fl_noblock = (ctx_flags & PFM_FL_SMPL_OVFL_NOBLOCK) ? 1 : 0; - ctx->ctx_fl_system = (ctx_flags & PFM_FL_SYSTEMWIDE) ? 1: 0; - ctx->ctx_fl_frozen = 0; + ctx->ctx_fl_inherit = ctx_flags & PFM_FL_INHERIT_MASK; + ctx->ctx_fl_noblock = (ctx_flags & PFM_FL_SMPL_OVFL_NOBLOCK) ? 1 : 0; + ctx->ctx_fl_system = (ctx_flags & PFM_FL_SYSTEM_WIDE) ? 1: 0; + ctx->ctx_fl_exclintr = (ctx_flags & PFM_FL_EXCL_INTR) ? 1: 0; + ctx->ctx_fl_frozen = 0; + + /* + * Keep track of the pmds we want to sample + * XXX: may be we don't need to save/restore the DEAR/IEAR pmds + * but we do need the BTB for sure. This is because of a hardware + * buffer of 1 only for non-BTB pmds. + */ + ctx->ctx_used_pmds[0] = tmp.pfr_ctx.smpl_regs; + ctx->ctx_used_pmcs[0] = 1; /* always save/restore PMC[0] */ sema_init(&ctx->ctx_restart_sem, 0); /* init this semaphore to locked */ - if (copy_to_user(req, &tmp, sizeof(tmp))) goto buffer_error; - DBprintk((" context=%p, pid=%d notify_sig %d notify_pid=%d\n",(void *)ctx, task->pid, ctx->ctx_notify_sig, ctx->ctx_notify_pid)); - DBprintk((" context=%p, pid=%d flags=0x%x inherit=%d noblock=%d system=%d\n",(void *)ctx, task->pid, ctx_flags, ctx->ctx_fl_inherit, ctx->ctx_fl_noblock, ctx->ctx_fl_system)); + if (copy_to_user(req, &tmp, sizeof(tmp))) { + ret = -EFAULT; + goto buffer_error; + } + + DBprintk((" context=%p, pid=%d notify_sig %d notify_task=%p\n",(void *)ctx, current->pid, ctx->ctx_notify_sig, ctx->ctx_notify_task)); + DBprintk((" context=%p, pid=%d flags=0x%x inherit=%d noblock=%d system=%d\n",(void *)ctx, current->pid, ctx_flags, ctx->ctx_fl_inherit, ctx->ctx_fl_noblock, ctx->ctx_fl_system)); + + /* + * when no notification is required, we can make this visible at the last moment + */ + if (pid == 0) current->thread.pfm_context = ctx; + + /* + * by default, we always include interrupts for system wide + * DCR.pp is set by default to zero by kernel in cpu_init() + */ + if (ctx->ctx_fl_system) { + if (ctx->ctx_fl_exclintr == 0) { + unsigned long dcr = ia64_get_dcr(); + + ia64_set_dcr(dcr|IA64_DCR_PP); + /* + * keep track of the kernel default value + */ + pfs_info.pfs_dfl_dcr = dcr; - /* link with task */ - task->thread.pfm_context = ctx; + DBprintk((" dcr.pp is set\n")); + } + } return 0; buffer_error: - vfree(ctx); - + pfm_context_free(ctx); +error: + /* + * undo session reservation + */ + if (ctx_flags & PFM_FL_SYSTEM_WIDE) { + pfs_info.pfs_sys_session = 0; + } else { + pfs_info.pfs_proc_sessions--; + } return ret; } @@ -656,8 +808,20 @@ /* upper part is ignored on rval */ ia64_set_pmd(cnum, ctx->ctx_pmds[i].smpl_rval); + + /* + * we must reset BTB index (clears pmd16.full to make + * sure we do not report the same branches twice. + * The non-blocking case in handled in update_counters() + */ + if (cnum == ctx->ctx_btb_counter) { + DBprintk(("reseting PMD16\n")); + ia64_set_pmd(16, 0); + } } } + /* just in case ! */ + ctx->ctx_ovfl_regs = 0; } static int @@ -695,20 +859,23 @@ } else if (PMC_IS_BTB(&tmp.pfr_reg.reg_value)) { ctx->ctx_btb_counter = cnum; } - +#if 0 if (tmp.pfr_reg.reg_flags & PFM_REGFL_OVFL_NOTIFY) ctx->ctx_pmds[cnum - PMU_FIRST_COUNTER].flags |= PFM_REGFL_OVFL_NOTIFY; +#endif } - + /* keep track of what we use */ + CTX_USED_PMC(ctx, cnum); ia64_set_pmc(cnum, tmp.pfr_reg.reg_value); - DBprintk((" setting PMC[%ld]=0x%lx flags=0x%x\n", cnum, tmp.pfr_reg.reg_value, ctx->ctx_pmds[cnum - PMU_FIRST_COUNTER].flags)); + + DBprintk((" setting PMC[%ld]=0x%lx flags=0x%x used_pmcs=0%lx\n", cnum, tmp.pfr_reg.reg_value, ctx->ctx_pmds[cnum - PMU_FIRST_COUNTER].flags, ctx->ctx_used_pmcs[0])); } /* * we have to set this here event hough we haven't necessarily started monitoring * because we may be context switched out */ - th->flags |= IA64_THREAD_PM_VALID; + if (ctx->ctx_fl_system==0) th->flags |= IA64_THREAD_PM_VALID; return 0; } @@ -741,25 +908,32 @@ ctx->ctx_pmds[k].val = tmp.pfr_reg.reg_value & ~pmu_conf.perf_ovfl_val; ctx->ctx_pmds[k].smpl_rval = tmp.pfr_reg.reg_smpl_reset; ctx->ctx_pmds[k].ovfl_rval = tmp.pfr_reg.reg_ovfl_reset; + + if (tmp.pfr_reg.reg_flags & PFM_REGFL_OVFL_NOTIFY) + ctx->ctx_pmds[cnum - PMU_FIRST_COUNTER].flags |= PFM_REGFL_OVFL_NOTIFY; } + /* keep track of what we use */ + CTX_USED_PMD(ctx, cnum); /* writes to unimplemented part is ignored, so this is safe */ ia64_set_pmd(cnum, tmp.pfr_reg.reg_value); /* to go away */ ia64_srlz_d(); - DBprintk((" setting PMD[%ld]: pmd.val=0x%lx pmd.ovfl_rval=0x%lx pmd.smpl_rval=0x%lx pmd=%lx\n", + DBprintk((" setting PMD[%ld]: ovfl_notify=%d pmd.val=0x%lx pmd.ovfl_rval=0x%lx pmd.smpl_rval=0x%lx pmd=%lx used_pmds=0%lx\n", cnum, + PMD_OVFL_NOTIFY(ctx, cnum - PMU_FIRST_COUNTER), ctx->ctx_pmds[k].val, ctx->ctx_pmds[k].ovfl_rval, ctx->ctx_pmds[k].smpl_rval, - ia64_get_pmd(cnum) & pmu_conf.perf_ovfl_val)); + ia64_get_pmd(cnum) & pmu_conf.perf_ovfl_val, + ctx->ctx_used_pmds[0])); } /* * we have to set this here event hough we haven't necessarily started monitoring * because we may be context switched out */ - th->flags |= IA64_THREAD_PM_VALID; + if (ctx->ctx_fl_system==0) th->flags |= IA64_THREAD_PM_VALID; return 0; } @@ -783,6 +957,8 @@ /* XXX: ctx locking may be required here */ for (i = 0; i < count; i++, req++) { + unsigned long reg_val = ~0, ctx_val = ~0; + if (copy_from_user(&tmp, req, sizeof(tmp))) return -EFAULT; if (!PMD_IS_IMPL(tmp.pfr_reg.reg_num)) return -EINVAL; @@ -791,23 +967,25 @@ if (ta == current){ val = ia64_get_pmd(tmp.pfr_reg.reg_num); } else { - val = th->pmd[tmp.pfr_reg.reg_num]; + val = reg_val = th->pmd[tmp.pfr_reg.reg_num]; } val &= pmu_conf.perf_ovfl_val; /* * lower part of .val may not be zero, so we must be an addition because of * residual count (see update_counters). */ - val += ctx->ctx_pmds[tmp.pfr_reg.reg_num - PMU_FIRST_COUNTER].val; + val += ctx_val = ctx->ctx_pmds[tmp.pfr_reg.reg_num - PMU_FIRST_COUNTER].val; } else { /* for now */ if (ta != current) return -EINVAL; + ia64_srlz_d(); val = ia64_get_pmd(tmp.pfr_reg.reg_num); } tmp.pfr_reg.reg_value = val; - DBprintk((" reading PMD[%ld]=0x%lx\n", tmp.pfr_reg.reg_num, val)); + DBprintk((" reading PMD[%ld]=0x%lx reg=0x%lx ctx_val=0x%lx pmc=0x%lx\n", + tmp.pfr_reg.reg_num, val, reg_val, ctx_val, ia64_get_pmc(tmp.pfr_reg.reg_num))); if (copy_to_user(req, &tmp, sizeof(tmp))) return -EFAULT; } @@ -822,7 +1000,7 @@ void *sem = &ctx->ctx_restart_sem; if (task == current) { - DBprintk((" restartig self %d frozen=%d \n", current->pid, ctx->ctx_fl_frozen)); + DBprintk((" restarting self %d frozen=%d \n", current->pid, ctx->ctx_fl_frozen)); pfm_reset_regs(ctx); @@ -871,6 +1049,23 @@ return 0; } +/* + * system-wide mode: propagate activation/desactivation throughout the tasklist + * + * XXX: does not work for SMP, of course + */ +static void +pfm_process_tasklist(int cmd) +{ + struct task_struct *p; + struct pt_regs *regs; + + for_each_task(p) { + regs = (struct pt_regs *)((unsigned long)p + IA64_STK_OFFSET); + regs--; + ia64_psr(regs)->pp = cmd; + } +} static int do_perfmonctl (struct task_struct *task, int cmd, int flags, perfmon_req_t *req, int count, struct pt_regs *regs) @@ -881,19 +1076,26 @@ memset(&tmp, 0, sizeof(tmp)); + if (ctx == NULL && cmd != PFM_CREATE_CONTEXT && cmd < PFM_DEBUG_BASE) { + DBprintk((" PFM_WRITE_PMCS: no context for task %d\n", task->pid)); + return -EINVAL; + } + switch (cmd) { case PFM_CREATE_CONTEXT: /* a context has already been defined */ if (ctx) return -EBUSY; - /* may be a temporary limitation */ + /* + * cannot directly create a context in another process + */ if (task != current) return -EINVAL; if (req == NULL || count != 1) return -EINVAL; if (!access_ok(VERIFY_READ, req, sizeof(struct perfmon_req_t)*count)) return -EFAULT; - return pfm_context_create(task, flags, req); + return pfm_context_create(flags, req); case PFM_WRITE_PMCS: /* we don't quite support this right now */ @@ -901,10 +1103,6 @@ if (!access_ok(VERIFY_READ, req, sizeof(struct perfmon_req_t)*count)) return -EFAULT; - if (!ctx) { - DBprintk((" PFM_WRITE_PMCS: no context for task %d\n", task->pid)); - return -EINVAL; - } return pfm_write_pmcs(task, req, count); case PFM_WRITE_PMDS: @@ -913,45 +1111,41 @@ if (!access_ok(VERIFY_READ, req, sizeof(struct perfmon_req_t)*count)) return -EFAULT; - if (!ctx) { - DBprintk((" PFM_WRITE_PMDS: no context for task %d\n", task->pid)); - return -EINVAL; - } return pfm_write_pmds(task, req, count); case PFM_START: /* we don't quite support this right now */ if (task != current) return -EINVAL; - if (!ctx) { - DBprintk((" PFM_START: no context for task %d\n", task->pid)); - return -EINVAL; - } + if (PMU_OWNER() && PMU_OWNER() != current && PFM_CAN_DO_LAZY()) pfm_lazy_save_regs(PMU_OWNER()); SET_PMU_OWNER(current); /* will start monitoring right after rfi */ ia64_psr(regs)->up = 1; + ia64_psr(regs)->pp = 1; + + if (ctx->ctx_fl_system) { + pfm_process_tasklist(1); + pfs_info.pfs_pp = 1; + } /* * mark the state as valid. * this will trigger save/restore at context switch */ - th->flags |= IA64_THREAD_PM_VALID; + if (ctx->ctx_fl_system==0) th->flags |= IA64_THREAD_PM_VALID; ia64_set_pmc(0, 0); ia64_srlz_d(); - break; + break; case PFM_ENABLE: /* we don't quite support this right now */ if (task != current) return -EINVAL; - if (!ctx) { - DBprintk((" PFM_ENABLE: no context for task %d\n", task->pid)); - return -EINVAL; - } + if (PMU_OWNER() && PMU_OWNER() != current && PFM_CAN_DO_LAZY()) pfm_lazy_save_regs(PMU_OWNER()); /* reset all registers to stable quiet state */ ia64_reset_pmu(); @@ -969,7 +1163,7 @@ * mark the state as valid. * this will trigger save/restore at context switch */ - th->flags |= IA64_THREAD_PM_VALID; + if (ctx->ctx_fl_system==0) th->flags |= IA64_THREAD_PM_VALID; /* simply unfreeze */ ia64_set_pmc(0, 0); @@ -983,54 +1177,41 @@ /* simply freeze */ ia64_set_pmc(0, 1); ia64_srlz_d(); + /* + * XXX: cannot really toggle IA64_THREAD_PM_VALID + * but context is still considered valid, so any + * read request would return something valid. Same + * thing when this task terminates (pfm_flush_regs()). + */ break; case PFM_READ_PMDS: if (!access_ok(VERIFY_READ, req, sizeof(struct perfmon_req_t)*count)) return -EFAULT; if (!access_ok(VERIFY_WRITE, req, sizeof(struct perfmon_req_t)*count)) return -EFAULT; - if (!ctx) { - DBprintk((" PFM_READ_PMDS: no context for task %d\n", task->pid)); - return -EINVAL; - } return pfm_read_pmds(task, req, count); case PFM_STOP: /* we don't quite support this right now */ if (task != current) return -EINVAL; - ia64_set_pmc(0, 1); - ia64_srlz_d(); - + /* simply stop monitors, not PMU */ ia64_psr(regs)->up = 0; + ia64_psr(regs)->pp = 0; - th->flags &= ~IA64_THREAD_PM_VALID; - - SET_PMU_OWNER(NULL); - - /* we probably will need some more cleanup here */ - break; - - case PFM_DEBUG_ON: - printk(" debugging on\n"); - pfm_debug = 1; - break; + if (ctx->ctx_fl_system) { + pfm_process_tasklist(0); + pfs_info.pfs_pp = 0; + } - case PFM_DEBUG_OFF: - printk(" debugging off\n"); - pfm_debug = 0; break; case PFM_RESTART: /* temporary, will most likely end up as a PFM_ENABLE */ - if ((th->flags & IA64_THREAD_PM_VALID) == 0) { + if ((th->flags & IA64_THREAD_PM_VALID) == 0 && ctx->ctx_fl_system==0) { printk(" PFM_RESTART not monitoring\n"); return -EINVAL; } - if (!ctx) { - printk(" PFM_RESTART no ctx for %d\n", task->pid); - return -EINVAL; - } if (CTX_OVFL_NOBLOCK(ctx) == 0 && ctx->ctx_fl_frozen==0) { printk("task %d without pmu_frozen set\n", task->pid); return -EINVAL; @@ -1038,6 +1219,37 @@ return pfm_do_restart(task); /* we only look at first entry */ + case PFM_DESTROY_CONTEXT: + /* we don't quite support this right now */ + if (task != current) return -EINVAL; + + /* first stop monitors */ + ia64_psr(regs)->up = 0; + ia64_psr(regs)->pp = 0; + + /* then freeze PMU */ + ia64_set_pmc(0, 1); + ia64_srlz_d(); + + /* don't save/restore on context switch */ + if (ctx->ctx_fl_system ==0) task->thread.flags &= ~IA64_THREAD_PM_VALID; + + SET_PMU_OWNER(NULL); + + /* now free context and related state */ + pfm_context_exit(task); + break; + + case PFM_DEBUG_ON: + printk("perfmon debugging on\n"); + pfm_debug = 1; + break; + + case PFM_DEBUG_OFF: + printk("perfmon debugging off\n"); + pfm_debug = 0; + break; + default: DBprintk((" UNknown command 0x%x\n", cmd)); return -EINVAL; @@ -1074,11 +1286,8 @@ /* XXX: pid interface is going away in favor of pfm context */ if (pid != current->pid) { read_lock(&tasklist_lock); - { - child = find_task_by_pid(pid); - if (child) - get_task_struct(child); - } + + child = find_task_by_pid(pid); if (!child) goto abort_call; @@ -1101,93 +1310,44 @@ return ret; } - -/* - * This function is invoked on the exit path of the kernel. Therefore it must make sure - * it does does modify the caller's input registers (in0-in7) in case of entry by system call - * which can be restarted. That's why it's declared as a system call and all 8 possible args - * are declared even though not used. - */ #if __GNUC__ >= 3 void asmlinkage -pfm_overflow_notify(void) +pfm_block_on_overflow(void) #else void asmlinkage -pfm_overflow_notify(u64 arg0, u64 arg1, u64 arg2, u64 arg3, u64 arg4, u64 arg5, u64 arg6, u64 arg7) +pfm_block_on_overflow(u64 arg0, u64 arg1, u64 arg2, u64 arg3, u64 arg4, u64 arg5, u64 arg6, u64 arg7) #endif { - struct task_struct *task; struct thread_struct *th = ¤t->thread; pfm_context_t *ctx = current->thread.pfm_context; - struct siginfo si; int ret; /* - * do some sanity checks first - */ - if (!ctx) { - printk("perfmon: process %d has no PFM context\n", current->pid); - return; - } - if (ctx->ctx_notify_pid < 2) { - printk("perfmon: process %d invalid notify_pid=%d\n", current->pid, ctx->ctx_notify_pid); - return; - } - - DBprintk((" current=%d ctx=%p bv=0%lx\n", current->pid, (void *)ctx, ctx->ctx_ovfl_regs)); - /* * NO matter what notify_pid is, * we clear overflow, won't notify again */ - th->pfm_pend_notify = 0; + th->pfm_must_block = 0; /* - * When measuring in kernel mode and non-blocking fashion, it is possible to - * get an overflow while executing this code. Therefore the state of pend_notify - * and ovfl_regs can be altered. The important point is not to loose any notification. - * It is fine to get called for nothing. To make sure we do collect as much state as - * possible, update_counters() always uses |= to add bit to the ovfl_regs field. - * - * In certain cases, it is possible to come here, with ovfl_regs == 0; - * - * XXX: pend_notify and ovfl_regs could be merged maybe ! + * do some sanity checks first */ - if (ctx->ctx_ovfl_regs == 0) { - printk("perfmon: spurious overflow notification from pid %d\n", current->pid); + if (!ctx) { + printk("perfmon: process %d has no PFM context\n", current->pid); return; } - read_lock(&tasklist_lock); - - task = find_task_by_pid(ctx->ctx_notify_pid); - - if (task) { - si.si_signo = ctx->ctx_notify_sig; - si.si_errno = 0; - si.si_code = PROF_OVFL; /* goes to user */ - si.si_addr = NULL; - si.si_pid = current->pid; /* who is sending */ - si.si_pfm_ovfl = ctx->ctx_ovfl_regs; - - DBprintk((" SIGPROF to %d @ %p\n", task->pid, (void *)task)); - - /* must be done with tasklist_lock locked */ - ret = send_sig_info(ctx->ctx_notify_sig, &si, task); - if (ret != 0) { - DBprintk((" send_sig_info(process %d, SIGPROF)=%d\n", ctx->ctx_notify_pid, ret)); - task = NULL; /* will cause return */ - } - } else { - printk("perfmon: notify_pid %d not found\n", ctx->ctx_notify_pid); + if (ctx->ctx_notify_task == 0) { + printk("perfmon: process %d has no task to notify\n", current->pid); + return; } - read_unlock(&tasklist_lock); + DBprintk((" current=%d task=%d\n", current->pid, ctx->ctx_notify_task->pid)); - /* now that we have released the lock handle error condition */ - if (!task || CTX_OVFL_NOBLOCK(ctx)) { - /* we clear all pending overflow bits in noblock mode */ - ctx->ctx_ovfl_regs = 0; + /* should not happen */ + if (CTX_OVFL_NOBLOCK(ctx)) { + printk("perfmon: process %d non-blocking ctx should not be here\n", current->pid); return; } + DBprintk((" CPU%d %d before sleep\n", smp_processor_id(), current->pid)); /* @@ -1211,9 +1371,6 @@ pfm_reset_regs(ctx); - /* now we can clear this mask */ - ctx->ctx_ovfl_regs = 0; - /* * Unlock sampling buffer and reset index atomically * XXX: not really needed when blocking @@ -1232,84 +1389,14 @@ } } -static void -perfmon_softint(unsigned long ignored) -{ - notification_info_t *info; - int my_cpu = smp_processor_id(); - struct task_struct *task; - struct siginfo si; - - info = notify_info+my_cpu; - - DBprintk((" CPU%d current=%d to_pid=%d from_pid=%d bv=0x%lx\n", \ - smp_processor_id(), current->pid, info->to_pid, info->from_pid, info->bitvect)); - - /* assumption check */ - if (info->from_pid == info->to_pid) { - DBprintk((" Tasklet assumption error: from=%d tor=%d\n", info->from_pid, info->to_pid)); - return; - } - - if (notification_is_invalid(info)) { - DBprintk((" invalid notification information\n")); - return; - } - - /* sanity check */ - if (info->to_pid == 1) { - DBprintk((" cannot notify init\n")); - return; - } - /* - * XXX: needs way more checks here to make sure we send to a task we have control over - */ - read_lock(&tasklist_lock); - - task = find_task_by_pid(info->to_pid); - - DBprintk((" after find %p\n", (void *)task)); - - if (task) { - int ret; - - si.si_signo = SIGPROF; - si.si_errno = 0; - si.si_code = PROF_OVFL; /* goes to user */ - si.si_addr = NULL; - si.si_pid = info->from_pid; /* who is sending */ - si.si_pfm_ovfl = info->bitvect; - - DBprintk((" SIGPROF to %d @ %p\n", task->pid, (void *)task)); - - /* must be done with tasklist_lock locked */ - ret = send_sig_info(SIGPROF, &si, task); - if (ret != 0) - DBprintk((" send_sig_info(process %d, SIGPROF)=%d\n", info->to_pid, ret)); - - /* invalidate notification */ - info->to_pid = info->from_pid = 0; - info->bitvect = 0; - } - - read_unlock(&tasklist_lock); - - DBprintk((" after unlock %p\n", (void *)task)); - - if (!task) { - printk("perfmon: CPU%d cannot find process %d\n", smp_processor_id(), info->to_pid); - } -} - /* * main overflow processing routine. * it can be called from the interrupt path or explicitely during the context switch code * Return: - * 0 : do not unfreeze the PMU - * 1 : PMU can be unfrozen + * new value of pmc[0]. if 0x0 then unfreeze, else keep frozen */ -static unsigned long -update_counters (struct task_struct *ta, u64 pmc0, struct pt_regs *regs) +unsigned long +update_counters (struct task_struct *task, u64 pmc0, struct pt_regs *regs) { unsigned long mask, i, cnum; struct thread_struct *th; @@ -1317,7 +1404,9 @@ unsigned long bv = 0; int my_cpu = smp_processor_id(); int ret = 1, buffer_is_full = 0; - int ovfl_is_smpl, can_notify, need_reset_pmd16=0; + int ovfl_has_long_recovery, can_notify, need_reset_pmd16=0; + struct siginfo si; + /* * It is never safe to access the task for which the overflow interrupt is destinated * using the current variable as the interrupt may occur in the middle of a context switch @@ -1331,23 +1420,23 @@ * valid one, i.e. the one that caused the interrupt. */ - if (ta == NULL) { + if (task == NULL) { DBprintk((" owners[%d]=NULL\n", my_cpu)); return 0x1; } - th = &ta->thread; + th = &task->thread; ctx = th->pfm_context; /* * XXX: debug test * Don't think this could happen given upfront tests */ - if ((th->flags & IA64_THREAD_PM_VALID) == 0) { - printk("perfmon: Spurious overflow interrupt: process %d not using perfmon\n", ta->pid); + if ((th->flags & IA64_THREAD_PM_VALID) == 0 && ctx->ctx_fl_system == 0) { + printk("perfmon: Spurious overflow interrupt: process %d not using perfmon\n", task->pid); return 0x1; } if (!ctx) { - printk("perfmon: Spurious overflow interrupt: process %d has no PFM context\n", ta->pid); + printk("perfmon: Spurious overflow interrupt: process %d has no PFM context\n", task->pid); return 0; } @@ -1355,16 +1444,21 @@ * sanity test. Should never happen */ if ((pmc0 & 0x1 )== 0) { - printk("perfmon: pid %d pmc0=0x%lx assumption error for freeze bit\n", ta->pid, pmc0); + printk("perfmon: pid %d pmc0=0x%lx assumption error for freeze bit\n", task->pid, pmc0); return 0x0; } mask = pmc0 >> PMU_FIRST_COUNTER; - DBprintk(("pmc0=0x%lx pid=%d\n", pmc0, ta->pid)); - - DBprintk(("ctx is in %s mode\n", CTX_OVFL_NOBLOCK(ctx) ? "NO-BLOCK" : "BLOCK")); + DBprintk(("pmc0=0x%lx pid=%d owner=%d iip=0x%lx, ctx is in %s mode used_pmds=0x%lx used_pmcs=0x%lx\n", + pmc0, task->pid, PMU_OWNER()->pid, regs->cr_iip, + CTX_OVFL_NOBLOCK(ctx) ? "NO-BLOCK" : "BLOCK", + ctx->ctx_used_pmds[0], + ctx->ctx_used_pmcs[0])); + /* + * XXX: need to record sample only when an EAR/BTB has overflowed + */ if (CTX_HAS_SMPL(ctx)) { pfm_smpl_buffer_desc_t *psb = ctx->ctx_smpl_buf; unsigned long *e, m, idx=0; @@ -1372,11 +1466,15 @@ int j; idx = ia64_fetch_and_add(1, &psb->psb_index); - DBprintk((" trying to record index=%ld entries=%ld\n", idx, psb->psb_entries)); + DBprintk((" recording index=%ld entries=%ld\n", idx, psb->psb_entries)); /* * XXX: there is a small chance that we could run out on index before resetting * but index is unsigned long, so it will take some time..... + * We use > instead of == because fetch_and_add() is off by one (see below) + * + * This case can happen in non-blocking mode or with multiple processes. + * For non-blocking, we need to reload and continue. */ if (idx > psb->psb_entries) { buffer_is_full = 1; @@ -1388,7 +1486,7 @@ h = (perfmon_smpl_entry_t *)(((char *)psb->psb_addr) + idx*(psb->psb_entry_size)); - h->pid = ta->pid; + h->pid = task->pid; h->cpu = my_cpu; h->rate = 0; h->ip = regs ? regs->cr_iip : 0x0; /* where did the fault happened */ @@ -1398,6 +1496,7 @@ h->stamp = perfmon_get_stamp(); e = (unsigned long *)(h+1); + /* * selectively store PMDs in increasing index number */ @@ -1406,35 +1505,66 @@ if (PMD_IS_COUNTER(j)) *e = ctx->ctx_pmds[j-PMU_FIRST_COUNTER].val + (ia64_get_pmd(j) & pmu_conf.perf_ovfl_val); - else + else { *e = ia64_get_pmd(j); /* slow */ + } DBprintk((" e=%p pmd%d =0x%lx\n", (void *)e, j, *e)); e++; } } - /* make the new entry visible to user, needs to be atomic */ + /* + * make the new entry visible to user, needs to be atomic + */ ia64_fetch_and_add(1, &psb->psb_hdr->hdr_count); DBprintk((" index=%ld entries=%ld hdr_count=%ld\n", idx, psb->psb_entries, psb->psb_hdr->hdr_count)); - - /* sampling buffer full ? */ + /* + * sampling buffer full ? + */ if (idx == (psb->psb_entries-1)) { - bv = mask; + /* + * will cause notification, cannot be 0 + */ + bv = mask << PMU_FIRST_COUNTER; + buffer_is_full = 1; DBprintk((" sampling buffer full must notify bv=0x%lx\n", bv)); - if (!CTX_OVFL_NOBLOCK(ctx)) goto buffer_full; + /* + * we do not reload here, when context is blocking + */ + if (!CTX_OVFL_NOBLOCK(ctx)) goto no_reload; + /* * here, we have a full buffer but we are in non-blocking mode - * so we need to reloads overflowed PMDs with sampling reset values - * and restart + * so we need to reload overflowed PMDs with sampling reset values + * and restart right away. */ } + /* FALL THROUGH */ } reload_pmds: - ovfl_is_smpl = CTX_OVFL_NOBLOCK(ctx) && buffer_is_full; - can_notify = CTX_HAS_SMPL(ctx) == 0 && ctx->ctx_notify_pid; + + /* + * in the case of a non-blocking context, we reload + * with the ovfl_rval when no user notification is taking place (short recovery) + * otherwise when the buffer is full which requires user interaction) then we use + * smpl_rval which is the long_recovery path (disturbance introduce by user execution). + * + * XXX: implies that when buffer is full then there is always notification. + */ + ovfl_has_long_recovery = CTX_OVFL_NOBLOCK(ctx) && buffer_is_full; + + /* + * XXX: CTX_HAS_SMPL() should really be something like CTX_HAS_SMPL() and is activated,i.e., + * one of the PMC is configured for EAR/BTB. + * + * When sampling, we can only notify when the sampling buffer is full. + */ + can_notify = CTX_HAS_SMPL(ctx) == 0 && ctx->ctx_notify_task; + + DBprintk((" ovfl_has_long_recovery=%d can_notify=%d\n", ovfl_has_long_recovery, can_notify)); for (i = 0, cnum = PMU_FIRST_COUNTER; mask ; cnum++, i++, mask >>= 1) { @@ -1456,7 +1586,7 @@ DBprintk((" pmod[%ld].val=0x%lx pmd=0x%lx\n", i, ctx->ctx_pmds[i].val, ia64_get_pmd(cnum)&pmu_conf.perf_ovfl_val)); if (can_notify && PMD_OVFL_NOTIFY(ctx, i)) { - DBprintk((" CPU%d should notify process %d with signal %d\n", my_cpu, ctx->ctx_notify_pid, ctx->ctx_notify_sig)); + DBprintk((" CPU%d should notify task %p with signal %d\n", my_cpu, ctx->ctx_notify_task, ctx->ctx_notify_sig)); bv |= 1 << i; } else { DBprintk((" CPU%d PMD[%ld] overflow, no notification\n", my_cpu, cnum)); @@ -1467,93 +1597,150 @@ */ /* writes to upper part are ignored, so this is safe */ - if (ovfl_is_smpl) { - DBprintk((" CPU%d PMD[%ld] reloaded with smpl_val=%lx\n", my_cpu, cnum,ctx->ctx_pmds[i].smpl_rval)); + if (ovfl_has_long_recovery) { + DBprintk((" CPU%d PMD[%ld] reload with smpl_val=%lx\n", my_cpu, cnum,ctx->ctx_pmds[i].smpl_rval)); ia64_set_pmd(cnum, ctx->ctx_pmds[i].smpl_rval); } else { - DBprintk((" CPU%d PMD[%ld] reloaded with ovfl_val=%lx\n", my_cpu, cnum,ctx->ctx_pmds[i].smpl_rval)); + DBprintk((" CPU%d PMD[%ld] reload with ovfl_val=%lx\n", my_cpu, cnum,ctx->ctx_pmds[i].smpl_rval)); ia64_set_pmd(cnum, ctx->ctx_pmds[i].ovfl_rval); } } if (cnum == ctx->ctx_btb_counter) need_reset_pmd16=1; } /* - * In case of BTB, overflow - * we need to reset the BTB index. + * In case of BTB overflow we need to reset the BTB index. */ if (need_reset_pmd16) { DBprintk(("reset PMD16\n")); ia64_set_pmd(16, 0); } -buffer_full: - /* see pfm_overflow_notify() on details for why we use |= here */ - ctx->ctx_ovfl_regs |= bv; - /* nobody to notify, return and unfreeze */ +no_reload: + + /* + * some counters overflowed, but they did not require + * user notification, so after having reloaded them above + * we simply restart + */ if (!bv) return 0x0; + ctx->ctx_ovfl_regs = bv; /* keep track of what to reset when unblocking */ + /* + * Now we know that: + * - we have some counters which overflowed (contains in bv) + * - someone has asked to be notified on overflow. + */ + + + /* + * If the notification task is still present, then notify_task is non + * null. It is clean by that task if it ever exits before we do. + */ - if (ctx->ctx_notify_pid == ta->pid) { - struct siginfo si; + if (ctx->ctx_notify_task) { si.si_errno = 0; si.si_addr = NULL; - si.si_pid = ta->pid; /* who is sending */ - + si.si_pid = task->pid; /* who is sending */ si.si_signo = ctx->ctx_notify_sig; /* is SIGPROF */ si.si_code = PROF_OVFL; /* goes to user */ si.si_pfm_ovfl = bv; + /* - * in this case, we don't stop the task, we let it go on. It will - * necessarily go to the signal handler (if any) when it goes back to - * user mode. + * when the target of the signal is not ourself, we have to be more + * careful. The notify_task may being cleared by the target task itself + * in release_thread(). We must ensure mutual exclusion here such that + * the signal is delivered (even to a dying task) safely. */ - DBprintk((" sending %d notification to self %d\n", si.si_signo, ta->pid)); - - /* this call is safe in an interrupt handler */ - ret = send_sig_info(ctx->ctx_notify_sig, &si, ta); - if (ret != 0) - printk(" send_sig_info(process %d, SIGPROF)=%d\n", ta->pid, ret); - /* - * no matter if we block or not, we keep PMU frozen and do not unfreeze on ctxsw - */ - ctx->ctx_fl_frozen = 1; + if (ctx->ctx_notify_task != current) { + /* + * grab the notification lock for this task + */ + spin_lock(&ctx->ctx_notify_lock); - } else { -#if 0 /* - * The tasklet is guaranteed to be scheduled for this CPU only + * now notify_task cannot be modified until we're done + * if NULL, they it got modified while we were in the handler */ - notify_info[my_cpu].to_pid = ctx->notify_pid; - notify_info[my_cpu].from_pid = ta->pid; /* for debug only */ - notify_info[my_cpu].bitvect = bv; - /* tasklet is inserted and active */ - tasklet_schedule(&pfm_tasklet); -#endif + if (ctx->ctx_notify_task == NULL) { + spin_unlock(&ctx->ctx_notify_lock); + goto lost_notify; + } /* - * stored the vector of overflowed registers for use in notification - * mark that a notification/blocking is pending (arm the trap) + * required by send_sig_info() to make sure the target + * task does not disappear on us. */ - th->pfm_pend_notify = 1; + read_lock(&tasklist_lock); + } + /* + * in this case, we don't stop the task, we let it go on. It will + * necessarily go to the signal handler (if any) when it goes back to + * user mode. + */ + DBprintk((" %d sending %d notification to %d\n", task->pid, si.si_signo, ctx->ctx_notify_task->pid)); + + + /* + * this call is safe in an interrupt handler, so does read_lock() on tasklist_lock + */ + ret = send_sig_info(ctx->ctx_notify_sig, &si, ctx->ctx_notify_task); + if (ret != 0) printk(" send_sig_info(process %d, SIGPROF)=%d\n", ctx->ctx_notify_task->pid, ret); + /* + * now undo the protections in order + */ + if (ctx->ctx_notify_task != current) { + read_unlock(&tasklist_lock); + spin_unlock(&ctx->ctx_notify_lock); + } /* - * if we do block, then keep PMU frozen until restart + * if we block set the pfm_must_block bit + * when in block mode, we can effectively block only when the notified + * task is not self, otherwise we would deadlock. + * in this configuration, the notification is sent, the task will not + * block on the way back to user mode, but the PMU will be kept frozen + * until PFM_RESTART. + * Note that here there is still a race condition with notify_task + * possibly being nullified behind our back, but this is fine because + * it can only be changed to NULL which by construction, can only be + * done when notify_task != current. So if it was already different + * before, changing it to NULL will still maintain this invariant. + * Of course, when it is equal to current it cannot change at this point. */ - if (!CTX_OVFL_NOBLOCK(ctx)) ctx->ctx_fl_frozen = 1; + if (!CTX_OVFL_NOBLOCK(ctx) && ctx->ctx_notify_task != current) { + th->pfm_must_block = 1; /* will cause blocking */ + } + } else { +lost_notify: + DBprintk((" notification task has disappeared !\n")); + /* + * for a non-blocking context, we make sure we do not fall into the pfm_overflow_notify() + * trap. Also in the case of a blocking context with lost notify process, then we do not + * want to block either (even though it is interruptible). In this case, the PMU will be kept + * frozen and the process will run to completion without monitoring enabled. + * + * Of course, we cannot loose notify process when self-monitoring. + */ + th->pfm_must_block = 0; - DBprintk((" process %d notify ovfl_regs=0x%lx\n", ta->pid, bv)); } /* - * keep PMU frozen (and overflowed bits cleared) when we have to stop, - * otherwise return a resume 'value' for PMC[0] - * - * XXX: maybe that's enough to get rid of ctx_fl_frozen ? + * if we block, we keep the PMU frozen. If non-blocking we restart. + * in the case of non-blocking were the notify process is lost, we also + * restart. */ - DBprintk((" will return pmc0=0x%x\n",ctx->ctx_fl_frozen ? 0x1 : 0x0)); + if (!CTX_OVFL_NOBLOCK(ctx)) + ctx->ctx_fl_frozen = 1; + else + ctx->ctx_fl_frozen = 0; + + DBprintk((" reload pmc0=0x%x must_block=%ld\n", + ctx->ctx_fl_frozen ? 0x1 : 0x0, th->pfm_must_block)); + return ctx->ctx_fl_frozen ? 0x1 : 0x0; } @@ -1595,10 +1782,17 @@ u64 pmc0 = ia64_get_pmc(0); int i; - p += sprintf(p, "PMC[0]=%lx\nPerfmon debug: %s\n", pmc0, pfm_debug ? "On" : "Off"); + p += sprintf(p, "CPU%d.pmc[0]=%lx\nPerfmon debug: %s\n", smp_processor_id(), pmc0, pfm_debug ? "On" : "Off"); + p += sprintf(p, "proc_sessions=%lu sys_sessions=%lu\n", + pfs_info.pfs_proc_sessions, + pfs_info.pfs_sys_session); + for(i=0; i < NR_CPUS; i++) { - if (cpu_is_online(i)) - p += sprintf(p, "CPU%d.PMU %d\n", i, pmu_owners[i].owner ? pmu_owners[i].owner->pid: 0); + if (cpu_is_online(i)) { + p += sprintf(p, "CPU%d.pmu_owner: %-6d\n", + i, + pmu_owners[i].owner ? pmu_owners[i].owner->pid: -1); + } } return p - page; } @@ -1648,8 +1842,8 @@ } pmu_conf.perf_ovfl_val = (1L << pm_info.pal_perf_mon_info_s.width) - 1; pmu_conf.max_counters = pm_info.pal_perf_mon_info_s.generic; - pmu_conf.num_pmds = find_num_pm_regs(pmu_conf.impl_regs); - pmu_conf.num_pmcs = find_num_pm_regs(&pmu_conf.impl_regs[4]); + pmu_conf.num_pmcs = find_num_pm_regs(pmu_conf.impl_regs); + pmu_conf.num_pmds = find_num_pm_regs(&pmu_conf.impl_regs[4]); printk("perfmon: %d bits counters (max value 0x%lx)\n", pm_info.pal_perf_mon_info_s.width, pmu_conf.perf_ovfl_val); printk("perfmon: %ld PMC/PMD pairs, %ld PMCs, %ld PMDs\n", pmu_conf.max_counters, pmu_conf.num_pmcs, pmu_conf.num_pmds); @@ -1681,21 +1875,19 @@ ia64_srlz_d(); } -/* - * XXX: for system wide this function MUST never be called - */ void pfm_save_regs (struct task_struct *ta) { struct task_struct *owner; + pfm_context_t *ctx; struct thread_struct *t; u64 pmc0, psr; + unsigned long mask; int i; - if (ta == NULL) { - panic(__FUNCTION__" task is NULL\n"); - } - t = &ta->thread; + t = &ta->thread; + ctx = ta->thread.pfm_context; + /* * We must make sure that we don't loose any potential overflow * interrupt while saving PMU context. In this code, external @@ -1715,7 +1907,7 @@ * in kernel. * By now, we could still have an overflow interrupt in-flight. */ - __asm__ __volatile__ ("rum psr.up;;"::: "memory"); + __asm__ __volatile__ ("rsm psr.up|psr.pp;;"::: "memory"); /* * Mark the PMU as not owned @@ -1744,7 +1936,6 @@ * next process does not start with monitoring on if not requested */ ia64_set_pmc(0, 1); - ia64_srlz_d(); /* * Check for overflow bits and proceed manually if needed @@ -1755,94 +1946,111 @@ * next time the task exits from the kernel. */ if (pmc0 & ~0x1) { - if (owner != ta) printk(__FUNCTION__" owner=%p task=%p\n", (void *)owner, (void *)ta); - printk(__FUNCTION__" Warning: pmc[0]=0x%lx explicit call\n", pmc0); - - pmc0 = update_counters(owner, pmc0, NULL); + update_counters(owner, pmc0, NULL); /* we will save the updated version of pmc0 */ } - /* * restore PSR for context switch to save */ __asm__ __volatile__ ("mov psr.l=%0;; srlz.i;;"::"r"(psr): "memory"); + /* + * we do not save registers if we can do lazy + */ + if (PFM_CAN_DO_LAZY()) { + SET_PMU_OWNER(owner); + return; + } /* * XXX needs further optimization. * Also must take holes into account */ - for (i=0; i< pmu_conf.num_pmds; i++) { - t->pmd[i] = ia64_get_pmd(i); + mask = ctx->ctx_used_pmds[0]; + for (i=0; mask; i++, mask>>=1) { + if (mask & 0x1) t->pmd[i] =ia64_get_pmd(i); } /* skip PMC[0], we handle it separately */ - for (i=1; i< pmu_conf.num_pmcs; i++) { - t->pmc[i] = ia64_get_pmc(i); + mask = ctx->ctx_used_pmcs[0]>>1; + for (i=1; mask; i++, mask>>=1) { + if (mask & 0x1) t->pmc[i] = ia64_get_pmc(i); } - /* * Throughout this code we could have gotten an overflow interrupt. It is transformed * into a spurious interrupt as soon as we give up pmu ownership. */ } -void -pfm_load_regs (struct task_struct *ta) +static void +pfm_lazy_save_regs (struct task_struct *ta) { - struct thread_struct *t = &ta->thread; - pfm_context_t *ctx = ta->thread.pfm_context; + pfm_context_t *ctx; + struct thread_struct *t; + unsigned long mask; int i; + DBprintk((" on [%d] by [%d]\n", ta->pid, current->pid)); + + t = &ta->thread; + ctx = ta->thread.pfm_context; /* * XXX needs further optimization. * Also must take holes into account */ - for (i=0; i< pmu_conf.num_pmds; i++) { - ia64_set_pmd(i, t->pmd[i]); + mask = ctx->ctx_used_pmds[0]; + for (i=0; mask; i++, mask>>=1) { + if (mask & 0x1) t->pmd[i] =ia64_get_pmd(i); } - - /* skip PMC[0] to avoid side effects */ - for (i=1; i< pmu_conf.num_pmcs; i++) { - ia64_set_pmc(i, t->pmc[i]); + + /* skip PMC[0], we handle it separately */ + mask = ctx->ctx_used_pmcs[0]>>1; + for (i=1; mask; i++, mask>>=1) { + if (mask & 0x1) t->pmc[i] = ia64_get_pmc(i); } + SET_PMU_OWNER(NULL); +} + +void +pfm_load_regs (struct task_struct *ta) +{ + struct thread_struct *t = &ta->thread; + pfm_context_t *ctx = ta->thread.pfm_context; + struct task_struct *owner; + unsigned long mask; + int i; + + owner = PMU_OWNER(); + if (owner == ta) goto skip_restore; + if (owner) pfm_lazy_save_regs(owner); - /* - * we first restore ownership of the PMU to the 'soon to be current' - * context. This way, if, as soon as we unfreeze the PMU at the end - * of this function, we get an interrupt, we attribute it to the correct - * task - */ SET_PMU_OWNER(ta); -#if 0 - /* - * check if we had pending overflow before context switching out - * If so, we invoke the handler manually, i.e. simulate interrupt. - * - * XXX: given that we do not use the tasklet anymore to stop, we can - * move this back to the pfm_save_regs() routine. - */ - if (t->pmc[0] & ~0x1) { - /* freeze set in pfm_save_regs() */ - DBprintk((" pmc[0]=0x%lx manual interrupt\n",t->pmc[0])); - update_counters(ta, t->pmc[0], NULL); + mask = ctx->ctx_used_pmds[0]; + for (i=0; mask; i++, mask>>=1) { + if (mask & 0x1) ia64_set_pmd(i, t->pmd[i]); } -#endif + /* skip PMC[0] to avoid side effects */ + mask = ctx->ctx_used_pmcs[0]>>1; + for (i=1; mask; i++, mask>>=1) { + if (mask & 0x1) ia64_set_pmc(i, t->pmc[i]); + } +skip_restore: /* * unfreeze only when possible */ if (ctx->ctx_fl_frozen == 0) { ia64_set_pmc(0, 0); ia64_srlz_d(); + /* place where we potentially (kernel level) start monitoring again */ } } /* * This function is called when a thread exits (from exit_thread()). - * This is a simplified pfm_save_regs() that simply flushes hthe current + * This is a simplified pfm_save_regs() that simply flushes the current * register state into the save area taking into account any pending * overflow. This time no notification is sent because the taks is dying * anyway. The inline processing of overflows avoids loosing some counts. @@ -1933,12 +2141,20 @@ /* collect latest results */ ctx->ctx_pmds[i].val += ia64_get_pmd(j) & pmu_conf.perf_ovfl_val; + /* + * now everything is in ctx_pmds[] and we need + * to clear the saved context from save_regs() such that + * pfm_read_pmds() gets the correct value + */ + ta->thread.pmd[j] = 0; + /* take care of overflow inline */ if (mask & 0x1) { ctx->ctx_pmds[i].val += 1 + pmu_conf.perf_ovfl_val; DBprintk((" PMD[%d] overflowed pmd=0x%lx pmds.val=0x%lx\n", j, ia64_get_pmd(j), ctx->ctx_pmds[i].val)); } + mask >>=1; } } @@ -1977,7 +2193,7 @@ /* clears all PMD registers */ for(i=0;i< pmu_conf.num_pmds; i++) { - if (PMD_IS_IMPL(i)) ia64_set_pmd(i,0); + if (PMD_IS_IMPL(i)) ia64_set_pmd(i,0); } ia64_srlz_d(); } @@ -1986,7 +2202,7 @@ * task is the newly created task */ int -pfm_inherit(struct task_struct *task) +pfm_inherit(struct task_struct *task, struct pt_regs *regs) { pfm_context_t *ctx = current->thread.pfm_context; pfm_context_t *nctx; @@ -1994,12 +2210,22 @@ int i, cnum; /* + * bypass completely for system wide + */ + if (pfs_info.pfs_sys_session) { + DBprintk((" enabling psr.pp for %d\n", task->pid)); + ia64_psr(regs)->pp = pfs_info.pfs_pp; + return 0; + } + + /* * takes care of easiest case first */ if (CTX_INHERIT_MODE(ctx) == PFM_FL_INHERIT_NONE) { DBprintk((" removing PFM context for %d\n", task->pid)); task->thread.pfm_context = NULL; - task->thread.pfm_pend_notify = 0; + task->thread.pfm_must_block = 0; + atomic_set(&task->thread.pfm_notifiers_check, 0); /* copy_thread() clears IA64_THREAD_PM_VALID */ return 0; } @@ -2009,9 +2235,11 @@ /* copy content */ *nctx = *ctx; - if (ctx->ctx_fl_inherit == PFM_FL_INHERIT_ONCE) { + if (CTX_INHERIT_MODE(ctx) == PFM_FL_INHERIT_ONCE) { nctx->ctx_fl_inherit = PFM_FL_INHERIT_NONE; + atomic_set(&task->thread.pfm_notifiers_check, 0); DBprintk((" downgrading to INHERIT_NONE for %d\n", task->pid)); + pfs_info.pfs_proc_sessions++; } /* initialize counters in new context */ @@ -2033,7 +2261,7 @@ sema_init(&nctx->ctx_restart_sem, 0); /* reset this semaphore to locked */ /* clear pending notification */ - th->pfm_pend_notify = 0; + th->pfm_must_block = 0; /* link with new task */ th->pfm_context = nctx; @@ -2052,7 +2280,10 @@ return 0; } -/* called from exit_thread() */ +/* + * called from release_thread(), at this point this task is not in the + * tasklist anymore + */ void pfm_context_exit(struct task_struct *task) { @@ -2068,16 +2299,126 @@ pfm_smpl_buffer_desc_t *psb = ctx->ctx_smpl_buf; /* if only user left, then remove */ - DBprintk((" pid %d: task %d sampling psb->refcnt=%d\n", current->pid, task->pid, psb->psb_refcnt.counter)); + DBprintk((" [%d] [%d] psb->refcnt=%d\n", current->pid, task->pid, psb->psb_refcnt.counter)); if (atomic_dec_and_test(&psb->psb_refcnt) ) { rvfree(psb->psb_hdr, psb->psb_size); vfree(psb); - DBprintk((" pid %d: cleaning task %d sampling buffer\n", current->pid, task->pid )); + DBprintk((" [%d] cleaning [%d] sampling buffer\n", current->pid, task->pid )); + } + } + DBprintk((" [%d] cleaning [%d] pfm_context @%p\n", current->pid, task->pid, (void *)ctx)); + + /* + * To avoid getting the notified task scan the entire process list + * when it exits because it would have pfm_notifiers_check set, we + * decrease it by 1 to inform the task, that one less task is going + * to send it notification. each new notifer increases this field by + * 1 in pfm_context_create(). Of course, there is race condition between + * decreasing the value and the notified task exiting. The danger comes + * from the fact that we have a direct pointer to its task structure + * thereby bypassing the tasklist. We must make sure that if we have + * notify_task!= NULL, the target task is still somewhat present. It may + * already be detached from the tasklist but that's okay. Note that it is + * okay if we 'miss the deadline' and the task scans the list for nothing, + * it will affect performance but not correctness. The correctness is ensured + * by using the notify_lock whic prevents the notify_task from changing on us. + * Once holdhing this lock, if we see notify_task!= NULL, then it will stay like + * that until we release the lock. If it is NULL already then we came too late. + */ + spin_lock(&ctx->ctx_notify_lock); + + if (ctx->ctx_notify_task) { + DBprintk((" [%d] [%d] atomic_sub on [%d] notifiers=%u\n", current->pid, task->pid, + ctx->ctx_notify_task->pid, + atomic_read(&ctx->ctx_notify_task->thread.pfm_notifiers_check))); + + atomic_sub(1, &ctx->ctx_notify_task->thread.pfm_notifiers_check); + } + + spin_unlock(&ctx->ctx_notify_lock); + + if (ctx->ctx_fl_system) { + /* + * if included interrupts (true by default), then reset + * to get default value + */ + if (ctx->ctx_fl_exclintr == 0) { + /* + * reload kernel default DCR value + */ + ia64_set_dcr(pfs_info.pfs_dfl_dcr); + DBprintk((" restored dcr to 0x%lx\n", pfs_info.pfs_dfl_dcr)); } + /* + * free system wide session slot + */ + pfs_info.pfs_sys_session = 0; + } else { + pfs_info.pfs_proc_sessions--; } - DBprintk((" pid %d: task %d pfm_context is freed @%p\n", current->pid, task->pid, (void *)ctx)); + pfm_context_free(ctx); + /* + * clean pfm state in thread structure, + */ + task->thread.pfm_context = NULL; + task->thread.pfm_must_block = 0; + /* pfm_notifiers is cleaned in pfm_cleanup_notifiers() */ + +} + +void +pfm_cleanup_notifiers(struct task_struct *task) +{ + struct task_struct *p; + pfm_context_t *ctx; + + DBprintk((" [%d] called\n", task->pid)); + + read_lock(&tasklist_lock); + + for_each_task(p) { + /* + * It is safe to do the 2-step test here, because thread.ctx + * is cleaned up only in release_thread() and at that point + * the task has been detached from the tasklist which is an + * operation which uses the write_lock() on the tasklist_lock + * so it cannot run concurrently to this loop. So we have the + * guarantee that if we find p and it has a perfmon ctx then + * it is going to stay like this for the entire execution of this + * loop. + */ + ctx = p->thread.pfm_context; + + DBprintk((" [%d] scanning task [%d] ctx=%p\n", task->pid, p->pid, ctx)); + + if (ctx && ctx->ctx_notify_task == task) { + DBprintk((" trying for notifier %d in %d\n", task->pid, p->pid)); + /* + * the spinlock is required to take care of a race condition + * with the send_sig_info() call. We must make sure that + * either the send_sig_info() completes using a valid task, + * or the notify_task is cleared before the send_sig_info() + * can pick up a stale value. Note that by the time this + * function is executed the 'task' is already detached from the + * tasklist. The problem is that the notifiers have a direct + * pointer to it. It is okay to send a signal to a task in this + * stage, it simply will have no effect. But it is better than sending + * to a completely destroyed task or worse to a new task using the same + * task_struct address. + */ + spin_lock(&ctx->ctx_notify_lock); + + ctx->ctx_notify_task = NULL; + + spin_unlock(&ctx->ctx_notify_lock); + + DBprintk((" done for notifier %d in %d\n", task->pid, p->pid)); + } + } + read_unlock(&tasklist_lock); + } #else /* !CONFIG_PERFMON */ diff -urN linux-2.4.10/arch/ia64/kernel/process.c linux-2.4.10-lia/arch/ia64/kernel/process.c --- linux-2.4.10/arch/ia64/kernel/process.c Tue Jul 31 10:30:08 2001 +++ linux-2.4.10-lia/arch/ia64/kernel/process.c Mon Sep 24 23:22:59 2001 @@ -63,7 +63,8 @@ { unsigned long ip = regs->cr_iip + ia64_psr(regs)->ri; - printk("\npsr : %016lx ifs : %016lx ip : [<%016lx>]\n", + printk("\nPid: %d, comm: %20s\n", current->pid, current->comm); + printk("psr : %016lx ifs : %016lx ip : [<%016lx>]\n", regs->cr_ipsr, regs->cr_ifs, ip); printk("unat: %016lx pfs : %016lx rsc : %016lx\n", regs->ar_unat, regs->ar_pfs, regs->ar_rsc); @@ -201,7 +202,7 @@ { unsigned long rbs, child_rbs, rbs_size, stack_offset, stack_top, stack_used; struct switch_stack *child_stack, *stack; - extern char ia64_ret_from_clone; + extern char ia64_ret_from_clone, ia32_ret_from_clone; struct pt_regs *child_ptregs; int retval = 0; @@ -250,7 +251,10 @@ child_ptregs->r12 = (unsigned long) (child_ptregs + 1); /* kernel sp */ child_ptregs->r13 = (unsigned long) p; /* set `current' pointer */ } - child_stack->b0 = (unsigned long) &ia64_ret_from_clone; + if (IS_IA32_PROCESS(regs)) + child_stack->b0 = (unsigned long) &ia32_ret_from_clone; + else + child_stack->b0 = (unsigned long) &ia64_ret_from_clone; child_stack->ar_bspstore = child_rbs + rbs_size; /* copy parts of thread_struct: */ @@ -285,9 +289,8 @@ ia32_save_state(p); #endif #ifdef CONFIG_PERFMON - p->thread.pfm_pend_notify = 0; if (p->thread.pfm_context) - retval = pfm_inherit(p); + retval = pfm_inherit(p, child_ptregs); #endif return retval; } @@ -441,11 +444,24 @@ } #ifdef CONFIG_PERFMON +/* + * By the time we get here, the task is detached from the tasklist. This is important + * because it means that no other tasks can ever find it as a notifiied task, therfore + * there is no race condition between this code and let's say a pfm_context_create(). + * Conversely, the pfm_cleanup_notifiers() cannot try to access a task's pfm context if + * this other task is in the middle of its own pfm_context_exit() because it would alreayd + * be out of the task list. Note that this case is very unlikely between a direct child + * and its parents (if it is the notified process) because of the way the exit is notified + * via SIGCHLD. + */ void release_thread (struct task_struct *task) { if (task->thread.pfm_context) pfm_context_exit(task); + + if(atomic_read(&task->thread.pfm_notifiers_check) >0) + pfm_cleanup_notifiers(task); } #endif @@ -524,6 +540,10 @@ void machine_halt (void) { +#if 0 + while (1) + ia64_pal_halt(0); +#endif } void diff -urN linux-2.4.10/arch/ia64/kernel/ptrace.c linux-2.4.10-lia/arch/ia64/kernel/ptrace.c --- linux-2.4.10/arch/ia64/kernel/ptrace.c Mon Sep 24 15:06:13 2001 +++ linux-2.4.10-lia/arch/ia64/kernel/ptrace.c Mon Sep 24 21:51:40 2001 @@ -2,7 +2,7 @@ * Kernel support for the ptrace() and syscall tracing interfaces. * * Copyright (C) 1999-2001 Hewlett-Packard Co - * Copyright (C) 1999-2001 David Mosberger-Tang + * David Mosberger-Tang * * Derived from the x86 and Alpha versions. Most of the code in here * could actually be factored into a common set of routines. @@ -794,11 +794,14 @@ * * Make sure the single step bit is not set. */ -void ptrace_disable(struct task_struct *child) +void +ptrace_disable (struct task_struct *child) { + struct ia64_psr *child_psr = ia64_psr(ia64_task_regs(child)); + /* make sure the single step/take-branch tra bits are not set: */ - ia64_psr(pt)->ss = 0; - ia64_psr(pt)->tb = 0; + child_psr->ss = 0; + child_psr->tb = 0; /* Turn off flag indicating that the KRBS is sync'd with child's VM: */ child->thread.flags &= ~IA64_THREAD_KRBS_SYNCED; @@ -855,6 +858,19 @@ if (child->p_pptr != current) goto out_tsk; + if (request != PTRACE_KILL) { + if (child->state != TASK_STOPPED) + goto out_tsk; + +#ifdef CONFIG_SMP + while (child->has_cpu) { + if (child->state != TASK_STOPPED) + goto out_tsk; + barrier(); + } +#endif + } + pt = ia64_task_regs(child); sw = (struct switch_stack *) (child->thread.ksp + 16); @@ -925,7 +941,7 @@ child->ptrace &= ~PT_TRACESYS; child->exit_code = data; - /* make sure the single step/take-branch tra bits are not set: */ + /* make sure the single step/taken-branch trap bits are not set: */ ia64_psr(pt)->ss = 0; ia64_psr(pt)->tb = 0; diff -urN linux-2.4.10/arch/ia64/kernel/sal.c linux-2.4.10-lia/arch/ia64/kernel/sal.c --- linux-2.4.10/arch/ia64/kernel/sal.c Thu Jan 4 12:50:17 2001 +++ linux-2.4.10-lia/arch/ia64/kernel/sal.c Mon Sep 24 21:51:59 2001 @@ -1,8 +1,8 @@ /* * System Abstraction Layer (SAL) interface routines. * - * Copyright (C) 1998, 1999 Hewlett-Packard Co - * Copyright (C) 1998, 1999 David Mosberger-Tang + * Copyright (C) 1998, 1999, 2001 Hewlett-Packard Co + * David Mosberger-Tang * Copyright (C) 1999 VA Linux Systems * Copyright (C) 1999 Walt Drummond */ @@ -18,8 +18,6 @@ #include #include -#define SAL_DEBUG - spinlock_t sal_lock = SPIN_LOCK_UNLOCKED; static struct { @@ -122,10 +120,8 @@ switch (*p) { case SAL_DESC_ENTRY_POINT: ep = (struct ia64_sal_desc_entry_point *) p; -#ifdef SAL_DEBUG - printk("sal[%d] - entry: pal_proc=0x%lx, sal_proc=0x%lx\n", - i, ep->pal_proc, ep->sal_proc); -#endif + printk("SAL: entry: pal_proc=0x%lx, sal_proc=0x%lx\n", + ep->pal_proc, ep->sal_proc); ia64_pal_handler_init(__va(ep->pal_proc)); ia64_sal_handler_init(__va(ep->sal_proc), __va(ep->gp)); break; @@ -138,17 +134,12 @@ #ifdef CONFIG_SMP { struct ia64_sal_desc_ap_wakeup *ap = (void *) p; -# ifdef SAL_DEBUG - printk("sal[%d] - wakeup type %x, 0x%lx\n", - i, ap->mechanism, ap->vector); -# endif + switch (ap->mechanism) { case IA64_SAL_AP_EXTERNAL_INT: ap_wakeup_vector = ap->vector; -# ifdef SAL_DEBUG printk("SAL: AP wakeup using external interrupt " "vector 0x%lx\n", ap_wakeup_vector); -# endif break; default: @@ -163,21 +154,13 @@ struct ia64_sal_desc_platform_feature *pf = (void *) p; printk("SAL: Platform features "); -#ifdef CONFIG_IA64_HAVE_IRQREDIR - /* - * Early versions of SAL say we don't have - * IRQ redirection, even though we do... - */ - pf->feature_mask |= (1 << 1); -#endif - if (pf->feature_mask & (1 << 0)) printk("BusLock "); if (pf->feature_mask & (1 << 1)) { printk("IRQ_Redirection "); #ifdef CONFIG_SMP - if (no_int_routing) + if (no_int_routing) smp_int_redirect &= ~SMP_IRQ_REDIRECTION; else smp_int_redirect |= SMP_IRQ_REDIRECTION; diff -urN linux-2.4.10/arch/ia64/kernel/setup.c linux-2.4.10-lia/arch/ia64/kernel/setup.c --- linux-2.4.10/arch/ia64/kernel/setup.c Tue Jul 31 10:30:08 2001 +++ linux-2.4.10-lia/arch/ia64/kernel/setup.c Mon Sep 24 21:52:16 2001 @@ -534,10 +534,13 @@ /* * Initialize default control register to defer all speculative faults. The * kernel MUST NOT depend on a particular setting of these bits (in other words, - * the kernel must have recovery code for all speculative accesses). + * the kernel must have recovery code for all speculative accesses). Turn on + * dcr.lc as per recommendation by the architecture team. Most IA-32 apps + * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll + * be fine). */ ia64_set_dcr( IA64_DCR_DM | IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR - | IA64_DCR_DA | IA64_DCR_DD); + | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC); #ifndef CONFIG_SMP ia64_set_fpu_owner(0); #endif diff -urN linux-2.4.10/arch/ia64/kernel/sigframe.h linux-2.4.10-lia/arch/ia64/kernel/sigframe.h --- linux-2.4.10/arch/ia64/kernel/sigframe.h Tue Jul 31 10:30:08 2001 +++ linux-2.4.10-lia/arch/ia64/kernel/sigframe.h Mon Sep 24 21:52:26 2001 @@ -7,10 +7,11 @@ unsigned long arg0; /* signum */ unsigned long arg1; /* siginfo pointer */ unsigned long arg2; /* sigcontext pointer */ + /* + * End of architected state. + */ - unsigned long rbs_base; /* base of new register backing store (or NULL) */ void *handler; /* pointer to the plabel of the signal handler */ - struct siginfo info; struct sigcontext sc; }; diff -urN linux-2.4.10/arch/ia64/kernel/signal.c linux-2.4.10-lia/arch/ia64/kernel/signal.c --- linux-2.4.10/arch/ia64/kernel/signal.c Tue Jul 31 10:30:08 2001 +++ linux-2.4.10-lia/arch/ia64/kernel/signal.c Mon Sep 24 21:52:38 2001 @@ -139,10 +139,9 @@ struct ia64_psr *psr = ia64_psr(&scr->pt); __copy_from_user(current->thread.fph, &sc->sc_fr[32], 96*16); - if (!psr->dfh) { - psr->mfh = 0; + psr->mfh = 0; /* drop signal handler's fph contents... */ + if (!psr->dfh) __ia64_load_fpu(current->thread.fph); - } } return err; } @@ -380,7 +379,8 @@ err = __put_user(sig, &frame->arg0); err |= __put_user(&frame->info, &frame->arg1); err |= __put_user(&frame->sc, &frame->arg2); - err |= __put_user(new_rbs, &frame->rbs_base); + err |= __put_user(new_rbs, &frame->sc.sc_rbs_base); + err |= __put_user(0, &frame->sc.sc_loadrs); /* initialize to zero */ err |= __put_user(ka->sa.sa_handler, &frame->handler); err |= copy_siginfo_to_user(&frame->info, info); @@ -460,6 +460,7 @@ long ia64_do_signal (sigset_t *oldset, struct sigscratch *scr, long in_syscall) { + struct signal_struct *sig; struct k_sigaction *ka; siginfo_t info; long restart = in_syscall; @@ -571,8 +572,8 @@ case SIGSTOP: current->state = TASK_STOPPED; current->exit_code = signr; - if (!(current->p_pptr->sig->action[SIGCHLD-1].sa.sa_flags - & SA_NOCLDSTOP)) + sig = current->p_pptr->sig; + if (sig && !(sig->action[SIGCHLD-1].sa.sa_flags & SA_NOCLDSTOP)) notify_parent(current, SIGCHLD); schedule(); continue; diff -urN linux-2.4.10/arch/ia64/kernel/smp.c linux-2.4.10-lia/arch/ia64/kernel/smp.c --- linux-2.4.10/arch/ia64/kernel/smp.c Tue Jul 31 10:30:08 2001 +++ linux-2.4.10-lia/arch/ia64/kernel/smp.c Mon Sep 24 21:53:18 2001 @@ -48,6 +48,7 @@ #include #include #include +#include /* The 'big kernel lock' */ spinlock_t kernel_flag = SPIN_LOCK_UNLOCKED; @@ -70,9 +71,6 @@ #define IPI_CALL_FUNC 0 #define IPI_CPU_STOP 1 -#ifndef CONFIG_ITANIUM_PTCG -# define IPI_FLUSH_TLB 2 -#endif /*!CONFIG_ITANIUM_PTCG */ static void stop_this_cpu (void) @@ -136,49 +134,6 @@ stop_this_cpu(); break; -#ifndef CONFIG_ITANIUM_PTCG - case IPI_FLUSH_TLB: - { - extern unsigned long flush_start, flush_end, flush_nbits, flush_rid; - extern atomic_t flush_cpu_count; - unsigned long saved_rid = ia64_get_rr(flush_start); - unsigned long end = flush_end; - unsigned long start = flush_start; - unsigned long nbits = flush_nbits; - - /* - * Current CPU may be running with different RID so we need to - * reload the RID of flushed address. Purging the translation - * also needs ALAT invalidation; we do not need "invala" here - * since it is done in ia64_leave_kernel. - */ - ia64_srlz_d(); - if (saved_rid != flush_rid) { - ia64_set_rr(flush_start, flush_rid); - ia64_srlz_d(); - } - - do { - /* - * Purge local TLB entries. - */ - __asm__ __volatile__ ("ptc.l %0,%1" :: - "r"(start), "r"(nbits<<2) : "memory"); - start += (1UL << nbits); - } while (start < end); - - ia64_insn_group_barrier(); - ia64_srlz_i(); /* srlz.i implies srlz.d */ - - if (saved_rid != flush_rid) { - ia64_set_rr(flush_start, saved_rid); - ia64_srlz_d(); - } - atomic_dec(&flush_cpu_count); - break; - } -#endif /* !CONFIG_ITANIUM_PTCG */ - default: printk(KERN_CRIT "Unknown IPI on CPU %d: %lu\n", this_cpu, which); break; @@ -228,30 +183,6 @@ platform_send_ipi(cpu, IA64_IPI_RESCHEDULE, IA64_IPI_DM_INT, 0); } -#ifndef CONFIG_ITANIUM_PTCG - -void -smp_send_flush_tlb (void) -{ - send_IPI_allbutself(IPI_FLUSH_TLB); -} - -void -smp_resend_flush_tlb (void) -{ - int i; - - /* - * Really need a null IPI but since this rarely should happen & since this code - * will go away, lets not add one. - */ - for (i = 0; i < smp_num_cpus; ++i) - if (i != smp_processor_id()) - smp_send_reschedule(i); -} - -#endif /* !CONFIG_ITANIUM_PTCG */ - void smp_flush_tlb_all (void) { @@ -277,10 +208,6 @@ { struct call_data_struct data; int cpus = 1; -#if (defined(CONFIG_ITANIUM_B0_SPECIFIC) \ - || defined(CONFIG_ITANIUM_B1_SPECIFIC) || defined(CONFIG_ITANIUM_B2_SPECIFIC)) - unsigned long timeout; -#endif if (cpuid == smp_processor_id()) { printk(__FUNCTION__" trying to call self\n"); @@ -295,26 +222,15 @@ atomic_set(&data.finished, 0); spin_lock_bh(&call_lock); - call_data = &data; - -#if (defined(CONFIG_ITANIUM_B0_SPECIFIC) \ - || defined(CONFIG_ITANIUM_B1_SPECIFIC) || defined(CONFIG_ITANIUM_B2_SPECIFIC)) - resend: - send_IPI_single(cpuid, IPI_CALL_FUNC); - /* Wait for response */ - timeout = jiffies + HZ; - while ((atomic_read(&data.started) != cpus) && time_before(jiffies, timeout)) - barrier(); - if (atomic_read(&data.started) != cpus) - goto resend; -#else + call_data = &data; + mb(); /* ensure store to call_data precedes setting of IPI_CALL_FUNC */ send_IPI_single(cpuid, IPI_CALL_FUNC); /* Wait for response */ while (atomic_read(&data.started) != cpus) barrier(); -#endif + if (wait) while (atomic_read(&data.finished) != cpus) barrier(); @@ -348,10 +264,6 @@ { struct call_data_struct data; int cpus = smp_num_cpus-1; -#if (defined(CONFIG_ITANIUM_B0_SPECIFIC) \ - || defined(CONFIG_ITANIUM_B1_SPECIFIC) || defined(CONFIG_ITANIUM_B2_SPECIFIC)) - unsigned long timeout; -#endif if (!cpus) return 0; @@ -364,27 +276,14 @@ atomic_set(&data.finished, 0); spin_lock_bh(&call_lock); - call_data = &data; - -#if (defined(CONFIG_ITANIUM_B0_SPECIFIC) \ - || defined(CONFIG_ITANIUM_B1_SPECIFIC) || defined(CONFIG_ITANIUM_B2_SPECIFIC)) - resend: - /* Send a message to all other CPUs and wait for them to respond */ - send_IPI_allbutself(IPI_CALL_FUNC); - /* Wait for response */ - timeout = jiffies + HZ; - while ((atomic_read(&data.started) != cpus) && time_before(jiffies, timeout)) - barrier(); - if (atomic_read(&data.started) != cpus) - goto resend; -#else + call_data = &data; + mb(); /* ensure store to call_data precedes setting of IPI_CALL_FUNC */ send_IPI_allbutself(IPI_CALL_FUNC); /* Wait for response */ while (atomic_read(&data.started) != cpus) barrier(); -#endif if (wait) while (atomic_read(&data.finished) != cpus) diff -urN linux-2.4.10/arch/ia64/kernel/smpboot.c linux-2.4.10-lia/arch/ia64/kernel/smpboot.c --- linux-2.4.10/arch/ia64/kernel/smpboot.c Tue Jul 31 10:30:08 2001 +++ linux-2.4.10-lia/arch/ia64/kernel/smpboot.c Mon Sep 24 21:53:33 2001 @@ -33,6 +33,7 @@ #include #include #include +#include #include #include #include @@ -42,6 +43,8 @@ #include #include +#define SMP_DEBUG 0 + #if SMP_DEBUG #define Dprintk(x...) printk(x) #else @@ -310,7 +313,7 @@ } -void __init +static void __init smp_callin (void) { int cpuid, phys_id; @@ -324,8 +327,7 @@ phys_id = hard_smp_processor_id(); if (test_and_set_bit(cpuid, &cpu_online_map)) { - printk("huh, phys CPU#0x%x, CPU#0x%x already present??\n", - phys_id, cpuid); + printk("huh, phys CPU#0x%x, CPU#0x%x already present??\n", phys_id, cpuid); BUG(); } @@ -341,6 +343,12 @@ * Get our bogomips. */ ia64_init_itm(); + +#ifdef CONFIG_IA64_MCA + ia64_mca_cmc_vector_setup(); /* Setup vector on AP & enable */ + ia64_mca_check_errors(); /* For post-failure MCA error logging */ +#endif + #ifdef CONFIG_PERFMON perfmon_init_percpu(); #endif @@ -364,14 +372,15 @@ { extern int cpu_idle (void); + Dprintk("start_secondary: starting CPU 0x%x\n", hard_smp_processor_id()); efi_map_pal_code(); cpu_init(); smp_callin(); - Dprintk("CPU %d is set to go. \n", smp_processor_id()); + Dprintk("CPU %d is set to go.\n", smp_processor_id()); while (!atomic_read(&smp_commenced)) ; - Dprintk("CPU %d is starting idle. \n", smp_processor_id()); + Dprintk("CPU %d is starting idle.\n", smp_processor_id()); return cpu_idle(); } @@ -415,7 +424,7 @@ unhash_process(idle); init_tasks[cpu] = idle; - Dprintk("Sending Wakeup Vector to AP 0x%x/0x%x.\n", cpu, sapicid); + Dprintk("Sending wakeup vector %u to AP 0x%x/0x%x.\n", ap_wakeup_vector, cpu, sapicid); platform_send_ipi(cpu, ap_wakeup_vector, IA64_IPI_DM_INT, 0); @@ -424,7 +433,6 @@ */ Dprintk("Waiting on callin_map ..."); for (timeout = 0; timeout < 100000; timeout++) { - Dprintk("."); if (test_bit(cpu, &cpu_callin_map)) break; /* It has booted */ udelay(100); diff -urN linux-2.4.10/arch/ia64/kernel/sys_ia64.c linux-2.4.10-lia/arch/ia64/kernel/sys_ia64.c --- linux-2.4.10/arch/ia64/kernel/sys_ia64.c Tue Jul 31 10:30:08 2001 +++ linux-2.4.10-lia/arch/ia64/kernel/sys_ia64.c Mon Sep 24 21:53:53 2001 @@ -19,24 +19,29 @@ #include #include -#define COLOR_ALIGN(addr) (((addr) + SHMLBA - 1) & ~(SHMLBA - 1)) - unsigned long arch_get_unmapped_area (struct file *filp, unsigned long addr, unsigned long len, unsigned long pgoff, unsigned long flags) { - struct vm_area_struct * vmm; long map_shared = (flags & MAP_SHARED); + unsigned long align_mask = PAGE_SIZE - 1; + struct vm_area_struct * vmm; if (len > RGN_MAP_LIMIT) return -ENOMEM; if (!addr) addr = TASK_UNMAPPED_BASE; - if (map_shared) - addr = COLOR_ALIGN(addr); - else - addr = PAGE_ALIGN(addr); + if (map_shared && (TASK_SIZE > 0xfffffffful)) + /* + * For 64-bit tasks, align shared segments to 1MB to avoid potential + * performance penalty due to virtual aliasing (see ASDM). For 32-bit + * tasks, we prefer to avoid exhausting the address space too quickly by + * limiting alignment to a single page. + */ + align_mask = SHMLBA - 1; + + addr = (addr + align_mask) & ~align_mask; for (vmm = find_vma(current->mm, addr); ; vmm = vmm->vm_next) { /* At this point: (!vmm || addr < vmm->vm_end). */ @@ -46,9 +51,7 @@ return -ENOMEM; if (!vmm || addr + len <= vmm->vm_start) return addr; - addr = vmm->vm_end; - if (map_shared) - addr = COLOR_ALIGN(addr); + addr = (vmm->vm_end + align_mask) & ~align_mask; } } @@ -184,8 +187,10 @@ if (!file) return -EBADF; - if (!file->f_op || !file->f_op->mmap) - return -ENODEV; + if (!file->f_op || !file->f_op->mmap) { + addr = -ENODEV; + goto out; + } } /* @@ -194,22 +199,26 @@ */ len = PAGE_ALIGN(len); if (len == 0) - return addr; + goto out; /* don't permit mappings into unmapped space or the virtual page table of a region: */ roff = rgn_offset(addr); - if ((len | roff | (roff + len)) >= RGN_MAP_LIMIT) - return -EINVAL; + if ((len | roff | (roff + len)) >= RGN_MAP_LIMIT) { + addr = -EINVAL; + goto out; + } /* don't permit mappings that would cross a region boundary: */ - if (rgn_index(addr) != rgn_index(addr + len)) - return -EINVAL; + if (rgn_index(addr) != rgn_index(addr + len)) { + addr = -EINVAL; + goto out; + } down_write(¤t->mm->mmap_sem); addr = do_mmap_pgoff(file, addr, len, prot, flags, pgoff); up_write(¤t->mm->mmap_sem); - if (file) +out: if (file) fput(file); return addr; } diff -urN linux-2.4.10/arch/ia64/kernel/time.c linux-2.4.10-lia/arch/ia64/kernel/time.c --- linux-2.4.10/arch/ia64/kernel/time.c Tue Jul 31 10:30:08 2001 +++ linux-2.4.10-lia/arch/ia64/kernel/time.c Mon Aug 13 23:55:26 2001 @@ -145,6 +145,9 @@ tv->tv_usec = usec; } +/* XXX there should be a cleaner way for declaring an alias... */ +asm (".global get_fast_time; get_fast_time = do_gettimeofday"); + static void timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) { diff -urN linux-2.4.10/arch/ia64/kernel/traps.c linux-2.4.10-lia/arch/ia64/kernel/traps.c --- linux-2.4.10/arch/ia64/kernel/traps.c Tue Jul 31 10:30:08 2001 +++ linux-2.4.10-lia/arch/ia64/kernel/traps.c Mon Sep 24 21:54:49 2001 @@ -1,20 +1,19 @@ /* * Architecture-specific trap handling. * - * Copyright (C) 1998-2000 Hewlett-Packard Co - * Copyright (C) 1998-2000 David Mosberger-Tang + * Copyright (C) 1998-2001 Hewlett-Packard Co + * David Mosberger-Tang * * 05/12/00 grao : added isr in siginfo for SIGFPE */ /* - * The fpu_fault() handler needs to be able to access and update all - * floating point registers. Those saved in pt_regs can be accessed - * through that structure, but those not saved, will be accessed - * directly. To make this work, we need to ensure that the compiler - * does not end up using a preserved floating point register on its - * own. The following achieves this by declaring preserved registers - * that are not marked as "fixed" as global register variables. + * fp_emulate() needs to be able to access and update all floating point registers. Those + * saved in pt_regs can be accessed through that structure, but those not saved, will be + * accessed directly. To make this work, we need to ensure that the compiler does not end + * up using a preserved floating point register on its own. The following achieves this + * by declaring preserved registers that are not marked as "fixed" as global register + * variables. */ register double f2 asm ("f2"); register double f3 asm ("f3"); register double f4 asm ("f4"); register double f5 asm ("f5"); @@ -33,13 +32,17 @@ #include #include #include +#include /* For unblank_screen() */ +#include #include #include #include #include +extern spinlock_t timerlist_lock; + static fpswa_interface_t *fpswa_interface; void __init @@ -51,22 +54,48 @@ fpswa_interface = __va(ia64_boot_param->fpswa); } +/* + * Unlock any spinlocks which will prevent us from getting the message out (timerlist_lock + * is acquired through the console unblank code) + */ void -die_if_kernel (char *str, struct pt_regs *regs, long err) +bust_spinlocks (int yes) { - if (user_mode(regs)) { -#if 0 - /* XXX for debugging only */ - printk ("!!die_if_kernel: %s(%d): %s %ld\n", - current->comm, current->pid, str, err); - show_regs(regs); + spin_lock_init(&timerlist_lock); + if (yes) { + oops_in_progress = 1; +#ifdef CONFIG_SMP + global_irq_lock = 0; /* Many serial drivers do __global_cli() */ #endif - return; + } else { + int loglevel_save = console_loglevel; +#ifdef CONFIG_VT + unblank_screen(); +#endif + oops_in_progress = 0; + /* + * OK, the message is on the console. Now we call printk() without + * oops_in_progress set so that printk will give klogd a poke. Hold onto + * your hats... + */ + console_loglevel = 15; /* NMI oopser may have shut the console up */ + printk(" "); + console_loglevel = loglevel_save; } +} - printk("%s[%d]: %s %ld\n", current->comm, current->pid, str, err); +void +die (const char *str, struct pt_regs *regs, long err) +{ + static spinlock_t die_lock = SPIN_LOCK_UNLOCKED; + console_verbose(); + spin_lock_irq(&die_lock); + bust_spinlocks(1); + printk("%s[%d]: %s %ld\n", current->comm, current->pid, str, err); show_regs(regs); + bust_spinlocks(0); + spin_unlock_irq(&die_lock); if (current->thread.flags & IA64_KERNEL_DEATH) { printk("die_if_kernel recursion detected.\n"); @@ -78,6 +107,13 @@ } void +die_if_kernel (char *str, struct pt_regs *regs, long err) +{ + if (!user_mode(regs)) + die(str, regs, err); +} + +void ia64_bad_break (unsigned long break_num, struct pt_regs *regs) { siginfo_t siginfo; @@ -169,14 +205,12 @@ } /* - * disabled_fph_fault() is called when a user-level process attempts - * to access one of the registers f32..f127 when it doesn't own the - * fp-high register partition. When this happens, we save the current - * fph partition in the task_struct of the fpu-owner (if necessary) - * and then load the fp-high partition of the current task (if - * necessary). Note that the kernel has access to fph by the time we - * get here, as the IVT's "Diabled FP-Register" handler takes care of - * clearing psr.dfh. + * disabled_fph_fault() is called when a user-level process attempts to access f32..f127 + * and it doesn't own the fp-high register partition. When this happens, we save the + * current fph partition in the task_struct of the fpu-owner (if necessary) and then load + * the fp-high partition of the current task (if necessary). Note that the kernel has + * access to fph by the time we get here, as the IVT's "Disabled FP-Register" handler takes + * care of clearing psr.dfh. */ static inline void disabled_fph_fault (struct pt_regs *regs) diff -urN linux-2.4.10/arch/ia64/kernel/unaligned.c linux-2.4.10-lia/arch/ia64/kernel/unaligned.c --- linux-2.4.10/arch/ia64/kernel/unaligned.c Tue Jul 31 10:30:08 2001 +++ linux-2.4.10-lia/arch/ia64/kernel/unaligned.c Mon Aug 13 23:56:34 2001 @@ -5,6 +5,7 @@ * Copyright (C) 1999-2000 Stephane Eranian * Copyright (C) 2001 David Mosberger-Tang * + * 2001/08/13 Correct size of extended floats (float_fsz) from 16 to 10 bytes. * 2001/01/17 Add support emulation of unaligned kernel accesses. */ #include @@ -908,7 +909,7 @@ * floating point operations sizes in bytes */ static const unsigned char float_fsz[4]={ - 16, /* extended precision (e) */ + 10, /* extended precision (e) */ 8, /* integer (8) */ 4, /* single precision (s) */ 8 /* double precision (d) */ @@ -978,11 +979,11 @@ unsigned long len = float_fsz[ld.x6_sz]; /* - * fr0 & fr1 don't need to be checked because Illegal Instruction - * faults have higher priority than unaligned faults. + * fr0 & fr1 don't need to be checked because Illegal Instruction faults have + * higher priority than unaligned faults. * - * r0 cannot be found as the base as it would never generate an - * unaligned reference. + * r0 cannot be found as the base as it would never generate an unaligned + * reference. */ /* @@ -996,8 +997,10 @@ * invalidate the ALAT entry and execute updates, if any. */ if (ld.x6_op != 0x2) { - /* this assumes little-endian byte-order: */ - + /* + * This assumes little-endian byte-order. Note that there is no "ldfpe" + * instruction: + */ if (copy_from_user(&fpr_init[0], (void *) ifa, len) || copy_from_user(&fpr_init[1], (void *) (ifa + len), len)) return -1; @@ -1337,7 +1340,7 @@ /* * IMPORTANT: - * Notice that the swictch statement DOES not cover all possible instructions + * Notice that the switch statement DOES not cover all possible instructions * that DO generate unaligned references. This is made on purpose because for some * instructions it DOES NOT make sense to try and emulate the access. Sometimes it * is WRONG to try and emulate. Here is a list of instruction we don't emulate i.e., diff -urN linux-2.4.10/arch/ia64/kernel/unwind.c linux-2.4.10-lia/arch/ia64/kernel/unwind.c --- linux-2.4.10/arch/ia64/kernel/unwind.c Tue Jul 31 10:30:08 2001 +++ linux-2.4.10-lia/arch/ia64/kernel/unwind.c Mon Sep 24 21:55:01 2001 @@ -504,7 +504,7 @@ return 0; } -inline int +int unw_access_pr (struct unw_frame_info *info, unsigned long *val, int write) { unsigned long *addr; diff -urN linux-2.4.10/arch/ia64/lib/clear_page.S linux-2.4.10-lia/arch/ia64/lib/clear_page.S --- linux-2.4.10/arch/ia64/lib/clear_page.S Tue Jul 31 10:30:08 2001 +++ linux-2.4.10-lia/arch/ia64/lib/clear_page.S Mon Sep 24 21:55:10 2001 @@ -47,5 +47,5 @@ br.cloop.dptk.few 1b ;; mov ar.lc = r2 // restore lc - br.ret.sptk.few rp + br.ret.sptk.many rp END(clear_page) diff -urN linux-2.4.10/arch/ia64/lib/clear_user.S linux-2.4.10-lia/arch/ia64/lib/clear_user.S --- linux-2.4.10/arch/ia64/lib/clear_user.S Tue Jul 31 10:30:08 2001 +++ linux-2.4.10-lia/arch/ia64/lib/clear_user.S Mon Sep 24 21:55:19 2001 @@ -8,7 +8,7 @@ * r8: number of bytes that didn't get cleared due to a fault * * Copyright (C) 1998, 1999, 2001 Hewlett-Packard Co - * Copyright (C) 1999 Stephane Eranian + * Stephane Eranian */ #include @@ -62,11 +62,11 @@ ;; // avoid WAW on CFM adds tmp=-1,len // br.ctop is repeat/until mov ret0=len // return value is length at this point -(p6) br.ret.spnt.few rp +(p6) br.ret.spnt.many rp ;; cmp.lt p6,p0=16,len // if len > 16 then long memset mov ar.lc=tmp // initialize lc for small count -(p6) br.cond.dptk.few long_do_clear +(p6) br.cond.dptk .long_do_clear ;; // WAR on ar.lc // // worst case 16 iterations, avg 8 iterations @@ -79,7 +79,7 @@ 1: EX( .Lexit1, st1 [buf]=r0,1 ) adds len=-1,len // countdown length using len - br.cloop.dptk.few 1b + br.cloop.dptk 1b ;; // avoid RAW on ar.lc // // .Lexit4: comes from byte by byte loop @@ -87,7 +87,7 @@ .Lexit1: mov ret0=len // faster than using ar.lc mov ar.lc=saved_lc - br.ret.sptk.few rp // end of short clear_user + br.ret.sptk.many rp // end of short clear_user // @@ -98,7 +98,7 @@ // instead of ret0 is due to the fact that the exception code // changes the values of r8. // -long_do_clear: +.long_do_clear: tbit.nz p6,p0=buf,0 // odd alignment (for long_do_clear) ;; EX( .Lexit3, (p6) st1 [buf]=r0,1 ) // 1-byte aligned @@ -119,7 +119,7 @@ ;; cmp.eq p6,p0=r0,cnt adds tmp=-1,cnt -(p6) br.cond.dpnt.few .dotail // we have less than 16 bytes left +(p6) br.cond.dpnt .dotail // we have less than 16 bytes left ;; adds buf2=8,buf // setup second base pointer mov ar.lc=tmp @@ -148,7 +148,7 @@ ;; // needed to get len correct when error st8 [buf2]=r0,16 adds len=-16,len - br.cloop.dptk.few 2b + br.cloop.dptk 2b ;; mov ar.lc=saved_lc // @@ -178,7 +178,7 @@ ;; EX( .Lexit2, (p7) st1 [buf]=r0 ) // only 1 byte left mov ret0=r0 // success - br.ret.dptk.few rp // end of most likely path + br.ret.sptk.many rp // end of most likely path // // Outlined error handling code @@ -205,5 +205,5 @@ .Lexit3: mov ret0=len mov ar.lc=saved_lc - br.ret.dptk.few rp + br.ret.sptk.many rp END(__do_clear_user) diff -urN linux-2.4.10/arch/ia64/lib/copy_page.S linux-2.4.10-lia/arch/ia64/lib/copy_page.S --- linux-2.4.10/arch/ia64/lib/copy_page.S Tue Jul 31 10:30:08 2001 +++ linux-2.4.10-lia/arch/ia64/lib/copy_page.S Mon Sep 24 21:55:37 2001 @@ -90,5 +90,5 @@ mov pr=saved_pr,0xffffffffffff0000 // restore predicates mov ar.pfs=saved_pfs mov ar.lc=saved_lc - br.ret.sptk.few rp + br.ret.sptk.many rp END(copy_page) diff -urN linux-2.4.10/arch/ia64/lib/copy_user.S linux-2.4.10-lia/arch/ia64/lib/copy_user.S --- linux-2.4.10/arch/ia64/lib/copy_user.S Tue Jul 31 10:30:08 2001 +++ linux-2.4.10-lia/arch/ia64/lib/copy_user.S Mon Sep 24 21:55:46 2001 @@ -19,8 +19,8 @@ * ret0 0 in case of success. The number of bytes NOT copied in * case of error. * - * Copyright (C) 2000 Hewlett-Packard Co - * Copyright (C) 2000 Stephane Eranian + * Copyright (C) 2000-2001 Hewlett-Packard Co + * Stephane Eranian * * Fixme: * - handle the case where we have more than 16 bytes and the alignment @@ -85,7 +85,7 @@ cmp.eq p8,p0=r0,len // check for zero length .save ar.lc, saved_lc mov saved_lc=ar.lc // preserve ar.lc (slow) -(p8) br.ret.spnt.few rp // empty mempcy() +(p8) br.ret.spnt.many rp // empty mempcy() ;; add enddst=dst,len // first byte after end of source add endsrc=src,len // first byte after end of destination @@ -103,26 +103,26 @@ cmp.lt p10,p7=COPY_BREAK,len // if len > COPY_BREAK then long copy xor tmp=src,dst // same alignment test prepare -(p10) br.cond.dptk.few long_copy_user +(p10) br.cond.dptk .long_copy_user ;; // RAW pr.rot/p16 ? // // Now we do the byte by byte loop with software pipeline // // p7 is necessarily false by now 1: - EX(failure_in_pipe1,(p16) ld1 val1[0]=[src1],1) - EX(failure_out,(EPI) st1 [dst1]=val1[PIPE_DEPTH-1],1) + EX(.failure_in_pipe1,(p16) ld1 val1[0]=[src1],1) + EX(.failure_out,(EPI) st1 [dst1]=val1[PIPE_DEPTH-1],1) br.ctop.dptk.few 1b ;; mov ar.lc=saved_lc mov pr=saved_pr,0xffffffffffff0000 mov ar.pfs=saved_pfs // restore ar.ec - br.ret.sptk.few rp // end of short memcpy + br.ret.sptk.many rp // end of short memcpy // // Not 8-byte aligned // -diff_align_copy_user: +.diff_align_copy_user: // At this point we know we have more than 16 bytes to copy // and also that src and dest do _not_ have the same alignment. and src2=0x7,src1 // src offset @@ -153,7 +153,7 @@ // We know src1 is not 8-byte aligned in this case. // cmp.eq p14,p15=r0,dst2 -(p15) br.cond.spnt.few 1f +(p15) br.cond.spnt 1f ;; sub t1=8,src2 mov t2=src2 @@ -163,7 +163,7 @@ ;; sub lshift=64,rshift ;; - br.cond.spnt.few word_copy_user + br.cond.spnt .word_copy_user ;; 1: cmp.leu p14,p15=src2,dst2 @@ -192,15 +192,15 @@ mov ar.lc=cnt ;; 2: - EX(failure_in_pipe2,(p16) ld1 val1[0]=[src1],1) - EX(failure_out,(EPI) st1 [dst1]=val1[PIPE_DEPTH-1],1) + EX(.failure_in_pipe2,(p16) ld1 val1[0]=[src1],1) + EX(.failure_out,(EPI) st1 [dst1]=val1[PIPE_DEPTH-1],1) br.ctop.dptk.few 2b ;; clrrrb ;; -word_copy_user: +.word_copy_user: cmp.gtu p9,p0=16,len1 -(p9) br.cond.spnt.few 4f // if (16 > len1) skip 8-byte copy +(p9) br.cond.spnt 4f // if (16 > len1) skip 8-byte copy ;; shr.u cnt=len1,3 // number of 64-bit words ;; @@ -232,24 +232,24 @@ #define EPI_1 p[PIPE_DEPTH-2] #define SWITCH(pred, shift) cmp.eq pred,p0=shift,rshift #define CASE(pred, shift) \ - (pred) br.cond.spnt.few copy_user_bit##shift + (pred) br.cond.spnt .copy_user_bit##shift #define BODY(rshift) \ -copy_user_bit##rshift: \ +.copy_user_bit##rshift: \ 1: \ - EX(failure_out,(EPI) st8 [dst1]=tmp,8); \ + EX(.failure_out,(EPI) st8 [dst1]=tmp,8); \ (EPI_1) shrp tmp=val1[PIPE_DEPTH-3],val1[PIPE_DEPTH-2],rshift; \ EX(3f,(p16) ld8 val1[0]=[src1],8); \ - br.ctop.dptk.few 1b; \ + br.ctop.dptk 1b; \ ;; \ - br.cond.sptk.few .diff_align_do_tail; \ + br.cond.sptk.many .diff_align_do_tail; \ 2: \ (EPI) st8 [dst1]=tmp,8; \ (EPI_1) shrp tmp=val1[PIPE_DEPTH-3],val1[PIPE_DEPTH-2],rshift; \ 3: \ (p16) mov val1[0]=r0; \ - br.ctop.dptk.few 2b; \ + br.ctop.dptk 2b; \ ;; \ - br.cond.sptk.few failure_in2 + br.cond.sptk.many .failure_in2 // // Since the instruction 'shrp' requires a fixed 128-bit value @@ -301,25 +301,25 @@ mov ar.lc=len1 ;; 5: - EX(failure_in_pipe1,(p16) ld1 val1[0]=[src1],1) - EX(failure_out,(EPI) st1 [dst1]=val1[PIPE_DEPTH-1],1) + EX(.failure_in_pipe1,(p16) ld1 val1[0]=[src1],1) + EX(.failure_out,(EPI) st1 [dst1]=val1[PIPE_DEPTH-1],1) br.ctop.dptk.few 5b ;; mov ar.lc=saved_lc mov pr=saved_pr,0xffffffffffff0000 mov ar.pfs=saved_pfs - br.ret.dptk.few rp + br.ret.sptk.many rp // // Beginning of long mempcy (i.e. > 16 bytes) // -long_copy_user: +.long_copy_user: tbit.nz p6,p7=src1,0 // odd alignement and tmp=7,tmp ;; cmp.eq p10,p8=r0,tmp mov len1=len // copy because of rotation -(p8) br.cond.dpnt.few diff_align_copy_user +(p8) br.cond.dpnt .diff_align_copy_user ;; // At this point we know we have more than 16 bytes to copy // and also that both src and dest have the same alignment @@ -327,11 +327,11 @@ // forward slowly until we reach 16byte alignment: no need to // worry about reaching the end of buffer. // - EX(failure_in1,(p6) ld1 val1[0]=[src1],1) // 1-byte aligned + EX(.failure_in1,(p6) ld1 val1[0]=[src1],1) // 1-byte aligned (p6) adds len1=-1,len1;; tbit.nz p7,p0=src1,1 ;; - EX(failure_in1,(p7) ld2 val1[1]=[src1],2) // 2-byte aligned + EX(.failure_in1,(p7) ld2 val1[1]=[src1],2) // 2-byte aligned (p7) adds len1=-2,len1;; tbit.nz p8,p0=src1,2 ;; @@ -339,28 +339,28 @@ // Stop bit not required after ld4 because if we fail on ld4 // we have never executed the ld1, therefore st1 is not executed. // - EX(failure_in1,(p8) ld4 val2[0]=[src1],4) // 4-byte aligned + EX(.failure_in1,(p8) ld4 val2[0]=[src1],4) // 4-byte aligned ;; - EX(failure_out,(p6) st1 [dst1]=val1[0],1) + EX(.failure_out,(p6) st1 [dst1]=val1[0],1) tbit.nz p9,p0=src1,3 ;; // // Stop bit not required after ld8 because if we fail on ld8 // we have never executed the ld2, therefore st2 is not executed. // - EX(failure_in1,(p9) ld8 val2[1]=[src1],8) // 8-byte aligned - EX(failure_out,(p7) st2 [dst1]=val1[1],2) + EX(.failure_in1,(p9) ld8 val2[1]=[src1],8) // 8-byte aligned + EX(.failure_out,(p7) st2 [dst1]=val1[1],2) (p8) adds len1=-4,len1 ;; - EX(failure_out, (p8) st4 [dst1]=val2[0],4) + EX(.failure_out, (p8) st4 [dst1]=val2[0],4) (p9) adds len1=-8,len1;; shr.u cnt=len1,4 // number of 128-bit (2x64bit) words ;; - EX(failure_out, (p9) st8 [dst1]=val2[1],8) + EX(.failure_out, (p9) st8 [dst1]=val2[1],8) tbit.nz p6,p0=len1,3 cmp.eq p7,p0=r0,cnt adds tmp=-1,cnt // br.ctop is repeat/until -(p7) br.cond.dpnt.few .dotail // we have less than 16 bytes left +(p7) br.cond.dpnt .dotail // we have less than 16 bytes left ;; adds src2=8,src1 adds dst2=8,dst1 @@ -370,12 +370,12 @@ // 16bytes/iteration // 2: - EX(failure_in3,(p16) ld8 val1[0]=[src1],16) + EX(.failure_in3,(p16) ld8 val1[0]=[src1],16) (p16) ld8 val2[0]=[src2],16 - EX(failure_out, (EPI) st8 [dst1]=val1[PIPE_DEPTH-1],16) + EX(.failure_out, (EPI) st8 [dst1]=val1[PIPE_DEPTH-1],16) (EPI) st8 [dst2]=val2[PIPE_DEPTH-1],16 - br.ctop.dptk.few 2b + br.ctop.dptk 2b ;; // RAW on src1 when fall through from loop // // Tail correction based on len only @@ -384,29 +384,28 @@ // is 16 byte aligned AND we have less than 16 bytes to copy. // .dotail: - EX(failure_in1,(p6) ld8 val1[0]=[src1],8) // at least 8 bytes + EX(.failure_in1,(p6) ld8 val1[0]=[src1],8) // at least 8 bytes tbit.nz p7,p0=len1,2 ;; - EX(failure_in1,(p7) ld4 val1[1]=[src1],4) // at least 4 bytes + EX(.failure_in1,(p7) ld4 val1[1]=[src1],4) // at least 4 bytes tbit.nz p8,p0=len1,1 ;; - EX(failure_in1,(p8) ld2 val2[0]=[src1],2) // at least 2 bytes + EX(.failure_in1,(p8) ld2 val2[0]=[src1],2) // at least 2 bytes tbit.nz p9,p0=len1,0 ;; - EX(failure_out, (p6) st8 [dst1]=val1[0],8) + EX(.failure_out, (p6) st8 [dst1]=val1[0],8) ;; - EX(failure_in1,(p9) ld1 val2[1]=[src1]) // only 1 byte left + EX(.failure_in1,(p9) ld1 val2[1]=[src1]) // only 1 byte left mov ar.lc=saved_lc ;; - EX(failure_out,(p7) st4 [dst1]=val1[1],4) + EX(.failure_out,(p7) st4 [dst1]=val1[1],4) mov pr=saved_pr,0xffffffffffff0000 ;; - EX(failure_out, (p8) st2 [dst1]=val2[0],2) + EX(.failure_out, (p8) st2 [dst1]=val2[0],2) mov ar.pfs=saved_pfs ;; - EX(failure_out, (p9) st1 [dst1]=val2[1]) - br.ret.dptk.few rp - + EX(.failure_out, (p9) st1 [dst1]=val2[1]) + br.ret.sptk.many rp // @@ -433,32 +432,32 @@ // pipeline going. We can't really do this inline because // p16 is always reset to 1 when lc > 0. // -failure_in_pipe1: +.failure_in_pipe1: sub ret0=endsrc,src1 // number of bytes to zero, i.e. not copied 1: (p16) mov val1[0]=r0 (EPI) st1 [dst1]=val1[PIPE_DEPTH-1],1 - br.ctop.dptk.few 1b + br.ctop.dptk 1b ;; mov pr=saved_pr,0xffffffffffff0000 mov ar.lc=saved_lc mov ar.pfs=saved_pfs - br.ret.dptk.few rp + br.ret.sptk.many rp // // This is the case where the byte by byte copy fails on the load // when we copy the head. We need to finish the pipeline and copy // zeros for the rest of the destination. Since this happens // at the top we still need to fill the body and tail. -failure_in_pipe2: +.failure_in_pipe2: sub ret0=endsrc,src1 // number of bytes to zero, i.e. not copied 2: (p16) mov val1[0]=r0 (EPI) st1 [dst1]=val1[PIPE_DEPTH-1],1 - br.ctop.dptk.few 2b + br.ctop.dptk 2b ;; sub len=enddst,dst1,1 // precompute len - br.cond.dptk.few failure_in1bis + br.cond.dptk.many .failure_in1bis ;; // @@ -533,9 +532,7 @@ // This means that we are in a situation similar the a fault in the // head part. That's nice! // -failure_in1: -// sub ret0=enddst,dst1 // number of bytes to zero, i.e. not copied -// sub len=enddst,dst1,1 +.failure_in1: sub ret0=endsrc,src1 // number of bytes to zero, i.e. not copied sub len=endsrc,src1,1 // @@ -546,18 +543,17 @@ // calling side. // ;; -failure_in1bis: // from (failure_in3) +.failure_in1bis: // from (.failure_in3) mov ar.lc=len // Continue with a stupid byte store. ;; 5: st1 [dst1]=r0,1 - br.cloop.dptk.few 5b + br.cloop.dptk 5b ;; -skip_loop: mov pr=saved_pr,0xffffffffffff0000 mov ar.lc=saved_lc mov ar.pfs=saved_pfs - br.ret.dptk.few rp + br.ret.sptk.many rp // // Here we simply restart the loop but instead @@ -569,7 +565,7 @@ // we MUST use src1/endsrc here and not dst1/enddst because // of the pipeline effect. // -failure_in3: +.failure_in3: sub ret0=endsrc,src1 // number of bytes to zero, i.e. not copied ;; 2: @@ -577,36 +573,36 @@ (p16) mov val2[0]=r0 (EPI) st8 [dst1]=val1[PIPE_DEPTH-1],16 (EPI) st8 [dst2]=val2[PIPE_DEPTH-1],16 - br.ctop.dptk.few 2b + br.ctop.dptk 2b ;; cmp.ne p6,p0=dst1,enddst // Do we need to finish the tail ? sub len=enddst,dst1,1 // precompute len -(p6) br.cond.dptk.few failure_in1bis +(p6) br.cond.dptk .failure_in1bis ;; mov pr=saved_pr,0xffffffffffff0000 mov ar.lc=saved_lc mov ar.pfs=saved_pfs - br.ret.dptk.few rp + br.ret.sptk.many rp -failure_in2: +.failure_in2: sub ret0=endsrc,src1 cmp.ne p6,p0=dst1,enddst // Do we need to finish the tail ? sub len=enddst,dst1,1 // precompute len -(p6) br.cond.dptk.few failure_in1bis +(p6) br.cond.dptk .failure_in1bis ;; mov pr=saved_pr,0xffffffffffff0000 mov ar.lc=saved_lc mov ar.pfs=saved_pfs - br.ret.dptk.few rp + br.ret.sptk.many rp // // handling of failures on stores: that's the easy part // -failure_out: +.failure_out: sub ret0=enddst,dst1 mov pr=saved_pr,0xffffffffffff0000 mov ar.lc=saved_lc mov ar.pfs=saved_pfs - br.ret.dptk.few rp + br.ret.sptk.many rp END(__copy_user) diff -urN linux-2.4.10/arch/ia64/lib/do_csum.S linux-2.4.10-lia/arch/ia64/lib/do_csum.S --- linux-2.4.10/arch/ia64/lib/do_csum.S Tue Jul 31 10:30:08 2001 +++ linux-2.4.10-lia/arch/ia64/lib/do_csum.S Mon Sep 24 21:56:08 2001 @@ -16,7 +16,6 @@ * back-to-back 8-byte words per loop. Clean up the initialization * for the loop. Support the cases where load latency = 1 or 2. * Set CONFIG_IA64_LOAD_LATENCY to 1 or 2 (default). - * */ #include @@ -130,7 +129,7 @@ ;; // avoid WAW on CFM mov tmp3=0x7 // a temporary mask/value add tmp1=buf,len // last byte's address -(p6) br.ret.spnt.few rp // return if true (hope we can avoid that) +(p6) br.ret.spnt.many rp // return if true (hope we can avoid that) and firstoff=7,buf // how many bytes off for first1 element tbit.nz p15,p0=buf,0 // is buf an odd address ? @@ -181,9 +180,9 @@ cmp.ltu p6,p0=result1[0],word1[0] // check the carry ;; (p6) adds result1[0]=1,result1[0] -(p8) br.cond.dptk.few do_csum_exit // if (within an 8-byte word) +(p8) br.cond.dptk .do_csum_exit // if (within an 8-byte word) ;; -(p11) br.cond.dptk.few do_csum16 // if (count is even) +(p11) br.cond.dptk .do_csum16 // if (count is even) ;; // Here count is odd. ld8 word1[1]=[first1],8 // load an 8-byte word @@ -196,14 +195,14 @@ ;; (p6) adds result1[0]=1,result1[0] ;; -(p9) br.cond.sptk.few do_csum_exit // if (count == 1) exit +(p9) br.cond.sptk .do_csum_exit // if (count == 1) exit // Fall through to caluculate the checksum, feeding result1[0] as // the initial value in result1[0]. ;; // // Calculate the checksum loading two 8-byte words per loop. // -do_csum16: +.do_csum16: mov saved_lc=ar.lc shr.u count=count,1 // we do 16 bytes per loop ;; @@ -225,7 +224,7 @@ ;; add first2=8,first1 ;; -(p9) br.cond.sptk.few do_csum_exit +(p9) br.cond.sptk .do_csum_exit ;; nop.m 0 nop.i 0 @@ -241,7 +240,7 @@ 2: (p16) ld8 word1[0]=[first1],16 (p16) ld8 word2[0]=[first2],16 - br.ctop.sptk.few 1b + br.ctop.sptk 1b ;; // Since len is a 32-bit value, carry cannot be larger than // a 64-bit value. @@ -263,7 +262,7 @@ ;; (p6) adds result1[0]=1,result1[0] ;; -do_csum_exit: +.do_csum_exit: movl tmp3=0xffffffff ;; // XXX Fixme @@ -299,7 +298,7 @@ ;; mov ar.lc=saved_lc (p15) shr.u ret0=ret0,64-16 // + shift back to position = swap bytes - br.ret.sptk.few rp + br.ret.sptk.many rp // I (Jun Nakajima) wrote an equivalent code (see below), but it was // not much better than the original. So keep the original there so that @@ -331,6 +330,6 @@ //(p15) mux1 ret0=ret0,@rev // reverse word // ;; //(p15) shr.u ret0=ret0,64-16 // + shift back to position = swap bytes -// br.ret.sptk.few rp +// br.ret.sptk.many rp END(do_csum) diff -urN linux-2.4.10/arch/ia64/lib/idiv32.S linux-2.4.10-lia/arch/ia64/lib/idiv32.S --- linux-2.4.10/arch/ia64/lib/idiv32.S Mon Oct 9 17:54:56 2000 +++ linux-2.4.10-lia/arch/ia64/lib/idiv32.S Mon Sep 24 21:56:20 2001 @@ -79,5 +79,5 @@ ;; #endif getf.sig r8 = f6 // transfer result to result register - br.ret.sptk rp + br.ret.sptk.many rp END(NAME) diff -urN linux-2.4.10/arch/ia64/lib/idiv64.S linux-2.4.10-lia/arch/ia64/lib/idiv64.S --- linux-2.4.10/arch/ia64/lib/idiv64.S Thu Apr 5 12:51:47 2001 +++ linux-2.4.10-lia/arch/ia64/lib/idiv64.S Mon Sep 24 21:56:27 2001 @@ -89,5 +89,5 @@ #endif getf.sig r8 = f17 // transfer result to result register ldf.fill f17 = [sp] - br.ret.sptk rp + br.ret.sptk.many rp END(NAME) diff -urN linux-2.4.10/arch/ia64/lib/memcpy.S linux-2.4.10-lia/arch/ia64/lib/memcpy.S --- linux-2.4.10/arch/ia64/lib/memcpy.S Thu Apr 5 12:51:47 2001 +++ linux-2.4.10-lia/arch/ia64/lib/memcpy.S Mon Sep 24 21:56:35 2001 @@ -9,20 +9,14 @@ * Output: * no return value * - * Copyright (C) 2000 Hewlett-Packard Co - * Copyright (C) 2000 Stephane Eranian - * Copyright (C) 2000 David Mosberger-Tang + * Copyright (C) 2000-2001 Hewlett-Packard Co + * Stephane Eranian + * David Mosberger-Tang */ #include #include -#if defined(CONFIG_ITANIUM_B0_SPECIFIC) || defined(CONFIG_ITANIUM_B1_SPECIFIC) -# define BRP(args...) nop.b 0 -#else -# define BRP(args...) brp.loop.imp args -#endif - GLOBAL_ENTRY(bcopy) .regstk 3,0,0,0 mov r8=in0 @@ -103,8 +97,8 @@ cmp.ne p6,p0=t0,r0 mov src=in1 // copy because of rotation -(p7) br.cond.spnt.few memcpy_short -(p6) br.cond.spnt.few memcpy_long +(p7) br.cond.spnt.few .memcpy_short +(p6) br.cond.spnt.few .memcpy_long ;; nop.m 0 ;; @@ -119,7 +113,7 @@ 1: { .mib (p[0]) ld8 val[0]=[src],8 nop.i 0 - BRP(1b, 2f) + brp.loop.imp 1b, 2f } 2: { .mfb (p[N-1])st8 [dst]=val[N-1],8 @@ -139,14 +133,14 @@ * issues, we want to avoid read-modify-write of entire words. */ .align 32 -memcpy_short: +.memcpy_short: adds cnt=-1,in2 // br.ctop is repeat/until mov ar.ec=MEM_LAT - BRP(1f, 2f) + brp.loop.imp 1f, 2f ;; mov ar.lc=cnt ;; - nop.m 0 + nop.m 0 ;; nop.m 0 nop.i 0 @@ -163,7 +157,7 @@ 1: { .mib (p[0]) ld1 val[0]=[src],1 nop.i 0 - BRP(1b, 2f) + brp.loop.imp 1b, 2f } ;; 2: { .mfb (p[MEM_LAT-1])st1 [dst]=val[MEM_LAT-1],1 @@ -202,7 +196,7 @@ #define LOG_LOOP_SIZE 6 -memcpy_long: +.memcpy_long: alloc t3=ar.pfs,3,Nrot,0,Nrot // resize register frame and t0=-8,src // t0 = src & ~7 and t2=7,src // t2 = src & 7 @@ -247,7 +241,7 @@ mov t4=ip } ;; and src2=-8,src // align source pointer - adds t4=memcpy_loops-1b,t4 + adds t4=.memcpy_loops-1b,t4 mov ar.ec=N and t0=7,src // t0 = src & 7 @@ -266,7 +260,7 @@ mov pr=cnt,0x38 // set (p5,p4,p3) to # of bytes last-word bytes to copy mov ar.lc=t2 ;; - nop.m 0 + nop.m 0 ;; nop.m 0 nop.i 0 @@ -278,7 +272,7 @@ br.sptk.few b6 ;; -memcpy_tail: +.memcpy_tail: // At this point, (p5,p4,p3) are set to the number of bytes left to copy (which is // less than 8) and t0 contains the last few bytes of the src buffer: (p5) st4 [dst]=t0,4 @@ -300,7 +294,7 @@ 1: { .mib \ (p[0]) ld8 val[0]=[src2],8; \ (p[MEM_LAT+3]) shrp w[0]=val[MEM_LAT+3],val[MEM_LAT+4-index],shift; \ - BRP(1b, 2f) \ + brp.loop.imp 1b, 2f \ }; \ 2: { .mfb \ (p[MEM_LAT+4]) st8 [dst]=w[1],8; \ @@ -311,8 +305,8 @@ ld8 val[N-1]=[src_end]; /* load last word (may be same as val[N]) */ \ ;; \ shrp t0=val[N-1],val[N-index],shift; \ - br memcpy_tail -memcpy_loops: + br .memcpy_tail +.memcpy_loops: COPY(0, 1) /* no point special casing this---it doesn't go any faster without shrp */ COPY(8, 0) COPY(16, 0) diff -urN linux-2.4.10/arch/ia64/lib/memset.S linux-2.4.10-lia/arch/ia64/lib/memset.S --- linux-2.4.10/arch/ia64/lib/memset.S Thu Apr 5 12:51:47 2001 +++ linux-2.4.10-lia/arch/ia64/lib/memset.S Mon Sep 24 21:56:50 2001 @@ -43,11 +43,11 @@ adds tmp=-1,len // br.ctop is repeat/until tbit.nz p6,p0=buf,0 // odd alignment -(p8) br.ret.spnt.few rp +(p8) br.ret.spnt.many rp cmp.lt p7,p0=16,len // if len > 16 then long memset mux1 val=val,@brcst // prepare value -(p7) br.cond.dptk.few long_memset +(p7) br.cond.dptk .long_memset ;; mov ar.lc=tmp // initialize lc for small count ;; // avoid RAW and WAW on ar.lc @@ -57,11 +57,11 @@ ;; // avoid RAW on ar.lc mov ar.lc=saved_lc mov ar.pfs=saved_pfs - br.ret.sptk.few rp // end of short memset + br.ret.sptk.many rp // end of short memset // at this point we know we have more than 16 bytes to copy // so we focus on alignment -long_memset: +.long_memset: (p6) st1 [buf]=val,1 // 1-byte aligned (p6) adds len=-1,len;; // sync because buf is modified tbit.nz p6,p0=buf,1 @@ -80,7 +80,7 @@ ;; cmp.eq p6,p0=r0,cnt adds tmp=-1,cnt -(p6) br.cond.dpnt.few .dotail // we have less than 16 bytes left +(p6) br.cond.dpnt .dotail // we have less than 16 bytes left ;; adds buf2=8,buf // setup second base pointer mov ar.lc=tmp @@ -104,5 +104,5 @@ mov ar.lc=saved_lc ;; (p6) st1 [buf]=val // only 1 byte left - br.ret.dptk.few rp + br.ret.sptk.many rp END(memset) diff -urN linux-2.4.10/arch/ia64/lib/strlen.S linux-2.4.10-lia/arch/ia64/lib/strlen.S --- linux-2.4.10/arch/ia64/lib/strlen.S Thu Apr 5 12:51:47 2001 +++ linux-2.4.10-lia/arch/ia64/lib/strlen.S Mon Sep 24 21:56:58 2001 @@ -11,7 +11,7 @@ * does not count the \0 * * Copyright (C) 1999, 2001 Hewlett-Packard Co - * Copyright (C) 1999 Stephane Eranian + * Stephane Eranian * * 09/24/99 S.Eranian add speculation recovery code */ @@ -116,7 +116,7 @@ ld8.s w[0]=[src],8 // speculatively load next to next cmp.eq.and p6,p0=8,val1 // p6 = p6 and val1==8 cmp.eq.and p6,p0=8,val2 // p6 = p6 and mask==8 -(p6) br.wtop.dptk.few 1b // loop until p6 == 0 +(p6) br.wtop.dptk 1b // loop until p6 == 0 ;; // // We must return try the recovery code iff @@ -127,14 +127,14 @@ // cmp.eq p8,p9=8,val1 // p6 = val1 had zero (disambiguate) tnat.nz p6,p7=val1 // test NaT on val1 -(p6) br.cond.spnt.few recover// jump to recovery if val1 is NaT +(p6) br.cond.spnt .recover // jump to recovery if val1 is NaT ;; // // if we come here p7 is true, i.e., initialized for // cmp // cmp.eq.and p7,p0=8,val1// val1==8? tnat.nz.and p7,p0=val2 // test NaT if val2 -(p7) br.cond.spnt.few recover// jump to recovery if val2 is NaT +(p7) br.cond.spnt .recover // jump to recovery if val2 is NaT ;; (p8) mov val1=val2 // the other test got us out of the loop (p8) adds src=-16,src // correct position when 3 ahead @@ -146,7 +146,7 @@ ;; sub ret0=ret0,tmp // adjust mov ar.pfs=saved_pfs // because of ar.ec, restore no matter what - br.ret.sptk.few rp // end of normal execution + br.ret.sptk.many rp // end of normal execution // // Outlined recovery code when speculation failed @@ -165,7 +165,7 @@ // - today we restart from the beginning of the string instead // of trying to continue where we left off. // -recover: +.recover: ld8 val=[base],8 // will fail if unrecoverable fault ;; or val=val,mask // remask first bytes @@ -180,7 +180,7 @@ czx1.r val1=val // search 0 byte from right ;; cmp.eq p6,p0=8,val1 // val1==8 ? -(p6) br.wtop.dptk.few 2b // loop until p6 == 0 +(p6) br.wtop.dptk 2b // loop until p6 == 0 ;; // (avoid WAW on p63) sub ret0=base,orig // distance from base sub tmp=8,val1 @@ -188,5 +188,5 @@ ;; sub ret0=ret0,tmp // length=now - back -1 mov ar.pfs=saved_pfs // because of ar.ec, restore no matter what - br.ret.sptk.few rp // end of successful recovery code + br.ret.sptk.many rp // end of successful recovery code END(strlen) diff -urN linux-2.4.10/arch/ia64/lib/strlen_user.S linux-2.4.10-lia/arch/ia64/lib/strlen_user.S --- linux-2.4.10/arch/ia64/lib/strlen_user.S Thu Apr 5 12:51:47 2001 +++ linux-2.4.10-lia/arch/ia64/lib/strlen_user.S Mon Sep 24 21:57:08 2001 @@ -8,8 +8,8 @@ * ret0 0 in case of fault, strlen(buffer)+1 otherwise * * Copyright (C) 1998, 1999, 2001 Hewlett-Packard Co - * Copyright (C) 1998, 1999, 2001 David Mosberger-Tang - * Copyright (C) 1998, 1999 Stephane Eranian + * David Mosberger-Tang + * Stephane Eranian * * 01/19/99 S.Eranian heavily enhanced version (see details below) * 09/24/99 S.Eranian added speculation recovery code @@ -108,7 +108,7 @@ mov ar.ec=r0 // clear epilogue counter (saved in ar.pfs) ;; add base=-16,src // keep track of aligned base - chk.s v[1], recover // if already NaT, then directly skip to recover + chk.s v[1], .recover // if already NaT, then directly skip to recover or v[1]=v[1],mask // now we have a safe initial byte pattern ;; 1: @@ -130,14 +130,14 @@ // cmp.eq p8,p9=8,val1 // p6 = val1 had zero (disambiguate) tnat.nz p6,p7=val1 // test NaT on val1 -(p6) br.cond.spnt.few recover// jump to recovery if val1 is NaT +(p6) br.cond.spnt .recover // jump to recovery if val1 is NaT ;; // // if we come here p7 is true, i.e., initialized for // cmp // cmp.eq.and p7,p0=8,val1// val1==8? tnat.nz.and p7,p0=val2 // test NaT if val2 -(p7) br.cond.spnt.few recover// jump to recovery if val2 is NaT +(p7) br.cond.spnt .recover // jump to recovery if val2 is NaT ;; (p8) mov val1=val2 // val2 contains the value (p8) adds src=-16,src // correct position when 3 ahead @@ -149,7 +149,7 @@ ;; sub ret0=ret0,tmp // length=now - back -1 mov ar.pfs=saved_pfs // because of ar.ec, restore no matter what - br.ret.sptk.few rp // end of normal execution + br.ret.sptk.many rp // end of normal execution // // Outlined recovery code when speculation failed @@ -162,7 +162,7 @@ // - today we restart from the beginning of the string instead // of trying to continue where we left off. // -recover: +.recover: EX(.Lexit1, ld8 val=[base],8) // load the initial bytes ;; or val=val,mask // remask first bytes @@ -185,7 +185,7 @@ ;; sub ret0=ret0,tmp // length=now - back -1 mov ar.pfs=saved_pfs // because of ar.ec, restore no matter what - br.ret.sptk.few rp // end of successful recovery code + br.ret.sptk.many rp // end of successful recovery code // // We failed even on the normal load (called from exception handler) @@ -194,5 +194,5 @@ mov ret0=0 mov pr=saved_pr,0xffffffffffff0000 mov ar.pfs=saved_pfs // because of ar.ec, restore no matter what - br.ret.sptk.few rp + br.ret.sptk.many rp END(__strlen_user) diff -urN linux-2.4.10/arch/ia64/lib/strncpy_from_user.S linux-2.4.10-lia/arch/ia64/lib/strncpy_from_user.S --- linux-2.4.10/arch/ia64/lib/strncpy_from_user.S Thu Apr 5 12:51:47 2001 +++ linux-2.4.10-lia/arch/ia64/lib/strncpy_from_user.S Mon Sep 24 21:57:19 2001 @@ -40,5 +40,5 @@ (p6) mov r8=in2 // buffer filled up---return buffer length (p7) sub r8=in1,r9,1 // return string length (excluding NUL character) [.Lexit:] - br.ret.sptk.few rp + br.ret.sptk.many rp END(__strncpy_from_user) diff -urN linux-2.4.10/arch/ia64/lib/strnlen_user.S linux-2.4.10-lia/arch/ia64/lib/strnlen_user.S --- linux-2.4.10/arch/ia64/lib/strnlen_user.S Thu Apr 5 12:51:47 2001 +++ linux-2.4.10-lia/arch/ia64/lib/strnlen_user.S Mon Sep 24 21:57:28 2001 @@ -33,7 +33,7 @@ add r9=1,r9 ;; cmp.eq p6,p0=r8,r0 -(p6) br.dpnt.few .Lexit +(p6) br.cond.dpnt .Lexit br.cloop.dptk.few .Loop1 add r9=1,in1 // NUL not found---return N+1 @@ -41,5 +41,5 @@ .Lexit: mov r8=r9 mov ar.lc=r16 // restore ar.lc - br.ret.sptk.few rp + br.ret.sptk.many rp END(__strnlen_user) diff -urN linux-2.4.10/arch/ia64/mm/fault.c linux-2.4.10-lia/arch/ia64/mm/fault.c --- linux-2.4.10/arch/ia64/mm/fault.c Thu Apr 5 12:51:47 2001 +++ linux-2.4.10-lia/arch/ia64/mm/fault.c Mon Sep 24 21:58:13 2001 @@ -1,8 +1,8 @@ /* * MMU fault handling support. * - * Copyright (C) 1998-2000 Hewlett-Packard Co - * Copyright (C) 1998-2000 David Mosberger-Tang + * Copyright (C) 1998-2001 Hewlett-Packard Co + * David Mosberger-Tang */ #include #include @@ -16,7 +16,7 @@ #include #include -extern void die_if_kernel (char *, struct pt_regs *, long); +extern void die (char *, struct pt_regs *, long); /* * This routine is analogous to expand_stack() but instead grows the @@ -46,16 +46,15 @@ void ia64_do_page_fault (unsigned long address, unsigned long isr, struct pt_regs *regs) { + int signal = SIGSEGV, code = SEGV_MAPERR; + struct vm_area_struct *vma, *prev_vma; struct mm_struct *mm = current->mm; struct exception_fixup fix; - struct vm_area_struct *vma, *prev_vma; struct siginfo si; - int signal = SIGSEGV; unsigned long mask; /* - * If we're in an interrupt or have no user - * context, we must not take the fault.. + * If we're in an interrupt or have no user context, we must not take the fault.. */ if (in_interrupt() || !mm) goto no_context; @@ -71,6 +70,8 @@ goto check_expansion; good_area: + code = SEGV_ACCERR; + /* OK, we've got a good vm_area for this memory area. Check the access permissions: */ # define VM_READ_BIT 0 @@ -89,12 +90,13 @@ if ((vma->vm_flags & mask) != mask) goto bad_area; + survive: /* * If for any reason at all we couldn't handle the fault, make * sure we exit gracefully rather than endlessly redo the * fault. */ - switch (handle_mm_fault(mm, vma, address, mask) != 0) { + switch (handle_mm_fault(mm, vma, address, mask)) { case 1: ++current->min_flt; break; @@ -147,7 +149,7 @@ if (user_mode(regs)) { si.si_signo = signal; si.si_errno = 0; - si.si_code = SI_KERNEL; + si.si_code = code; si.si_addr = (void *) address; force_sig_info(signal, &si, current); return; @@ -174,17 +176,29 @@ } /* - * Oops. The kernel tried to access some bad page. We'll have - * to terminate things with extreme prejudice. + * Oops. The kernel tried to access some bad page. We'll have to terminate things + * with extreme prejudice. */ - printk(KERN_ALERT "Unable to handle kernel paging request at " - "virtual address %016lx\n", address); - die_if_kernel("Oops", regs, isr); + bust_spinlocks(1); + + if (address < PAGE_SIZE) + printk(KERN_ALERT "Unable to handle kernel NULL pointer dereference"); + else + printk(KERN_ALERT "Unable to handle kernel paging request at " + "virtual address %016lx\n", address); + die("Oops", regs, isr); + bust_spinlocks(0); do_exit(SIGKILL); return; out_of_memory: up_read(&mm->mmap_sem); + if (current->pid == 1) { + current->policy |= SCHED_YIELD; + schedule(); + down_read(&mm->mmap_sem); + goto survive; + } printk("VM: killing process %s\n", current->comm); if (user_mode(regs)) do_exit(SIGKILL); diff -urN linux-2.4.10/arch/ia64/mm/tlb.c linux-2.4.10-lia/arch/ia64/mm/tlb.c --- linux-2.4.10/arch/ia64/mm/tlb.c Tue Jul 31 10:30:08 2001 +++ linux-2.4.10-lia/arch/ia64/mm/tlb.c Mon Sep 24 21:59:16 2001 @@ -2,7 +2,7 @@ * TLB support routines. * * Copyright (C) 1998-2001 Hewlett-Packard Co - * Copyright (C) 1998-2001 David Mosberger-Tang + * David Mosberger-Tang * * 08/02/00 A. Mallick * Modified RID allocation for SMP @@ -41,89 +41,6 @@ }; /* - * Seralize usage of ptc.g - */ -spinlock_t ptcg_lock = SPIN_LOCK_UNLOCKED; /* see */ - -#if defined(CONFIG_SMP) && !defined(CONFIG_ITANIUM_PTCG) - -#include - -unsigned long flush_end, flush_start, flush_nbits, flush_rid; -atomic_t flush_cpu_count; - -/* - * flush_tlb_no_ptcg is called with ptcg_lock locked - */ -static inline void -flush_tlb_no_ptcg (unsigned long start, unsigned long end, unsigned long nbits) -{ - extern void smp_send_flush_tlb (void); - unsigned long saved_tpr = 0; - unsigned long flags; - - /* - * Some times this is called with interrupts disabled and causes - * dead-lock; to avoid this we enable interrupt and raise the TPR - * to enable ONLY IPI. - */ - __save_flags(flags); - if (!(flags & IA64_PSR_I)) { - saved_tpr = ia64_get_tpr(); - ia64_srlz_d(); - ia64_set_tpr(IA64_IPI_VECTOR - 16); - ia64_srlz_d(); - local_irq_enable(); - } - - spin_lock(&ptcg_lock); - flush_rid = ia64_get_rr(start); - ia64_srlz_d(); - flush_start = start; - flush_end = end; - flush_nbits = nbits; - atomic_set(&flush_cpu_count, smp_num_cpus - 1); - smp_send_flush_tlb(); - /* - * Purge local TLB entries. ALAT invalidation is done in ia64_leave_kernel. - */ - do { - asm volatile ("ptc.l %0,%1" :: "r"(start), "r"(nbits<<2) : "memory"); - start += (1UL << nbits); - } while (start < end); - - ia64_srlz_i(); /* srlz.i implies srlz.d */ - - /* - * Wait for other CPUs to finish purging entries. - */ -#if defined(CONFIG_ITANIUM_BSTEP_SPECIFIC) - { - extern void smp_resend_flush_tlb (void); - unsigned long start = ia64_get_itc(); - - while (atomic_read(&flush_cpu_count) > 0) { - if ((ia64_get_itc() - start) > 400000UL) { - smp_resend_flush_tlb(); - start = ia64_get_itc(); - } - } - } -#else - while (atomic_read(&flush_cpu_count)) { - /* Nothing */ - } -#endif - if (!(flags & IA64_PSR_I)) { - local_irq_disable(); - ia64_set_tpr(saved_tpr); - ia64_srlz_d(); - } -} - -#endif /* CONFIG_SMP && !CONFIG_ITANIUM_PTCG */ - -/* * Acquire the ia64_ctx.lock before calling this function! */ void @@ -162,6 +79,26 @@ flush_tlb_all(); } +static void +ia64_global_tlb_purge (unsigned long start, unsigned long end, unsigned long nbits) +{ + static spinlock_t ptcg_lock = SPIN_LOCK_UNLOCKED; + + /* HW requires global serialization of ptc.ga. */ + spin_lock(&ptcg_lock); + { + do { + /* + * Flush ALAT entries also. + */ + asm volatile ("ptc.ga %0,%1;;srlz.i;;" :: "r"(start), "r"(nbits<<2) + : "memory"); + start += (1UL << nbits); + } while (start < end); + } + spin_unlock(&ptcg_lock); +} + void __flush_tlb_all (void) { @@ -222,23 +159,15 @@ } start &= ~((1UL << nbits) - 1); -#if defined(CONFIG_SMP) && !defined(CONFIG_ITANIUM_PTCG) - flush_tlb_no_ptcg(start, end, nbits); -#else - spin_lock(&ptcg_lock); do { # ifdef CONFIG_SMP - /* - * Flush ALAT entries also. - */ - asm volatile ("ptc.ga %0,%1;;srlz.i;;" :: "r"(start), "r"(nbits<<2) : "memory"); + platform_global_tlb_purge(start, end, nbits); # else asm volatile ("ptc.l %0,%1" :: "r"(start), "r"(nbits<<2) : "memory"); # endif start += (1UL << nbits); } while (start < end); -#endif /* CONFIG_SMP && !defined(CONFIG_ITANIUM_PTCG) */ - spin_unlock(&ptcg_lock); + ia64_insn_group_barrier(); ia64_srlz_i(); /* srlz.i implies srlz.d */ ia64_insn_group_barrier(); diff -urN linux-2.4.10/arch/ia64/sn/sn1/llsc4.c linux-2.4.10-lia/arch/ia64/sn/sn1/llsc4.c --- linux-2.4.10/arch/ia64/sn/sn1/llsc4.c Thu Apr 5 12:51:47 2001 +++ linux-2.4.10-lia/arch/ia64/sn/sn1/llsc4.c Mon Aug 13 23:58:03 2001 @@ -35,16 +35,6 @@ static int inttest=0; #endif -#ifdef IA64_SEMFIX_INSN -#undef IA64_SEMFIX_INSN -#endif -#ifdef IA64_SEMFIX -#undef IA64_SEMFIX -#endif -# define IA64_SEMFIX_INSN -# define IA64_SEMFIX "" - - /* * Test parameter table for AUTOTEST */ @@ -192,7 +182,6 @@ printk (" llscfail \t%s\tForce a failure to test the trigger & error messages\n", fail_enabled ? "on" : "off"); printk (" llscselt \t%s\tSelective triger on failures\n", selective_trigger ? "on" : "off"); printk (" llscblkadr \t%s\tDump data block addresses\n", dump_block_addrs_opt ? "on" : "off"); - printk (" SEMFIX: %s\n", IA64_SEMFIX); printk ("\n"); } __setup("autotest", autotest_enable); diff -urN linux-2.4.10/arch/ia64/tools/print_offsets.c linux-2.4.10-lia/arch/ia64/tools/print_offsets.c --- linux-2.4.10/arch/ia64/tools/print_offsets.c Tue Jul 31 10:30:09 2001 +++ linux-2.4.10-lia/arch/ia64/tools/print_offsets.c Mon Sep 24 21:59:30 2001 @@ -61,7 +61,7 @@ { "IA64_TASK_THREAD_SIGMASK_OFFSET",offsetof (struct task_struct, thread.un.sigmask) }, #endif #ifdef CONFIG_PERFMON - { "IA64_TASK_PFM_NOTIFY_OFFSET", offsetof(struct task_struct, thread.pfm_pend_notify) }, + { "IA64_TASK_PFM_MUST_BLOCK_OFFSET",offsetof(struct task_struct, thread.pfm_must_block) }, #endif { "IA64_TASK_PID_OFFSET", offsetof (struct task_struct, pid) }, { "IA64_TASK_MM_OFFSET", offsetof (struct task_struct, mm) }, @@ -165,17 +165,18 @@ { "IA64_SIGCONTEXT_FR6_OFFSET", offsetof (struct sigcontext, sc_fr[6]) }, { "IA64_SIGCONTEXT_PR_OFFSET", offsetof (struct sigcontext, sc_pr) }, { "IA64_SIGCONTEXT_R12_OFFSET", offsetof (struct sigcontext, sc_gr[12]) }, + { "IA64_SIGCONTEXT_RBS_BASE_OFFSET",offsetof (struct sigcontext, sc_rbs_base) }, + { "IA64_SIGCONTEXT_LOADRS_OFFSET", offsetof (struct sigcontext, sc_loadrs) }, { "IA64_SIGFRAME_ARG0_OFFSET", offsetof (struct sigframe, arg0) }, { "IA64_SIGFRAME_ARG1_OFFSET", offsetof (struct sigframe, arg1) }, { "IA64_SIGFRAME_ARG2_OFFSET", offsetof (struct sigframe, arg2) }, - { "IA64_SIGFRAME_RBS_BASE_OFFSET", offsetof (struct sigframe, rbs_base) }, { "IA64_SIGFRAME_HANDLER_OFFSET", offsetof (struct sigframe, handler) }, { "IA64_SIGFRAME_SIGCONTEXT_OFFSET", offsetof (struct sigframe, sc) }, { "IA64_CLONE_VFORK", CLONE_VFORK }, { "IA64_CLONE_VM", CLONE_VM }, { "IA64_CPU_IRQ_COUNT_OFFSET", offsetof (struct cpuinfo_ia64, irq_stat.f.irq_count) }, { "IA64_CPU_BH_COUNT_OFFSET", offsetof (struct cpuinfo_ia64, irq_stat.f.bh_count) }, - { "IA64_CPU_PHYS_STACKED_SIZE_P8_OFFSET", offsetof (struct cpuinfo_ia64, phys_stacked_size_p8) }, + { "IA64_CPU_PHYS_STACKED_SIZE_P8_OFFSET",offsetof (struct cpuinfo_ia64, phys_stacked_size_p8)}, }; static const char *tabs = "\t\t\t\t\t\t\t\t\t\t"; diff -urN linux-2.4.10/drivers/acpi/Makefile linux-2.4.10-lia/drivers/acpi/Makefile --- linux-2.4.10/drivers/acpi/Makefile Mon Sep 24 15:06:37 2001 +++ linux-2.4.10-lia/drivers/acpi/Makefile Mon Sep 24 21:59:51 2001 @@ -39,7 +39,7 @@ obj-$(CONFIG_ACPI) += os.o acpi_ksyms.o obj-$(CONFIG_ACPI) += $(foreach dir,$(acpi-subdirs),$(dir)/$(dir).o) ifdef CONFIG_ACPI_KERNEL_CONFIG - obj-$(CONFIG_ACPI) += acpiconf.o osconf.o + obj-$(CONFIG_ACPI) += acpiconf.o osconf.o driver.o endif obj-$(CONFIG_ACPI) += driver.o diff -urN linux-2.4.10/drivers/acpi/acpiconf.c linux-2.4.10-lia/drivers/acpi/acpiconf.c --- linux-2.4.10/drivers/acpi/acpiconf.c Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/acpi/acpiconf.c Mon Sep 24 22:00:01 2001 @@ -0,0 +1,593 @@ +/* + * acpiconf.c - ACPI based kernel configuration + * + * Copyright (C) 2000-2001 Intel Corp. + * Copyright (C) 2000-2001 J.I. Lee + * + * Revision History: + * 9/15/2000 J.I. + * Major revision: for new ACPI initialization requirements + * 11/15/2000 J.I. + * Major revision: ACPI 2.0 tables support + * 04/23/2001 J.I. + * Rewrote functions to support multiple _PRTs of child P2Ps + * under root pci bus + */ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include "acpi.h" +#include "osconf.h" +#include "acpiconf.h" + + +static int acpi_cf_initialized __initdata = 0; + +acpi_status __init +acpi_cf_init ( + void * rsdp + ) +{ + acpi_status status; + + acpi_os_bind_osd(ACPI_CF_PHASE_BOOTTIME); + + status = acpi_initialize_subsystem (); + if (ACPI_FAILURE(status)) { + printk ("Acpi cfg:initialize_subsystem error=0x%x\n", status); + return status; + } + dprintk(("Acpi cfg:initialize_subsystem pass\n")); + + status = acpi_load_tables (); + if (ACPI_FAILURE(status)) { + printk ("Acpi cfg:load firmware tables error=0x%x\n", status); + acpi_terminate(); + return status; + } + dprintk(("Acpi cfg:load firmware tables pass\n")); + + status = acpi_enable_subsystem (ACPI_FULL_INITIALIZATION); + if (ACPI_FAILURE(status)) { + printk ("Acpi cfg:enable_subsystem error=0x%x\n", status); + acpi_terminate(); + return status; + } + dprintk(("Acpi cfg:enable_subsystem pass\n")); + + acpi_cf_initialized++; + + return AE_OK; +} + + +acpi_status __init +acpi_cf_terminate ( void ) +{ + acpi_status status; + + if (! ACPI_CF_INITIALIZED()) { + acpi_os_bind_osd(ACPI_CF_PHASE_RUNTIME); + return AE_ERROR; + } + + status = acpi_disable (); + if (ACPI_FAILURE(status)) { + printk ("Acpi cfg:disable fail=0x%x\n", status); + /* fall thru...*/ + } + + status = acpi_terminate (); + if (ACPI_FAILURE(status)) { + printk ("Acpi cfg:acpi terminate error=0x%x\n", status); + /* fall thru...*/ + } + + acpi_cf_cleanup(); + acpi_os_bind_osd(ACPI_CF_PHASE_RUNTIME); + + acpi_cf_initialized--; + + return status; +} + + +acpi_status __init +acpi_cf_get_pci_vectors ( + struct pci_vector_struct **vectors, + int *num_pci_vectors + ) +{ + acpi_status status; + void *prts; + + if (! ACPI_CF_INITIALIZED()) { + status = acpi_cf_init((void *)efi.acpi); + if (ACPI_FAILURE (status)) + return status; + } + + *vectors = NULL; + *num_pci_vectors = 0; + + status = acpi_cf_get_prt (&prts); + if (ACPI_FAILURE (status)) { + printk("Acpi cfg: get prt fail\n"); + return status; + } + + status = acpi_cf_convert_prt_to_vectors (prts, vectors, num_pci_vectors); +#ifdef CONFIG_ACPI_KERNEL_CONFIG_DEBUG + if (ACPI_SUCCESS(status)) { + acpi_cf_print_pci_vectors (*vectors, *num_pci_vectors); + } +#endif + printk("Acpi cfg: get PCI interrupt vectors %s\n", + (ACPI_SUCCESS(status))?"pass":"fail"); + + return status; +} + + +static pci_routing_table *pci_routing_tables[PCI_MAX_BUS] __initdata = {NULL}; + + +typedef struct _acpi_rpb { + NATIVE_UINT rpb_busnum; + NATIVE_UINT lastbusnum; + acpi_handle rpb_handle; +} acpi_rpb_t; + + +static acpi_status __init +acpi_cf_evaluate_method ( + acpi_handle handle, + UINT8 *method_name, + NATIVE_UINT *nuint + ) +{ + UINT32 tnuint = 0; + acpi_status status; + + acpi_buffer ret_buf; + acpi_object *ext_obj; + UINT8 buf[PATHNAME_MAX]; + + + ret_buf.length = PATHNAME_MAX; + ret_buf.pointer = (void *) buf; + + status = acpi_evaluate_object(handle, method_name, NULL, &ret_buf); + if (ACPI_FAILURE(status)) { + if (status == AE_NOT_FOUND) { + printk("Acpi cfg: no %s found\n", method_name); + } else { + printk("Acpi cfg: %s fail=0x%x\n", method_name, status); + } + } else { + ext_obj = (acpi_object *) ret_buf.pointer; + + switch (ext_obj->type) { + case ACPI_TYPE_INTEGER: + tnuint = (NATIVE_UINT) ext_obj->integer.value; + break; + default: + printk("Acpi cfg: %s obj type incorrect\n", method_name); + status = AE_TYPE; + break; + } + } + + *nuint = tnuint; + return (status); +} + + +static acpi_status __init +acpi_cf_evaluate_PRT ( + acpi_handle handle, + pci_routing_table **prt + ) +{ + acpi_buffer acpi_buffer; + acpi_status status; + + acpi_buffer.length = 0; + acpi_buffer.pointer = NULL; + + status = acpi_get_irq_routing_table (handle, &acpi_buffer); + + switch (status) { + case AE_BUFFER_OVERFLOW: + dprintk(("Acpi cfg: _PRT found. need %d bytes\n", + acpi_buffer.length)); + break; /* found */ + default: + printk("Acpi cfg: _PRT fail=0x%x\n", status); + case AE_NOT_FOUND: + return status; + } + + *prt = (pci_routing_table *) acpi_os_callocate (acpi_buffer.length); + if (!*prt) { + printk("Acpi cfg: callocate %d bytes for _PRT fail\n", + acpi_buffer.length); + return AE_NO_MEMORY; + } + acpi_buffer.pointer = (void *) *prt; + + status = acpi_get_irq_routing_table (handle, &acpi_buffer); + if (ACPI_FAILURE(status)) { + printk("Acpi cfg: _PRT fail=0x%x.\n", status); + acpi_os_free(prt); + } + + return status; +} + +static acpi_status __init +acpi_cf_get_root_pci_callback ( + acpi_handle handle, + UINT32 Level, + void *context, + void **retval + ) +{ + NATIVE_UINT busnum = 0; + acpi_status status; + acpi_rpb_t rpb; + pci_routing_table *prt; + + UINT8 path_name[PATHNAME_MAX]; +#ifdef CONFIG_ACPI_KERNEL_CONFIG_DEBUG + acpi_buffer ret_buf; + + ret_buf.length = PATHNAME_MAX; + ret_buf.pointer = (void *) path_name; + + status = acpi_get_name(handle, ACPI_FULL_PATHNAME, &ret_buf); +#else + memset(path_name, 0, sizeof (path_name)); +#endif + + /* + * get bus number of this pci root bridge + */ + status = acpi_cf_evaluate_method(handle, METHOD_NAME__BBN, &busnum); + if (ACPI_FAILURE(status)) { + printk("Acpi cfg:%s evaluate _BBN fail=0x%x\n", + path_name, status); + return (status); + } + printk("Acpi cfg:%s ROOT PCI bus %ld\n", path_name, busnum); + + /* + * evaluate root pci bridge's _CRS for Bus number range for child P2P + * (bus min/max/len) - not yet. + */ + + /* + * get immediate _PRT of this root pci bridge if any + */ + status = acpi_cf_evaluate_PRT (handle, &prt); + switch(status) { + case AE_NOT_FOUND: + break; + default: + if (ACPI_FAILURE(status)) { + printk("Acpi cfg:%s _PRT fail=0x%x\n", + path_name, status); + return status; + } + dprintk(("Acpi cfg:%s bus %ld got _PRT\n", path_name, busnum)); + acpi_cf_add_to_pci_routing_tables (busnum, prt); + break; + } + + + /* + * walk down this root pci bridge to get _PRTs if any + */ + rpb.rpb_busnum = rpb.lastbusnum = busnum; + rpb.rpb_handle = handle; + status = acpi_walk_namespace ( ACPI_TYPE_DEVICE, + handle, + ACPI_UINT32_MAX, + acpi_cf_get_prt_callback, + &rpb, + NULL ); + if (ACPI_FAILURE(status)) + printk("Acpi cfg:%s walk namespace for _PRT error=0x%x\n", + path_name, status); + + return (status); +} + + +/* + * handle _PRTs of immediate P2Ps of root pci. + */ +static acpi_status __init +acpi_cf_associate_prt_to_bus ( + acpi_handle handle, + acpi_rpb_t *rpb, + NATIVE_UINT *retbusnum, + NATIVE_UINT depth + ) +{ + acpi_status status; + UINT32 segbus; + NATIVE_UINT devfn; + UINT8 bn; + + UINT8 path_name[PATHNAME_MAX]; + acpi_pci_id pci_id; + +#ifdef CONFIG_ACPI_KERNEL_CONFIG_DEBUG + acpi_buffer ret_buf; + + ret_buf.length = PATHNAME_MAX; + ret_buf.pointer = (void *) path_name; + + status = acpi_get_name(handle, ACPI_FULL_PATHNAME, &ret_buf); +#else + memset(path_name, 0, sizeof (path_name)); +#endif + + /* + * get devfn from _ADR + */ + status = acpi_cf_evaluate_method(handle, METHOD_NAME__ADR, &devfn); + if (ACPI_FAILURE(status)) { + *retbusnum = rpb->rpb_busnum + 1; + printk("Acpi cfg:%s _ADR fail=0x%x. Set busnum to %ld\n", + path_name, status, *retbusnum); + return AE_OK; + } + dprintk(("Acpi cfg:%s _ADR =0x%x\n", path_name, (UINT32)devfn)); + + + /* + * access pci config space for bus number + * segbus = from rpb, devfn = from _ADR + */ + pci_id.segment = 0; + pci_id.bus = (u16)(rpb->rpb_busnum & 0xffffffff); + pci_id.device = (u16)((devfn >> 16) & 0xffff); + pci_id.function = (u16)(devfn & 0xffff); + + status = acpi_os_read_pci_configuration(&pci_id, PCI_PRIMARY_BUS, + &bn, 1); + if (ACPI_FAILURE(status)) { + *retbusnum = rpb->rpb_busnum + 1; + printk("Acpi cfg:%s pci read fail=0x%x. b:df:a=%x:%x:%x\n", + path_name, status, segbus, (UINT32)devfn, + PCI_PRIMARY_BUS); + printk("Acpi cfg:%s Set busnum to %ld\n", + path_name, *retbusnum); + return AE_OK; + } + dprintk(("Acpi cfg:%s pribus %d\n", path_name, bn)); + + + status = acpi_os_read_pci_configuration(&pci_id, PCI_SECONDARY_BUS, + &bn, 1); + if (ACPI_FAILURE(status)) { + *retbusnum = rpb->rpb_busnum + 1; + printk("Acpi cfg:%s pci read fail=0x%x. b:df:a=%x:%x:%x\n", + path_name, status, segbus, (UINT32)devfn, + PCI_SECONDARY_BUS); + printk("Acpi cfg:%s Set busnum to %ld\n", + path_name, *retbusnum); + return AE_OK; + } + dprintk(("Acpi cfg:%s busnum %d\n", path_name, bn)); + + *retbusnum = (NATIVE_UINT)bn; + return AE_OK; +} + + +static acpi_status __init +acpi_cf_get_prt ( + void **prts + ) +{ + acpi_status status; + + status = acpi_get_devices ( PCI_ROOT_HID_STRING, + acpi_cf_get_root_pci_callback, + NULL, + NULL ); + + if (ACPI_FAILURE(status)) { + printk("Acpi cfg:get_device PCI ROOT HID error=0x%x\n", status); + } + + *prts = (void *)pci_routing_tables; + + return status; +} + +static acpi_status __init +acpi_cf_get_prt_callback ( + acpi_handle handle, + UINT32 Level, + void *context, + void **retval + ) +{ + pci_routing_table *prt; + NATIVE_UINT busnum = 0; + NATIVE_UINT temp = 0x0F; + acpi_status status; + + UINT8 path_name[PATHNAME_MAX]; + +#ifdef CONFIG_ACPI_KERNEL_CONFIG_DEBUG + acpi_buffer ret_buf; + + ret_buf.length = PATHNAME_MAX; + ret_buf.pointer = (void *) path_name; + + status = acpi_get_name(handle, ACPI_FULL_PATHNAME, &ret_buf); +#else + memset(path_name, 0, sizeof (path_name)); +#endif + + status = acpi_cf_evaluate_PRT (handle, &prt); + switch(status) { + case AE_NOT_FOUND: + return AE_OK; + default: + if (ACPI_FAILURE(status)) { + printk("Acpi cfg:%s _PRT fail=0x%x\n", + path_name, status); + return status; + } + } + + /* + * evaluate _STA in case this device does not exist + */ + status = acpi_cf_evaluate_method(handle, METHOD_NAME__STA, &temp); + switch(status) { + case AE_NOT_FOUND: + break; + default: + if (ACPI_FAILURE(status)) { + printk("Acpi cfg:%s _STA fail=0x%x\n", + path_name, status); + return status; + } + if (!(temp & ACPI_STA_DEVICE_PRESENT)) { + dprintk(("Acpi cfg:%s not exist. _PRT discarded\n", + path_name)); + acpi_os_free(prt); + return AE_OK; + } + break; + } + + /* + * associate a bus number to this _PRT since + * this _PRT is not on root pci bridge + */ + acpi_cf_associate_prt_to_bus(handle, context, &busnum, 0); + + printk("Acpi cfg:%s busnum %ld got _PRT\n", path_name, busnum); + acpi_cf_add_to_pci_routing_tables (busnum, prt); + + return AE_OK; +} + + +static void __init +acpi_cf_add_to_pci_routing_tables ( + NATIVE_UINT busnum, + pci_routing_table *prt + ) +{ + if ( busnum >= PCI_MAX_BUS ) { + printk("Acpi cfg:invalid pci bus number %ld\n", busnum); + acpi_os_free(prt); + return; + } + + if (pci_routing_tables[busnum]) { + printk("Acpi cfg:duplicate PRT for pci bus %ld. overiding...\n", busnum); + acpi_os_free(pci_routing_tables[busnum]); + } + + pci_routing_tables[busnum] = prt; +} + + +#define DUMPVECTOR(pv) printk("PCI bus=0x%x id=0x%x pin=0x%x irq=0x%x\n", pv->bus, pv->pci_id, pv->pin, pv->irq); + +static acpi_status __init +acpi_cf_convert_prt_to_vectors ( + void *prts, + struct pci_vector_struct **vectors, + int *num_pci_vectors + ) +{ + struct pci_vector_struct *pvec; + pci_routing_table **pprts, *prt, *prtf; + int nvec = 0; + int i; + + + pprts = (pci_routing_table **)prts; + + for ( i = 0; i < PCI_MAX_BUS; i++) { + prt = *pprts++; + if (prt) { + for ( ; prt->length > 0; nvec++) { + prt = (pci_routing_table *) ((NATIVE_UINT)prt + (NATIVE_UINT)prt->length); + } + } + } + + *num_pci_vectors = nvec; + *vectors = acpi_os_callocate (sizeof(struct pci_vector_struct) * nvec); + if (!*vectors) { + printk("Acpi cfg: callocate for pci_vector error\n"); + return AE_NO_MEMORY; + } + + pvec = *vectors; + pprts = (pci_routing_table **)prts; + + for ( i = 0; i < PCI_MAX_BUS; i++) { + prt = prtf = *pprts++; + if (prt) { + for ( ; prt->length > 0; pvec++) { + pvec->bus = (UINT16)i; + pvec->pci_id = prt->address; + pvec->pin = (UINT8)prt->pin; + pvec->irq = (UINT8)prt->source_index; + + prt = (pci_routing_table *) ((NATIVE_UINT)prt + (NATIVE_UINT)prt->length); + } + acpi_os_free((void *)prtf); + } + } + + return AE_OK; +} + + +void __init +acpi_cf_cleanup ( void ) +{ + /* nothing to free, pci_vectors are used by the kernel */ +} + + +#ifdef CONFIG_ACPI_KERNEL_CONFIG_DEBUG +void __init +acpi_cf_print_pci_vectors ( + struct pci_vector_struct *vectors, + int num_pci_vectors + ) +{ + struct pci_vector_struct *pvec; + int i; + + printk("number of PCI interrupt vectors = %d\n", num_pci_vectors); + + pvec = vectors; + for (i = 0; i < num_pci_vectors; i++) { + DUMPVECTOR(pvec); + pvec++; + } +} +#endif diff -urN linux-2.4.10/drivers/acpi/acpiconf.h linux-2.4.10-lia/drivers/acpi/acpiconf.h --- linux-2.4.10/drivers/acpi/acpiconf.h Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/acpi/acpiconf.h Mon Sep 24 22:21:57 2001 @@ -0,0 +1,63 @@ +/* + * acpiconf.h - ACPI based kernel configuration + * + * Copyright (C) 2000 Intel Corp. + * Copyright (C) 2000 J.I. Lee + */ + +#include + +#define PCI_MAX_BUS 0x100 +#define ACPI_STA_DEVICE_PRESENT 0x01 + +#ifdef CONFIG_ACPI_KERNEL_CONFIG_DEBUG +#define ACPI_CF_INITIALIZED() (acpi_cf_initialized > 0) +#undef dprintk +#define dprintk(a) printk a +#else +#define ACPI_CF_INITIALIZED() 1 +#undef dprintk +#define dprintk(a) +#endif + + +extern +void __init +acpi_os_bind_osd(int acpi_phase); + + +static +acpi_status __init +acpi_cf_get_prt (void **prts); + + +static +acpi_status __init +acpi_cf_get_prt_callback ( + acpi_handle handle, + UINT32 level, + void *context, + void **retval + ); + + +static +void __init +acpi_cf_add_to_pci_routing_tables ( + NATIVE_UINT busnum, + pci_routing_table *prt + ); + + +static +acpi_status __init +acpi_cf_convert_prt_to_vectors ( + void *prts, + struct pci_vector_struct **vectors, + int *num_pci_vectors + ); + + +void __init +acpi_cf_cleanup ( void ); + diff -urN linux-2.4.10/drivers/acpi/hardware/hwacpi.c linux-2.4.10-lia/drivers/acpi/hardware/hwacpi.c --- linux-2.4.10/drivers/acpi/hardware/hwacpi.c Mon Sep 24 15:06:41 2001 +++ linux-2.4.10-lia/drivers/acpi/hardware/hwacpi.c Mon Sep 24 22:00:26 2001 @@ -196,6 +196,7 @@ { acpi_status status = AE_NO_HARDWARE_RESPONSE; + u32 retries = 20; FUNCTION_TRACE ("Hw_set_mode"); @@ -220,11 +221,14 @@ /* Give the platform some time to react */ - acpi_os_stall (5000); + while (retries-- > 0) { + acpi_os_stall (5000); - if (acpi_hw_get_mode () == mode) { - ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Mode %X successfully enabled\n", mode)); - status = AE_OK; + if (acpi_hw_get_mode () == mode) { + ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Mode %X successfully enabled\n", mode)); + status = AE_OK; + break; + } } return_ACPI_STATUS (status); diff -urN linux-2.4.10/drivers/acpi/include/actypes.h linux-2.4.10-lia/drivers/acpi/include/actypes.h --- linux-2.4.10/drivers/acpi/include/actypes.h Mon Sep 24 15:06:42 2001 +++ linux-2.4.10-lia/drivers/acpi/include/actypes.h Mon Sep 24 22:00:40 2001 @@ -60,6 +60,7 @@ typedef int INT32; typedef unsigned int UINT32; typedef COMPILER_DEPENDENT_UINT64 UINT64; +typedef long INT64; typedef UINT64 NATIVE_UINT; typedef INT64 NATIVE_INT; diff -urN linux-2.4.10/drivers/acpi/os.c linux-2.4.10-lia/drivers/acpi/os.c --- linux-2.4.10/drivers/acpi/os.c Mon Sep 24 15:06:43 2001 +++ linux-2.4.10-lia/drivers/acpi/os.c Mon Sep 24 21:30:48 2001 @@ -31,6 +31,8 @@ * - Fixed improper kernel_thread parameters */ +#include + #include #include #include @@ -48,7 +50,8 @@ #ifdef _IA64 #include -#endif +#include +#endif #define _COMPONENT ACPI_OS_SERVICES MODULE_NAME ("os") @@ -61,6 +64,33 @@ /***************************************************************************** + * Function Binding + *****************************************************************************/ + +#ifdef CONFIG_ACPI_KERNEL_CONFIG +#include "osconf.h" + +struct acpi_osd acpi_osd_rt = { + /* these are runtime osd entries that differ from boottime entries */ + acpi_os_allocate_rt, + acpi_os_callocate_rt, + acpi_os_free_rt, + acpi_os_queue_for_execution_rt, + acpi_os_read_pci_configuration_rt, + acpi_os_write_pci_configuration_rt, + acpi_os_stall_rt +}; +#else +#define acpi_os_allocate_rt acpi_os_allocate +#define acpi_os_callocate_rt acpi_os_callocate +#define acpi_os_free_rt acpi_os_free +#define acpi_os_queue_for_execution_rt acpi_os_queue_for_execution +#define acpi_os_read_pci_configuration_rt acpi_os_read_pci_configuration +#define acpi_os_write_pci_configuration_rt acpi_os_write_pci_configuration +#define acpi_os_stall_rt acpi_os_stall +#endif + +/***************************************************************************** * Debugger Stuff *****************************************************************************/ @@ -137,13 +167,13 @@ } void * -acpi_os_allocate(u32 size) +acpi_os_allocate_rt(u32 size) { return kmalloc(size, GFP_KERNEL); } void * -acpi_os_callocate(u32 size) +acpi_os_callocate_rt(u32 size) { void *ptr = acpi_os_allocate(size); if (ptr) @@ -153,7 +183,7 @@ } void -acpi_os_free(void *ptr) +acpi_os_free_rt(void *ptr) { kfree(ptr); } @@ -233,12 +263,105 @@ (*acpi_irq_handler)(acpi_irq_context); } +#ifdef CONFIG_ACPI_KERNEL_CONFIG +struct irqaction acpiirqaction; +/* + * codes from request_irq and free_irq. + */ acpi_status acpi_os_install_interrupt_handler(u32 irq, OSD_HANDLER handler, void *context) { -#ifdef _IA64 + struct irqaction *act; + int retval; + + if (irq >= NR_IRQS) { + printk("ACPI: install SCI handler fail: invalid irq%d\n", irq); + return AE_ERROR; + } + + if (!handler) { + printk("ACPI: install SCI handler fail: invalid handler\n"); + return AE_ERROR; + } + + act = & acpiirqaction; + irq = isa_irq_to_vector(irq); -#endif /*_IA64*/ + acpi_irq_irq = irq; + acpi_irq_handler = handler; + acpi_irq_context = context; + + act->handler = acpi_irq; + act->flags = SA_INTERRUPT | SA_SHIRQ; + act->mask = 0; + act->name = "acpi"; + act->next = NULL; + act->dev_id = acpi_irq; + + retval = setup_irq(irq, act); + if (retval) { + printk("ACPI: install SCI handler fail: setup_irq\n"); + acpi_irq_handler = NULL; + return AE_ERROR; + } + printk("ACPI: install SCI %d handler pass\n", irq); + + return AE_OK; +} + +acpi_status +acpi_os_remove_interrupt_handler(u32 irq, OSD_HANDLER handler) +{ + irq_desc_t *desc; + struct irqaction **p; + unsigned long flags; + + if (!acpi_irq_handler) + return AE_OK; + + irq = isa_irq_to_vector(irq); + if (irq != acpi_irq_irq) return AE_ERROR; + + acpi_irq_handler = NULL; + + desc = irq_desc(irq); + spin_lock_irqsave(&desc->lock,flags); + p = &desc->action; + for (;;) { + struct irqaction * action = *p; + if (action) { + struct irqaction **pp = p; + p = &action->next; + if (action->dev_id != acpi_irq) + continue; + + /* Found it - now remove it from the list of entries */ + *pp = action->next; + if (!desc->action) { + desc->status |= IRQ_DISABLED; + desc->handler->shutdown(irq); + } + spin_unlock_irqrestore(&desc->lock,flags); + +#ifdef CONFIG_SMP + /* Wait to make sure it's not being used on another CPU */ + while (desc->status & IRQ_INPROGRESS) + barrier(); +#endif + return AE_OK; + } + printk("ACPI: Trying to free free IRQ%d\n",irq); + spin_unlock_irqrestore(&desc->lock,flags); + return AE_OK; + } + + return AE_OK; +} + +#else +acpi_status +acpi_os_install_interrupt_handler(u32 irq, OSD_HANDLER handler, void *context) +{ acpi_irq_irq = irq; acpi_irq_handler = handler; acpi_irq_context = context; @@ -267,6 +390,7 @@ return AE_OK; } +#endif /* * Running in interpreter thread context, safe to sleep @@ -280,7 +404,7 @@ } void -acpi_os_stall(u32 us) +acpi_os_stall_rt(u32 us) { if (us > 10000) { mdelay(us / 1000); @@ -322,7 +446,7 @@ acpi_status acpi_os_write_port( ACPI_IO_ADDRESS port, - u32 value, + NATIVE_UINT value, u32 width) { switch (width) @@ -375,7 +499,7 @@ acpi_status acpi_os_write_memory( ACPI_PHYSICAL_ADDRESS phys_addr, - u32 value, + NATIVE_UINT value, u32 width) { switch (width) @@ -468,7 +592,7 @@ #else /*CONFIG_ACPI_PCI*/ acpi_status -acpi_os_read_pci_configuration ( +acpi_os_read_pci_configuration_rt ( acpi_pci_id *pci_id, u32 reg, void *value, @@ -502,10 +626,10 @@ } acpi_status -acpi_os_write_pci_configuration ( +acpi_os_write_pci_configuration_rt ( acpi_pci_id *pci_id, u32 reg, - u32 value, + NATIVE_UINT value, u32 width) { int devfn = PCI_DEVFN(pci_id->device, pci_id->function); @@ -620,6 +744,22 @@ acpi_os_free(dpc); } } + +#ifdef CONFIG_ACPI_KERNEL_CONFIG +/* + * Queue for interpreter thread + */ + +acpi_status +acpi_os_queue_for_execution_rt( + u32 priority, + OSD_EXECUTION_CALLBACK callback, + void *context) +{ + (*callback)(context); + return AE_OK; +} +#endif acpi_status acpi_os_queue_for_execution( diff -urN linux-2.4.10/drivers/acpi/osconf.c linux-2.4.10-lia/drivers/acpi/osconf.c --- linux-2.4.10/drivers/acpi/osconf.c Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/acpi/osconf.c Mon Sep 24 22:00:48 2001 @@ -0,0 +1,286 @@ +/* + * osconf.c - ACPI OS-dependent functions for Kernel Boot/Configuration time + * + * Copyright (C) 2000 Intel Corp. + * Copyright (C) 2000 J.I. Lee + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "acpi.h" +#include "osconf.h" + + +static void * __init acpi_os_allocate_bt(u32 size); +static void * __init acpi_os_callocate_bt(u32 size); +static void __init acpi_os_free_bt(void *ptr); +static void __init acpi_os_stall_bt(u32 us); + +static acpi_status __init +acpi_os_queue_for_execution_bt( + u32 priority, + OSD_EXECUTION_CALLBACK callback, + void *context + ); + +static acpi_status __init +acpi_os_read_pci_configuration_bt( acpi_pci_id *pci_id, u32 reg, void *value, u32 width); + +static acpi_status __init +acpi_os_write_pci_configuration_bt( acpi_pci_id *pci_id, u32 reg, NATIVE_UINT value, u32 width); + + +extern struct acpi_osd acpi_osd_rt; +static struct acpi_osd acpi_osd_bt __initdata = { + /* these are boottime osd entries that differ from runtime entries */ + acpi_os_allocate_bt, + acpi_os_callocate_bt, + acpi_os_free_bt, + acpi_os_queue_for_execution_bt, + acpi_os_read_pci_configuration_bt, + acpi_os_write_pci_configuration_bt, + acpi_os_stall_bt +}; +static struct acpi_osd *acpi_osd = &acpi_osd_rt; + +#ifdef CONFIG_ACPI_KERNEL_CONFIG_BM_PROFILE +static void __init +acpi_cf_bm_statistics( void ); +#endif + +void __init +acpi_os_bind_osd(int acpi_phase) +{ + switch (acpi_phase) { + case ACPI_CF_PHASE_BOOTTIME: + acpi_osd = &acpi_osd_bt; + printk("Acpi cfg:bind to Boot time Acpi OSD\n"); + break; + case ACPI_CF_PHASE_RUNTIME: + default: + acpi_osd = &acpi_osd_rt; + printk("Acpi cfg:bind to Run time Acpi OSD\n"); +#ifdef CONFIG_ACPI_KERNEL_CONFIG_BM_PROFILE + acpi_cf_bm_statistics(); +#endif + break; + } +} + +void * +acpi_os_allocate(u32 size) +{ + return acpi_osd->allocate(size); +} + +void * +acpi_os_callocate(u32 size) +{ + return acpi_osd->callocate(size); +} + +void +acpi_os_free(void *ptr) +{ + acpi_osd->free(ptr); + return; +} + +void +acpi_os_stall(u32 us) +{ + acpi_osd->stall(us); + return; +} + +acpi_status +acpi_os_read_pci_configuration( acpi_pci_id *pci_id, u32 reg, void *value, u32 width) +{ + return acpi_osd->read_pci_configuration(pci_id, reg, value, width); +} + + +acpi_status +acpi_os_write_pci_configuration( acpi_pci_id *pci_id, u32 reg, NATIVE_UINT value, u32 width) +{ + return acpi_osd->write_pci_configuration(pci_id, reg, value, width); +} + + +#ifdef CONFIG_ACPI_KERNEL_CONFIG_BM_PROFILE +/* + * Let's profile bootmem usage to see how much we consume. J.I. + */ +static unsigned long bm_alloc_size __initdata = 0; +static unsigned long bm_alloc_size_max __initdata = 0; +static unsigned long bm_alloc_count_max __initdata = 0; +static unsigned long bm_free_count_max __initdata = 0; + +static void __init +acpi_cf_bm_checkin(void *ptr, u32 size) +{ + bm_alloc_count_max++; + bm_alloc_size += size; + if (bm_alloc_size > bm_alloc_size_max) + bm_alloc_size_max = bm_alloc_size; +}; + +static void __init +acpi_cf_bm_checkout(void *ptr, u32 size) +{ + bm_free_count_max++; + bm_alloc_size -= size; +}; + +static void __init +acpi_cf_bm_statistics( void ) +{ + printk("Acpi cfg:bm_alloc_size_max =%ld bytes\n", bm_alloc_size_max); + printk("Acpi cfg:bm_alloc_count_max=%ld\n", bm_alloc_count_max); + printk("Acpi cfg:bm_free_count_max =%ld\n", bm_free_count_max); +} +#endif + + +static void * __init +acpi_os_allocate_bt(u32 size) +{ + void *ptr; + + size += sizeof(unsigned long); + ptr = alloc_bootmem(size); + + if (ptr) { +#ifdef CONFIG_ACPI_KERNEL_CONFIG_BM_PROFILE + acpi_cf_bm_checkin(ptr, size); +#endif + *((unsigned long *)ptr) = (unsigned long)size; + ptr += sizeof(unsigned long); + } + + return ptr; +} + +static void * __init +acpi_os_callocate_bt(u32 size) +{ + void *ptr = acpi_os_allocate_bt(size); + + return ptr; +} + +static void __init +acpi_os_free_bt(void *ptr) +{ + unsigned long size; + + ptr -= sizeof(size); + size = *((unsigned long *)ptr); + +#ifdef CONFIG_ACPI_KERNEL_CONFIG_BM_PROFILE + acpi_cf_bm_checkout(ptr, (unsigned long)size); +#endif + //if (size) + free_bootmem (__pa((unsigned long)ptr), (u32)size); +} + + +static void __init +acpi_os_stall_bt(u32 us) +{ + unsigned long start = ia64_get_itc(); + unsigned long cycles = us*733; /* XXX: 733 or 800 */ + while (ia64_get_itc() - start < cycles) + /* skip */; +} + + +static acpi_status __init +acpi_os_queue_for_execution_bt( + u32 priority, + OSD_EXECUTION_CALLBACK callback, + void *context) +{ + /* + * run callback immediately + */ + (*callback)(context); + return AE_OK; +} + + +static acpi_status __init +acpi_os_read_pci_configuration_bt ( + acpi_pci_id *pci_id, + u32 reg, + void *value, + u32 width) +{ + unsigned int devfn; + s64 status; + u64 lval; + + devfn = PCI_DEVFN(pci_id->device, pci_id->function); + + switch (width) + { + case 8: + status = ia64_sal_pci_config_read(PCI_CONFIG_ADDRESS((pci_id->bus), devfn, reg), 1, &lval); + *(u8*)value = (u8)lval; + break; + case 16: + status = ia64_sal_pci_config_read(PCI_CONFIG_ADDRESS((pci_id->bus), devfn, reg), 2, &lval); + *(u16*)value = (u16)lval; + break; + case 32: + status = ia64_sal_pci_config_read(PCI_CONFIG_ADDRESS((pci_id->bus), devfn, reg), 4, &lval); + *(u32*)value = (u32)lval; + break; + default: + BUG(); + } + + return status; +} + + +static acpi_status __init +acpi_os_write_pci_configuration_bt ( + acpi_pci_id *pci_id, + u32 reg, + NATIVE_UINT value, + u32 width) +{ + unsigned int devfn; + s64 status; + + devfn = PCI_DEVFN(pci_id->device, pci_id->function); + + switch (width) + { + case 8: + status = ia64_sal_pci_config_write(PCI_CONFIG_ADDRESS((pci_id->bus), devfn, reg), 1, value); + break; + case 16: + status = ia64_sal_pci_config_write(PCI_CONFIG_ADDRESS((pci_id->bus), devfn, reg), 2, value); + break; + case 32: + status = ia64_sal_pci_config_write(PCI_CONFIG_ADDRESS((pci_id->bus), devfn, reg), 4, value); + break; + default: + BUG(); + } + + return status; +} diff -urN linux-2.4.10/drivers/acpi/osconf.h linux-2.4.10-lia/drivers/acpi/osconf.h --- linux-2.4.10/drivers/acpi/osconf.h Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/acpi/osconf.h Mon Sep 24 22:01:49 2001 @@ -0,0 +1,57 @@ +/* + * osconf.h - ACPI OS-dependent headers for Kernel Boot/Configuration time + * + * Copyright (C) 2000 Intel Corp. + * Copyright (C) 2000 J.I. Lee + */ + + +struct acpi_osd { + void * (*allocate)(u32 size); + void * (*callocate)(u32 size); + void (*free)(void *ptr); + acpi_status (*queue_for_exec)(u32 pri, OSD_EXECUTION_CALLBACK cb, void *context); + acpi_status (*read_pci_configuration)(acpi_pci_id *pci_id, u32 reg, void *value, u32 width); + acpi_status (*write_pci_configuration)(acpi_pci_id *pci_id, u32 reg, NATIVE_UINT value, u32 width); + void (*stall)(u32 us); +}; + + +#define PCI_CONFIG_ADDRESS(bus, devfn, where) \ + (((u64) bus << 16) | ((u64) (devfn & 0xff) << 8) | (where & 0xff)) + +#define ACPI_CF_PHASE_BOOTTIME 0x00 +#define ACPI_CF_PHASE_RUNTIME 0x01 + + +/* acpi_osd functions */ +void * acpi_os_allocate(u32 size); +void * acpi_os_callocate(u32 size); +void acpi_os_free(void *ptr); +void acpi_os_stall(u32 us); + +acpi_status +acpi_os_read_pci_configuration( acpi_pci_id *pci_id, u32 reg, void *value, u32 width ); + +acpi_status +acpi_os_write_pci_configuration( acpi_pci_id *pci_id, u32 reg, NATIVE_UINT value, u32 width ); + + +/* acpi_osd_rt functions */ +extern void * acpi_os_allocate_rt(u32 size); +extern void * acpi_os_callocate_rt(u32 size); +extern void acpi_os_free_rt(void *ptr); +extern void acpi_os_stall_rt(u32 us); + +extern acpi_status +acpi_os_queue_for_execution_rt( + u32 priority, + OSD_EXECUTION_CALLBACK callback, + void *context + ); + +extern acpi_status +acpi_os_read_pci_configuration_rt( acpi_pci_id *pci_id, u32 reg, void *value, u32 width ); + +extern acpi_status +acpi_os_write_pci_configuration_rt( acpi_pci_id *pci_id, u32 reg, NATIVE_UINT value, u32 width ); diff -urN linux-2.4.10/drivers/acpi/ospm/include/ec.h linux-2.4.10-lia/drivers/acpi/ospm/include/ec.h --- linux-2.4.10/drivers/acpi/ospm/include/ec.h Mon Sep 24 15:06:44 2001 +++ linux-2.4.10-lia/drivers/acpi/ospm/include/ec.h Mon Sep 24 22:03:30 2001 @@ -167,14 +167,14 @@ acpi_status ec_io_read ( EC_CONTEXT *ec, - u32 io_port, + ACPI_IO_ADDRESS io_port, u8 *data, EC_EVENT wait_event); acpi_status ec_io_write ( EC_CONTEXT *ec, - u32 io_port, + ACPI_IO_ADDRESS io_port, u8 data, EC_EVENT wait_event); diff -urN linux-2.4.10/drivers/acpi/ospm/system/sm_osl.c linux-2.4.10-lia/drivers/acpi/ospm/system/sm_osl.c --- linux-2.4.10/drivers/acpi/ospm/system/sm_osl.c Mon Sep 24 15:06:44 2001 +++ linux-2.4.10-lia/drivers/acpi/ospm/system/sm_osl.c Mon Sep 24 22:03:42 2001 @@ -33,7 +33,9 @@ #include #include #include +#ifndef __ia64__ #include +#endif #include #include @@ -278,6 +280,7 @@ int *eof, void *context) { +#ifndef _IA64 char *str = page; int len; u32 sec,min,hr; @@ -351,6 +354,9 @@ *start = page; return len; +#else + return 0; +#endif } static int get_date_field(char **str, u32 *value) @@ -381,6 +387,7 @@ unsigned long count, void *data) { +#ifndef _IA64 char buf[30]; char *str = buf; u32 sec,min,hr; @@ -520,6 +527,9 @@ error = 0; out: return error ? error : count; +#else + return 0; +#endif } static int diff -urN linux-2.4.10/drivers/char/Config.in linux-2.4.10-lia/drivers/char/Config.in --- linux-2.4.10/drivers/char/Config.in Mon Sep 24 15:06:56 2001 +++ linux-2.4.10-lia/drivers/char/Config.in Mon Sep 24 15:22:27 2001 @@ -206,6 +206,9 @@ dep_tristate '/dev/agpgart (AGP Support)' CONFIG_AGP $CONFIG_DRM_AGP if [ "$CONFIG_AGP" != "n" ]; then bool ' Intel 440LX/BX/GX and I815/I840/I850 support' CONFIG_AGP_INTEL + if [ "$CONFIG_IA64" != "n" ]; then + bool ' Intel 460GX support' CONFIG_AGP_I460 + fi bool ' Intel I810/I815 (on-board) support' CONFIG_AGP_I810 bool ' VIA chipset support' CONFIG_AGP_VIA bool ' AMD Irongate, 761, and 762 support' CONFIG_AGP_AMD @@ -214,7 +217,17 @@ bool ' Serverworks LE/HE support' CONFIG_AGP_SWORKS fi -source drivers/char/drm/Config.in +bool 'Direct Rendering Manager (XFree86 DRI support)' CONFIG_DRM + +if [ "$CONFIG_DRM" = "y" ]; then + bool ' Build drivers for new (XFree 4.1) DRM' CONFIG_DRM_NEW + if [ "$CONFIG_DRM_NEW" = "y" ]; then + source drivers/char/drm/Config.in + else + define_bool CONFIG_DRM_OLD y + source drivers/char/drm-4.0/Config.in + fi +fi if [ "$CONFIG_HOTPLUG" = "y" -a "$CONFIG_PCMCIA" != "n" ]; then source drivers/char/pcmcia/Config.in diff -urN linux-2.4.10/drivers/char/Makefile linux-2.4.10-lia/drivers/char/Makefile --- linux-2.4.10/drivers/char/Makefile Mon Sep 24 15:06:56 2001 +++ linux-2.4.10-lia/drivers/char/Makefile Mon Sep 24 21:30:41 2001 @@ -25,7 +25,7 @@ misc.o pty.o random.o selection.o serial.o \ sonypi.o tty_io.o tty_ioctl.o -mod-subdirs := joystick ftape drm pcmcia +mod-subdirs := joystick ftape drm pcmcia drm-4.0 list-multi := @@ -138,6 +138,7 @@ obj-$(CONFIG_MAGIC_SYSRQ) += sysrq.o obj-$(CONFIG_ATARI_DSP56K) += dsp56k.o +obj-$(CONFIG_SIM_SERIAL) += simserial.o obj-$(CONFIG_ROCKETPORT) += rocket.o obj-$(CONFIG_MOXA_SMARTIO) += mxser.o obj-$(CONFIG_MOXA_INTELLIO) += moxa.o @@ -198,7 +199,8 @@ obj-$(CONFIG_QIC02_TAPE) += tpqic02.o subdir-$(CONFIG_FTAPE) += ftape -subdir-$(CONFIG_DRM) += drm +subdir-$(CONFIG_DRM_NEW) += drm +subdir-$(CONFIG_DRM_OLD) += drm-4.0 subdir-$(CONFIG_PCMCIA) += pcmcia subdir-$(CONFIG_AGP) += agp diff -urN linux-2.4.10/drivers/char/agp/agp.h linux-2.4.10-lia/drivers/char/agp/agp.h --- linux-2.4.10/drivers/char/agp/agp.h Mon Sep 24 15:06:56 2001 +++ linux-2.4.10-lia/drivers/char/agp/agp.h Mon Sep 24 15:25:54 2001 @@ -84,8 +84,8 @@ void *dev_private_data; struct pci_dev *dev; gatt_mask *masks; - unsigned long *gatt_table; - unsigned long *gatt_table_real; + u32 *gatt_table; + u32 *gatt_table_real; unsigned long scratch_page; unsigned long gart_bus_addr; unsigned long gatt_bus_addr; @@ -111,6 +111,7 @@ void (*cleanup) (void); void (*tlb_flush) (agp_memory *); unsigned long (*mask_memory) (unsigned long, int); + unsigned long (*unmask_memory) (unsigned long); void (*cache_flush) (void); int (*create_gatt_table) (void); int (*free_gatt_table) (void); @@ -146,6 +147,10 @@ #define A_IDXFIX() (A_SIZE_FIX(agp_bridge.aperture_sizes) + i) #define MAXKEY (4096 * 32) +#ifndef max +#define max(a,b) (((a)>(b))?(a):(b)) +#endif + #define AGPGART_MODULE_NAME "agpgart" #define PFX AGPGART_MODULE_NAME ": " @@ -199,6 +204,9 @@ #ifndef PCI_DEVICE_ID_INTEL_82443GX_1 #define PCI_DEVICE_ID_INTEL_82443GX_1 0x71a1 #endif +#ifndef PCI_DEVICE_ID_INTEL_460GX +#define PCI_DEVICE_ID_INTEL_460GX 0x84ea +#endif #ifndef PCI_DEVICE_ID_AMD_IRONGATE_0 #define PCI_DEVICE_ID_AMD_IRONGATE_0 0x7006 #endif @@ -240,6 +248,15 @@ #define INTEL_AGPCTRL 0xb0 #define INTEL_NBXCFG 0x50 #define INTEL_ERRSTS 0x91 + +/* Intel 460GX Registers */ +#define INTEL_I460_APBASE 0x10 +#define INTEL_I460_BAPBASE 0x98 +#define INTEL_I460_GXBCTL 0xa0 +#define INTEL_I460_AGPSIZ 0xa2 +#define INTEL_I460_ATTBASE 0xfe200000 +#define INTEL_I460_GATT_VALID (1UL << 24) +#define INTEL_I460_GATT_COHERENT (1UL << 25) /* intel i840 registers */ #define INTEL_I840_MCHCFG 0x50 diff -urN linux-2.4.10/drivers/char/agp/agpgart_be.c linux-2.4.10-lia/drivers/char/agp/agpgart_be.c --- linux-2.4.10/drivers/char/agp/agpgart_be.c Mon Sep 24 15:06:56 2001 +++ linux-2.4.10-lia/drivers/char/agp/agpgart_be.c Mon Sep 24 16:11:04 2001 @@ -22,6 +22,7 @@ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * + * 460GX support by Chris Ahna */ #include #include @@ -43,6 +44,9 @@ #include #include #include +#include +#include +#include #include #include "agp.h" @@ -60,7 +64,7 @@ EXPORT_SYMBOL(agp_backend_release); static void flush_cache(void); - + static struct agp_bridge_data agp_bridge; static int agp_try_unsupported __initdata = 0; @@ -205,19 +209,56 @@ agp_bridge.free_by_type(curr); return; } - if (curr->page_count != 0) { - for (i = 0; i < curr->page_count; i++) { - curr->memory[i] &= ~(0x00000fff); - agp_bridge.agp_destroy_page((unsigned long) - phys_to_virt(curr->memory[i])); + if(agp_bridge.cant_use_aperture == 0) { + if (curr->page_count != 0) { + for (i = 0; i < curr->page_count; i++) { + curr->memory[i] = agp_bridge.unmask_memory( + curr->memory[i]); + agp_bridge.agp_destroy_page((unsigned long) + phys_to_virt(curr->memory[i])); + } } + } else { + vfree(curr->vmptr); } + agp_free_key(curr->key); vfree(curr->memory); kfree(curr); MOD_DEC_USE_COUNT; } +#define IN_VMALLOC(_x) (((_x) >= VMALLOC_START) && ((_x) < VMALLOC_END)) + +/* + * Look up and return the pte corresponding to addr. We only do this for + * agp_ioremap'ed addresses. + */ +static pte_t * agp_lookup_pte(unsigned long addr) { + + pgd_t *dir; + pmd_t *pmd; + pte_t *pte; + + if(!IN_VMALLOC(addr)) + return NULL; + + dir = pgd_offset_k(addr); + pmd = pmd_offset(dir, addr); + + if(pmd) { + pte = pte_offset(pmd, addr); + + if(pte) { + return pte; + } else { + return NULL; + } + } else { + return NULL; + } +} + #define ENTRIES_PER_PAGE (PAGE_SIZE / sizeof(unsigned long)) agp_memory *agp_allocate_memory(size_t page_count, u32 type) @@ -247,24 +288,60 @@ scratch_pages = (page_count + ENTRIES_PER_PAGE - 1) / ENTRIES_PER_PAGE; new = agp_create_memory(scratch_pages); - if (new == NULL) { MOD_DEC_USE_COUNT; return NULL; } - for (i = 0; i < page_count; i++) { - new->memory[i] = agp_bridge.agp_alloc_page(); - if (new->memory[i] == 0) { - /* Free this structure */ - agp_free_memory(new); + if(agp_bridge.cant_use_aperture == 0) { + for (i = 0; i < page_count; i++) { + new->memory[i] = agp_bridge.agp_alloc_page(); + + if (new->memory[i] == 0) { + /* Free this structure */ + agp_free_memory(new); + return NULL; + } + new->memory[i] = + agp_bridge.mask_memory( + virt_to_phys((void *) new->memory[i]), + type); + new->page_count++; + } + } else { + void *vmblock; + unsigned long vaddr, paddr; + pte_t *pte; + + vmblock = __vmalloc(page_count << PAGE_SHIFT, GFP_KERNEL, +#ifdef __ia64__ + pgprot_writecombine(PAGE_KERNEL)); +#else + PAGE_KERNEL); +#endif + if(vmblock == NULL) { + MOD_DEC_USE_COUNT; return NULL; } - new->memory[i] = - agp_bridge.mask_memory( - virt_to_phys((void *) new->memory[i]), - type); - new->page_count++; + + new->vmptr = vmblock; + vaddr = (unsigned long) vmblock; + + for(i = 0; i < page_count; i++, vaddr += PAGE_SIZE) { + pte = agp_lookup_pte(vaddr); + if(pte == NULL) { + MOD_DEC_USE_COUNT; + return NULL; + } +#ifdef __ia64__ + paddr = pte_val(*pte) & _PFN_MASK; +#else + paddr = pte_val(*pte) & PAGE_MASK; +#endif + new->memory[i] = agp_bridge.mask_memory(paddr, type); + } + + new->page_count = page_count; } return new; @@ -353,12 +430,13 @@ curr->is_flushed = TRUE; } ret_val = agp_bridge.insert_memory(curr, pg_start, curr->type); - + if (ret_val != 0) { return ret_val; } curr->is_bound = TRUE; curr->pg_start = pg_start; + return 0; } @@ -377,6 +455,7 @@ if (ret_val != 0) { return ret_val; } + curr->is_bound = FALSE; curr->pg_start = 0; return 0; @@ -387,9 +466,9 @@ /* * Driver routines - start * Currently this module supports the following chipsets: - * i810, i815, 440lx, 440bx, 440gx, i840, i850, via vp3, via mvp3, - * via kx133, via kt133, amd irongate, amd 761, amd 762, ALi M1541, - * and generic support for the SiS chipsets. + * i810, 440lx, 440bx, 440gx, 460gx, i840, i850, via vp3, via mvp3, via kx133, + * via kt133, amd irongate, ALi M1541, and generic support for the SiS + * chipsets. */ /* Generic Agp routines - Start */ @@ -614,7 +693,7 @@ for (page = virt_to_page(table); page <= virt_to_page(table_end); page++) set_bit(PG_reserved, &page->flags); - agp_bridge.gatt_table_real = (unsigned long *) table; + agp_bridge.gatt_table_real = (u32 *) table; CACHE_FLUSH(); agp_bridge.gatt_table = ioremap_nocache(virt_to_phys(table), (PAGE_SIZE * (1 << page_order))); @@ -832,6 +911,11 @@ agp_bridge.agp_enable(mode); } +static unsigned long agp_generic_unmask_memory(unsigned long addr) +{ + return addr & ~(0x00000fff); +} + /* End - Generic Agp routines */ #ifdef CONFIG_AGP_I810 @@ -1096,6 +1180,7 @@ agp_bridge.cleanup = intel_i810_cleanup; agp_bridge.tlb_flush = intel_i810_tlbflush; agp_bridge.mask_memory = intel_i810_mask_memory; + agp_bridge.unmask_memory = agp_generic_unmask_memory; agp_bridge.agp_enable = intel_i810_agp_enable; agp_bridge.cache_flush = global_cache_flush; agp_bridge.create_gatt_table = agp_generic_create_gatt_table; @@ -1115,6 +1200,633 @@ #endif /* CONFIG_AGP_I810 */ +#ifdef CONFIG_AGP_I460 + +/* BIOS configures the chipset so that one of two apbase registers are used */ +static u8 intel_i460_dynamic_apbase = 0x10; + +/* 460 supports multiple GART page sizes, so GART pageshift is dynamic */ +static u8 intel_i460_pageshift = 12; + +/* Keep track of which is larger, chipset or kernel page size. */ +static u32 intel_i460_cpk = 1; + +/* Structure for tracking partial use of 4MB GART pages */ +static u32 **i460_pg_detail = NULL; +static u32 *i460_pg_count = NULL; + +#define I460_CPAGES_PER_KPAGE (PAGE_SIZE >> intel_i460_pageshift) +#define I460_KPAGES_PER_CPAGE ((1 << intel_i460_pageshift) >> PAGE_SHIFT) + +#define I460_SRAM_IO_DISABLE (1 << 4) +#define I460_BAPBASE_ENABLE (1 << 3) +#define I460_AGPSIZ_MASK 0x7 +#define I460_4M_PS (1 << 1) + +#define log2(x) ffz(~(x)) + +static int intel_i460_fetch_size(void) +{ + int i; + u8 temp; + aper_size_info_8 *values; + + /* Determine the GART page size */ + pci_read_config_byte(agp_bridge.dev, INTEL_I460_GXBCTL, &temp); + intel_i460_pageshift = (temp & I460_4M_PS) ? 22 : 12; + + values = A_SIZE_8(agp_bridge.aperture_sizes); + + pci_read_config_byte(agp_bridge.dev, INTEL_I460_AGPSIZ, &temp); + + /* Exit now if the IO drivers for the GART SRAMS are turned off */ + if(temp & I460_SRAM_IO_DISABLE) { + printk("[agpgart] GART SRAMS disabled on 460GX chipset\n"); + printk("[agpgart] AGPGART operation not possible\n"); + return 0; + } + + /* Make sure we don't try to create an 2 ^ 23 entry GATT */ + if((intel_i460_pageshift == 0) && ((temp & I460_AGPSIZ_MASK) == 4)) { + printk("[agpgart] We can't have a 32GB aperture with 4KB" + " GART pages\n"); + return 0; + } + + /* Determine the proper APBASE register */ + if(temp & I460_BAPBASE_ENABLE) + intel_i460_dynamic_apbase = INTEL_I460_BAPBASE; + else intel_i460_dynamic_apbase = INTEL_I460_APBASE; + + for (i = 0; i < agp_bridge.num_aperture_sizes; i++) { + + /* + * Dynamically calculate the proper num_entries and page_order + * values for the define aperture sizes. Take care not to + * shift off the end of values[i].size. + */ + values[i].num_entries = (values[i].size << 8) >> + (intel_i460_pageshift - 12); + values[i].page_order = log2((sizeof(u32)*values[i].num_entries) + >> PAGE_SHIFT); + } + + for (i = 0; i < agp_bridge.num_aperture_sizes; i++) { + /* Neglect control bits when matching up size_value */ + if ((temp & I460_AGPSIZ_MASK) == values[i].size_value) { + agp_bridge.previous_size = + agp_bridge.current_size = (void *) (values + i); + agp_bridge.aperture_size_idx = i; + return values[i].size; + } + } + + return 0; +} + +/* There isn't anything to do here since 460 has no GART TLB. */ +static void intel_i460_tlb_flush(agp_memory * mem) +{ + return; +} + +/* + * This utility function is needed to prevent corruption of the control bits + * which are stored along with the aperture size in 460's AGPSIZ register + */ +static void intel_i460_write_agpsiz(u8 size_value) +{ + u8 temp; + + pci_read_config_byte(agp_bridge.dev, INTEL_I460_AGPSIZ, &temp); + pci_write_config_byte(agp_bridge.dev, INTEL_I460_AGPSIZ, + ((temp & ~I460_AGPSIZ_MASK) | size_value)); +} + +static void intel_i460_cleanup(void) +{ + aper_size_info_8 *previous_size; + + previous_size = A_SIZE_8(agp_bridge.previous_size); + intel_i460_write_agpsiz(previous_size->size_value); + + if(intel_i460_cpk == 0) + { + vfree(i460_pg_detail); + vfree(i460_pg_count); + } +} + + +/* Control bits for Out-Of-GART coherency and Burst Write Combining */ +#define I460_GXBCTL_OOG (1UL << 0) +#define I460_GXBCTL_BWC (1UL << 2) + +static int intel_i460_configure(void) +{ + union { + u32 small[2]; + u64 large; + } temp; + u8 scratch; + int i; + + aper_size_info_8 *current_size; + + temp.large = 0; + + current_size = A_SIZE_8(agp_bridge.current_size); + intel_i460_write_agpsiz(current_size->size_value); + + /* + * Do the necessary rigmarole to read all eight bytes of APBASE. + * This has to be done since the AGP aperture can be above 4GB on + * 460 based systems. + */ + pci_read_config_dword(agp_bridge.dev, intel_i460_dynamic_apbase, + &(temp.small[0])); + pci_read_config_dword(agp_bridge.dev, intel_i460_dynamic_apbase + 4, + &(temp.small[1])); + + /* Clear BAR control bits */ + agp_bridge.gart_bus_addr = temp.large & ~((1UL << 3) - 1); + + pci_read_config_byte(agp_bridge.dev, INTEL_I460_GXBCTL, &scratch); + pci_write_config_byte(agp_bridge.dev, INTEL_I460_GXBCTL, + (scratch & 0x02) | I460_GXBCTL_OOG | I460_GXBCTL_BWC); + + /* + * Initialize partial allocation trackers if a GART page is bigger than + * a kernel page. + */ + if(I460_CPAGES_PER_KPAGE >= 1) { + intel_i460_cpk = 1; + } else { + intel_i460_cpk = 0; + + i460_pg_detail = (void *) vmalloc(sizeof(*i460_pg_detail) * + current_size->num_entries); + i460_pg_count = (void *) vmalloc(sizeof(*i460_pg_count) * + current_size->num_entries); + + for (i = 0; i < current_size->num_entries; i++) { + i460_pg_count[i] = 0; + i460_pg_detail[i] = NULL; + } + } + + return 0; +} + +static int intel_i460_create_gatt_table(void) { + + char *table; + int i; + int page_order; + int num_entries; + void *temp; + unsigned int read_back; + + /* + * Load up the fixed address of the GART SRAMS which hold our + * GATT table. + */ + table = (char *) __va(INTEL_I460_ATTBASE); + + temp = agp_bridge.current_size; + page_order = A_SIZE_8(temp)->page_order; + num_entries = A_SIZE_8(temp)->num_entries; + + agp_bridge.gatt_table_real = (u32 *) table; + agp_bridge.gatt_table = ioremap_nocache(virt_to_phys(table), + (PAGE_SIZE * (1 << page_order))); + agp_bridge.gatt_bus_addr = virt_to_phys(agp_bridge.gatt_table_real); + + for (i = 0; i < num_entries; i++) { + agp_bridge.gatt_table[i] = 0; + } + + /* + * The 460 spec says we have to read the last location written to + * make sure that all writes have taken effect + */ + read_back = agp_bridge.gatt_table[i - 1]; + + return 0; +} + +static int intel_i460_free_gatt_table(void) +{ + int num_entries; + int i; + void *temp; + unsigned int read_back; + + temp = agp_bridge.current_size; + + num_entries = A_SIZE_8(temp)->num_entries; + + for (i = 0; i < num_entries; i++) { + agp_bridge.gatt_table[i] = 0; + } + + /* + * The 460 spec says we have to read the last location written to + * make sure that all writes have taken effect + */ + read_back = agp_bridge.gatt_table[i - 1]; + + iounmap(agp_bridge.gatt_table); + + return 0; +} + +/* These functions are called when PAGE_SIZE exceeds the GART page size */ + +static int intel_i460_insert_memory_cpk(agp_memory * mem, + off_t pg_start, int type) +{ + int i, j, k, num_entries; + void *temp; + unsigned int hold; + unsigned int read_back; + + /* + * The rest of the kernel will compute page offsets in terms of + * PAGE_SIZE. + */ + pg_start = I460_CPAGES_PER_KPAGE * pg_start; + + temp = agp_bridge.current_size; + num_entries = A_SIZE_8(temp)->num_entries; + + if((pg_start + I460_CPAGES_PER_KPAGE * mem->page_count) > num_entries) { + printk("[agpgart] Looks like we're out of AGP memory\n"); + return -EINVAL; + } + + j = pg_start; + while (j < (pg_start + I460_CPAGES_PER_KPAGE * mem->page_count)) { + if (!PGE_EMPTY(agp_bridge.gatt_table[j])) { + return -EBUSY; + } + j++; + } + + if (mem->is_flushed == FALSE) { + CACHE_FLUSH(); + mem->is_flushed = TRUE; + } + + for (i = 0, j = pg_start; i < mem->page_count; i++) { + + hold = (unsigned int) (mem->memory[i]); + + for (k = 0; k < I460_CPAGES_PER_KPAGE; k++, j++, hold++) + agp_bridge.gatt_table[j] = hold; + } + + /* + * The 460 spec says we have to read the last location written to + * make sure that all writes have taken effect + */ + read_back = agp_bridge.gatt_table[j - 1]; + + return 0; +} + +static int intel_i460_remove_memory_cpk(agp_memory * mem, off_t pg_start, + int type) +{ + int i; + unsigned int read_back; + + pg_start = I460_CPAGES_PER_KPAGE * pg_start; + + for (i = pg_start; i < (pg_start + I460_CPAGES_PER_KPAGE * + mem->page_count); i++) + agp_bridge.gatt_table[i] = 0; + + /* + * The 460 spec says we have to read the last location written to + * make sure that all writes have taken effect + */ + read_back = agp_bridge.gatt_table[i - 1]; + + return 0; +} + +/* + * These functions are called when the GART page size exceeds PAGE_SIZE. + * + * This situation is interesting since AGP memory allocations that are + * smaller than a single GART page are possible. The structures i460_pg_count + * and i460_pg_detail track partial allocation of the large GART pages to + * work around this issue. + * + * i460_pg_count[pg_num] tracks the number of kernel pages in use within + * GART page pg_num. i460_pg_detail[pg_num] is an array containing a + * psuedo-GART entry for each of the aforementioned kernel pages. The whole + * of i460_pg_detail is equivalent to a giant GATT with page size equal to + * that of the kernel. + */ + +static void *intel_i460_alloc_large_page(int pg_num) +{ + int i; + void *bp, *bp_end; + struct page *page; + + i460_pg_detail[pg_num] = (void *) vmalloc(sizeof(u32) * + I460_KPAGES_PER_CPAGE); + if(i460_pg_detail[pg_num] == NULL) { + printk("[agpgart] Out of memory, we're in trouble...\n"); + return NULL; + } + + for(i = 0; i < I460_KPAGES_PER_CPAGE; i++) + i460_pg_detail[pg_num][i] = 0; + + bp = (void *) __get_free_pages(GFP_KERNEL, + intel_i460_pageshift - PAGE_SHIFT); + if(bp == NULL) { + printk("[agpgart] Couldn't alloc 4M GART page...\n"); + return NULL; + } + + bp_end = bp + ((PAGE_SIZE * + (1 << (intel_i460_pageshift - PAGE_SHIFT))) - 1); + + for (page = virt_to_page(bp); page <= virt_to_page(bp_end); page++) + { + atomic_inc(&page->count); + set_bit(PG_locked, &page->flags); + atomic_inc(&agp_bridge.current_memory_agp); + } + + return bp; +} + +static void intel_i460_free_large_page(int pg_num, unsigned long addr) +{ + struct page *page; + void *bp, *bp_end; + + bp = (void *) __va(addr); + bp_end = bp + (PAGE_SIZE * + (1 << (intel_i460_pageshift - PAGE_SHIFT))); + + vfree(i460_pg_detail[pg_num]); + i460_pg_detail[pg_num] = NULL; + + for (page = virt_to_page(bp); page < virt_to_page(bp_end); page++) + { + atomic_dec(&page->count); + clear_bit(PG_locked, &page->flags); + wake_up(&page->wait); + atomic_dec(&agp_bridge.current_memory_agp); + } + + free_pages((unsigned long) bp, intel_i460_pageshift - PAGE_SHIFT); +} + +static int intel_i460_insert_memory_kpc(agp_memory * mem, + off_t pg_start, int type) +{ + int i, pg, start_pg, end_pg, start_offset, end_offset, idx; + int num_entries; + void *temp; + unsigned int read_back; + + temp = agp_bridge.current_size; + num_entries = A_SIZE_8(temp)->num_entries; + + /* Figure out what pg_start means in terms of our large GART pages */ + start_pg = pg_start / I460_KPAGES_PER_CPAGE; + start_offset = pg_start % I460_KPAGES_PER_CPAGE; + end_pg = (pg_start + mem->page_count - 1) / + I460_KPAGES_PER_CPAGE; + end_offset = (pg_start + mem->page_count - 1) % + I460_KPAGES_PER_CPAGE; + + if(end_pg > num_entries) + { + printk("[agpgart] Looks like we're out of AGP memory\n"); + return -EINVAL; + } + + /* Check if the requested region of the aperture is free */ + for(pg = start_pg; pg <= end_pg; pg++) + { + /* Allocate new GART pages if necessary */ + if(i460_pg_detail[pg] == NULL) { + temp = intel_i460_alloc_large_page(pg); + if(temp == NULL) + return -ENOMEM; + agp_bridge.gatt_table[pg] = agp_bridge.mask_memory( + (unsigned long) temp, 0); + read_back = agp_bridge.gatt_table[pg]; + } + + for(idx = ((pg == start_pg) ? start_offset : 0); + idx < ((pg == end_pg) ? (end_offset + 1) + : I460_KPAGES_PER_CPAGE); + idx++) + { + if(i460_pg_detail[pg][idx] != 0) + return -EBUSY; + } + } + + if (mem->is_flushed == FALSE) { + CACHE_FLUSH(); + mem->is_flushed = TRUE; + } + + for(pg = start_pg, i = 0; pg <= end_pg; pg++) + { + for(idx = ((pg == start_pg) ? start_offset : 0); + idx < ((pg == end_pg) ? (end_offset + 1) + : I460_KPAGES_PER_CPAGE); + idx++, i++) + { + i460_pg_detail[pg][idx] = agp_bridge.gatt_table[pg] + + ((idx * PAGE_SIZE) >> 12); + i460_pg_count[pg]++; + + /* Finally we fill in mem->memory... */ + mem->memory[i] = ((unsigned long) (0xffffff & + i460_pg_detail[pg][idx])) << 12; + } + } + + return 0; +} + +static int intel_i460_remove_memory_kpc(agp_memory * mem, + off_t pg_start, int type) +{ + int i, pg, start_pg, end_pg, start_offset, end_offset, idx; + int num_entries; + void *temp; + unsigned int read_back; + unsigned long addr; + + temp = agp_bridge.current_size; + num_entries = A_SIZE_8(temp)->num_entries; + + /* Figure out what pg_start means in terms of our large GART pages */ + start_pg = pg_start / I460_KPAGES_PER_CPAGE; + start_offset = pg_start % I460_KPAGES_PER_CPAGE; + end_pg = (pg_start + mem->page_count - 1) / + I460_KPAGES_PER_CPAGE; + end_offset = (pg_start + mem->page_count - 1) % + I460_KPAGES_PER_CPAGE; + + for(i = 0, pg = start_pg; pg <= end_pg; pg++) + { + for(idx = ((pg == start_pg) ? start_offset : 0); + idx < ((pg == end_pg) ? (end_offset + 1) + : I460_KPAGES_PER_CPAGE); + idx++, i++) + { + mem->memory[i] = 0; + i460_pg_detail[pg][idx] = 0; + i460_pg_count[pg]--; + } + + /* Free GART pages if they are unused */ + if(i460_pg_count[pg] == 0) { + addr = (0xffffffUL & (unsigned long) + (agp_bridge.gatt_table[pg])) << 12; + + agp_bridge.gatt_table[pg] = 0; + read_back = agp_bridge.gatt_table[pg]; + + intel_i460_free_large_page(pg, addr); + } + } + + return 0; +} + +/* Dummy routines to call the approriate {cpk,kpc} function */ + +static int intel_i460_insert_memory(agp_memory * mem, + off_t pg_start, int type) +{ + if(intel_i460_cpk) + return intel_i460_insert_memory_cpk(mem, pg_start, type); + else + return intel_i460_insert_memory_kpc(mem, pg_start, type); +} + +static int intel_i460_remove_memory(agp_memory * mem, + off_t pg_start, int type) +{ + if(intel_i460_cpk) + return intel_i460_remove_memory_cpk(mem, pg_start, type); + else + return intel_i460_remove_memory_kpc(mem, pg_start, type); +} + +/* + * If the kernel page size is smaller that the chipset page size, we don't + * want to allocate memory until we know where it is to be bound in the + * aperture (a multi-kernel-page alloc might fit inside of an already + * allocated GART page). Consequently, don't allocate or free anything + * if i460_cpk (meaning chipset pages per kernel page) isn't set. + * + * Let's just hope nobody counts on the allocated AGP memory being there + * before bind time (I don't think current drivers do)... + */ +static unsigned long intel_i460_alloc_page(void) +{ + if(intel_i460_cpk) + return agp_generic_alloc_page(); + + /* Returning NULL would cause problems */ + return ((unsigned long) ~0UL); +} + +static void intel_i460_destroy_page(unsigned long page) +{ + if(intel_i460_cpk) + agp_generic_destroy_page(page); +} + +static gatt_mask intel_i460_masks[] = +{ + { + INTEL_I460_GATT_VALID, + 0 + } +}; + +static unsigned long intel_i460_mask_memory(unsigned long addr, int type) +{ + /* Make sure the returned address is a valid GATT entry */ + return (agp_bridge.masks[0].mask | (((addr & + ~((1 << intel_i460_pageshift) - 1)) & 0xffffff000) >> 12)); +} + +static unsigned long intel_i460_unmask_memory(unsigned long addr) +{ + /* Turn a GATT entry into a physical address */ + return ((addr & 0xffffff) << 12); +} + +static aper_size_info_8 intel_i460_sizes[3] = +{ + /* + * The 32GB aperture is only available with a 4M GART page size. + * Due to the dynamic GART page size, we can't figure out page_order + * or num_entries until runtime. + */ + {32768, 0, 0, 4}, + {1024, 0, 0, 2}, + {256, 0, 0, 1} +}; + +static int __init intel_i460_setup (struct pci_dev *pdev) +{ + + agp_bridge.masks = intel_i460_masks; + agp_bridge.num_of_masks = 1; + agp_bridge.aperture_sizes = (void *) intel_i460_sizes; + agp_bridge.size_type = U8_APER_SIZE; + agp_bridge.num_aperture_sizes = 3; + agp_bridge.dev_private_data = NULL; + agp_bridge.needs_scratch_page = FALSE; + agp_bridge.configure = intel_i460_configure; + agp_bridge.fetch_size = intel_i460_fetch_size; + agp_bridge.cleanup = intel_i460_cleanup; + agp_bridge.tlb_flush = intel_i460_tlb_flush; + agp_bridge.mask_memory = intel_i460_mask_memory; + agp_bridge.unmask_memory = intel_i460_unmask_memory; + agp_bridge.agp_enable = agp_generic_agp_enable; + agp_bridge.cache_flush = global_cache_flush; + agp_bridge.create_gatt_table = intel_i460_create_gatt_table; + agp_bridge.free_gatt_table = intel_i460_free_gatt_table; + agp_bridge.insert_memory = intel_i460_insert_memory; + agp_bridge.remove_memory = intel_i460_remove_memory; + agp_bridge.alloc_by_type = agp_generic_alloc_by_type; + agp_bridge.free_by_type = agp_generic_free_by_type; + agp_bridge.agp_alloc_page = intel_i460_alloc_page; + agp_bridge.agp_destroy_page = intel_i460_destroy_page; +#if 0 + agp_bridge.suspend = ??; + agp_bridge.resume = ??; +#endif + agp_bridge.cant_use_aperture = 1; + + return 0; + + (void) pdev; /* unused */ +} + +#endif /* CONFIG_AGP_I460 */ + #ifdef CONFIG_AGP_INTEL static int intel_fetch_size(void) @@ -1295,6 +2007,7 @@ agp_bridge.cleanup = intel_cleanup; agp_bridge.tlb_flush = intel_tlbflush; agp_bridge.mask_memory = intel_mask_memory; + agp_bridge.unmask_memory = agp_generic_unmask_memory; agp_bridge.agp_enable = agp_generic_agp_enable; agp_bridge.cache_flush = global_cache_flush; agp_bridge.create_gatt_table = agp_generic_create_gatt_table; @@ -1328,6 +2041,7 @@ agp_bridge.cleanup = intel_cleanup; agp_bridge.tlb_flush = intel_tlbflush; agp_bridge.mask_memory = intel_mask_memory; + agp_bridge.unmask_memory = agp_generic_unmask_memory; agp_bridge.agp_enable = agp_generic_agp_enable; agp_bridge.cache_flush = global_cache_flush; agp_bridge.create_gatt_table = agp_generic_create_gatt_table; @@ -1361,6 +2075,7 @@ agp_bridge.cleanup = intel_cleanup; agp_bridge.tlb_flush = intel_tlbflush; agp_bridge.mask_memory = intel_mask_memory; + agp_bridge.unmask_memory = agp_generic_unmask_memory; agp_bridge.agp_enable = agp_generic_agp_enable; agp_bridge.cache_flush = global_cache_flush; agp_bridge.create_gatt_table = agp_generic_create_gatt_table; @@ -1481,6 +2196,7 @@ agp_bridge.cleanup = via_cleanup; agp_bridge.tlb_flush = via_tlbflush; agp_bridge.mask_memory = via_mask_memory; + agp_bridge.unmask_memory = agp_generic_unmask_memory; agp_bridge.agp_enable = agp_generic_agp_enable; agp_bridge.cache_flush = global_cache_flush; agp_bridge.create_gatt_table = agp_generic_create_gatt_table; @@ -1595,6 +2311,7 @@ agp_bridge.cleanup = sis_cleanup; agp_bridge.tlb_flush = sis_tlbflush; agp_bridge.mask_memory = sis_mask_memory; + agp_bridge.unmask_memory = agp_generic_unmask_memory; agp_bridge.agp_enable = agp_generic_agp_enable; agp_bridge.cache_flush = global_cache_flush; agp_bridge.create_gatt_table = agp_generic_create_gatt_table; @@ -1617,8 +2334,8 @@ #ifdef CONFIG_AGP_AMD typedef struct _amd_page_map { - unsigned long *real; - unsigned long *remapped; + u32 *real; + u32 *remapped; } amd_page_map; static struct _amd_irongate_private { @@ -1631,7 +2348,7 @@ { int i; - page_map->real = (unsigned long *) __get_free_page(GFP_KERNEL); + page_map->real = (u32 *) __get_free_page(GFP_KERNEL); if (page_map->real == NULL) { return -ENOMEM; } @@ -1886,7 +2603,7 @@ off_t pg_start, int type) { int i, j, num_entries; - unsigned long *cur_gatt; + u32 *cur_gatt; unsigned long addr; num_entries = A_SIZE_LVL2(agp_bridge.current_size)->num_entries; @@ -1926,7 +2643,7 @@ int type) { int i; - unsigned long *cur_gatt; + u32 *cur_gatt; unsigned long addr; if (type != 0 || mem->type != 0) { @@ -1973,6 +2690,7 @@ agp_bridge.cleanup = amd_irongate_cleanup; agp_bridge.tlb_flush = amd_irongate_tlbflush; agp_bridge.mask_memory = amd_irongate_mask_memory; + agp_bridge.unmask_memory = agp_generic_unmask_memory; agp_bridge.agp_enable = agp_generic_agp_enable; agp_bridge.cache_flush = global_cache_flush; agp_bridge.create_gatt_table = amd_create_gatt_table; @@ -2221,6 +2939,7 @@ agp_bridge.cleanup = ali_cleanup; agp_bridge.tlb_flush = ali_tlbflush; agp_bridge.mask_memory = ali_mask_memory; + agp_bridge.unmask_memory = agp_generic_unmask_memory; agp_bridge.agp_enable = agp_generic_agp_enable; agp_bridge.cache_flush = ali_cache_flush; agp_bridge.create_gatt_table = agp_generic_create_gatt_table; @@ -2997,6 +3716,15 @@ #endif /* CONFIG_AGP_INTEL */ +#ifdef CONFIG_AGP_I460 + { PCI_DEVICE_ID_INTEL_460GX, + PCI_VENDOR_ID_INTEL, + INTEL_460GX, + "Intel", + "460GX", + intel_i460_setup }, +#endif + #ifdef CONFIG_AGP_SIS { PCI_DEVICE_ID_SI_630, PCI_VENDOR_ID_SI, @@ -3165,6 +3893,18 @@ return -ENODEV; } +static int agp_check_supported_device(struct pci_dev *dev) { + + int i; + + for(i = 0; i < ARRAY_SIZE (agp_bridge_info); i++) { + if(dev->vendor == agp_bridge_info[i].vendor_id && + dev->device == agp_bridge_info[i].device_id) + return 1; + } + + return 0; +} /* Supported Device Scanning routine */ @@ -3174,8 +3914,14 @@ u8 cap_ptr = 0x00; u32 cap_id, scratch; - if ((dev = pci_find_class(PCI_CLASS_BRIDGE_HOST << 8, NULL)) == NULL) - return -ENODEV; + /* + * Some systems have multiple host bridges (i.e. BigSur), so + * we can't just use the first one we find. + */ + do { + if ((dev = pci_find_class(PCI_CLASS_BRIDGE_HOST << 8, dev)) == NULL) + return -ENODEV; + } while(!agp_check_supported_device(dev)); agp_bridge.dev = dev; diff -urN linux-2.4.10/drivers/char/drm/Config.in linux-2.4.10-lia/drivers/char/drm/Config.in --- linux-2.4.10/drivers/char/drm/Config.in Wed Aug 8 09:42:10 2001 +++ linux-2.4.10-lia/drivers/char/drm/Config.in Wed Aug 15 20:52:09 2001 @@ -5,12 +5,9 @@ # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. # -bool 'Direct Rendering Manager (XFree86 4.1.0 and higher DRI support)' CONFIG_DRM -if [ "$CONFIG_DRM" != "n" ]; then - tristate ' 3dfx Banshee/Voodoo3+' CONFIG_DRM_TDFX - tristate ' 3dlabs GMX 2000' CONFIG_DRM_GAMMA - tristate ' ATI Rage 128' CONFIG_DRM_R128 - dep_tristate ' ATI Radeon' CONFIG_DRM_RADEON $CONFIG_AGP - dep_tristate ' Intel I810' CONFIG_DRM_I810 $CONFIG_AGP - dep_tristate ' Matrox g200/g400' CONFIG_DRM_MGA $CONFIG_AGP -fi +tristate ' 3dfx Banshee/Voodoo3+' CONFIG_DRM_TDFX +tristate ' 3dlabs GMX 2000' CONFIG_DRM_GAMMA +tristate ' ATI Rage 128' CONFIG_DRM_R128 +dep_tristate ' ATI Radeon' CONFIG_DRM_RADEON $CONFIG_AGP +dep_tristate ' Intel I810' CONFIG_DRM_I810 $CONFIG_AGP +dep_tristate ' Matrox g200/g400' CONFIG_DRM_MGA $CONFIG_AGP diff -urN linux-2.4.10/drivers/char/drm/ati_pcigart.h linux-2.4.10-lia/drivers/char/drm/ati_pcigart.h --- linux-2.4.10/drivers/char/drm/ati_pcigart.h Mon Sep 24 15:06:57 2001 +++ linux-2.4.10-lia/drivers/char/drm/ati_pcigart.h Mon Sep 24 15:57:21 2001 @@ -30,7 +30,10 @@ #define __NO_VERSION__ #include "drmP.h" -#if PAGE_SIZE == 8192 +#if PAGE_SIZE == 16384 +# define ATI_PCIGART_TABLE_ORDER 1 +# define ATI_PCIGART_TABLE_PAGES (1 << 1) +#elif PAGE_SIZE == 8192 # define ATI_PCIGART_TABLE_ORDER 2 # define ATI_PCIGART_TABLE_PAGES (1 << 2) #elif PAGE_SIZE == 4096 @@ -103,6 +106,7 @@ goto done; } +#if defined(__alpha__) && (LINUX_VERSION_CODE >= 0x020400) if ( !dev->pdev ) { DRM_ERROR( "PCI device unknown!\n" ); goto done; @@ -117,6 +121,9 @@ address = 0; goto done; } +#else + bus_address = virt_to_bus( (void *)address ); +#endif pci_gart = (u32 *)address; @@ -126,6 +133,7 @@ memset( pci_gart, 0, ATI_MAX_PCIGART_PAGES * sizeof(u32) ); for ( i = 0 ; i < pages ; i++ ) { +#if defined(__alpha__) && (LINUX_VERSION_CODE >= 0x020400) /* we need to support large memory configurations */ entry->busaddr[i] = pci_map_single(dev->pdev, page_address( entry->pagelist[i] ), @@ -139,7 +147,9 @@ goto done; } page_base = (u32) entry->busaddr[i]; - +#else + page_base = page_to_bus( entry->pagelist[i] ); +#endif for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) { *pci_gart++ = cpu_to_le32( page_base ); page_base += ATI_PCIGART_PAGE_SIZE; @@ -164,6 +174,7 @@ unsigned long addr, dma_addr_t bus_addr) { +#if defined(__alpha__) && (LINUX_VERSION_CODE >= 0x020400) drm_sg_mem_t *entry = dev->sg; unsigned long pages; int i; @@ -188,6 +199,8 @@ PAGE_SIZE, PCI_DMA_TODEVICE); } } + +#endif if ( addr ) { DRM(ati_free_pcigart_table)( addr ); diff -urN linux-2.4.10/drivers/char/drm/drmP.h linux-2.4.10-lia/drivers/char/drm/drmP.h --- linux-2.4.10/drivers/char/drm/drmP.h Mon Sep 24 15:06:58 2001 +++ linux-2.4.10-lia/drivers/char/drm/drmP.h Mon Sep 24 16:13:22 2001 @@ -367,12 +367,12 @@ /* Mapping helper macros */ #define DRM_IOREMAP(map) \ - (map)->handle = DRM(ioremap)( (map)->offset, (map)->size ) + (map)->handle = DRM(ioremap)( (map)->offset, (map)->size, (dev) ) #define DRM_IOREMAPFREE(map) \ do { \ if ( (map)->handle && (map)->size ) \ - DRM(ioremapfree)( (map)->handle, (map)->size ); \ + DRM(ioremapfree)( (map)->handle, (map)->size, (dev) ); \ } while (0) #define DRM_FIND_MAP(_map, _o) \ @@ -826,8 +826,8 @@ extern unsigned long DRM(alloc_pages)(int order, int area); extern void DRM(free_pages)(unsigned long address, int order, int area); -extern void *DRM(ioremap)(unsigned long offset, unsigned long size); -extern void DRM(ioremapfree)(void *pt, unsigned long size); +extern void *DRM(ioremap)(unsigned long offset, unsigned long size, drm_device_t *dev); +extern void DRM(ioremapfree)(void *pt, unsigned long size, drm_device_t *dev); #if __REALLY_HAVE_AGP extern agp_memory *DRM(alloc_agp)(int pages, u32 type); diff -urN linux-2.4.10/drivers/char/drm/drm_agpsupport.h linux-2.4.10-lia/drivers/char/drm/drm_agpsupport.h --- linux-2.4.10/drivers/char/drm/drm_agpsupport.h Mon Sep 24 15:06:58 2001 +++ linux-2.4.10-lia/drivers/char/drm/drm_agpsupport.h Mon Sep 24 16:17:25 2001 @@ -275,6 +275,7 @@ case INTEL_I815: head->chipset = "Intel i815"; break; case INTEL_I840: head->chipset = "Intel i840"; break; case INTEL_I850: head->chipset = "Intel i850"; break; + case INTEL_460GX: head->chipset = "Intel 460GX"; break; #endif case VIA_GENERIC: head->chipset = "VIA"; break; diff -urN linux-2.4.10/drivers/char/drm/drm_bufs.h linux-2.4.10-lia/drivers/char/drm/drm_bufs.h --- linux-2.4.10/drivers/char/drm/drm_bufs.h Fri Aug 10 18:14:41 2001 +++ linux-2.4.10-lia/drivers/char/drm/drm_bufs.h Mon Aug 20 18:09:30 2001 @@ -107,7 +107,7 @@ switch ( map->type ) { case _DRM_REGISTERS: case _DRM_FRAME_BUFFER: -#if !defined(__sparc__) && !defined(__alpha__) +#if !defined(__sparc__) && !defined(__alpha__) && !defined(__ia64__) if ( map->offset + map->size < map->offset || map->offset < virt_to_phys(high_memory) ) { DRM(free)( map, sizeof(*map), DRM_MEM_MAPS ); @@ -124,7 +124,7 @@ MTRR_TYPE_WRCOMB, 1 ); } #endif - map->handle = DRM(ioremap)( map->offset, map->size ); + map->handle = DRM(ioremap)( map->offset, map->size, dev ); break; case _DRM_SHM: @@ -249,7 +249,7 @@ DRM_DEBUG("mtrr_del = %d\n", retcode); } #endif - DRM(ioremapfree)(map->handle, map->size); + DRM(ioremapfree)(map->handle, map->size, dev); break; case _DRM_SHM: vfree(map->handle); diff -urN linux-2.4.10/drivers/char/drm/drm_drv.h linux-2.4.10-lia/drivers/char/drm/drm_drv.h --- linux-2.4.10/drivers/char/drm/drm_drv.h Mon Sep 24 15:06:58 2001 +++ linux-2.4.10-lia/drivers/char/drm/drm_drv.h Mon Sep 24 15:25:55 2001 @@ -439,7 +439,7 @@ DRM_DEBUG( "mtrr_del=%d\n", retcode ); } #endif - DRM(ioremapfree)( map->handle, map->size ); + DRM(ioremapfree)( map->handle, map->size, dev ); break; case _DRM_SHM: vfree(map->handle); diff -urN linux-2.4.10/drivers/char/drm/drm_memory.h linux-2.4.10-lia/drivers/char/drm/drm_memory.h --- linux-2.4.10/drivers/char/drm/drm_memory.h Fri Aug 10 18:14:41 2001 +++ linux-2.4.10-lia/drivers/char/drm/drm_memory.h Wed Aug 22 11:05:01 2001 @@ -306,9 +306,14 @@ } } -void *DRM(ioremap)(unsigned long offset, unsigned long size) +void *DRM(ioremap)(unsigned long offset, unsigned long size, drm_device_t *dev) { void *pt; +#if __REALLY_HAVE_AGP + drm_map_t *map = NULL; + drm_map_list_t *r_list; + struct list_head *list; +#endif if (!size) { DRM_MEM_ERROR(DRM_MEM_MAPPINGS, @@ -316,12 +321,51 @@ return NULL; } +#if __REALLY_HAVE_AGP + if(dev->agp->cant_use_aperture == 0) + goto standard_ioremap; + + list_for_each(list, &dev->maplist->head) { + r_list = (drm_map_list_t *)list; + map = r_list->map; + if (!map) continue; + if (map->offset <= offset && + (map->offset + map->size) >= (offset + size)) + break; + } + + if(map && map->type == _DRM_AGP) { + struct drm_agp_mem *agpmem; + + for(agpmem = dev->agp->memory; agpmem; + agpmem = agpmem->next) { + if(agpmem->bound <= offset && + (agpmem->bound + (agpmem->pages + << PAGE_SHIFT)) >= (offset + size)) + break; + } + + if(agpmem == NULL) + goto ioremap_failure; + + pt = agpmem->memory->vmptr + (offset - agpmem->bound); + goto ioremap_success; + } + +standard_ioremap: +#endif if (!(pt = ioremap(offset, size))) { +#if __REALLY_HAVE_AGP +ioremap_failure: +#endif spin_lock(&DRM(mem_lock)); ++DRM(mem_stats)[DRM_MEM_MAPPINGS].fail_count; spin_unlock(&DRM(mem_lock)); return NULL; } +#if __REALLY_HAVE_AGP +ioremap_success: +#endif spin_lock(&DRM(mem_lock)); ++DRM(mem_stats)[DRM_MEM_MAPPINGS].succeed_count; DRM(mem_stats)[DRM_MEM_MAPPINGS].bytes_allocated += size; @@ -329,7 +373,7 @@ return pt; } -void DRM(ioremapfree)(void *pt, unsigned long size) +void DRM(ioremapfree)(void *pt, unsigned long size, drm_device_t *dev) { int alloc_count; int free_count; @@ -337,7 +381,11 @@ if (!pt) DRM_MEM_ERROR(DRM_MEM_MAPPINGS, "Attempt to free NULL pointer\n"); +#if __REALLY_HAVE_AGP + else if(dev->agp->cant_use_aperture == 0) +#else else +#endif iounmap(pt); spin_lock(&DRM(mem_lock)); diff -urN linux-2.4.10/drivers/char/drm/drm_scatter.h linux-2.4.10-lia/drivers/char/drm/drm_scatter.h --- linux-2.4.10/drivers/char/drm/drm_scatter.h Mon Sep 24 15:06:58 2001 +++ linux-2.4.10-lia/drivers/char/drm/drm_scatter.h Mon Sep 24 15:25:55 2001 @@ -47,9 +47,11 @@ vfree( entry->virtual ); +#if defined(__alpha__) && (LINUX_VERSION_CODE >= 0x020400) DRM(free)( entry->busaddr, entry->pages * sizeof(*entry->busaddr), DRM_MEM_PAGES ); +#endif DRM(free)( entry->pagelist, entry->pages * sizeof(*entry->pagelist), DRM_MEM_PAGES ); @@ -97,6 +99,7 @@ return -ENOMEM; } +#if defined(__alpha__) && (LINUX_VERSION_CODE >= 0x020400) entry->busaddr = DRM(alloc)( pages * sizeof(*entry->busaddr), DRM_MEM_PAGES ); if ( !entry->busaddr ) { @@ -109,12 +112,15 @@ return -ENOMEM; } memset( (void *)entry->busaddr, 0, pages * sizeof(*entry->busaddr) ); +#endif entry->virtual = vmalloc_32( pages << PAGE_SHIFT ); if ( !entry->virtual ) { +#if defined(__alpha__) && (LINUX_VERSION_CODE >= 0x020400) DRM(free)( entry->busaddr, entry->pages * sizeof(*entry->busaddr), DRM_MEM_PAGES ); +#endif DRM(free)( entry->pagelist, entry->pages * sizeof(*entry->pagelist), DRM_MEM_PAGES ); diff -urN linux-2.4.10/drivers/char/drm/drm_vm.h linux-2.4.10-lia/drivers/char/drm/drm_vm.h --- linux-2.4.10/drivers/char/drm/drm_vm.h Mon Sep 24 15:06:58 2001 +++ linux-2.4.10-lia/drivers/char/drm/drm_vm.h Mon Sep 24 16:16:20 2001 @@ -89,7 +89,7 @@ if (map && map->type == _DRM_AGP) { unsigned long offset = address - vma->vm_start; - unsigned long baddr = VM_OFFSET(vma) + offset; + unsigned long baddr = VM_OFFSET(vma) + offset, paddr; struct drm_agp_mem *agpmem; struct page *page; @@ -115,8 +115,19 @@ * Get the page, inc the use count, and return it */ offset = (baddr - agpmem->bound) >> PAGE_SHIFT; - agpmem->memory->memory[offset] &= dev->agp->page_mask; - page = virt_to_page(__va(agpmem->memory->memory[offset])); + + /* + * This is bad. What we really want to do here is unmask + * the GART table entry held in the agp_memory structure. + * There isn't a convenient way to call agp_bridge.unmask_ + * memory from here, so hard code it for now. + */ +#if defined(__ia64__) + paddr = (agpmem->memory->memory[offset] & 0xffffff) << 12; +#else + paddr = agpmem->memory->memory[offset] & dev->agp->page_mask; +#endif + page = virt_to_page(__va(paddr)); get_page(page); DRM_DEBUG("baddr = 0x%lx page = 0x%p, offset = 0x%lx\n", @@ -255,7 +266,7 @@ DRM_DEBUG("mtrr_del = %d\n", retcode); } #endif - DRM(ioremapfree)(map->handle, map->size); + DRM(ioremapfree)(map->handle, map->size, dev); break; case _DRM_SHM: vfree(map->handle); @@ -503,15 +514,21 @@ switch (map->type) { case _DRM_AGP: -#if defined(__alpha__) - /* - * On Alpha we can't talk to bus dma address from the - * CPU, so for memory of type DRM_AGP, we'll deal with - * sorting out the real physical pages and mappings - * in nopage() - */ - vma->vm_ops = &DRM(vm_ops); - break; +#if __REALLY_HAVE_AGP + if(dev->agp->cant_use_aperture == 1) { + /* + * On some systems we can't talk to bus dma address from + * the CPU, so for memory of type DRM_AGP, we'll deal + * with sorting out the real physical pages and mappings + * in nopage() + */ + vma->vm_ops = &DRM(vm_ops); +#if defined(__ia64__) + if (map->type != _DRM_AGP) + vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); +#endif + goto mapswitch_out; + } #endif /* fall through to _DRM_FRAME_BUFFER... */ case _DRM_FRAME_BUFFER: @@ -523,8 +540,7 @@ pgprot_val(vma->vm_page_prot) &= ~_PAGE_PWT; } #elif defined(__ia64__) - if (map->type != _DRM_AGP) - vma->vm_page_prot = + vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); #elif defined(__powerpc__) pgprot_val(vma->vm_page_prot) |= _PAGE_NO_CACHE | _PAGE_GUARDED; @@ -566,6 +582,9 @@ default: return -EINVAL; /* This should never happen. */ } +#if __REALLY_HAVE_AGP +mapswitch_out: +#endif vma->vm_flags |= VM_LOCKED | VM_SHM; /* Don't swap */ #if LINUX_VERSION_CODE < 0x020203 /* KERNEL_VERSION(2,2,3) */ diff -urN linux-2.4.10/drivers/char/drm/i810_dma.c linux-2.4.10-lia/drivers/char/drm/i810_dma.c --- linux-2.4.10/drivers/char/drm/i810_dma.c Wed Aug 8 09:42:15 2001 +++ linux-2.4.10-lia/drivers/char/drm/i810_dma.c Mon Aug 20 18:09:34 2001 @@ -315,7 +315,7 @@ if(dev_priv->ring.virtual_start) { DRM(ioremapfree)((void *) dev_priv->ring.virtual_start, - dev_priv->ring.Size); + dev_priv->ring.Size, dev); } if(dev_priv->hw_status_page != 0UL) { i810_free_page(dev, dev_priv->hw_status_page); @@ -329,7 +329,8 @@ for (i = 0; i < dma->buf_count; i++) { drm_buf_t *buf = dma->buflist[ i ]; drm_i810_buf_priv_t *buf_priv = buf->dev_private; - DRM(ioremapfree)(buf_priv->kernel_virtual, buf->total); + DRM(ioremapfree)(buf_priv->kernel_virtual, + buf->total, dev); } } return 0; @@ -402,7 +403,7 @@ *buf_priv->in_use = I810_BUF_FREE; buf_priv->kernel_virtual = DRM(ioremap)(buf->bus_address, - buf->total); + buf->total, dev); } return 0; } @@ -458,7 +459,7 @@ dev_priv->ring.virtual_start = DRM(ioremap)(dev->agp->base + init->ring_start, - init->ring_size); + init->ring_size, dev); if (dev_priv->ring.virtual_start == NULL) { dev->dev_private = (void *) dev_priv; diff -urN linux-2.4.10/drivers/char/drm/mga_dma.c linux-2.4.10-lia/drivers/char/drm/mga_dma.c --- linux-2.4.10/drivers/char/drm/mga_dma.c Wed Aug 8 09:42:15 2001 +++ linux-2.4.10-lia/drivers/char/drm/mga_dma.c Mon Aug 20 18:09:34 2001 @@ -557,9 +557,9 @@ (drm_mga_sarea_t *)((u8 *)dev_priv->sarea->handle + init->sarea_priv_offset); - DRM_IOREMAP( dev_priv->warp ); - DRM_IOREMAP( dev_priv->primary ); - DRM_IOREMAP( dev_priv->buffers ); + DRM_IOREMAP( dev_priv->warp, dev ); + DRM_IOREMAP( dev_priv->primary, dev ); + DRM_IOREMAP( dev_priv->buffers, dev ); if(!dev_priv->warp->handle || !dev_priv->primary->handle || @@ -647,9 +647,9 @@ if ( dev->dev_private ) { drm_mga_private_t *dev_priv = dev->dev_private; - DRM_IOREMAPFREE( dev_priv->warp ); - DRM_IOREMAPFREE( dev_priv->primary ); - DRM_IOREMAPFREE( dev_priv->buffers ); + DRM_IOREMAPFREE( dev_priv->warp, dev ); + DRM_IOREMAPFREE( dev_priv->primary, dev ); + DRM_IOREMAPFREE( dev_priv->buffers, dev ); if ( dev_priv->head != NULL ) { mga_freelist_cleanup( dev ); diff -urN linux-2.4.10/drivers/char/drm/r128_cce.c linux-2.4.10-lia/drivers/char/drm/r128_cce.c --- linux-2.4.10/drivers/char/drm/r128_cce.c Mon Sep 24 15:06:58 2001 +++ linux-2.4.10-lia/drivers/char/drm/r128_cce.c Mon Sep 24 15:25:55 2001 @@ -216,7 +216,22 @@ int i; for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { +#ifndef CONFIG_AGP_I460 if ( GET_RING_HEAD( &dev_priv->ring ) == dev_priv->ring.tail ) { +#else + /* + * XXX - this is (I think) a 460GX specific hack + * + * When doing texturing, ring.tail sometimes gets ahead of + * PM4_BUFFER_DL_WPTR by 2; consequently, the card processes + * its whole quota of instructions and *ring.head is still 2 + * short of ring.tail. Work around this for now in lieu of + * a better solution. + */ + if ( GET_RING_HEAD( &dev_priv->ring ) == dev_priv->ring.tail || + ( dev_priv->ring.tail - + GET_RING_HEAD( &dev_priv->ring ) ) == 2 ) { +#endif int pm4stat = R128_READ( R128_PM4_STAT ); if ( ( (pm4stat & R128_PM4_FIFOCNT_MASK) >= dev_priv->cce_fifo_size ) && @@ -341,8 +356,27 @@ SET_RING_HEAD( &dev_priv->ring, 0 ); if ( !dev_priv->is_pci ) { +#if defined(CONFIG_AGP_I460) && defined(__ia64__) + /* + * XXX - This is a 460GX specific hack + * + * We have to hack this right now. 460GX isn't claiming PCI + * writes from the card into the AGP aperture. Because of this, + * we have to get space outside of the aperture for RPTR_ADDR. + */ + if( dev->agp->agp_info.chipset == INTEL_460GX ) { + unsigned long alt_rh_off; + + alt_rh_off = __get_free_page(GFP_KERNEL | GFP_DMA); + atomic_inc(&virt_to_page(alt_rh_off)->count); + set_bit(PG_locked, &virt_to_page(alt_rh_off)->flags); + + dev_priv->ring.head = (__volatile__ u32 *) alt_rh_off; + SET_RING_HEAD( &dev_priv->ring, 0 ); + } +#endif R128_WRITE( R128_PM4_BUFFER_DL_RPTR_ADDR, - dev_priv->ring_rptr->offset ); + __pa( dev_priv->ring.head ) ); } else { drm_sg_mem_t *entry = dev->sg; unsigned long tmp_ofs, page_ofs; @@ -350,11 +384,20 @@ tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle; page_ofs = tmp_ofs >> PAGE_SHIFT; +#if defined(__alpha__) && (LINUX_VERSION_CODE >= 0x020400) R128_WRITE( R128_PM4_BUFFER_DL_RPTR_ADDR, entry->busaddr[page_ofs]); DRM_DEBUG( "ring rptr: offset=0x%08x handle=0x%08lx\n", entry->busaddr[page_ofs], entry->handle + tmp_ofs ); +#else + R128_WRITE( R128_PM4_BUFFER_DL_RPTR_ADDR, + page_to_bus(entry->pagelist[page_ofs])); + + DRM_DEBUG( "ring rptr: offset=0x%08lx handle=0x%08lx\n", + page_to_bus(entry->pagelist[page_ofs]), + entry->handle + tmp_ofs ); +#endif } /* Set watermark control */ @@ -550,9 +593,9 @@ init->sarea_priv_offset); if ( !dev_priv->is_pci ) { - DRM_IOREMAP( dev_priv->cce_ring ); - DRM_IOREMAP( dev_priv->ring_rptr ); - DRM_IOREMAP( dev_priv->buffers ); + DRM_IOREMAP( dev_priv->cce_ring, dev ); + DRM_IOREMAP( dev_priv->ring_rptr, dev ); + DRM_IOREMAP( dev_priv->buffers, dev ); if(!dev_priv->cce_ring->handle || !dev_priv->ring_rptr->handle || !dev_priv->buffers->handle) { @@ -624,9 +667,9 @@ drm_r128_private_t *dev_priv = dev->dev_private; if ( !dev_priv->is_pci ) { - DRM_IOREMAPFREE( dev_priv->cce_ring ); - DRM_IOREMAPFREE( dev_priv->ring_rptr ); - DRM_IOREMAPFREE( dev_priv->buffers ); + DRM_IOREMAPFREE( dev_priv->cce_ring, dev ); + DRM_IOREMAPFREE( dev_priv->ring_rptr, dev ); + DRM_IOREMAPFREE( dev_priv->buffers, dev ); } else { if (!DRM(ati_pcigart_cleanup)( dev, dev_priv->phys_pci_gart, @@ -634,6 +677,21 @@ DRM_ERROR( "failed to cleanup PCI GART!\n" ); } +#if defined(CONFIG_AGP_I460) && defined(__ia64__) + /* + * Free the page we grabbed for RPTR_ADDR + */ + if( dev->agp->agp_info.chipset == INTEL_460GX ) { + unsigned long alt_rh_off = + (unsigned long) dev_priv->ring.head; + + atomic_dec(&virt_to_page(alt_rh_off)->count); + clear_bit(PG_locked, &virt_to_page(alt_rh_off)->flags); + wake_up(&virt_to_page(alt_rh_off)->wait); + free_page(alt_rh_off); + } +#endif + DRM(free)( dev->dev_private, sizeof(drm_r128_private_t), DRM_MEM_DRIVER ); dev->dev_private = NULL; diff -urN linux-2.4.10/drivers/char/drm/radeon_cp.c linux-2.4.10-lia/drivers/char/drm/radeon_cp.c --- linux-2.4.10/drivers/char/drm/radeon_cp.c Mon Sep 24 15:06:58 2001 +++ linux-2.4.10-lia/drivers/char/drm/radeon_cp.c Mon Sep 24 15:25:55 2001 @@ -612,8 +612,27 @@ dev_priv->ring.tail = cur_read_ptr; if ( !dev_priv->is_pci ) { +#if defined(CONFIG_AGP_I460) && defined(__ia64__) + /* + * XXX - This is a 460GX specific hack + * + * We have to hack this right now. 460GX isn't claiming PCI + * writes from the card into the AGP aperture. Because of this, + * we have to get space outside of the aperture for RPTR_ADDR. + */ + if( dev->agp->agp_info.chipset == INTEL_460GX ) { + unsigned long alt_rh_off; + + alt_rh_off = __get_free_page(GFP_KERNEL | GFP_DMA); + atomic_inc(&virt_to_page(alt_rh_off)->count); + set_bit(PG_locked, &virt_to_page(alt_rh_off)->flags); + + dev_priv->ring.head = (__volatile__ u32 *) alt_rh_off; + *dev_priv->ring.head = cur_read_ptr; + } +#endif RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR, - dev_priv->ring_rptr->offset ); + __pa( dev_priv->ring.head ) ); } else { drm_sg_mem_t *entry = dev->sg; unsigned long tmp_ofs, page_ofs; @@ -621,11 +640,19 @@ tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle; page_ofs = tmp_ofs >> PAGE_SHIFT; +#if defined(__alpha__) && (LINUX_VERSION_CODE >= 0x020400) + RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR, + entry->busaddr[page_ofs]); + DRM_DEBUG( "ring rptr: offset=0x%08x handle=0x%08lx\n", + entry->busaddr[page_ofs], + entry->handle + tmp_ofs ); +#else RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]); DRM_DEBUG( "ring rptr: offset=0x%08x handle=0x%08lx\n", entry->busaddr[page_ofs], entry->handle + tmp_ofs ); +#endif } /* Set ring buffer size */ @@ -836,9 +863,9 @@ init->sarea_priv_offset); if ( !dev_priv->is_pci ) { - DRM_IOREMAP( dev_priv->cp_ring ); - DRM_IOREMAP( dev_priv->ring_rptr ); - DRM_IOREMAP( dev_priv->buffers ); + DRM_IOREMAP( dev_priv->cp_ring, dev ); + DRM_IOREMAP( dev_priv->ring_rptr, dev ); + DRM_IOREMAP( dev_priv->buffers, dev ); if(!dev_priv->cp_ring->handle || !dev_priv->ring_rptr->handle || !dev_priv->buffers->handle) { @@ -983,9 +1010,9 @@ drm_radeon_private_t *dev_priv = dev->dev_private; if ( !dev_priv->is_pci ) { - DRM_IOREMAPFREE( dev_priv->cp_ring ); - DRM_IOREMAPFREE( dev_priv->ring_rptr ); - DRM_IOREMAPFREE( dev_priv->buffers ); + DRM_IOREMAPFREE( dev_priv->cp_ring, dev ); + DRM_IOREMAPFREE( dev_priv->ring_rptr, dev ); + DRM_IOREMAPFREE( dev_priv->buffers, dev ); } else { if (!DRM(ati_pcigart_cleanup)( dev, dev_priv->phys_pci_gart, @@ -993,6 +1020,21 @@ DRM_ERROR( "failed to cleanup PCI GART!\n" ); } +#if defined(CONFIG_AGP_I460) && defined(__ia64__) + /* + * Free the page we grabbed for RPTR_ADDR + */ + if( dev->agp->agp_info.chipset == INTEL_460GX ) { + unsigned long alt_rh_off = + (unsigned long) dev_priv->ring.head; + + atomic_dec(&virt_to_page(alt_rh_off)->count); + clear_bit(PG_locked, &virt_to_page(alt_rh_off)->flags); + wake_up(&virt_to_page(alt_rh_off)->wait); + free_page(alt_rh_off); + } +#endif + DRM(free)( dev->dev_private, sizeof(drm_radeon_private_t), DRM_MEM_DRIVER ); dev->dev_private = NULL; diff -urN linux-2.4.10/drivers/char/drm-4.0/Config.in linux-2.4.10-lia/drivers/char/drm-4.0/Config.in --- linux-2.4.10/drivers/char/drm-4.0/Config.in Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/Config.in Wed Aug 15 20:52:11 2001 @@ -0,0 +1,13 @@ +# +# drm device configuration +# +# This driver provides support for the +# Direct Rendering Infrastructure (DRI) in XFree86 4.x. +# + +tristate ' 3dfx Banshee/Voodoo3+' CONFIG_DRM40_TDFX +tristate ' 3dlabs GMX 2000' CONFIG_DRM40_GAMMA +dep_tristate ' ATI Rage 128' CONFIG_DRM40_R128 $CONFIG_AGP +dep_tristate ' ATI Radeon' CONFIG_DRM40_RADEON $CONFIG_AGP +dep_tristate ' Intel I810' CONFIG_DRM40_I810 $CONFIG_AGP +dep_tristate ' Matrox g200/g400' CONFIG_DRM40_MGA $CONFIG_AGP diff -urN linux-2.4.10/drivers/char/drm-4.0/Makefile linux-2.4.10-lia/drivers/char/drm-4.0/Makefile --- linux-2.4.10/drivers/char/drm-4.0/Makefile Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/Makefile Wed Aug 15 20:52:11 2001 @@ -0,0 +1,104 @@ +# +# Makefile for the drm device driver. This driver provides support for +# the Direct Rendering Infrastructure (DRI) in XFree86 4.x. +# + +O_TARGET := drm.o + +export-objs := gamma_drv.o tdfx_drv.o r128_drv.o ffb_drv.o mga_drv.o \ + i810_drv.o + +# lib-objs are included in every module so that radical changes to the +# architecture of the DRM support library can be made at a later time. +# +# The downside is that each module is larger, and a system that uses +# more than one module (i.e., a dual-head system) will use more memory +# (but a system that uses exactly one module will use the same amount of +# memory). +# +# The upside is that if the DRM support library ever becomes insufficient +# for new families of cards, a new library can be implemented for those new +# cards without impacting the drivers for the old cards. This is significant, +# because testing architectural changes to old cards may be impossible, and +# may delay the implementation of a better architecture. We've traded slight +# memory waste (in the dual-head case) for greatly improved long-term +# maintainability. +# +# NOTE: lib-objs will be eliminated in future versions, thereby +# eliminating the need to compile the .o files into every module, but +# for now we still need them. +# + +lib-objs := init.o memory.o proc.o auth.o context.o drawable.o bufs.o +lib-objs += lists.o lock.o ioctl.o fops.o vm.o dma.o ctxbitmap.o + +ifeq ($(CONFIG_AGP),y) + lib-objs += agpsupport.o +else + ifeq ($(CONFIG_AGP),m) + lib-objs += agpsupport.o + endif +endif + +list-multi := gamma.o tdfx.o r128.o ffb.o mga.o i810.o +gamma-objs := gamma_drv.o gamma_dma.o +tdfx-objs := tdfx_drv.o tdfx_context.o +r128-objs := r128_drv.o r128_cce.o r128_context.o r128_bufs.o r128_state.o +ffb-objs := ffb_drv.o ffb_context.o +mga-objs := mga_drv.o mga_dma.o mga_context.o mga_bufs.o mga_state.o +i810-objs := i810_drv.o i810_dma.o i810_context.o i810_bufs.o +radeon-objs := radeon_drv.o radeon_cp.o radeon_context.o radeon_bufs.o radeon_state.o + +obj-$(CONFIG_DRM40_GAMMA) += gamma.o +obj-$(CONFIG_DRM40_TDFX) += tdfx.o +obj-$(CONFIG_DRM40_R128) += r128.o +obj-$(CONFIG_DRM40_RADEON)+= radeon.o +obj-$(CONFIG_DRM40_FFB) += ffb.o +obj-$(CONFIG_DRM40_MGA) += mga.o +obj-$(CONFIG_DRM40_I810) += i810.o + + +# When linking into the kernel, link the library just once. +# If making modules, we include the library into each module + +lib-objs-mod := $(patsubst %.o,%-mod.o,$(lib-objs)) + +ifdef MAKING_MODULES + lib = drmlib-mod.a +else + obj-y += drmlib.a +endif + +include $(TOPDIR)/Rules.make + +$(patsubst %.o,%.c,$(lib-objs-mod)): + @ln -sf $(subst -mod,,$@) $@ + +drmlib-mod.a: $(lib-objs-mod) + rm -f $@ + $(AR) $(EXTRA_ARFLAGS) rcs $@ $(lib-objs-mod) + +drmlib.a: $(lib-objs) + rm -f $@ + $(AR) $(EXTRA_ARFLAGS) rcs $@ $(lib-objs) + +gamma.o: $(gamma-objs) $(lib) + $(LD) -r -o $@ $(gamma-objs) $(lib) + +tdfx.o: $(tdfx-objs) $(lib) + $(LD) -r -o $@ $(tdfx-objs) $(lib) + +mga.o: $(mga-objs) $(lib) + $(LD) -r -o $@ $(mga-objs) $(lib) + +i810.o: $(i810-objs) $(lib) + $(LD) -r -o $@ $(i810-objs) $(lib) + +r128.o: $(r128-objs) $(lib) + $(LD) -r -o $@ $(r128-objs) $(lib) + +radeon.o: $(radeon-objs) $(lib) + $(LD) -r -o $@ $(radeon-objs) $(lib) + +ffb.o: $(ffb-objs) $(lib) + $(LD) -r -o $@ $(ffb-objs) $(lib) diff -urN linux-2.4.10/drivers/char/drm-4.0/README.drm linux-2.4.10-lia/drivers/char/drm-4.0/README.drm --- linux-2.4.10/drivers/char/drm-4.0/README.drm Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/README.drm Wed Aug 15 20:52:11 2001 @@ -0,0 +1,46 @@ +************************************************************ +* For the very latest on DRI development, please see: * +* http://dri.sourceforge.net/ * +************************************************************ + +The Direct Rendering Manager (drm) is a device-independent kernel-level +device driver that provides support for the XFree86 Direct Rendering +Infrastructure (DRI). + +The DRM supports the Direct Rendering Infrastructure (DRI) in four major +ways: + + 1. The DRM provides synchronized access to the graphics hardware via + the use of an optimized two-tiered lock. + + 2. The DRM enforces the DRI security policy for access to the graphics + hardware by only allowing authenticated X11 clients access to + restricted regions of memory. + + 3. The DRM provides a generic DMA engine, complete with multiple + queues and the ability to detect the need for an OpenGL context + switch. + + 4. The DRM is extensible via the use of small device-specific modules + that rely extensively on the API exported by the DRM module. + + +Documentation on the DRI is available from: + http://precisioninsight.com/piinsights.html + +For specific information about kernel-level support, see: + + The Direct Rendering Manager, Kernel Support for the Direct Rendering + Infrastructure + http://precisioninsight.com/dr/drm.html + + Hardware Locking for the Direct Rendering Infrastructure + http://precisioninsight.com/dr/locking.html + + A Security Analysis of the Direct Rendering Infrastructure + http://precisioninsight.com/dr/security.html + +************************************************************ +* For the very latest on DRI development, please see: * +* http://dri.sourceforge.net/ * +************************************************************ diff -urN linux-2.4.10/drivers/char/drm-4.0/agpsupport.c linux-2.4.10-lia/drivers/char/drm-4.0/agpsupport.c --- linux-2.4.10/drivers/char/drm-4.0/agpsupport.c Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/agpsupport.c Mon Aug 20 18:09:34 2001 @@ -0,0 +1,349 @@ +/* agpsupport.c -- DRM support for AGP/GART backend -*- linux-c -*- + * Created: Mon Dec 13 09:56:45 1999 by faith@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Author: Rickard E. (Rik) Faith + * + */ + +#define __NO_VERSION__ +#include "drmP.h" +#include +#include +#if LINUX_VERSION_CODE < 0x020400 +#include "agpsupport-pre24.h" +#else +#define DRM_AGP_GET (drm_agp_t *)inter_module_get("drm_agp") +#define DRM_AGP_PUT inter_module_put("drm_agp") +#endif + +static const drm_agp_t *drm_agp = NULL; + +int drm_agp_info(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + agp_kern_info *kern; + drm_agp_info_t info; + + if (!dev->agp->acquired || !drm_agp->copy_info) return -EINVAL; + + kern = &dev->agp->agp_info; + info.agp_version_major = kern->version.major; + info.agp_version_minor = kern->version.minor; + info.mode = kern->mode; + info.aperture_base = kern->aper_base; + info.aperture_size = kern->aper_size * 1024 * 1024; + info.memory_allowed = kern->max_memory << PAGE_SHIFT; + info.memory_used = kern->current_memory << PAGE_SHIFT; + info.id_vendor = kern->device->vendor; + info.id_device = kern->device->device; + + if (copy_to_user((drm_agp_info_t *)arg, &info, sizeof(info))) + return -EFAULT; + return 0; +} + +int drm_agp_acquire(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + int retcode; + + if (dev->agp->acquired || !drm_agp->acquire) return -EINVAL; + if ((retcode = drm_agp->acquire())) return retcode; + dev->agp->acquired = 1; + return 0; +} + +int drm_agp_release(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + + if (!dev->agp->acquired || !drm_agp->release) return -EINVAL; + drm_agp->release(); + dev->agp->acquired = 0; + return 0; + +} + +void _drm_agp_release(void) +{ + if (drm_agp->release) drm_agp->release(); +} + +int drm_agp_enable(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_agp_mode_t mode; + + if (!dev->agp->acquired || !drm_agp->enable) return -EINVAL; + + if (copy_from_user(&mode, (drm_agp_mode_t *)arg, sizeof(mode))) + return -EFAULT; + + dev->agp->mode = mode.mode; + drm_agp->enable(mode.mode); + dev->agp->base = dev->agp->agp_info.aper_base; + dev->agp->enabled = 1; + return 0; +} + +int drm_agp_alloc(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_agp_buffer_t request; + drm_agp_mem_t *entry; + agp_memory *memory; + unsigned long pages; + u32 type; + if (!dev->agp->acquired) return -EINVAL; + if (copy_from_user(&request, (drm_agp_buffer_t *)arg, sizeof(request))) + return -EFAULT; + if (!(entry = drm_alloc(sizeof(*entry), DRM_MEM_AGPLISTS))) + return -ENOMEM; + + memset(entry, 0, sizeof(*entry)); + + pages = (request.size + PAGE_SIZE - 1) / PAGE_SIZE; + type = (u32) request.type; + + if (!(memory = drm_alloc_agp(pages, type))) { + drm_free(entry, sizeof(*entry), DRM_MEM_AGPLISTS); + return -ENOMEM; + } + + entry->handle = (unsigned long)memory->memory; + entry->memory = memory; + entry->bound = 0; + entry->pages = pages; + entry->prev = NULL; + entry->next = dev->agp->memory; + if (dev->agp->memory) dev->agp->memory->prev = entry; + dev->agp->memory = entry; + + request.handle = entry->handle; + request.physical = memory->physical; + + if (copy_to_user((drm_agp_buffer_t *)arg, &request, sizeof(request))) { + dev->agp->memory = entry->next; + dev->agp->memory->prev = NULL; + drm_free_agp(memory, pages); + drm_free(entry, sizeof(*entry), DRM_MEM_AGPLISTS); + return -EFAULT; + } + return 0; +} + +static drm_agp_mem_t *drm_agp_lookup_entry(drm_device_t *dev, + unsigned long handle) +{ + drm_agp_mem_t *entry; + + for (entry = dev->agp->memory; entry; entry = entry->next) { + if (entry->handle == handle) return entry; + } + return NULL; +} + +int drm_agp_unbind(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_agp_binding_t request; + drm_agp_mem_t *entry; + + if (!dev->agp->acquired) return -EINVAL; + if (copy_from_user(&request, (drm_agp_binding_t *)arg, sizeof(request))) + return -EFAULT; + if (!(entry = drm_agp_lookup_entry(dev, request.handle))) + return -EINVAL; + if (!entry->bound) return -EINVAL; + return drm_unbind_agp(entry->memory); +} + +int drm_agp_bind(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_agp_binding_t request; + drm_agp_mem_t *entry; + int retcode; + int page; + + if (!dev->agp->acquired || !drm_agp->bind_memory) return -EINVAL; + if (copy_from_user(&request, (drm_agp_binding_t *)arg, sizeof(request))) + return -EFAULT; + if (!(entry = drm_agp_lookup_entry(dev, request.handle))) + return -EINVAL; + if (entry->bound) return -EINVAL; + page = (request.offset + PAGE_SIZE - 1) / PAGE_SIZE; + if ((retcode = drm_bind_agp(entry->memory, page))) return retcode; + entry->bound = dev->agp->base + (page << PAGE_SHIFT); + DRM_DEBUG("base = 0x%lx entry->bound = 0x%lx\n", + dev->agp->base, entry->bound); + return 0; +} + +int drm_agp_free(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_agp_buffer_t request; + drm_agp_mem_t *entry; + + if (!dev->agp->acquired) return -EINVAL; + if (copy_from_user(&request, (drm_agp_buffer_t *)arg, sizeof(request))) + return -EFAULT; + if (!(entry = drm_agp_lookup_entry(dev, request.handle))) + return -EINVAL; + if (entry->bound) drm_unbind_agp(entry->memory); + + if (entry->prev) entry->prev->next = entry->next; + else dev->agp->memory = entry->next; + if (entry->next) entry->next->prev = entry->prev; + drm_free_agp(entry->memory, entry->pages); + drm_free(entry, sizeof(*entry), DRM_MEM_AGPLISTS); + return 0; +} + +drm_agp_head_t *drm_agp_init(void) +{ + drm_agp_head_t *head = NULL; + + drm_agp = DRM_AGP_GET; + if (drm_agp) { + if (!(head = drm_alloc(sizeof(*head), DRM_MEM_AGPLISTS))) + return NULL; + memset((void *)head, 0, sizeof(*head)); + drm_agp->copy_info(&head->agp_info); + if (head->agp_info.chipset == NOT_SUPPORTED) { + drm_free(head, sizeof(*head), DRM_MEM_AGPLISTS); + return NULL; + } + head->memory = NULL; + switch (head->agp_info.chipset) { + case INTEL_GENERIC: head->chipset = "Intel"; break; + case INTEL_LX: head->chipset = "Intel 440LX"; break; + case INTEL_BX: head->chipset = "Intel 440BX"; break; + case INTEL_GX: head->chipset = "Intel 440GX"; break; + case INTEL_I810: head->chipset = "Intel i810"; break; + +#if LINUX_VERSION_CODE >= 0x020400 + case INTEL_I840: head->chipset = "Intel i840"; break; +#endif + case INTEL_460GX: head->chipset = "Intel 460GX"; break; + + case VIA_GENERIC: head->chipset = "VIA"; break; + case VIA_VP3: head->chipset = "VIA VP3"; break; + case VIA_MVP3: head->chipset = "VIA MVP3"; break; + +#if LINUX_VERSION_CODE >= 0x020400 + case VIA_MVP4: head->chipset = "VIA MVP4"; break; + case VIA_APOLLO_KX133: head->chipset = "VIA Apollo KX133"; + break; + case VIA_APOLLO_KT133: head->chipset = "VIA Apollo KT133"; + break; +#endif + + case VIA_APOLLO_PRO: head->chipset = "VIA Apollo Pro"; + break; + case SIS_GENERIC: head->chipset = "SiS"; break; + case AMD_GENERIC: head->chipset = "AMD"; break; + case AMD_IRONGATE: head->chipset = "AMD Irongate"; break; + case ALI_GENERIC: head->chipset = "ALi"; break; + case ALI_M1541: head->chipset = "ALi M1541"; break; + case ALI_M1621: head->chipset = "ALi M1621"; break; + case ALI_M1631: head->chipset = "ALi M1631"; break; + case ALI_M1632: head->chipset = "ALi M1632"; break; + case ALI_M1641: head->chipset = "ALi M1641"; break; + case ALI_M1647: head->chipset = "ALi M1647"; break; + case ALI_M1651: head->chipset = "ALi M1651"; break; + case SVWRKS_GENERIC: head->chipset = "Serverworks Generic"; + break; + case SVWRKS_HE: head->chipset = "Serverworks HE"; break; + case SVWRKS_LE: head->chipset = "Serverworks LE"; break; + + default: head->chipset = "Unknown"; break; + } +#if LINUX_VERSION_CODE <= 0x020408 + head->cant_use_aperture = 0; + head->page_mask = ~(0xfff); +#else + head->cant_use_aperture = head->agp_info.cant_use_aperture; + head->page_mask = head->agp_info.page_mask; +#endif + + DRM_INFO("AGP %d.%d on %s @ 0x%08lx %ZuMB\n", + head->agp_info.version.major, + head->agp_info.version.minor, + head->chipset, + head->agp_info.aper_base, + head->agp_info.aper_size); + } + return head; +} + +void drm_agp_uninit(void) +{ + DRM_AGP_PUT; + drm_agp = NULL; +} + +agp_memory *drm_agp_allocate_memory(size_t pages, u32 type) +{ + if (!drm_agp->allocate_memory) return NULL; + return drm_agp->allocate_memory(pages, type); +} + +int drm_agp_free_memory(agp_memory *handle) +{ + if (!handle || !drm_agp->free_memory) return 0; + drm_agp->free_memory(handle); + return 1; +} + +int drm_agp_bind_memory(agp_memory *handle, off_t start) +{ + if (!handle || !drm_agp->bind_memory) return -EINVAL; + return drm_agp->bind_memory(handle, start); +} + +int drm_agp_unbind_memory(agp_memory *handle) +{ + if (!handle || !drm_agp->unbind_memory) return -EINVAL; + return drm_agp->unbind_memory(handle); +} diff -urN linux-2.4.10/drivers/char/drm-4.0/auth.c linux-2.4.10-lia/drivers/char/drm-4.0/auth.c --- linux-2.4.10/drivers/char/drm-4.0/auth.c Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/auth.c Wed Aug 15 20:52:11 2001 @@ -0,0 +1,162 @@ +/* auth.c -- IOCTLs for authentication -*- linux-c -*- + * Created: Tue Feb 2 08:37:54 1999 by faith@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rickard E. (Rik) Faith + * + */ + +#define __NO_VERSION__ +#include "drmP.h" + +static int drm_hash_magic(drm_magic_t magic) +{ + return magic & (DRM_HASH_SIZE-1); +} + +static drm_file_t *drm_find_file(drm_device_t *dev, drm_magic_t magic) +{ + drm_file_t *retval = NULL; + drm_magic_entry_t *pt; + int hash = drm_hash_magic(magic); + + down(&dev->struct_sem); + for (pt = dev->magiclist[hash].head; pt; pt = pt->next) { + if (pt->magic == magic) { + retval = pt->priv; + break; + } + } + up(&dev->struct_sem); + return retval; +} + +int drm_add_magic(drm_device_t *dev, drm_file_t *priv, drm_magic_t magic) +{ + int hash; + drm_magic_entry_t *entry; + + DRM_DEBUG("%d\n", magic); + + hash = drm_hash_magic(magic); + entry = drm_alloc(sizeof(*entry), DRM_MEM_MAGIC); + if (!entry) return -ENOMEM; + entry->magic = magic; + entry->priv = priv; + entry->next = NULL; + + down(&dev->struct_sem); + if (dev->magiclist[hash].tail) { + dev->magiclist[hash].tail->next = entry; + dev->magiclist[hash].tail = entry; + } else { + dev->magiclist[hash].head = entry; + dev->magiclist[hash].tail = entry; + } + up(&dev->struct_sem); + + return 0; +} + +int drm_remove_magic(drm_device_t *dev, drm_magic_t magic) +{ + drm_magic_entry_t *prev = NULL; + drm_magic_entry_t *pt; + int hash; + + DRM_DEBUG("%d\n", magic); + hash = drm_hash_magic(magic); + + down(&dev->struct_sem); + for (pt = dev->magiclist[hash].head; pt; prev = pt, pt = pt->next) { + if (pt->magic == magic) { + if (dev->magiclist[hash].head == pt) { + dev->magiclist[hash].head = pt->next; + } + if (dev->magiclist[hash].tail == pt) { + dev->magiclist[hash].tail = prev; + } + if (prev) { + prev->next = pt->next; + } + up(&dev->struct_sem); + return 0; + } + } + up(&dev->struct_sem); + + drm_free(pt, sizeof(*pt), DRM_MEM_MAGIC); + + return -EINVAL; +} + +int drm_getmagic(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + static drm_magic_t sequence = 0; + static spinlock_t lock = SPIN_LOCK_UNLOCKED; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_auth_t auth; + + /* Find unique magic */ + if (priv->magic) { + auth.magic = priv->magic; + } else { + do { + spin_lock(&lock); + if (!sequence) ++sequence; /* reserve 0 */ + auth.magic = sequence++; + spin_unlock(&lock); + } while (drm_find_file(dev, auth.magic)); + priv->magic = auth.magic; + drm_add_magic(dev, priv, auth.magic); + } + + DRM_DEBUG("%u\n", auth.magic); + if (copy_to_user((drm_auth_t *)arg, &auth, sizeof(auth))) + return -EFAULT; + return 0; +} + +int drm_authmagic(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_auth_t auth; + drm_file_t *file; + + if (copy_from_user(&auth, (drm_auth_t *)arg, sizeof(auth))) + return -EFAULT; + DRM_DEBUG("%u\n", auth.magic); + if ((file = drm_find_file(dev, auth.magic))) { + file->authenticated = 1; + drm_remove_magic(dev, auth.magic); + return 0; + } + return -EINVAL; +} diff -urN linux-2.4.10/drivers/char/drm-4.0/bufs.c linux-2.4.10-lia/drivers/char/drm-4.0/bufs.c --- linux-2.4.10/drivers/char/drm-4.0/bufs.c Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/bufs.c Mon Aug 20 18:09:34 2001 @@ -0,0 +1,543 @@ +/* bufs.c -- IOCTLs to manage buffers -*- linux-c -*- + * Created: Tue Feb 2 08:37:54 1999 by faith@precisioninsight.com + * + * Copyright 1999, 2000 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rickard E. (Rik) Faith + * + */ + +#define __NO_VERSION__ +#include +#include "drmP.h" +#include "linux/un.h" + + /* Compute order. Can be made faster. */ +int drm_order(unsigned long size) +{ + int order; + unsigned long tmp; + + for (order = 0, tmp = size; tmp >>= 1; ++order); + if (size & ~(1 << order)) ++order; + return order; +} + +int drm_addmap(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_map_t *map; + + if (!(filp->f_mode & 3)) return -EACCES; /* Require read/write */ + + map = drm_alloc(sizeof(*map), DRM_MEM_MAPS); + if (!map) return -ENOMEM; + if (copy_from_user(map, (drm_map_t *)arg, sizeof(*map))) { + drm_free(map, sizeof(*map), DRM_MEM_MAPS); + return -EFAULT; + } + + DRM_DEBUG("offset = 0x%08lx, size = 0x%08lx, type = %d\n", + map->offset, map->size, map->type); + if ((map->offset & (~PAGE_MASK)) || (map->size & (~PAGE_MASK))) { + drm_free(map, sizeof(*map), DRM_MEM_MAPS); + return -EINVAL; + } + map->mtrr = -1; + map->handle = 0; + + switch (map->type) { + case _DRM_REGISTERS: + case _DRM_FRAME_BUFFER: +#if !defined(__sparc__) && !defined(__ia64__) + if (map->offset + map->size < map->offset + || map->offset < virt_to_phys(high_memory)) { + drm_free(map, sizeof(*map), DRM_MEM_MAPS); + return -EINVAL; + } +#endif +#ifdef CONFIG_MTRR + if (map->type == _DRM_FRAME_BUFFER + || (map->flags & _DRM_WRITE_COMBINING)) { + map->mtrr = mtrr_add(map->offset, map->size, + MTRR_TYPE_WRCOMB, 1); + } +#endif + map->handle = drm_ioremap(map->offset, map->size, dev); + break; + + + case _DRM_SHM: + map->handle = (void *)drm_alloc_pages(drm_order(map->size) + - PAGE_SHIFT, + DRM_MEM_SAREA); + DRM_DEBUG("%ld %d %p\n", map->size, drm_order(map->size), + map->handle); + if (!map->handle) { + drm_free(map, sizeof(*map), DRM_MEM_MAPS); + return -ENOMEM; + } + map->offset = (unsigned long)map->handle; + if (map->flags & _DRM_CONTAINS_LOCK) { + dev->lock.hw_lock = map->handle; /* Pointer to lock */ + } + break; +#if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE) + case _DRM_AGP: + map->offset = map->offset + dev->agp->base; + break; +#endif + default: + drm_free(map, sizeof(*map), DRM_MEM_MAPS); + return -EINVAL; + } + + down(&dev->struct_sem); + if (dev->maplist) { + ++dev->map_count; + dev->maplist = drm_realloc(dev->maplist, + (dev->map_count-1) + * sizeof(*dev->maplist), + dev->map_count + * sizeof(*dev->maplist), + DRM_MEM_MAPS); + } else { + dev->map_count = 1; + dev->maplist = drm_alloc(dev->map_count*sizeof(*dev->maplist), + DRM_MEM_MAPS); + } + dev->maplist[dev->map_count-1] = map; + up(&dev->struct_sem); + + if (copy_to_user((drm_map_t *)arg, map, sizeof(*map))) + return -EFAULT; + if (map->type != _DRM_SHM) { + if (copy_to_user(&((drm_map_t *)arg)->handle, + &map->offset, + sizeof(map->offset))) + return -EFAULT; + } + return 0; +} + +int drm_addbufs(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_device_dma_t *dma = dev->dma; + drm_buf_desc_t request; + int count; + int order; + int size; + int total; + int page_order; + drm_buf_entry_t *entry; + unsigned long page; + drm_buf_t *buf; + int alignment; + unsigned long offset; + int i; + int byte_count; + int page_count; + + if (!dma) return -EINVAL; + + if (copy_from_user(&request, + (drm_buf_desc_t *)arg, + sizeof(request))) + return -EFAULT; + + count = request.count; + order = drm_order(request.size); + size = 1 << order; + + DRM_DEBUG("count = %d, size = %d (%d), order = %d, queue_count = %d\n", + request.count, request.size, size, order, dev->queue_count); + + if (order < DRM_MIN_ORDER || order > DRM_MAX_ORDER) return -EINVAL; + if (dev->queue_count) return -EBUSY; /* Not while in use */ + + alignment = (request.flags & _DRM_PAGE_ALIGN) ? PAGE_ALIGN(size):size; + page_order = order - PAGE_SHIFT > 0 ? order - PAGE_SHIFT : 0; + total = PAGE_SIZE << page_order; + + spin_lock(&dev->count_lock); + if (dev->buf_use) { + spin_unlock(&dev->count_lock); + return -EBUSY; + } + atomic_inc(&dev->buf_alloc); + spin_unlock(&dev->count_lock); + + down(&dev->struct_sem); + entry = &dma->bufs[order]; + if (entry->buf_count) { + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); + return -ENOMEM; /* May only call once for each order */ + } + + if(count < 0 || count > 4096) + { + up(&dev->struct_sem); + return -EINVAL; + } + + entry->buflist = drm_alloc(count * sizeof(*entry->buflist), + DRM_MEM_BUFS); + if (!entry->buflist) { + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); + return -ENOMEM; + } + memset(entry->buflist, 0, count * sizeof(*entry->buflist)); + + entry->seglist = drm_alloc(count * sizeof(*entry->seglist), + DRM_MEM_SEGS); + if (!entry->seglist) { + drm_free(entry->buflist, + count * sizeof(*entry->buflist), + DRM_MEM_BUFS); + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); + return -ENOMEM; + } + memset(entry->seglist, 0, count * sizeof(*entry->seglist)); + + dma->pagelist = drm_realloc(dma->pagelist, + dma->page_count * sizeof(*dma->pagelist), + (dma->page_count + (count << page_order)) + * sizeof(*dma->pagelist), + DRM_MEM_PAGES); + DRM_DEBUG("pagelist: %d entries\n", + dma->page_count + (count << page_order)); + + + entry->buf_size = size; + entry->page_order = page_order; + byte_count = 0; + page_count = 0; + while (entry->buf_count < count) { + if (!(page = drm_alloc_pages(page_order, DRM_MEM_DMA))) break; + entry->seglist[entry->seg_count++] = page; + for (i = 0; i < (1 << page_order); i++) { + DRM_DEBUG("page %d @ 0x%08lx\n", + dma->page_count + page_count, + page + PAGE_SIZE * i); + dma->pagelist[dma->page_count + page_count++] + = page + PAGE_SIZE * i; + } + for (offset = 0; + offset + size <= total && entry->buf_count < count; + offset += alignment, ++entry->buf_count) { + buf = &entry->buflist[entry->buf_count]; + buf->idx = dma->buf_count + entry->buf_count; + buf->total = alignment; + buf->order = order; + buf->used = 0; + buf->offset = (dma->byte_count + byte_count + offset); + buf->address = (void *)(page + offset); + buf->next = NULL; + buf->waiting = 0; + buf->pending = 0; + init_waitqueue_head(&buf->dma_wait); + buf->pid = 0; +#if DRM_DMA_HISTOGRAM + buf->time_queued = 0; + buf->time_dispatched = 0; + buf->time_completed = 0; + buf->time_freed = 0; +#endif + DRM_DEBUG("buffer %d @ %p\n", + entry->buf_count, buf->address); + } + byte_count += PAGE_SIZE << page_order; + } + + dma->buflist = drm_realloc(dma->buflist, + dma->buf_count * sizeof(*dma->buflist), + (dma->buf_count + entry->buf_count) + * sizeof(*dma->buflist), + DRM_MEM_BUFS); + for (i = dma->buf_count; i < dma->buf_count + entry->buf_count; i++) + dma->buflist[i] = &entry->buflist[i - dma->buf_count]; + + dma->buf_count += entry->buf_count; + dma->seg_count += entry->seg_count; + dma->page_count += entry->seg_count << page_order; + dma->byte_count += PAGE_SIZE * (entry->seg_count << page_order); + + drm_freelist_create(&entry->freelist, entry->buf_count); + for (i = 0; i < entry->buf_count; i++) { + drm_freelist_put(dev, &entry->freelist, &entry->buflist[i]); + } + + up(&dev->struct_sem); + + request.count = entry->buf_count; + request.size = size; + + if (copy_to_user((drm_buf_desc_t *)arg, + &request, + sizeof(request))) + return -EFAULT; + + atomic_dec(&dev->buf_alloc); + return 0; +} + +int drm_infobufs(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_device_dma_t *dma = dev->dma; + drm_buf_info_t request; + int i; + int count; + + if (!dma) return -EINVAL; + + spin_lock(&dev->count_lock); + if (atomic_read(&dev->buf_alloc)) { + spin_unlock(&dev->count_lock); + return -EBUSY; + } + ++dev->buf_use; /* Can't allocate more after this call */ + spin_unlock(&dev->count_lock); + + if (copy_from_user(&request, + (drm_buf_info_t *)arg, + sizeof(request))) + return -EFAULT; + + for (i = 0, count = 0; i < DRM_MAX_ORDER+1; i++) { + if (dma->bufs[i].buf_count) ++count; + } + + DRM_DEBUG("count = %d\n", count); + + if (request.count >= count) { + for (i = 0, count = 0; i < DRM_MAX_ORDER+1; i++) { + if (dma->bufs[i].buf_count) { + if (copy_to_user(&request.list[count].count, + &dma->bufs[i].buf_count, + sizeof(dma->bufs[0] + .buf_count)) || + copy_to_user(&request.list[count].size, + &dma->bufs[i].buf_size, + sizeof(dma->bufs[0].buf_size)) || + copy_to_user(&request.list[count].low_mark, + &dma->bufs[i] + .freelist.low_mark, + sizeof(dma->bufs[0] + .freelist.low_mark)) || + copy_to_user(&request.list[count] + .high_mark, + &dma->bufs[i] + .freelist.high_mark, + sizeof(dma->bufs[0] + .freelist.high_mark))) + return -EFAULT; + + DRM_DEBUG("%d %d %d %d %d\n", + i, + dma->bufs[i].buf_count, + dma->bufs[i].buf_size, + dma->bufs[i].freelist.low_mark, + dma->bufs[i].freelist.high_mark); + ++count; + } + } + } + request.count = count; + + if (copy_to_user((drm_buf_info_t *)arg, + &request, + sizeof(request))) + return -EFAULT; + + return 0; +} + +int drm_markbufs(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_device_dma_t *dma = dev->dma; + drm_buf_desc_t request; + int order; + drm_buf_entry_t *entry; + + if (!dma) return -EINVAL; + + if (copy_from_user(&request, + (drm_buf_desc_t *)arg, + sizeof(request))) + return -EFAULT; + + DRM_DEBUG("%d, %d, %d\n", + request.size, request.low_mark, request.high_mark); + order = drm_order(request.size); + if (order < DRM_MIN_ORDER || order > DRM_MAX_ORDER) return -EINVAL; + entry = &dma->bufs[order]; + + if (request.low_mark < 0 || request.low_mark > entry->buf_count) + return -EINVAL; + if (request.high_mark < 0 || request.high_mark > entry->buf_count) + return -EINVAL; + + entry->freelist.low_mark = request.low_mark; + entry->freelist.high_mark = request.high_mark; + + return 0; +} + +int drm_freebufs(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_device_dma_t *dma = dev->dma; + drm_buf_free_t request; + int i; + int idx; + drm_buf_t *buf; + + if (!dma) return -EINVAL; + + if (copy_from_user(&request, + (drm_buf_free_t *)arg, + sizeof(request))) + return -EFAULT; + + DRM_DEBUG("%d\n", request.count); + for (i = 0; i < request.count; i++) { + if (copy_from_user(&idx, + &request.list[i], + sizeof(idx))) + return -EFAULT; + if (idx < 0 || idx >= dma->buf_count) { + DRM_ERROR("Index %d (of %d max)\n", + idx, dma->buf_count - 1); + return -EINVAL; + } + buf = dma->buflist[idx]; + if (buf->pid != current->pid) { + DRM_ERROR("Process %d freeing buffer owned by %d\n", + current->pid, buf->pid); + return -EINVAL; + } + drm_free_buffer(dev, buf); + } + + return 0; +} + +int drm_mapbufs(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_device_dma_t *dma = dev->dma; + int retcode = 0; + const int zero = 0; + unsigned long virtual; + unsigned long address; + drm_buf_map_t request; + int i; + + if (!dma) return -EINVAL; + + DRM_DEBUG("\n"); + + spin_lock(&dev->count_lock); + if (atomic_read(&dev->buf_alloc)) { + spin_unlock(&dev->count_lock); + return -EBUSY; + } + ++dev->buf_use; /* Can't allocate more after this call */ + spin_unlock(&dev->count_lock); + + if (copy_from_user(&request, + (drm_buf_map_t *)arg, + sizeof(request))) + return -EFAULT; + + if (request.count >= dma->buf_count) { + down_write(¤t->mm->mmap_sem); + virtual = do_mmap(filp, 0, dma->byte_count, + PROT_READ|PROT_WRITE, MAP_SHARED, 0); + up_write(¤t->mm->mmap_sem); + if (virtual > -1024UL) { + /* Real error */ + retcode = (signed long)virtual; + goto done; + } + request.virtual = (void *)virtual; + + for (i = 0; i < dma->buf_count; i++) { + if (copy_to_user(&request.list[i].idx, + &dma->buflist[i]->idx, + sizeof(request.list[0].idx))) { + retcode = -EFAULT; + goto done; + } + if (copy_to_user(&request.list[i].total, + &dma->buflist[i]->total, + sizeof(request.list[0].total))) { + retcode = -EFAULT; + goto done; + } + if (copy_to_user(&request.list[i].used, + &zero, + sizeof(zero))) { + retcode = -EFAULT; + goto done; + } + address = virtual + dma->buflist[i]->offset; + if (copy_to_user(&request.list[i].address, + &address, + sizeof(address))) { + retcode = -EFAULT; + goto done; + } + } + } +done: + request.count = dma->buf_count; + DRM_DEBUG("%d buffers, retcode = %d\n", request.count, retcode); + + if (copy_to_user((drm_buf_map_t *)arg, + &request, + sizeof(request))) + return -EFAULT; + + return retcode; +} diff -urN linux-2.4.10/drivers/char/drm-4.0/context.c linux-2.4.10-lia/drivers/char/drm-4.0/context.c --- linux-2.4.10/drivers/char/drm-4.0/context.c Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/context.c Wed Aug 15 20:52:11 2001 @@ -0,0 +1,321 @@ +/* context.c -- IOCTLs for contexts and DMA queues -*- linux-c -*- + * Created: Tue Feb 2 08:37:54 1999 by faith@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rickard E. (Rik) Faith + * + */ + +#define __NO_VERSION__ +#include "drmP.h" + +static int drm_init_queue(drm_device_t *dev, drm_queue_t *q, drm_ctx_t *ctx) +{ + DRM_DEBUG("\n"); + + if (atomic_read(&q->use_count) != 1 + || atomic_read(&q->finalization) + || atomic_read(&q->block_count)) { + DRM_ERROR("New queue is already in use: u%d f%d b%d\n", + atomic_read(&q->use_count), + atomic_read(&q->finalization), + atomic_read(&q->block_count)); + } + + atomic_set(&q->finalization, 0); + atomic_set(&q->block_count, 0); + atomic_set(&q->block_read, 0); + atomic_set(&q->block_write, 0); + atomic_set(&q->total_queued, 0); + atomic_set(&q->total_flushed, 0); + atomic_set(&q->total_locks, 0); + + init_waitqueue_head(&q->write_queue); + init_waitqueue_head(&q->read_queue); + init_waitqueue_head(&q->flush_queue); + + q->flags = ctx->flags; + + drm_waitlist_create(&q->waitlist, dev->dma->buf_count); + + return 0; +} + + +/* drm_alloc_queue: +PRE: 1) dev->queuelist[0..dev->queue_count] is allocated and will not + disappear (so all deallocation must be done after IOCTLs are off) + 2) dev->queue_count < dev->queue_slots + 3) dev->queuelist[i].use_count == 0 and + dev->queuelist[i].finalization == 0 if i not in use +POST: 1) dev->queuelist[i].use_count == 1 + 2) dev->queue_count < dev->queue_slots */ + +static int drm_alloc_queue(drm_device_t *dev) +{ + int i; + drm_queue_t *queue; + int oldslots; + int newslots; + /* Check for a free queue */ + for (i = 0; i < dev->queue_count; i++) { + atomic_inc(&dev->queuelist[i]->use_count); + if (atomic_read(&dev->queuelist[i]->use_count) == 1 + && !atomic_read(&dev->queuelist[i]->finalization)) { + DRM_DEBUG("%d (free)\n", i); + return i; + } + atomic_dec(&dev->queuelist[i]->use_count); + } + /* Allocate a new queue */ + + queue = drm_alloc(sizeof(*queue), DRM_MEM_QUEUES); + if(queue == NULL) + return -ENOMEM; + + memset(queue, 0, sizeof(*queue)); + down(&dev->struct_sem); + atomic_set(&queue->use_count, 1); + + ++dev->queue_count; + if (dev->queue_count >= dev->queue_slots) { + oldslots = dev->queue_slots * sizeof(*dev->queuelist); + if (!dev->queue_slots) dev->queue_slots = 1; + dev->queue_slots *= 2; + newslots = dev->queue_slots * sizeof(*dev->queuelist); + + dev->queuelist = drm_realloc(dev->queuelist, + oldslots, + newslots, + DRM_MEM_QUEUES); + if (!dev->queuelist) { + up(&dev->struct_sem); + DRM_DEBUG("out of memory\n"); + return -ENOMEM; + } + } + dev->queuelist[dev->queue_count-1] = queue; + + up(&dev->struct_sem); + DRM_DEBUG("%d (new)\n", dev->queue_count - 1); + return dev->queue_count - 1; +} + +int drm_resctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_ctx_res_t res; + drm_ctx_t ctx; + int i; + + DRM_DEBUG("%d\n", DRM_RESERVED_CONTEXTS); + if (copy_from_user(&res, (drm_ctx_res_t *)arg, sizeof(res))) + return -EFAULT; + if (res.count >= DRM_RESERVED_CONTEXTS) { + memset(&ctx, 0, sizeof(ctx)); + for (i = 0; i < DRM_RESERVED_CONTEXTS; i++) { + ctx.handle = i; + if (copy_to_user(&res.contexts[i], + &i, + sizeof(i))) + return -EFAULT; + } + } + res.count = DRM_RESERVED_CONTEXTS; + if (copy_to_user((drm_ctx_res_t *)arg, &res, sizeof(res))) + return -EFAULT; + return 0; +} + + +int drm_addctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ctx_t ctx; + + if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx))) + return -EFAULT; + if ((ctx.handle = drm_alloc_queue(dev)) == DRM_KERNEL_CONTEXT) { + /* Init kernel's context and get a new one. */ + drm_init_queue(dev, dev->queuelist[ctx.handle], &ctx); + ctx.handle = drm_alloc_queue(dev); + } + drm_init_queue(dev, dev->queuelist[ctx.handle], &ctx); + DRM_DEBUG("%d\n", ctx.handle); + if (copy_to_user((drm_ctx_t *)arg, &ctx, sizeof(ctx))) + return -EFAULT; + return 0; +} + +int drm_modctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ctx_t ctx; + drm_queue_t *q; + + if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx))) + return -EFAULT; + + DRM_DEBUG("%d\n", ctx.handle); + + if (ctx.handle < 0 || ctx.handle >= dev->queue_count) return -EINVAL; + q = dev->queuelist[ctx.handle]; + + atomic_inc(&q->use_count); + if (atomic_read(&q->use_count) == 1) { + /* No longer in use */ + atomic_dec(&q->use_count); + return -EINVAL; + } + + if (DRM_BUFCOUNT(&q->waitlist)) { + atomic_dec(&q->use_count); + return -EBUSY; + } + + q->flags = ctx.flags; + + atomic_dec(&q->use_count); + return 0; +} + +int drm_getctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ctx_t ctx; + drm_queue_t *q; + + if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx))) + return -EFAULT; + + DRM_DEBUG("%d\n", ctx.handle); + + if (ctx.handle >= dev->queue_count) return -EINVAL; + q = dev->queuelist[ctx.handle]; + + atomic_inc(&q->use_count); + if (atomic_read(&q->use_count) == 1) { + /* No longer in use */ + atomic_dec(&q->use_count); + return -EINVAL; + } + + ctx.flags = q->flags; + atomic_dec(&q->use_count); + + if (copy_to_user((drm_ctx_t *)arg, &ctx, sizeof(ctx))) + return -EFAULT; + + return 0; +} + +int drm_switchctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ctx_t ctx; + + if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx))) + return -EFAULT; + DRM_DEBUG("%d\n", ctx.handle); + return drm_context_switch(dev, dev->last_context, ctx.handle); +} + +int drm_newctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ctx_t ctx; + + if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx))) + return -EFAULT; + DRM_DEBUG("%d\n", ctx.handle); + drm_context_switch_complete(dev, ctx.handle); + + return 0; +} + +int drm_rmctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ctx_t ctx; + drm_queue_t *q; + drm_buf_t *buf; + + if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx))) + return -EFAULT; + DRM_DEBUG("%d\n", ctx.handle); + + if (ctx.handle >= dev->queue_count) return -EINVAL; + q = dev->queuelist[ctx.handle]; + + atomic_inc(&q->use_count); + if (atomic_read(&q->use_count) == 1) { + /* No longer in use */ + atomic_dec(&q->use_count); + return -EINVAL; + } + + atomic_inc(&q->finalization); /* Mark queue in finalization state */ + atomic_sub(2, &q->use_count); /* Mark queue as unused (pending + finalization) */ + + while (test_and_set_bit(0, &dev->interrupt_flag)) { + schedule(); + if (signal_pending(current)) { + clear_bit(0, &dev->interrupt_flag); + return -EINTR; + } + } + /* Remove queued buffers */ + while ((buf = drm_waitlist_get(&q->waitlist))) { + drm_free_buffer(dev, buf); + } + clear_bit(0, &dev->interrupt_flag); + + /* Wakeup blocked processes */ + wake_up_interruptible(&q->read_queue); + wake_up_interruptible(&q->write_queue); + wake_up_interruptible(&q->flush_queue); + + /* Finalization over. Queue is made + available when both use_count and + finalization become 0, which won't + happen until all the waiting processes + stop waiting. */ + atomic_dec(&q->finalization); + return 0; +} diff -urN linux-2.4.10/drivers/char/drm-4.0/ctxbitmap.c linux-2.4.10-lia/drivers/char/drm-4.0/ctxbitmap.c --- linux-2.4.10/drivers/char/drm-4.0/ctxbitmap.c Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/ctxbitmap.c Wed Aug 15 20:52:11 2001 @@ -0,0 +1,85 @@ +/* ctxbitmap.c -- Context bitmap management -*- linux-c -*- + * Created: Thu Jan 6 03:56:42 2000 by jhartmann@precisioninsight.com + * + * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Author: Jeff Hartmann + * + */ + +#define __NO_VERSION__ +#include "drmP.h" + +void drm_ctxbitmap_free(drm_device_t *dev, int ctx_handle) +{ + if (ctx_handle < 0) goto failed; + + if (ctx_handle < DRM_MAX_CTXBITMAP) { + clear_bit(ctx_handle, dev->ctx_bitmap); + return; + } +failed: + DRM_ERROR("Attempt to free invalid context handle: %d\n", + ctx_handle); + return; +} + +int drm_ctxbitmap_next(drm_device_t *dev) +{ + int bit; + + bit = find_first_zero_bit(dev->ctx_bitmap, DRM_MAX_CTXBITMAP); + if (bit < DRM_MAX_CTXBITMAP) { + set_bit(bit, dev->ctx_bitmap); + DRM_DEBUG("drm_ctxbitmap_next bit : %d\n", bit); + return bit; + } + return -1; +} + +int drm_ctxbitmap_init(drm_device_t *dev) +{ + int i; + int temp; + + dev->ctx_bitmap = (unsigned long *) drm_alloc(PAGE_SIZE, + DRM_MEM_CTXBITMAP); + if(dev->ctx_bitmap == NULL) { + return -ENOMEM; + } + memset((void *) dev->ctx_bitmap, 0, PAGE_SIZE); + for(i = 0; i < DRM_RESERVED_CONTEXTS; i++) { + temp = drm_ctxbitmap_next(dev); + DRM_DEBUG("drm_ctxbitmap_init : %d\n", temp); + } + + return 0; +} + +void drm_ctxbitmap_cleanup(drm_device_t *dev) +{ + drm_free((void *)dev->ctx_bitmap, PAGE_SIZE, + DRM_MEM_CTXBITMAP); +} + diff -urN linux-2.4.10/drivers/char/drm-4.0/dma.c linux-2.4.10-lia/drivers/char/drm-4.0/dma.c --- linux-2.4.10/drivers/char/drm-4.0/dma.c Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/dma.c Wed Aug 15 20:52:11 2001 @@ -0,0 +1,546 @@ +/* dma.c -- DMA IOCTL and function support -*- linux-c -*- + * Created: Fri Mar 19 14:30:16 1999 by faith@precisioninsight.com + * + * Copyright 1999, 2000 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rickard E. (Rik) Faith + * + */ + +#define __NO_VERSION__ +#include "drmP.h" + +#include /* For task queue support */ + +void drm_dma_setup(drm_device_t *dev) +{ + int i; + + if (!(dev->dma = drm_alloc(sizeof(*dev->dma), DRM_MEM_DRIVER))) { + printk(KERN_ERR "drm_dma_setup: can't drm_alloc dev->dma"); + return; + } + memset(dev->dma, 0, sizeof(*dev->dma)); + for (i = 0; i <= DRM_MAX_ORDER; i++) + memset(&dev->dma->bufs[i], 0, sizeof(dev->dma->bufs[0])); +} + +void drm_dma_takedown(drm_device_t *dev) +{ + drm_device_dma_t *dma = dev->dma; + int i, j; + + if (!dma) return; + + /* Clear dma buffers */ + for (i = 0; i <= DRM_MAX_ORDER; i++) { + if (dma->bufs[i].seg_count) { + DRM_DEBUG("order %d: buf_count = %d," + " seg_count = %d\n", + i, + dma->bufs[i].buf_count, + dma->bufs[i].seg_count); + for (j = 0; j < dma->bufs[i].seg_count; j++) { + drm_free_pages(dma->bufs[i].seglist[j], + dma->bufs[i].page_order, + DRM_MEM_DMA); + } + drm_free(dma->bufs[i].seglist, + dma->bufs[i].seg_count + * sizeof(*dma->bufs[0].seglist), + DRM_MEM_SEGS); + } + if(dma->bufs[i].buf_count) { + for(j = 0; j < dma->bufs[i].buf_count; j++) { + if(dma->bufs[i].buflist[j].dev_private) { + drm_free(dma->bufs[i].buflist[j].dev_private, + dma->bufs[i].buflist[j].dev_priv_size, + DRM_MEM_BUFS); + } + } + drm_free(dma->bufs[i].buflist, + dma->bufs[i].buf_count * + sizeof(*dma->bufs[0].buflist), + DRM_MEM_BUFS); + drm_freelist_destroy(&dma->bufs[i].freelist); + } + } + + if (dma->buflist) { + drm_free(dma->buflist, + dma->buf_count * sizeof(*dma->buflist), + DRM_MEM_BUFS); + } + + if (dma->pagelist) { + drm_free(dma->pagelist, + dma->page_count * sizeof(*dma->pagelist), + DRM_MEM_PAGES); + } + drm_free(dev->dma, sizeof(*dev->dma), DRM_MEM_DRIVER); + dev->dma = NULL; +} + +#if DRM_DMA_HISTOGRAM +/* This is slow, but is useful for debugging. */ +int drm_histogram_slot(unsigned long count) +{ + int value = DRM_DMA_HISTOGRAM_INITIAL; + int slot; + + for (slot = 0; + slot < DRM_DMA_HISTOGRAM_SLOTS; + ++slot, value = DRM_DMA_HISTOGRAM_NEXT(value)) { + if (count < value) return slot; + } + return DRM_DMA_HISTOGRAM_SLOTS - 1; +} + +void drm_histogram_compute(drm_device_t *dev, drm_buf_t *buf) +{ + cycles_t queued_to_dispatched; + cycles_t dispatched_to_completed; + cycles_t completed_to_freed; + int q2d, d2c, c2f, q2c, q2f; + + if (buf->time_queued) { + queued_to_dispatched = (buf->time_dispatched + - buf->time_queued); + dispatched_to_completed = (buf->time_completed + - buf->time_dispatched); + completed_to_freed = (buf->time_freed + - buf->time_completed); + + q2d = drm_histogram_slot(queued_to_dispatched); + d2c = drm_histogram_slot(dispatched_to_completed); + c2f = drm_histogram_slot(completed_to_freed); + + q2c = drm_histogram_slot(queued_to_dispatched + + dispatched_to_completed); + q2f = drm_histogram_slot(queued_to_dispatched + + dispatched_to_completed + + completed_to_freed); + + atomic_inc(&dev->histo.total); + atomic_inc(&dev->histo.queued_to_dispatched[q2d]); + atomic_inc(&dev->histo.dispatched_to_completed[d2c]); + atomic_inc(&dev->histo.completed_to_freed[c2f]); + + atomic_inc(&dev->histo.queued_to_completed[q2c]); + atomic_inc(&dev->histo.queued_to_freed[q2f]); + + } + buf->time_queued = 0; + buf->time_dispatched = 0; + buf->time_completed = 0; + buf->time_freed = 0; +} +#endif + +void drm_free_buffer(drm_device_t *dev, drm_buf_t *buf) +{ + drm_device_dma_t *dma = dev->dma; + + if (!buf) return; + + buf->waiting = 0; + buf->pending = 0; + buf->pid = 0; + buf->used = 0; +#if DRM_DMA_HISTOGRAM + buf->time_completed = get_cycles(); +#endif + if (waitqueue_active(&buf->dma_wait)) { + wake_up_interruptible(&buf->dma_wait); + } else { + /* If processes are waiting, the last one + to wake will put the buffer on the free + list. If no processes are waiting, we + put the buffer on the freelist here. */ + drm_freelist_put(dev, &dma->bufs[buf->order].freelist, buf); + } +} + +void drm_reclaim_buffers(drm_device_t *dev, pid_t pid) +{ + drm_device_dma_t *dma = dev->dma; + int i; + + if (!dma) return; + for (i = 0; i < dma->buf_count; i++) { + if (dma->buflist[i]->pid == pid) { + switch (dma->buflist[i]->list) { + case DRM_LIST_NONE: + drm_free_buffer(dev, dma->buflist[i]); + break; + case DRM_LIST_WAIT: + dma->buflist[i]->list = DRM_LIST_RECLAIM; + break; + default: + /* Buffer already on hardware. */ + break; + } + } + } +} + +int drm_context_switch(drm_device_t *dev, int old, int new) +{ + char buf[64]; + drm_queue_t *q; + + atomic_inc(&dev->total_ctx); + + if (test_and_set_bit(0, &dev->context_flag)) { + DRM_ERROR("Reentering -- FIXME\n"); + return -EBUSY; + } + +#if DRM_DMA_HISTOGRAM + dev->ctx_start = get_cycles(); +#endif + + DRM_DEBUG("Context switch from %d to %d\n", old, new); + + if (new >= dev->queue_count) { + clear_bit(0, &dev->context_flag); + return -EINVAL; + } + + if (new == dev->last_context) { + clear_bit(0, &dev->context_flag); + return 0; + } + + q = dev->queuelist[new]; + atomic_inc(&q->use_count); + if (atomic_read(&q->use_count) == 1) { + atomic_dec(&q->use_count); + clear_bit(0, &dev->context_flag); + return -EINVAL; + } + + if (drm_flags & DRM_FLAG_NOCTX) { + drm_context_switch_complete(dev, new); + } else { + sprintf(buf, "C %d %d\n", old, new); + drm_write_string(dev, buf); + } + + atomic_dec(&q->use_count); + + return 0; +} + +int drm_context_switch_complete(drm_device_t *dev, int new) +{ + drm_device_dma_t *dma = dev->dma; + + dev->last_context = new; /* PRE/POST: This is the _only_ writer. */ + dev->last_switch = jiffies; + + if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { + DRM_ERROR("Lock isn't held after context switch\n"); + } + + if (!dma || !(dma->next_buffer && dma->next_buffer->while_locked)) { + if (drm_lock_free(dev, &dev->lock.hw_lock->lock, + DRM_KERNEL_CONTEXT)) { + DRM_ERROR("Cannot free lock\n"); + } + } + +#if DRM_DMA_HISTOGRAM + atomic_inc(&dev->histo.ctx[drm_histogram_slot(get_cycles() + - dev->ctx_start)]); + +#endif + clear_bit(0, &dev->context_flag); + wake_up_interruptible(&dev->context_wait); + + return 0; +} + +void drm_clear_next_buffer(drm_device_t *dev) +{ + drm_device_dma_t *dma = dev->dma; + + dma->next_buffer = NULL; + if (dma->next_queue && !DRM_BUFCOUNT(&dma->next_queue->waitlist)) { + wake_up_interruptible(&dma->next_queue->flush_queue); + } + dma->next_queue = NULL; +} + + +int drm_select_queue(drm_device_t *dev, void (*wrapper)(unsigned long)) +{ + int i; + int candidate = -1; + int j = jiffies; + + if (!dev) { + DRM_ERROR("No device\n"); + return -1; + } + if (!dev->queuelist || !dev->queuelist[DRM_KERNEL_CONTEXT]) { + /* This only happens between the time the + interrupt is initialized and the time + the queues are initialized. */ + return -1; + } + + /* Doing "while locked" DMA? */ + if (DRM_WAITCOUNT(dev, DRM_KERNEL_CONTEXT)) { + return DRM_KERNEL_CONTEXT; + } + + /* If there are buffers on the last_context + queue, and we have not been executing + this context very long, continue to + execute this context. */ + if (dev->last_switch <= j + && dev->last_switch + DRM_TIME_SLICE > j + && DRM_WAITCOUNT(dev, dev->last_context)) { + return dev->last_context; + } + + /* Otherwise, find a candidate */ + for (i = dev->last_checked + 1; i < dev->queue_count; i++) { + if (DRM_WAITCOUNT(dev, i)) { + candidate = dev->last_checked = i; + break; + } + } + + if (candidate < 0) { + for (i = 0; i < dev->queue_count; i++) { + if (DRM_WAITCOUNT(dev, i)) { + candidate = dev->last_checked = i; + break; + } + } + } + + if (wrapper + && candidate >= 0 + && candidate != dev->last_context + && dev->last_switch <= j + && dev->last_switch + DRM_TIME_SLICE > j) { + if (dev->timer.expires != dev->last_switch + DRM_TIME_SLICE) { + del_timer(&dev->timer); + dev->timer.function = wrapper; + dev->timer.data = (unsigned long)dev; + dev->timer.expires = dev->last_switch+DRM_TIME_SLICE; + add_timer(&dev->timer); + } + return -1; + } + + return candidate; +} + + +int drm_dma_enqueue(drm_device_t *dev, drm_dma_t *d) +{ + int i; + drm_queue_t *q; + drm_buf_t *buf; + int idx; + int while_locked = 0; + drm_device_dma_t *dma = dev->dma; + DECLARE_WAITQUEUE(entry, current); + + DRM_DEBUG("%d\n", d->send_count); + + if (d->flags & _DRM_DMA_WHILE_LOCKED) { + int context = dev->lock.hw_lock->lock; + + if (!_DRM_LOCK_IS_HELD(context)) { + DRM_ERROR("No lock held during \"while locked\"" + " request\n"); + return -EINVAL; + } + if (d->context != _DRM_LOCKING_CONTEXT(context) + && _DRM_LOCKING_CONTEXT(context) != DRM_KERNEL_CONTEXT) { + DRM_ERROR("Lock held by %d while %d makes" + " \"while locked\" request\n", + _DRM_LOCKING_CONTEXT(context), + d->context); + return -EINVAL; + } + q = dev->queuelist[DRM_KERNEL_CONTEXT]; + while_locked = 1; + } else { + q = dev->queuelist[d->context]; + } + + + atomic_inc(&q->use_count); + if (atomic_read(&q->block_write)) { + add_wait_queue(&q->write_queue, &entry); + atomic_inc(&q->block_count); + for (;;) { + current->state = TASK_INTERRUPTIBLE; + if (!atomic_read(&q->block_write)) break; + schedule(); + if (signal_pending(current)) { + atomic_dec(&q->use_count); + remove_wait_queue(&q->write_queue, &entry); + return -EINTR; + } + } + atomic_dec(&q->block_count); + current->state = TASK_RUNNING; + remove_wait_queue(&q->write_queue, &entry); + } + + for (i = 0; i < d->send_count; i++) { + idx = d->send_indices[i]; + if (idx < 0 || idx >= dma->buf_count) { + atomic_dec(&q->use_count); + DRM_ERROR("Index %d (of %d max)\n", + d->send_indices[i], dma->buf_count - 1); + return -EINVAL; + } + buf = dma->buflist[ idx ]; + if (buf->pid != current->pid) { + atomic_dec(&q->use_count); + DRM_ERROR("Process %d using buffer owned by %d\n", + current->pid, buf->pid); + return -EINVAL; + } + if (buf->list != DRM_LIST_NONE) { + atomic_dec(&q->use_count); + DRM_ERROR("Process %d using buffer %d on list %d\n", + current->pid, buf->idx, buf->list); + } + buf->used = d->send_sizes[i]; + buf->while_locked = while_locked; + buf->context = d->context; + if (!buf->used) { + DRM_ERROR("Queueing 0 length buffer\n"); + } + if (buf->pending) { + atomic_dec(&q->use_count); + DRM_ERROR("Queueing pending buffer:" + " buffer %d, offset %d\n", + d->send_indices[i], i); + return -EINVAL; + } + if (buf->waiting) { + atomic_dec(&q->use_count); + DRM_ERROR("Queueing waiting buffer:" + " buffer %d, offset %d\n", + d->send_indices[i], i); + return -EINVAL; + } + buf->waiting = 1; + if (atomic_read(&q->use_count) == 1 + || atomic_read(&q->finalization)) { + drm_free_buffer(dev, buf); + } else { + drm_waitlist_put(&q->waitlist, buf); + atomic_inc(&q->total_queued); + } + } + atomic_dec(&q->use_count); + + return 0; +} + +static int drm_dma_get_buffers_of_order(drm_device_t *dev, drm_dma_t *d, + int order) +{ + int i; + drm_buf_t *buf; + drm_device_dma_t *dma = dev->dma; + + for (i = d->granted_count; i < d->request_count; i++) { + buf = drm_freelist_get(&dma->bufs[order].freelist, + d->flags & _DRM_DMA_WAIT); + if (!buf) break; + if (buf->pending || buf->waiting) { + DRM_ERROR("Free buffer %d in use by %d (w%d, p%d)\n", + buf->idx, + buf->pid, + buf->waiting, + buf->pending); + } + buf->pid = current->pid; + if (copy_to_user(&d->request_indices[i], + &buf->idx, + sizeof(buf->idx))) + return -EFAULT; + + if (copy_to_user(&d->request_sizes[i], + &buf->total, + sizeof(buf->total))) + return -EFAULT; + + ++d->granted_count; + } + return 0; +} + + +int drm_dma_get_buffers(drm_device_t *dev, drm_dma_t *dma) +{ + int order; + int retcode = 0; + int tmp_order; + + order = drm_order(dma->request_size); + + dma->granted_count = 0; + retcode = drm_dma_get_buffers_of_order(dev, dma, order); + + if (dma->granted_count < dma->request_count + && (dma->flags & _DRM_DMA_SMALLER_OK)) { + for (tmp_order = order - 1; + !retcode + && dma->granted_count < dma->request_count + && tmp_order >= DRM_MIN_ORDER; + --tmp_order) { + + retcode = drm_dma_get_buffers_of_order(dev, dma, + tmp_order); + } + } + + if (dma->granted_count < dma->request_count + && (dma->flags & _DRM_DMA_LARGER_OK)) { + for (tmp_order = order + 1; + !retcode + && dma->granted_count < dma->request_count + && tmp_order <= DRM_MAX_ORDER; + ++tmp_order) { + + retcode = drm_dma_get_buffers_of_order(dev, dma, + tmp_order); + } + } + return 0; +} diff -urN linux-2.4.10/drivers/char/drm-4.0/drawable.c linux-2.4.10-lia/drivers/char/drm-4.0/drawable.c --- linux-2.4.10/drivers/char/drm-4.0/drawable.c Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/drawable.c Wed Aug 15 20:52:11 2001 @@ -0,0 +1,51 @@ +/* drawable.c -- IOCTLs for drawables -*- linux-c -*- + * Created: Tue Feb 2 08:37:54 1999 by faith@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rickard E. (Rik) Faith + * + */ + +#define __NO_VERSION__ +#include "drmP.h" + +int drm_adddraw(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_draw_t draw; + + draw.handle = 0; /* NOOP */ + DRM_DEBUG("%d\n", draw.handle); + if (copy_to_user((drm_draw_t *)arg, &draw, sizeof(draw))) + return -EFAULT; + return 0; +} + +int drm_rmdraw(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + return 0; /* NOOP */ +} diff -urN linux-2.4.10/drivers/char/drm-4.0/drm.h linux-2.4.10-lia/drivers/char/drm-4.0/drm.h --- linux-2.4.10/drivers/char/drm-4.0/drm.h Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/drm.h Mon Aug 20 18:09:34 2001 @@ -0,0 +1,414 @@ +/* drm.h -- Header for Direct Rendering Manager -*- linux-c -*- + * Created: Mon Jan 4 10:05:05 1999 by faith@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rickard E. (Rik) Faith + * + * Acknowledgements: + * Dec 1999, Richard Henderson , move to generic cmpxchg. + * + */ + +#ifndef _DRM_H_ +#define _DRM_H_ + +#include +#if defined(__linux__) +#include /* For _IO* macros */ +#define DRM_IOCTL_NR(n) _IOC_NR(n) +#elif defined(__FreeBSD__) +#include +#define DRM_IOCTL_NR(n) ((n) & 0xff) +#endif + +#define DRM_PROC_DEVICES "/proc/devices" +#define DRM_PROC_MISC "/proc/misc" +#define DRM_PROC_DRM "/proc/drm" +#define DRM_DEV_DRM "/dev/drm" +#define DRM_DEV_MODE (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP) +#define DRM_DEV_UID 0 +#define DRM_DEV_GID 0 + + +#define DRM_NAME "drm" /* Name in kernel, /dev, and /proc */ +#define DRM_MIN_ORDER 5 /* At least 2^5 bytes = 32 bytes */ +#define DRM_MAX_ORDER 22 /* Up to 2^22 bytes = 4MB */ +#define DRM_RAM_PERCENT 10 /* How much system ram can we lock? */ + +#define _DRM_LOCK_HELD 0x80000000 /* Hardware lock is held */ +#define _DRM_LOCK_CONT 0x40000000 /* Hardware lock is contended */ +#define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD) +#define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT) +#define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT)) + +typedef unsigned long drm_handle_t; +typedef unsigned int drm_context_t; +typedef unsigned int drm_drawable_t; +typedef unsigned int drm_magic_t; + +/* Warning: If you change this structure, make sure you change + * XF86DRIClipRectRec in the server as well */ + +typedef struct drm_clip_rect { + unsigned short x1; + unsigned short y1; + unsigned short x2; + unsigned short y2; +} drm_clip_rect_t; + +/* Seperate include files for the i810/mga/r128 specific structures */ +#include "mga_drm.h" +#include "i810_drm.h" +#include "r128_drm.h" +#include "radeon_drm.h" +#ifdef CONFIG_DRM40_SIS +#include "sis_drm.h" +#endif + +typedef struct drm_version { + int version_major; /* Major version */ + int version_minor; /* Minor version */ + int version_patchlevel;/* Patch level */ + size_t name_len; /* Length of name buffer */ + char *name; /* Name of driver */ + size_t date_len; /* Length of date buffer */ + char *date; /* User-space buffer to hold date */ + size_t desc_len; /* Length of desc buffer */ + char *desc; /* User-space buffer to hold desc */ +} drm_version_t; + +typedef struct drm_unique { + size_t unique_len; /* Length of unique */ + char *unique; /* Unique name for driver instantiation */ +} drm_unique_t; + +typedef struct drm_list { + int count; /* Length of user-space structures */ + drm_version_t *version; +} drm_list_t; + +typedef struct drm_block { + int unused; +} drm_block_t; + +typedef struct drm_control { + enum { + DRM_ADD_COMMAND, + DRM_RM_COMMAND, + DRM_INST_HANDLER, + DRM_UNINST_HANDLER + } func; + int irq; +} drm_control_t; + +typedef enum drm_map_type { + _DRM_FRAME_BUFFER = 0, /* WC (no caching), no core dump */ + _DRM_REGISTERS = 1, /* no caching, no core dump */ + _DRM_SHM = 2, /* shared, cached */ + _DRM_AGP = 3 /* AGP/GART */ +} drm_map_type_t; + +typedef enum drm_map_flags { + _DRM_RESTRICTED = 0x01, /* Cannot be mapped to user-virtual */ + _DRM_READ_ONLY = 0x02, + _DRM_LOCKED = 0x04, /* shared, cached, locked */ + _DRM_KERNEL = 0x08, /* kernel requires access */ + _DRM_WRITE_COMBINING = 0x10, /* use write-combining if available */ + _DRM_CONTAINS_LOCK = 0x20 /* SHM page that contains lock */ +} drm_map_flags_t; + +typedef struct drm_map { + unsigned long offset; /* Requested physical address (0 for SAREA)*/ + unsigned long size; /* Requested physical size (bytes) */ + drm_map_type_t type; /* Type of memory to map */ + drm_map_flags_t flags; /* Flags */ + void *handle; /* User-space: "Handle" to pass to mmap */ + /* Kernel-space: kernel-virtual address */ + int mtrr; /* MTRR slot used */ + /* Private data */ +} drm_map_t; + +typedef enum drm_lock_flags { + _DRM_LOCK_READY = 0x01, /* Wait until hardware is ready for DMA */ + _DRM_LOCK_QUIESCENT = 0x02, /* Wait until hardware quiescent */ + _DRM_LOCK_FLUSH = 0x04, /* Flush this context's DMA queue first */ + _DRM_LOCK_FLUSH_ALL = 0x08, /* Flush all DMA queues first */ + /* These *HALT* flags aren't supported yet + -- they will be used to support the + full-screen DGA-like mode. */ + _DRM_HALT_ALL_QUEUES = 0x10, /* Halt all current and future queues */ + _DRM_HALT_CUR_QUEUES = 0x20 /* Halt all current queues */ +} drm_lock_flags_t; + +typedef struct drm_lock { + int context; + drm_lock_flags_t flags; +} drm_lock_t; + +typedef enum drm_dma_flags { /* These values *MUST* match xf86drm.h */ + /* Flags for DMA buffer dispatch */ + _DRM_DMA_BLOCK = 0x01, /* Block until buffer dispatched. + Note, the buffer may not yet have + been processed by the hardware -- + getting a hardware lock with the + hardware quiescent will ensure + that the buffer has been + processed. */ + _DRM_DMA_WHILE_LOCKED = 0x02, /* Dispatch while lock held */ + _DRM_DMA_PRIORITY = 0x04, /* High priority dispatch */ + + /* Flags for DMA buffer request */ + _DRM_DMA_WAIT = 0x10, /* Wait for free buffers */ + _DRM_DMA_SMALLER_OK = 0x20, /* Smaller-than-requested buffers ok */ + _DRM_DMA_LARGER_OK = 0x40 /* Larger-than-requested buffers ok */ +} drm_dma_flags_t; + +typedef struct drm_buf_desc { + int count; /* Number of buffers of this size */ + int size; /* Size in bytes */ + int low_mark; /* Low water mark */ + int high_mark; /* High water mark */ + enum { + _DRM_PAGE_ALIGN = 0x01, /* Align on page boundaries for DMA */ + _DRM_AGP_BUFFER = 0x02 /* Buffer is in agp space */ + } flags; + unsigned long agp_start; /* Start address of where the agp buffers + * are in the agp aperture */ +} drm_buf_desc_t; + +typedef struct drm_buf_info { + int count; /* Entries in list */ + drm_buf_desc_t *list; +} drm_buf_info_t; + +typedef struct drm_buf_free { + int count; + int *list; +} drm_buf_free_t; + +typedef struct drm_buf_pub { + int idx; /* Index into master buflist */ + int total; /* Buffer size */ + int used; /* Amount of buffer in use (for DMA) */ + void *address; /* Address of buffer */ +} drm_buf_pub_t; + +typedef struct drm_buf_map { + int count; /* Length of buflist */ + void *virtual; /* Mmaped area in user-virtual */ + drm_buf_pub_t *list; /* Buffer information */ +} drm_buf_map_t; + +typedef struct drm_dma { + /* Indices here refer to the offset into + buflist in drm_buf_get_t. */ + int context; /* Context handle */ + int send_count; /* Number of buffers to send */ + int *send_indices; /* List of handles to buffers */ + int *send_sizes; /* Lengths of data to send */ + drm_dma_flags_t flags; /* Flags */ + int request_count; /* Number of buffers requested */ + int request_size; /* Desired size for buffers */ + int *request_indices; /* Buffer information */ + int *request_sizes; + int granted_count; /* Number of buffers granted */ +} drm_dma_t; + +typedef enum { + _DRM_CONTEXT_PRESERVED = 0x01, + _DRM_CONTEXT_2DONLY = 0x02 +} drm_ctx_flags_t; + +typedef struct drm_ctx { + drm_context_t handle; + drm_ctx_flags_t flags; +} drm_ctx_t; + +typedef struct drm_ctx_res { + int count; + drm_ctx_t *contexts; +} drm_ctx_res_t; + +typedef struct drm_draw { + drm_drawable_t handle; +} drm_draw_t; + +typedef struct drm_auth { + drm_magic_t magic; +} drm_auth_t; + +typedef struct drm_irq_busid { + int irq; + int busnum; + int devnum; + int funcnum; +} drm_irq_busid_t; + +typedef struct drm_agp_mode { + unsigned long mode; +} drm_agp_mode_t; + + /* For drm_agp_alloc -- allocated a buffer */ +typedef struct drm_agp_buffer { + unsigned long size; /* In bytes -- will round to page boundary */ + unsigned long handle; /* Used for BIND/UNBIND ioctls */ + unsigned long type; /* Type of memory to allocate */ + unsigned long physical; /* Physical used by i810 */ +} drm_agp_buffer_t; + + /* For drm_agp_bind */ +typedef struct drm_agp_binding { + unsigned long handle; /* From drm_agp_buffer */ + unsigned long offset; /* In bytes -- will round to page boundary */ +} drm_agp_binding_t; + +typedef struct drm_agp_info { + int agp_version_major; + int agp_version_minor; + unsigned long mode; + unsigned long aperture_base; /* physical address */ + unsigned long aperture_size; /* bytes */ + unsigned long memory_allowed; /* bytes */ + unsigned long memory_used; + + /* PCI information */ + unsigned short id_vendor; + unsigned short id_device; +} drm_agp_info_t; + +#define DRM_IOCTL_BASE 'd' +#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr) +#define DRM_IOR(nr,size) _IOR(DRM_IOCTL_BASE,nr,size) +#define DRM_IOW(nr,size) _IOW(DRM_IOCTL_BASE,nr,size) +#define DRM_IOWR(nr,size) _IOWR(DRM_IOCTL_BASE,nr,size) + + +#define DRM_IOCTL_VERSION DRM_IOWR(0x00, drm_version_t) +#define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, drm_unique_t) +#define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, drm_auth_t) +#define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, drm_irq_busid_t) + +#define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, drm_unique_t) +#define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, drm_auth_t) +#define DRM_IOCTL_BLOCK DRM_IOWR(0x12, drm_block_t) +#define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, drm_block_t) +#define DRM_IOCTL_CONTROL DRM_IOW( 0x14, drm_control_t) +#define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, drm_map_t) +#define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, drm_buf_desc_t) +#define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, drm_buf_desc_t) +#define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, drm_buf_info_t) +#define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, drm_buf_map_t) +#define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, drm_buf_free_t) + +#define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, drm_ctx_t) +#define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, drm_ctx_t) +#define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, drm_ctx_t) +#define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, drm_ctx_t) +#define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, drm_ctx_t) +#define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, drm_ctx_t) +#define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, drm_ctx_res_t) +#define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, drm_draw_t) +#define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, drm_draw_t) +#define DRM_IOCTL_DMA DRM_IOWR(0x29, drm_dma_t) +#define DRM_IOCTL_LOCK DRM_IOW( 0x2a, drm_lock_t) +#define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, drm_lock_t) +#define DRM_IOCTL_FINISH DRM_IOW( 0x2c, drm_lock_t) + +#define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30) +#define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31) +#define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, drm_agp_mode_t) +#define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, drm_agp_info_t) +#define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, drm_agp_buffer_t) +#define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, drm_agp_buffer_t) +#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, drm_agp_binding_t) +#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, drm_agp_binding_t) + +/* Mga specific ioctls */ +#define DRM_IOCTL_MGA_INIT DRM_IOW( 0x40, drm_mga_init_t) +#define DRM_IOCTL_MGA_SWAP DRM_IOW( 0x41, drm_mga_swap_t) +#define DRM_IOCTL_MGA_CLEAR DRM_IOW( 0x42, drm_mga_clear_t) +#define DRM_IOCTL_MGA_ILOAD DRM_IOW( 0x43, drm_mga_iload_t) +#define DRM_IOCTL_MGA_VERTEX DRM_IOW( 0x44, drm_mga_vertex_t) +#define DRM_IOCTL_MGA_FLUSH DRM_IOW( 0x45, drm_lock_t ) +#define DRM_IOCTL_MGA_INDICES DRM_IOW( 0x46, drm_mga_indices_t) +#define DRM_IOCTL_MGA_BLIT DRM_IOW( 0x47, drm_mga_blit_t) + +/* I810 specific ioctls */ +#define DRM_IOCTL_I810_INIT DRM_IOW( 0x40, drm_i810_init_t) +#define DRM_IOCTL_I810_VERTEX DRM_IOW( 0x41, drm_i810_vertex_t) +#define DRM_IOCTL_I810_CLEAR DRM_IOW( 0x42, drm_i810_clear_t) +#define DRM_IOCTL_I810_FLUSH DRM_IO( 0x43) +#define DRM_IOCTL_I810_GETAGE DRM_IO( 0x44) +#define DRM_IOCTL_I810_GETBUF DRM_IOWR(0x45, drm_i810_dma_t) +#define DRM_IOCTL_I810_SWAP DRM_IO( 0x46) +#define DRM_IOCTL_I810_COPY DRM_IOW( 0x47, drm_i810_copy_t) +#define DRM_IOCTL_I810_DOCOPY DRM_IO( 0x48) + +/* Rage 128 specific ioctls */ +#define DRM_IOCTL_R128_INIT DRM_IOW( 0x40, drm_r128_init_t) +#define DRM_IOCTL_R128_CCE_START DRM_IO( 0x41) +#define DRM_IOCTL_R128_CCE_STOP DRM_IOW( 0x42, drm_r128_cce_stop_t) +#define DRM_IOCTL_R128_CCE_RESET DRM_IO( 0x43) +#define DRM_IOCTL_R128_CCE_IDLE DRM_IO( 0x44) +#define DRM_IOCTL_R128_RESET DRM_IO( 0x46) +#define DRM_IOCTL_R128_SWAP DRM_IO( 0x47) +#define DRM_IOCTL_R128_CLEAR DRM_IOW( 0x48, drm_r128_clear_t) +#define DRM_IOCTL_R128_VERTEX DRM_IOW( 0x49, drm_r128_vertex_t) +#define DRM_IOCTL_R128_INDICES DRM_IOW( 0x4a, drm_r128_indices_t) +#define DRM_IOCTL_R128_BLIT DRM_IOW( 0x4b, drm_r128_blit_t) +#define DRM_IOCTL_R128_DEPTH DRM_IOW( 0x4c, drm_r128_depth_t) +#define DRM_IOCTL_R128_STIPPLE DRM_IOW( 0x4d, drm_r128_stipple_t) +#define DRM_IOCTL_R128_PACKET DRM_IOWR(0x4e, drm_r128_packet_t) + +/* Radeon specific ioctls */ +#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( 0x40, drm_radeon_init_t) +#define DRM_IOCTL_RADEON_CP_START DRM_IO( 0x41) +#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( 0x42, drm_radeon_cp_stop_t) +#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( 0x43) +#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( 0x44) +#define DRM_IOCTL_RADEON_RESET DRM_IO( 0x45) +#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( 0x46, drm_radeon_fullscreen_t) +#define DRM_IOCTL_RADEON_SWAP DRM_IO( 0x47) +#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( 0x48, drm_radeon_clear_t) +#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( 0x49, drm_radeon_vertex_t) +#define DRM_IOCTL_RADEON_INDICES DRM_IOW( 0x4a, drm_radeon_indices_t) +#define DRM_IOCTL_RADEON_BLIT DRM_IOW( 0x4b, drm_radeon_blit_t) +#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( 0x4c, drm_radeon_stipple_t) +#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(0x4d, drm_radeon_indirect_t) + +#ifdef CONFIG_DRM40_SIS +/* SiS specific ioctls */ +#define SIS_IOCTL_FB_ALLOC DRM_IOWR(0x44, drm_sis_mem_t) +#define SIS_IOCTL_FB_FREE DRM_IOW( 0x45, drm_sis_mem_t) +#define SIS_IOCTL_AGP_INIT DRM_IOWR(0x53, drm_sis_agp_t) +#define SIS_IOCTL_AGP_ALLOC DRM_IOWR(0x54, drm_sis_mem_t) +#define SIS_IOCTL_AGP_FREE DRM_IOW( 0x55, drm_sis_mem_t) +#define SIS_IOCTL_FLIP DRM_IOW( 0x48, drm_sis_flip_t) +#define SIS_IOCTL_FLIP_INIT DRM_IO( 0x49) +#define SIS_IOCTL_FLIP_FINAL DRM_IO( 0x50) +#endif + +#endif diff -urN linux-2.4.10/drivers/char/drm-4.0/drmP.h linux-2.4.10-lia/drivers/char/drm-4.0/drmP.h --- linux-2.4.10/drivers/char/drm-4.0/drmP.h Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/drmP.h Mon Sep 24 22:58:44 2001 @@ -0,0 +1,839 @@ +/* drmP.h -- Private header for Direct Rendering Manager -*- linux-c -*- + * Created: Mon Jan 4 10:05:05 1999 by faith@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rickard E. (Rik) Faith + * + */ + +#ifndef _DRM_P_H_ +#define _DRM_P_H_ + +#ifdef __KERNEL__ +#ifdef __alpha__ +/* add include of current.h so that "current" is defined + * before static inline funcs in wait.h. Doing this so we + * can build the DRM (part of PI DRI). 4/21/2000 S + B */ +#include +#endif /* __alpha__ */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include /* For (un)lock_kernel */ +#include +#ifdef __alpha__ +#include /* For pte_wrprotect */ +#endif +#include +#include +#include +#ifdef CONFIG_MTRR +#include +#endif +#if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE) +#include +#include +#endif +#if LINUX_VERSION_CODE >= 0x020100 /* KERNEL_VERSION(2,1,0) */ +#include +#include +#endif +#if LINUX_VERSION_CODE < 0x020400 +#include "compat-pre24.h" +#endif +#include "drm.h" + +#define DRM_DEBUG_CODE 2 /* Include debugging code (if > 1, then + also include looping detection. */ +#define DRM_DMA_HISTOGRAM 1 /* Make histogram of DMA latency. */ + +#define DRM_HASH_SIZE 16 /* Size of key hash table */ +#define DRM_KERNEL_CONTEXT 0 /* Change drm_resctx if changed */ +#define DRM_RESERVED_CONTEXTS 1 /* Change drm_resctx if changed */ +#define DRM_LOOPING_LIMIT 5000000 +#define DRM_BSZ 1024 /* Buffer size for /dev/drm? output */ +#define DRM_TIME_SLICE (HZ/20) /* Time slice for GLXContexts */ +#define DRM_LOCK_SLICE 1 /* Time slice for lock, in jiffies */ + +#define DRM_FLAG_DEBUG 0x01 +#define DRM_FLAG_NOCTX 0x02 + +#define DRM_MEM_DMA 0 +#define DRM_MEM_SAREA 1 +#define DRM_MEM_DRIVER 2 +#define DRM_MEM_MAGIC 3 +#define DRM_MEM_IOCTLS 4 +#define DRM_MEM_MAPS 5 +#define DRM_MEM_VMAS 6 +#define DRM_MEM_BUFS 7 +#define DRM_MEM_SEGS 8 +#define DRM_MEM_PAGES 9 +#define DRM_MEM_FILES 10 +#define DRM_MEM_QUEUES 11 +#define DRM_MEM_CMDS 12 +#define DRM_MEM_MAPPINGS 13 +#define DRM_MEM_BUFLISTS 14 +#define DRM_MEM_AGPLISTS 15 +#define DRM_MEM_TOTALAGP 16 +#define DRM_MEM_BOUNDAGP 17 +#define DRM_MEM_CTXBITMAP 18 + +#define DRM_MAX_CTXBITMAP (PAGE_SIZE * 8) + + /* Backward compatibility section */ + /* _PAGE_WT changed to _PAGE_PWT in 2.2.6 */ +#ifndef _PAGE_PWT +#define _PAGE_PWT _PAGE_WT +#endif + /* Wait queue declarations changed in 2.3.1 */ +#ifndef DECLARE_WAITQUEUE +#define DECLARE_WAITQUEUE(w,c) struct wait_queue w = { c, NULL } +typedef struct wait_queue *wait_queue_head_t; +#define init_waitqueue_head(q) *q = NULL; +#endif + + /* _PAGE_4M changed to _PAGE_PSE in 2.3.23 */ +#ifndef _PAGE_PSE +#define _PAGE_PSE _PAGE_4M +#endif + + /* vm_offset changed to vm_pgoff in 2.3.25 */ +#if LINUX_VERSION_CODE < 0x020319 +#define VM_OFFSET(vma) ((vma)->vm_offset) +#else +#define VM_OFFSET(vma) ((vma)->vm_pgoff << PAGE_SHIFT) +#endif + + /* *_nopage return values defined in 2.3.26 */ +#ifndef NOPAGE_SIGBUS +#define NOPAGE_SIGBUS 0 +#endif +#ifndef NOPAGE_OOM +#define NOPAGE_OOM 0 +#endif + + /* module_init/module_exit added in 2.3.13 */ +#ifndef module_init +#define module_init(x) int init_module(void) { return x(); } +#endif +#ifndef module_exit +#define module_exit(x) void cleanup_module(void) { x(); } +#endif + + /* Generic cmpxchg added in 2.3.x */ +#ifndef __HAVE_ARCH_CMPXCHG + /* Include this here so that driver can be + used with older kernels. */ +#if defined(__alpha__) +static __inline__ unsigned long +__cmpxchg_u32(volatile int *m, int old, int new) +{ + unsigned long prev, cmp; + + __asm__ __volatile__( + "1: ldl_l %0,%2\n" + " cmpeq %0,%3,%1\n" + " beq %1,2f\n" + " mov %4,%1\n" + " stl_c %1,%2\n" + " beq %1,3f\n" + "2: mb\n" + ".subsection 2\n" + "3: br 1b\n" + ".previous" + : "=&r"(prev), "=&r"(cmp), "=m"(*m) + : "r"((long) old), "r"(new), "m"(*m)); + + return prev; +} + +static __inline__ unsigned long +__cmpxchg_u64(volatile long *m, unsigned long old, unsigned long new) +{ + unsigned long prev, cmp; + + __asm__ __volatile__( + "1: ldq_l %0,%2\n" + " cmpeq %0,%3,%1\n" + " beq %1,2f\n" + " mov %4,%1\n" + " stq_c %1,%2\n" + " beq %1,3f\n" + "2: mb\n" + ".subsection 2\n" + "3: br 1b\n" + ".previous" + : "=&r"(prev), "=&r"(cmp), "=m"(*m) + : "r"((long) old), "r"(new), "m"(*m)); + + return prev; +} + +static __inline__ unsigned long +__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size) +{ + switch (size) { + case 4: + return __cmpxchg_u32(ptr, old, new); + case 8: + return __cmpxchg_u64(ptr, old, new); + } + return old; +} +#define cmpxchg(ptr,o,n) \ + ({ \ + __typeof__(*(ptr)) _o_ = (o); \ + __typeof__(*(ptr)) _n_ = (n); \ + (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \ + (unsigned long)_n_, sizeof(*(ptr))); \ + }) + +#elif __i386__ +static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old, + unsigned long new, int size) +{ + unsigned long prev; + switch (size) { + case 1: + __asm__ __volatile__(LOCK_PREFIX "cmpxchgb %b1,%2" + : "=a"(prev) + : "q"(new), "m"(*__xg(ptr)), "0"(old) + : "memory"); + return prev; + case 2: + __asm__ __volatile__(LOCK_PREFIX "cmpxchgw %w1,%2" + : "=a"(prev) + : "q"(new), "m"(*__xg(ptr)), "0"(old) + : "memory"); + return prev; + case 4: + __asm__ __volatile__(LOCK_PREFIX "cmpxchgl %1,%2" + : "=a"(prev) + : "q"(new), "m"(*__xg(ptr)), "0"(old) + : "memory"); + return prev; + } + return old; +} + +#define cmpxchg(ptr,o,n) \ + ((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o), \ + (unsigned long)(n),sizeof(*(ptr)))) +#endif /* i386 & alpha */ +#endif + + /* Macros to make printk easier */ +#define DRM_ERROR(fmt, arg...) \ + printk(KERN_ERR "[" DRM_NAME ":" __FUNCTION__ "] *ERROR* " fmt , ##arg) +#define DRM_MEM_ERROR(area, fmt, arg...) \ + printk(KERN_ERR "[" DRM_NAME ":" __FUNCTION__ ":%s] *ERROR* " fmt , \ + drm_mem_stats[area].name , ##arg) +#define DRM_INFO(fmt, arg...) printk(KERN_INFO "[" DRM_NAME "] " fmt , ##arg) + +#if DRM_DEBUG_CODE +#define DRM_DEBUG(fmt, arg...) \ + do { \ + if (drm_flags&DRM_FLAG_DEBUG) \ + printk(KERN_DEBUG \ + "[" DRM_NAME ":" __FUNCTION__ "] " fmt , \ + ##arg); \ + } while (0) +#else +#define DRM_DEBUG(fmt, arg...) do { } while (0) +#endif + +#define DRM_PROC_LIMIT (PAGE_SIZE-80) + +#define DRM_PROC_PRINT(fmt, arg...) \ + len += sprintf(&buf[len], fmt , ##arg); \ + if (len > DRM_PROC_LIMIT) return len; + +#define DRM_PROC_PRINT_RET(ret, fmt, arg...) \ + len += sprintf(&buf[len], fmt , ##arg); \ + if (len > DRM_PROC_LIMIT) { ret; return len; } + + /* Internal types and structures */ +#define DRM_ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0])) +#define DRM_MIN(a,b) ((a)<(b)?(a):(b)) +#define DRM_MAX(a,b) ((a)>(b)?(a):(b)) + +#define DRM_LEFTCOUNT(x) (((x)->rp + (x)->count - (x)->wp) % ((x)->count + 1)) +#define DRM_BUFCOUNT(x) ((x)->count - DRM_LEFTCOUNT(x)) +#define DRM_WAITCOUNT(dev,idx) DRM_BUFCOUNT(&dev->queuelist[idx]->waitlist) + +typedef int drm_ioctl_t(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); + +typedef struct drm_ioctl_desc { + drm_ioctl_t *func; + int auth_needed; + int root_only; +} drm_ioctl_desc_t; + +typedef struct drm_devstate { + pid_t owner; /* X server pid holding x_lock */ + +} drm_devstate_t; + +typedef struct drm_magic_entry { + drm_magic_t magic; + struct drm_file *priv; + struct drm_magic_entry *next; +} drm_magic_entry_t; + +typedef struct drm_magic_head { + struct drm_magic_entry *head; + struct drm_magic_entry *tail; +} drm_magic_head_t; + +typedef struct drm_vma_entry { + struct vm_area_struct *vma; + struct drm_vma_entry *next; + pid_t pid; +} drm_vma_entry_t; + +typedef struct drm_buf { + int idx; /* Index into master buflist */ + int total; /* Buffer size */ + int order; /* log-base-2(total) */ + int used; /* Amount of buffer in use (for DMA) */ + unsigned long offset; /* Byte offset (used internally) */ + void *address; /* Address of buffer */ + unsigned long bus_address; /* Bus address of buffer */ + struct drm_buf *next; /* Kernel-only: used for free list */ + __volatile__ int waiting; /* On kernel DMA queue */ + __volatile__ int pending; /* On hardware DMA queue */ + wait_queue_head_t dma_wait; /* Processes waiting */ + pid_t pid; /* PID of holding process */ + int context; /* Kernel queue for this buffer */ + int while_locked;/* Dispatch this buffer while locked */ + enum { + DRM_LIST_NONE = 0, + DRM_LIST_FREE = 1, + DRM_LIST_WAIT = 2, + DRM_LIST_PEND = 3, + DRM_LIST_PRIO = 4, + DRM_LIST_RECLAIM = 5 + } list; /* Which list we're on */ + +#if DRM_DMA_HISTOGRAM + cycles_t time_queued; /* Queued to kernel DMA queue */ + cycles_t time_dispatched; /* Dispatched to hardware */ + cycles_t time_completed; /* Completed by hardware */ + cycles_t time_freed; /* Back on freelist */ +#endif + + int dev_priv_size; /* Size of buffer private stoarge */ + void *dev_private; /* Per-buffer private storage */ +} drm_buf_t; + +#if DRM_DMA_HISTOGRAM +#define DRM_DMA_HISTOGRAM_SLOTS 9 +#define DRM_DMA_HISTOGRAM_INITIAL 10 +#define DRM_DMA_HISTOGRAM_NEXT(current) ((current)*10) +typedef struct drm_histogram { + atomic_t total; + + atomic_t queued_to_dispatched[DRM_DMA_HISTOGRAM_SLOTS]; + atomic_t dispatched_to_completed[DRM_DMA_HISTOGRAM_SLOTS]; + atomic_t completed_to_freed[DRM_DMA_HISTOGRAM_SLOTS]; + + atomic_t queued_to_completed[DRM_DMA_HISTOGRAM_SLOTS]; + atomic_t queued_to_freed[DRM_DMA_HISTOGRAM_SLOTS]; + + atomic_t dma[DRM_DMA_HISTOGRAM_SLOTS]; + atomic_t schedule[DRM_DMA_HISTOGRAM_SLOTS]; + atomic_t ctx[DRM_DMA_HISTOGRAM_SLOTS]; + atomic_t lacq[DRM_DMA_HISTOGRAM_SLOTS]; + atomic_t lhld[DRM_DMA_HISTOGRAM_SLOTS]; +} drm_histogram_t; +#endif + + /* bufs is one longer than it has to be */ +typedef struct drm_waitlist { + int count; /* Number of possible buffers */ + drm_buf_t **bufs; /* List of pointers to buffers */ + drm_buf_t **rp; /* Read pointer */ + drm_buf_t **wp; /* Write pointer */ + drm_buf_t **end; /* End pointer */ + spinlock_t read_lock; + spinlock_t write_lock; +} drm_waitlist_t; + +typedef struct drm_freelist { + int initialized; /* Freelist in use */ + atomic_t count; /* Number of free buffers */ + drm_buf_t *next; /* End pointer */ + + wait_queue_head_t waiting; /* Processes waiting on free bufs */ + int low_mark; /* Low water mark */ + int high_mark; /* High water mark */ + atomic_t wfh; /* If waiting for high mark */ + spinlock_t lock; +} drm_freelist_t; + +typedef struct drm_buf_entry { + int buf_size; + int buf_count; + drm_buf_t *buflist; + int seg_count; + int page_order; + unsigned long *seglist; + + drm_freelist_t freelist; +} drm_buf_entry_t; + +typedef struct drm_hw_lock { + __volatile__ unsigned int lock; + char padding[60]; /* Pad to cache line */ +} drm_hw_lock_t; + +typedef struct drm_file { + int authenticated; + int minor; + pid_t pid; + uid_t uid; + drm_magic_t magic; + unsigned long ioctl_count; + struct drm_file *next; + struct drm_file *prev; + struct drm_device *dev; + int remove_auth_on_close; +} drm_file_t; + + +typedef struct drm_queue { + atomic_t use_count; /* Outstanding uses (+1) */ + atomic_t finalization; /* Finalization in progress */ + atomic_t block_count; /* Count of processes waiting */ + atomic_t block_read; /* Queue blocked for reads */ + wait_queue_head_t read_queue; /* Processes waiting on block_read */ + atomic_t block_write; /* Queue blocked for writes */ + wait_queue_head_t write_queue; /* Processes waiting on block_write */ + atomic_t total_queued; /* Total queued statistic */ + atomic_t total_flushed;/* Total flushes statistic */ + atomic_t total_locks; /* Total locks statistics */ + drm_ctx_flags_t flags; /* Context preserving and 2D-only */ + drm_waitlist_t waitlist; /* Pending buffers */ + wait_queue_head_t flush_queue; /* Processes waiting until flush */ +} drm_queue_t; + +typedef struct drm_lock_data { + drm_hw_lock_t *hw_lock; /* Hardware lock */ + pid_t pid; /* PID of lock holder (0=kernel) */ + wait_queue_head_t lock_queue; /* Queue of blocked processes */ + unsigned long lock_time; /* Time of last lock in jiffies */ +} drm_lock_data_t; + +typedef struct drm_device_dma { + /* Performance Counters */ + atomic_t total_prio; /* Total DRM_DMA_PRIORITY */ + atomic_t total_bytes; /* Total bytes DMA'd */ + atomic_t total_dmas; /* Total DMA buffers dispatched */ + + atomic_t total_missed_dma; /* Missed drm_do_dma */ + atomic_t total_missed_lock; /* Missed lock in drm_do_dma */ + atomic_t total_missed_free; /* Missed drm_free_this_buffer */ + atomic_t total_missed_sched;/* Missed drm_dma_schedule */ + + atomic_t total_tried; /* Tried next_buffer */ + atomic_t total_hit; /* Sent next_buffer */ + atomic_t total_lost; /* Lost interrupt */ + + drm_buf_entry_t bufs[DRM_MAX_ORDER+1]; + int buf_count; + drm_buf_t **buflist; /* Vector of pointers info bufs */ + int seg_count; + int page_count; + unsigned long *pagelist; + unsigned long byte_count; + enum { + _DRM_DMA_USE_AGP = 0x01 + } flags; + + /* DMA support */ + drm_buf_t *this_buffer; /* Buffer being sent */ + drm_buf_t *next_buffer; /* Selected buffer to send */ + drm_queue_t *next_queue; /* Queue from which buffer selected*/ + wait_queue_head_t waiting; /* Processes waiting on free bufs */ +} drm_device_dma_t; + +#if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE) +typedef struct drm_agp_mem { + unsigned long handle; + agp_memory *memory; + unsigned long bound; /* address */ + int pages; + struct drm_agp_mem *prev; + struct drm_agp_mem *next; +} drm_agp_mem_t; + +typedef struct drm_agp_head { + agp_kern_info agp_info; + const char *chipset; + drm_agp_mem_t *memory; + unsigned long mode; + int enabled; + int acquired; + unsigned long base; + int agp_mtrr; + int cant_use_aperture; + unsigned long page_mask; +} drm_agp_head_t; +#endif + +typedef struct drm_sigdata { + int context; + drm_hw_lock_t *lock; +} drm_sigdata_t; + +typedef struct drm_device { + const char *name; /* Simple driver name */ + char *unique; /* Unique identifier: e.g., busid */ + int unique_len; /* Length of unique field */ + dev_t device; /* Device number for mknod */ + char *devname; /* For /proc/interrupts */ + + int blocked; /* Blocked due to VC switch? */ + struct proc_dir_entry *root; /* Root for this device's entries */ + + /* Locks */ + spinlock_t count_lock; /* For inuse, open_count, buf_use */ + struct semaphore struct_sem; /* For others */ + + /* Usage Counters */ + int open_count; /* Outstanding files open */ + atomic_t ioctl_count; /* Outstanding IOCTLs pending */ + atomic_t vma_count; /* Outstanding vma areas open */ + int buf_use; /* Buffers in use -- cannot alloc */ + atomic_t buf_alloc; /* Buffer allocation in progress */ + + /* Performance Counters */ + atomic_t total_open; + atomic_t total_close; + atomic_t total_ioctl; + atomic_t total_irq; /* Total interruptions */ + atomic_t total_ctx; /* Total context switches */ + + atomic_t total_locks; + atomic_t total_unlocks; + atomic_t total_contends; + atomic_t total_sleeps; + + /* Authentication */ + drm_file_t *file_first; + drm_file_t *file_last; + drm_magic_head_t magiclist[DRM_HASH_SIZE]; + + /* Memory management */ + drm_map_t **maplist; /* Vector of pointers to regions */ + int map_count; /* Number of mappable regions */ + + drm_vma_entry_t *vmalist; /* List of vmas (for debugging) */ + drm_lock_data_t lock; /* Information on hardware lock */ + + /* DMA queues (contexts) */ + int queue_count; /* Number of active DMA queues */ + int queue_reserved; /* Number of reserved DMA queues */ + int queue_slots; /* Actual length of queuelist */ + drm_queue_t **queuelist; /* Vector of pointers to DMA queues */ + drm_device_dma_t *dma; /* Optional pointer for DMA support */ + + /* Context support */ + int irq; /* Interrupt used by board */ + __volatile__ long context_flag; /* Context swapping flag */ + __volatile__ long interrupt_flag; /* Interruption handler flag */ + __volatile__ long dma_flag; /* DMA dispatch flag */ + struct timer_list timer; /* Timer for delaying ctx switch */ + wait_queue_head_t context_wait; /* Processes waiting on ctx switch */ + int last_checked; /* Last context checked for DMA */ + int last_context; /* Last current context */ + unsigned long last_switch; /* jiffies at last context switch */ + struct tq_struct tq; + cycles_t ctx_start; + cycles_t lck_start; +#if DRM_DMA_HISTOGRAM + drm_histogram_t histo; +#endif + + /* Callback to X server for context switch + and for heavy-handed reset. */ + char buf[DRM_BSZ]; /* Output buffer */ + char *buf_rp; /* Read pointer */ + char *buf_wp; /* Write pointer */ + char *buf_end; /* End pointer */ + struct fasync_struct *buf_async;/* Processes waiting for SIGIO */ + wait_queue_head_t buf_readers; /* Processes waiting to read */ + wait_queue_head_t buf_writers; /* Processes waiting to ctx switch */ + +#if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE) + drm_agp_head_t *agp; +#endif + unsigned long *ctx_bitmap; + void *dev_private; + drm_sigdata_t sigdata; /* For block_all_signals */ + sigset_t sigmask; +} drm_device_t; + + /* Internal function definitions */ + + /* Misc. support (init.c) */ +extern int drm_flags; +extern void drm_parse_options(char *s); +extern int drm_cpu_valid(void); + + + /* Device support (fops.c) */ +extern int drm_open_helper(struct inode *inode, struct file *filp, + drm_device_t *dev); +extern int drm_flush(struct file *filp); +extern int drm_release(struct inode *inode, struct file *filp); +extern int drm_fasync(int fd, struct file *filp, int on); +extern ssize_t drm_read(struct file *filp, char *buf, size_t count, + loff_t *off); +extern int drm_write_string(drm_device_t *dev, const char *s); +extern unsigned int drm_poll(struct file *filp, struct poll_table_struct *wait); + + /* Mapping support (vm.c) */ +#if LINUX_VERSION_CODE < 0x020317 +extern unsigned long drm_vm_nopage(struct vm_area_struct *vma, + unsigned long address, + int write_access); +extern unsigned long drm_vm_shm_nopage(struct vm_area_struct *vma, + unsigned long address, + int write_access); +extern unsigned long drm_vm_shm_nopage_lock(struct vm_area_struct *vma, + unsigned long address, + int write_access); +extern unsigned long drm_vm_dma_nopage(struct vm_area_struct *vma, + unsigned long address, + int write_access); +#else + /* Return type changed in 2.3.23 */ +extern struct page *drm_vm_nopage(struct vm_area_struct *vma, + unsigned long address, + int write_access); +extern struct page *drm_vm_shm_nopage(struct vm_area_struct *vma, + unsigned long address, + int write_access); +extern struct page *drm_vm_shm_nopage_lock(struct vm_area_struct *vma, + unsigned long address, + int write_access); +extern struct page *drm_vm_dma_nopage(struct vm_area_struct *vma, + unsigned long address, + int write_access); +#endif +extern void drm_vm_open(struct vm_area_struct *vma); +extern void drm_vm_close(struct vm_area_struct *vma); +extern int drm_mmap_dma(struct file *filp, + struct vm_area_struct *vma); +extern int drm_mmap(struct file *filp, struct vm_area_struct *vma); + + + /* Proc support (proc.c) */ +extern int drm_proc_init(drm_device_t *dev); +extern int drm_proc_cleanup(void); + + /* Memory management support (memory.c) */ +extern void drm_mem_init(void); +extern int drm_mem_info(char *buf, char **start, off_t offset, + int len, int *eof, void *data); +extern void *drm_alloc(size_t size, int area); +extern void *drm_realloc(void *oldpt, size_t oldsize, size_t size, + int area); +extern char *drm_strdup(const char *s, int area); +extern void drm_strfree(const char *s, int area); +extern void drm_free(void *pt, size_t size, int area); +extern unsigned long drm_alloc_pages(int order, int area); +extern void drm_free_pages(unsigned long address, int order, + int area); +extern void *drm_ioremap(unsigned long offset, unsigned long size, + drm_device_t *dev); +extern void drm_ioremapfree(void *pt, unsigned long size, + drm_device_t *dev); + +#if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE) +extern agp_memory *drm_alloc_agp(int pages, u32 type); +extern int drm_free_agp(agp_memory *handle, int pages); +extern int drm_bind_agp(agp_memory *handle, unsigned int start); +extern int drm_unbind_agp(agp_memory *handle); +#endif + + + /* Buffer management support (bufs.c) */ +extern int drm_order(unsigned long size); +extern int drm_addmap(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_addbufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_infobufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_markbufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_freebufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_mapbufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); + + + /* Buffer list management support (lists.c) */ +extern int drm_waitlist_create(drm_waitlist_t *bl, int count); +extern int drm_waitlist_destroy(drm_waitlist_t *bl); +extern int drm_waitlist_put(drm_waitlist_t *bl, drm_buf_t *buf); +extern drm_buf_t *drm_waitlist_get(drm_waitlist_t *bl); + +extern int drm_freelist_create(drm_freelist_t *bl, int count); +extern int drm_freelist_destroy(drm_freelist_t *bl); +extern int drm_freelist_put(drm_device_t *dev, drm_freelist_t *bl, + drm_buf_t *buf); +extern drm_buf_t *drm_freelist_get(drm_freelist_t *bl, int block); + + /* DMA support (gen_dma.c) */ +extern void drm_dma_setup(drm_device_t *dev); +extern void drm_dma_takedown(drm_device_t *dev); +extern void drm_free_buffer(drm_device_t *dev, drm_buf_t *buf); +extern void drm_reclaim_buffers(drm_device_t *dev, pid_t pid); +extern int drm_context_switch(drm_device_t *dev, int old, int new); +extern int drm_context_switch_complete(drm_device_t *dev, int new); +extern void drm_clear_next_buffer(drm_device_t *dev); +extern int drm_select_queue(drm_device_t *dev, + void (*wrapper)(unsigned long)); +extern int drm_dma_enqueue(drm_device_t *dev, drm_dma_t *dma); +extern int drm_dma_get_buffers(drm_device_t *dev, drm_dma_t *dma); +#if DRM_DMA_HISTOGRAM +extern int drm_histogram_slot(unsigned long count); +extern void drm_histogram_compute(drm_device_t *dev, drm_buf_t *buf); +#endif + + + /* Misc. IOCTL support (ioctl.c) */ +extern int drm_irq_busid(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_getunique(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_setunique(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); + + + /* Context IOCTL support (context.c) */ +extern int drm_resctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_addctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_modctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_getctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_switchctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_newctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_rmctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); + + + /* Drawable IOCTL support (drawable.c) */ +extern int drm_adddraw(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_rmdraw(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); + + + /* Authentication IOCTL support (auth.c) */ +extern int drm_add_magic(drm_device_t *dev, drm_file_t *priv, + drm_magic_t magic); +extern int drm_remove_magic(drm_device_t *dev, drm_magic_t magic); +extern int drm_getmagic(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_authmagic(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); + + + /* Locking IOCTL support (lock.c) */ +extern int drm_block(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_unblock(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_lock_take(__volatile__ unsigned int *lock, + unsigned int context); +extern int drm_lock_transfer(drm_device_t *dev, + __volatile__ unsigned int *lock, + unsigned int context); +extern int drm_lock_free(drm_device_t *dev, + __volatile__ unsigned int *lock, + unsigned int context); +extern int drm_finish(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_flush_unblock(drm_device_t *dev, int context, + drm_lock_flags_t flags); +extern int drm_flush_block_and_flush(drm_device_t *dev, int context, + drm_lock_flags_t flags); +extern int drm_notifier(void *priv); + + /* Context Bitmap support (ctxbitmap.c) */ +extern int drm_ctxbitmap_init(drm_device_t *dev); +extern void drm_ctxbitmap_cleanup(drm_device_t *dev); +extern int drm_ctxbitmap_next(drm_device_t *dev); +extern void drm_ctxbitmap_free(drm_device_t *dev, int ctx_handle); + +#if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE) + /* AGP/GART support (agpsupport.c) */ +extern drm_agp_head_t *drm_agp_init(void); +extern void drm_agp_uninit(void); +extern int drm_agp_acquire(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern void _drm_agp_release(void); +extern int drm_agp_release(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_agp_enable(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_agp_info(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_agp_alloc(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_agp_free(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_agp_unbind(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_agp_bind(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern agp_memory *drm_agp_allocate_memory(size_t pages, u32 type); +extern int drm_agp_free_memory(agp_memory *handle); +extern int drm_agp_bind_memory(agp_memory *handle, off_t start); +extern int drm_agp_unbind_memory(agp_memory *handle); +#endif +#endif +#endif diff -urN linux-2.4.10/drivers/char/drm-4.0/ffb_context.c linux-2.4.10-lia/drivers/char/drm-4.0/ffb_context.c --- linux-2.4.10/drivers/char/drm-4.0/ffb_context.c Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/ffb_context.c Wed Aug 15 20:52:11 2001 @@ -0,0 +1,540 @@ +/* $Id: ffb_context.c,v 1.4 2000/08/29 07:01:55 davem Exp $ + * ffb_context.c: Creator/Creator3D DRI/DRM context switching. + * + * Copyright (C) 2000 David S. Miller (davem@redhat.com) + * + * Almost entirely stolen from tdfx_context.c, see there + * for authors. + */ + +#include +#include + +#include "drmP.h" + +#include "ffb_drv.h" + +static int ffb_alloc_queue(drm_device_t *dev, int is_2d_only) +{ + ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) (dev + 1); + int i; + + for (i = 0; i < FFB_MAX_CTXS; i++) { + if (fpriv->hw_state[i] == NULL) + break; + } + if (i == FFB_MAX_CTXS) + return -1; + + fpriv->hw_state[i] = kmalloc(sizeof(struct ffb_hw_context), GFP_KERNEL); + if (fpriv->hw_state[i] == NULL) + return -1; + + fpriv->hw_state[i]->is_2d_only = is_2d_only; + + /* Plus one because 0 is the special DRM_KERNEL_CONTEXT. */ + return i + 1; +} + +static void ffb_save_context(ffb_dev_priv_t *fpriv, int idx) +{ + ffb_fbcPtr ffb = fpriv->regs; + struct ffb_hw_context *ctx; + int i; + + ctx = fpriv->hw_state[idx - 1]; + if (idx == 0 || ctx == NULL) + return; + + if (ctx->is_2d_only) { + /* 2D applications only care about certain pieces + * of state. + */ + ctx->drawop = upa_readl(&ffb->drawop); + ctx->ppc = upa_readl(&ffb->ppc); + ctx->wid = upa_readl(&ffb->wid); + ctx->fg = upa_readl(&ffb->fg); + ctx->bg = upa_readl(&ffb->bg); + ctx->xclip = upa_readl(&ffb->xclip); + ctx->fbc = upa_readl(&ffb->fbc); + ctx->rop = upa_readl(&ffb->rop); + ctx->cmp = upa_readl(&ffb->cmp); + ctx->matchab = upa_readl(&ffb->matchab); + ctx->magnab = upa_readl(&ffb->magnab); + ctx->pmask = upa_readl(&ffb->pmask); + ctx->xpmask = upa_readl(&ffb->xpmask); + ctx->lpat = upa_readl(&ffb->lpat); + ctx->fontxy = upa_readl(&ffb->fontxy); + ctx->fontw = upa_readl(&ffb->fontw); + ctx->fontinc = upa_readl(&ffb->fontinc); + + /* stencil/stencilctl only exists on FFB2+ and later + * due to the introduction of 3DRAM-III. + */ + if (fpriv->ffb_type == ffb2_vertical_plus || + fpriv->ffb_type == ffb2_horizontal_plus) { + ctx->stencil = upa_readl(&ffb->stencil); + ctx->stencilctl = upa_readl(&ffb->stencilctl); + } + + for (i = 0; i < 32; i++) + ctx->area_pattern[i] = upa_readl(&ffb->pattern[i]); + ctx->ucsr = upa_readl(&ffb->ucsr); + return; + } + + /* Fetch drawop. */ + ctx->drawop = upa_readl(&ffb->drawop); + + /* If we were saving the vertex registers, this is where + * we would do it. We would save 32 32-bit words starting + * at ffb->suvtx. + */ + + /* Capture rendering attributes. */ + + ctx->ppc = upa_readl(&ffb->ppc); /* Pixel Processor Control */ + ctx->wid = upa_readl(&ffb->wid); /* Current WID */ + ctx->fg = upa_readl(&ffb->fg); /* Constant FG color */ + ctx->bg = upa_readl(&ffb->bg); /* Constant BG color */ + ctx->consty = upa_readl(&ffb->consty); /* Constant Y */ + ctx->constz = upa_readl(&ffb->constz); /* Constant Z */ + ctx->xclip = upa_readl(&ffb->xclip); /* X plane clip */ + ctx->dcss = upa_readl(&ffb->dcss); /* Depth Cue Scale Slope */ + ctx->vclipmin = upa_readl(&ffb->vclipmin); /* Primary XY clip, minimum */ + ctx->vclipmax = upa_readl(&ffb->vclipmax); /* Primary XY clip, maximum */ + ctx->vclipzmin = upa_readl(&ffb->vclipzmin); /* Primary Z clip, minimum */ + ctx->vclipzmax = upa_readl(&ffb->vclipzmax); /* Primary Z clip, maximum */ + ctx->dcsf = upa_readl(&ffb->dcsf); /* Depth Cue Scale Front Bound */ + ctx->dcsb = upa_readl(&ffb->dcsb); /* Depth Cue Scale Back Bound */ + ctx->dczf = upa_readl(&ffb->dczf); /* Depth Cue Scale Z Front */ + ctx->dczb = upa_readl(&ffb->dczb); /* Depth Cue Scale Z Back */ + ctx->blendc = upa_readl(&ffb->blendc); /* Alpha Blend Control */ + ctx->blendc1 = upa_readl(&ffb->blendc1); /* Alpha Blend Color 1 */ + ctx->blendc2 = upa_readl(&ffb->blendc2); /* Alpha Blend Color 2 */ + ctx->fbc = upa_readl(&ffb->fbc); /* Frame Buffer Control */ + ctx->rop = upa_readl(&ffb->rop); /* Raster Operation */ + ctx->cmp = upa_readl(&ffb->cmp); /* Compare Controls */ + ctx->matchab = upa_readl(&ffb->matchab); /* Buffer A/B Match Ops */ + ctx->matchc = upa_readl(&ffb->matchc); /* Buffer C Match Ops */ + ctx->magnab = upa_readl(&ffb->magnab); /* Buffer A/B Magnitude Ops */ + ctx->magnc = upa_readl(&ffb->magnc); /* Buffer C Magnitude Ops */ + ctx->pmask = upa_readl(&ffb->pmask); /* RGB Plane Mask */ + ctx->xpmask = upa_readl(&ffb->xpmask); /* X Plane Mask */ + ctx->ypmask = upa_readl(&ffb->ypmask); /* Y Plane Mask */ + ctx->zpmask = upa_readl(&ffb->zpmask); /* Z Plane Mask */ + + /* Auxiliary Clips. */ + ctx->auxclip0min = upa_readl(&ffb->auxclip[0].min); + ctx->auxclip0max = upa_readl(&ffb->auxclip[0].max); + ctx->auxclip1min = upa_readl(&ffb->auxclip[1].min); + ctx->auxclip1max = upa_readl(&ffb->auxclip[1].max); + ctx->auxclip2min = upa_readl(&ffb->auxclip[2].min); + ctx->auxclip2max = upa_readl(&ffb->auxclip[2].max); + ctx->auxclip3min = upa_readl(&ffb->auxclip[3].min); + ctx->auxclip3max = upa_readl(&ffb->auxclip[3].max); + + ctx->lpat = upa_readl(&ffb->lpat); /* Line Pattern */ + ctx->fontxy = upa_readl(&ffb->fontxy); /* XY Font Coordinate */ + ctx->fontw = upa_readl(&ffb->fontw); /* Font Width */ + ctx->fontinc = upa_readl(&ffb->fontinc); /* Font X/Y Increment */ + + /* These registers/features only exist on FFB2 and later chips. */ + if (fpriv->ffb_type >= ffb2_prototype) { + ctx->dcss1 = upa_readl(&ffb->dcss1); /* Depth Cue Scale Slope 1 */ + ctx->dcss2 = upa_readl(&ffb->dcss2); /* Depth Cue Scale Slope 2 */ + ctx->dcss2 = upa_readl(&ffb->dcss3); /* Depth Cue Scale Slope 3 */ + ctx->dcs2 = upa_readl(&ffb->dcs2); /* Depth Cue Scale 2 */ + ctx->dcs3 = upa_readl(&ffb->dcs3); /* Depth Cue Scale 3 */ + ctx->dcs4 = upa_readl(&ffb->dcs4); /* Depth Cue Scale 4 */ + ctx->dcd2 = upa_readl(&ffb->dcd2); /* Depth Cue Depth 2 */ + ctx->dcd3 = upa_readl(&ffb->dcd3); /* Depth Cue Depth 3 */ + ctx->dcd4 = upa_readl(&ffb->dcd4); /* Depth Cue Depth 4 */ + + /* And stencil/stencilctl only exists on FFB2+ and later + * due to the introduction of 3DRAM-III. + */ + if (fpriv->ffb_type == ffb2_vertical_plus || + fpriv->ffb_type == ffb2_horizontal_plus) { + ctx->stencil = upa_readl(&ffb->stencil); + ctx->stencilctl = upa_readl(&ffb->stencilctl); + } + } + + /* Save the 32x32 area pattern. */ + for (i = 0; i < 32; i++) + ctx->area_pattern[i] = upa_readl(&ffb->pattern[i]); + + /* Finally, stash away the User Constol/Status Register. */ + ctx->ucsr = upa_readl(&ffb->ucsr); +} + +static void ffb_restore_context(ffb_dev_priv_t *fpriv, int old, int idx) +{ + ffb_fbcPtr ffb = fpriv->regs; + struct ffb_hw_context *ctx; + int i; + + ctx = fpriv->hw_state[idx - 1]; + if (idx == 0 || ctx == NULL) + return; + + if (ctx->is_2d_only) { + /* 2D applications only care about certain pieces + * of state. + */ + upa_writel(ctx->drawop, &ffb->drawop); + + /* If we were restoring the vertex registers, this is where + * we would do it. We would restore 32 32-bit words starting + * at ffb->suvtx. + */ + + upa_writel(ctx->ppc, &ffb->ppc); + upa_writel(ctx->wid, &ffb->wid); + upa_writel(ctx->fg, &ffb->fg); + upa_writel(ctx->bg, &ffb->bg); + upa_writel(ctx->xclip, &ffb->xclip); + upa_writel(ctx->fbc, &ffb->fbc); + upa_writel(ctx->rop, &ffb->rop); + upa_writel(ctx->cmp, &ffb->cmp); + upa_writel(ctx->matchab, &ffb->matchab); + upa_writel(ctx->magnab, &ffb->magnab); + upa_writel(ctx->pmask, &ffb->pmask); + upa_writel(ctx->xpmask, &ffb->xpmask); + upa_writel(ctx->lpat, &ffb->lpat); + upa_writel(ctx->fontxy, &ffb->fontxy); + upa_writel(ctx->fontw, &ffb->fontw); + upa_writel(ctx->fontinc, &ffb->fontinc); + + /* stencil/stencilctl only exists on FFB2+ and later + * due to the introduction of 3DRAM-III. + */ + if (fpriv->ffb_type == ffb2_vertical_plus || + fpriv->ffb_type == ffb2_horizontal_plus) { + upa_writel(ctx->stencil, &ffb->stencil); + upa_writel(ctx->stencilctl, &ffb->stencilctl); + upa_writel(0x80000000, &ffb->fbc); + upa_writel((ctx->stencilctl | 0x80000), + &ffb->rawstencilctl); + upa_writel(ctx->fbc, &ffb->fbc); + } + + for (i = 0; i < 32; i++) + upa_writel(ctx->area_pattern[i], &ffb->pattern[i]); + upa_writel((ctx->ucsr & 0xf0000), &ffb->ucsr); + return; + } + + /* Restore drawop. */ + upa_writel(ctx->drawop, &ffb->drawop); + + /* If we were restoring the vertex registers, this is where + * we would do it. We would restore 32 32-bit words starting + * at ffb->suvtx. + */ + + /* Restore rendering attributes. */ + + upa_writel(ctx->ppc, &ffb->ppc); /* Pixel Processor Control */ + upa_writel(ctx->wid, &ffb->wid); /* Current WID */ + upa_writel(ctx->fg, &ffb->fg); /* Constant FG color */ + upa_writel(ctx->bg, &ffb->bg); /* Constant BG color */ + upa_writel(ctx->consty, &ffb->consty); /* Constant Y */ + upa_writel(ctx->constz, &ffb->constz); /* Constant Z */ + upa_writel(ctx->xclip, &ffb->xclip); /* X plane clip */ + upa_writel(ctx->dcss, &ffb->dcss); /* Depth Cue Scale Slope */ + upa_writel(ctx->vclipmin, &ffb->vclipmin); /* Primary XY clip, minimum */ + upa_writel(ctx->vclipmax, &ffb->vclipmax); /* Primary XY clip, maximum */ + upa_writel(ctx->vclipzmin, &ffb->vclipzmin); /* Primary Z clip, minimum */ + upa_writel(ctx->vclipzmax, &ffb->vclipzmax); /* Primary Z clip, maximum */ + upa_writel(ctx->dcsf, &ffb->dcsf); /* Depth Cue Scale Front Bound */ + upa_writel(ctx->dcsb, &ffb->dcsb); /* Depth Cue Scale Back Bound */ + upa_writel(ctx->dczf, &ffb->dczf); /* Depth Cue Scale Z Front */ + upa_writel(ctx->dczb, &ffb->dczb); /* Depth Cue Scale Z Back */ + upa_writel(ctx->blendc, &ffb->blendc); /* Alpha Blend Control */ + upa_writel(ctx->blendc1, &ffb->blendc1); /* Alpha Blend Color 1 */ + upa_writel(ctx->blendc2, &ffb->blendc2); /* Alpha Blend Color 2 */ + upa_writel(ctx->fbc, &ffb->fbc); /* Frame Buffer Control */ + upa_writel(ctx->rop, &ffb->rop); /* Raster Operation */ + upa_writel(ctx->cmp, &ffb->cmp); /* Compare Controls */ + upa_writel(ctx->matchab, &ffb->matchab); /* Buffer A/B Match Ops */ + upa_writel(ctx->matchc, &ffb->matchc); /* Buffer C Match Ops */ + upa_writel(ctx->magnab, &ffb->magnab); /* Buffer A/B Magnitude Ops */ + upa_writel(ctx->magnc, &ffb->magnc); /* Buffer C Magnitude Ops */ + upa_writel(ctx->pmask, &ffb->pmask); /* RGB Plane Mask */ + upa_writel(ctx->xpmask, &ffb->xpmask); /* X Plane Mask */ + upa_writel(ctx->ypmask, &ffb->ypmask); /* Y Plane Mask */ + upa_writel(ctx->zpmask, &ffb->zpmask); /* Z Plane Mask */ + + /* Auxiliary Clips. */ + upa_writel(ctx->auxclip0min, &ffb->auxclip[0].min); + upa_writel(ctx->auxclip0max, &ffb->auxclip[0].max); + upa_writel(ctx->auxclip1min, &ffb->auxclip[1].min); + upa_writel(ctx->auxclip1max, &ffb->auxclip[1].max); + upa_writel(ctx->auxclip2min, &ffb->auxclip[2].min); + upa_writel(ctx->auxclip2max, &ffb->auxclip[2].max); + upa_writel(ctx->auxclip3min, &ffb->auxclip[3].min); + upa_writel(ctx->auxclip3max, &ffb->auxclip[3].max); + + upa_writel(ctx->lpat, &ffb->lpat); /* Line Pattern */ + upa_writel(ctx->fontxy, &ffb->fontxy); /* XY Font Coordinate */ + upa_writel(ctx->fontw, &ffb->fontw); /* Font Width */ + upa_writel(ctx->fontinc, &ffb->fontinc); /* Font X/Y Increment */ + + /* These registers/features only exist on FFB2 and later chips. */ + if (fpriv->ffb_type >= ffb2_prototype) { + upa_writel(ctx->dcss1, &ffb->dcss1); /* Depth Cue Scale Slope 1 */ + upa_writel(ctx->dcss2, &ffb->dcss2); /* Depth Cue Scale Slope 2 */ + upa_writel(ctx->dcss3, &ffb->dcss2); /* Depth Cue Scale Slope 3 */ + upa_writel(ctx->dcs2, &ffb->dcs2); /* Depth Cue Scale 2 */ + upa_writel(ctx->dcs3, &ffb->dcs3); /* Depth Cue Scale 3 */ + upa_writel(ctx->dcs4, &ffb->dcs4); /* Depth Cue Scale 4 */ + upa_writel(ctx->dcd2, &ffb->dcd2); /* Depth Cue Depth 2 */ + upa_writel(ctx->dcd3, &ffb->dcd3); /* Depth Cue Depth 3 */ + upa_writel(ctx->dcd4, &ffb->dcd4); /* Depth Cue Depth 4 */ + + /* And stencil/stencilctl only exists on FFB2+ and later + * due to the introduction of 3DRAM-III. + */ + if (fpriv->ffb_type == ffb2_vertical_plus || + fpriv->ffb_type == ffb2_horizontal_plus) { + /* Unfortunately, there is a hardware bug on + * the FFB2+ chips which prevents a normal write + * to the stencil control register from working + * as it should. + * + * The state controlled by the FFB stencilctl register + * really gets transferred to the per-buffer instances + * of the stencilctl register in the 3DRAM chips. + * + * The bug is that FFB does not update buffer C correctly, + * so we have to do it by hand for them. + */ + + /* This will update buffers A and B. */ + upa_writel(ctx->stencil, &ffb->stencil); + upa_writel(ctx->stencilctl, &ffb->stencilctl); + + /* Force FFB to use buffer C 3dram regs. */ + upa_writel(0x80000000, &ffb->fbc); + upa_writel((ctx->stencilctl | 0x80000), + &ffb->rawstencilctl); + + /* Now restore the correct FBC controls. */ + upa_writel(ctx->fbc, &ffb->fbc); + } + } + + /* Restore the 32x32 area pattern. */ + for (i = 0; i < 32; i++) + upa_writel(ctx->area_pattern[i], &ffb->pattern[i]); + + /* Finally, stash away the User Constol/Status Register. + * The only state we really preserve here is the picking + * control. + */ + upa_writel((ctx->ucsr & 0xf0000), &ffb->ucsr); +} + +#define FFB_UCSR_FB_BUSY 0x01000000 +#define FFB_UCSR_RP_BUSY 0x02000000 +#define FFB_UCSR_ALL_BUSY (FFB_UCSR_RP_BUSY|FFB_UCSR_FB_BUSY) + +static void FFBWait(ffb_fbcPtr ffb) +{ + int limit = 100000; + + do { + u32 regval = upa_readl(&ffb->ucsr); + + if ((regval & FFB_UCSR_ALL_BUSY) == 0) + break; + } while (--limit); +} + +int ffb_context_switch(drm_device_t *dev, int old, int new) +{ + ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) (dev + 1); + + atomic_inc(&dev->total_ctx); + +#if DRM_DMA_HISTOGRAM + dev->ctx_start = get_cycles(); +#endif + + DRM_DEBUG("Context switch from %d to %d\n", old, new); + + if (new == dev->last_context || + dev->last_context == 0) { + dev->last_context = new; + return 0; + } + + FFBWait(fpriv->regs); + ffb_save_context(fpriv, old); + ffb_restore_context(fpriv, old, new); + FFBWait(fpriv->regs); + + dev->last_context = new; + + return 0; +} + +int ffb_resctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_ctx_res_t res; + drm_ctx_t ctx; + int i; + + DRM_DEBUG("%d\n", DRM_RESERVED_CONTEXTS); + if (copy_from_user(&res, (drm_ctx_res_t *)arg, sizeof(res))) + return -EFAULT; + if (res.count >= DRM_RESERVED_CONTEXTS) { + memset(&ctx, 0, sizeof(ctx)); + for (i = 0; i < DRM_RESERVED_CONTEXTS; i++) { + ctx.handle = i; + if (copy_to_user(&res.contexts[i], + &i, + sizeof(i))) + return -EFAULT; + } + } + res.count = DRM_RESERVED_CONTEXTS; + if (copy_to_user((drm_ctx_res_t *)arg, &res, sizeof(res))) + return -EFAULT; + return 0; +} + + +int ffb_addctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ctx_t ctx; + int idx; + + if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx))) + return -EFAULT; + idx = ffb_alloc_queue(dev, (ctx.flags & _DRM_CONTEXT_2DONLY)); + if (idx < 0) + return -ENFILE; + + DRM_DEBUG("%d\n", ctx.handle); + ctx.handle = idx; + if (copy_to_user((drm_ctx_t *)arg, &ctx, sizeof(ctx))) + return -EFAULT; + return 0; +} + +int ffb_modctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) (dev + 1); + struct ffb_hw_context *hwctx; + drm_ctx_t ctx; + int idx; + + if (copy_from_user(&ctx, (drm_ctx_t*)arg, sizeof(ctx))) + return -EFAULT; + + idx = ctx.handle; + if (idx <= 0 || idx >= FFB_MAX_CTXS) + return -EINVAL; + + hwctx = fpriv->hw_state[idx - 1]; + if (hwctx == NULL) + return -EINVAL; + + if ((ctx.flags & _DRM_CONTEXT_2DONLY) == 0) + hwctx->is_2d_only = 0; + else + hwctx->is_2d_only = 1; + + return 0; +} + +int ffb_getctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) (dev + 1); + struct ffb_hw_context *hwctx; + drm_ctx_t ctx; + int idx; + + if (copy_from_user(&ctx, (drm_ctx_t*)arg, sizeof(ctx))) + return -EFAULT; + + idx = ctx.handle; + if (idx <= 0 || idx >= FFB_MAX_CTXS) + return -EINVAL; + + hwctx = fpriv->hw_state[idx - 1]; + if (hwctx == NULL) + return -EINVAL; + + if (hwctx->is_2d_only != 0) + ctx.flags = _DRM_CONTEXT_2DONLY; + else + ctx.flags = 0; + + if (copy_to_user((drm_ctx_t*)arg, &ctx, sizeof(ctx))) + return -EFAULT; + + return 0; +} + +int ffb_switchctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ctx_t ctx; + + if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx))) + return -EFAULT; + DRM_DEBUG("%d\n", ctx.handle); + return ffb_context_switch(dev, dev->last_context, ctx.handle); +} + +int ffb_newctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_ctx_t ctx; + + if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx))) + return -EFAULT; + DRM_DEBUG("%d\n", ctx.handle); + + return 0; +} + +int ffb_rmctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_ctx_t ctx; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) (dev + 1); + int idx; + + if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx))) + return -EFAULT; + DRM_DEBUG("%d\n", ctx.handle); + + idx = ctx.handle - 1; + if (idx < 0 || idx >= FFB_MAX_CTXS) + return -EINVAL; + + if (fpriv->hw_state[idx] != NULL) { + kfree(fpriv->hw_state[idx]); + fpriv->hw_state[idx] = NULL; + } + return 0; +} diff -urN linux-2.4.10/drivers/char/drm-4.0/ffb_drv.c linux-2.4.10-lia/drivers/char/drm-4.0/ffb_drv.c --- linux-2.4.10/drivers/char/drm-4.0/ffb_drv.c Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/ffb_drv.c Mon Aug 20 18:09:34 2001 @@ -0,0 +1,951 @@ +/* $Id: ffb_drv.c,v 1.14 2001/05/24 12:01:47 davem Exp $ + * ffb_drv.c: Creator/Creator3D direct rendering driver. + * + * Copyright (C) 2000 David S. Miller (davem@redhat.com) + */ + +#include "drmP.h" + +#include +#include +#include +#include +#include + +#include "ffb_drv.h" + +#define FFB_NAME "ffb" +#define FFB_DESC "Creator/Creator3D" +#define FFB_DATE "20000517" +#define FFB_MAJOR 0 +#define FFB_MINOR 0 +#define FFB_PATCHLEVEL 1 + +/* Forward declarations. */ +int ffb_init(void); +void ffb_cleanup(void); +static int ffb_version(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +static int ffb_open(struct inode *inode, struct file *filp); +static int ffb_release(struct inode *inode, struct file *filp); +static int ffb_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +static int ffb_lock(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +static int ffb_unlock(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +static int ffb_mmap(struct file *filp, struct vm_area_struct *vma); +static unsigned long ffb_get_unmapped_area(struct file *, unsigned long, unsigned long, unsigned long, unsigned long); + +/* From ffb_context.c */ +extern int ffb_resctx(struct inode *, struct file *, unsigned int, unsigned long); +extern int ffb_addctx(struct inode *, struct file *, unsigned int, unsigned long); +extern int ffb_modctx(struct inode *, struct file *, unsigned int, unsigned long); +extern int ffb_getctx(struct inode *, struct file *, unsigned int, unsigned long); +extern int ffb_switchctx(struct inode *, struct file *, unsigned int, unsigned long); +extern int ffb_newctx(struct inode *, struct file *, unsigned int, unsigned long); +extern int ffb_rmctx(struct inode *, struct file *, unsigned int, unsigned long); +extern int ffb_context_switch(drm_device_t *, int, int); + +static struct file_operations ffb_fops = { + owner: THIS_MODULE, + open: ffb_open, + flush: drm_flush, + release: ffb_release, + ioctl: ffb_ioctl, + mmap: ffb_mmap, + read: drm_read, + fasync: drm_fasync, + poll: drm_poll, + get_unmapped_area: ffb_get_unmapped_area, +}; + +/* This is just a template, we make a new copy for each FFB + * we discover at init time so that each one gets a unique + * misc device minor number. + */ +static struct miscdevice ffb_misc = { + minor: MISC_DYNAMIC_MINOR, + name: FFB_NAME, + fops: &ffb_fops, +}; + +static drm_ioctl_desc_t ffb_ioctls[] = { + [DRM_IOCTL_NR(DRM_IOCTL_VERSION)] = { ffb_version, 0, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_GET_UNIQUE)] = { drm_getunique, 0, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_GET_MAGIC)] = { drm_getmagic, 0, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_IRQ_BUSID)] = { drm_irq_busid, 0, 1 }, /* XXX */ + + [DRM_IOCTL_NR(DRM_IOCTL_SET_UNIQUE)] = { drm_setunique, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_BLOCK)] = { drm_block, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_UNBLOCK)] = { drm_unblock, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_AUTH_MAGIC)] = { drm_authmagic, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_ADD_MAP)] = { drm_addmap, 1, 1 }, + + /* The implementation is currently a nop just like on tdfx. + * Later we can do something more clever. -DaveM + */ + [DRM_IOCTL_NR(DRM_IOCTL_ADD_CTX)] = { ffb_addctx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_RM_CTX)] = { ffb_rmctx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_MOD_CTX)] = { ffb_modctx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_GET_CTX)] = { ffb_getctx, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_SWITCH_CTX)] = { ffb_switchctx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_NEW_CTX)] = { ffb_newctx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_RES_CTX)] = { ffb_resctx, 1, 0 }, + + [DRM_IOCTL_NR(DRM_IOCTL_ADD_DRAW)] = { drm_adddraw, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_RM_DRAW)] = { drm_rmdraw, 1, 1 }, + + [DRM_IOCTL_NR(DRM_IOCTL_LOCK)] = { ffb_lock, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_UNLOCK)] = { ffb_unlock, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_FINISH)] = { drm_finish, 1, 0 }, +}; +#define FFB_IOCTL_COUNT DRM_ARRAY_SIZE(ffb_ioctls) + +#ifdef MODULE +static char *ffb = NULL; +#endif + +MODULE_AUTHOR("David S. Miller (davem@redhat.com)"); +MODULE_DESCRIPTION("Sun Creator/Creator3D DRI"); + +static int ffb_takedown(drm_device_t *dev) +{ + int i; + drm_magic_entry_t *pt, *next; + drm_map_t *map; + drm_vma_entry_t *vma, *vma_next; + + DRM_DEBUG("\n"); + + down(&dev->struct_sem); + del_timer(&dev->timer); + + if (dev->devname) { + drm_free(dev->devname, strlen(dev->devname)+1, DRM_MEM_DRIVER); + dev->devname = NULL; + } + + if (dev->unique) { + drm_free(dev->unique, strlen(dev->unique)+1, DRM_MEM_DRIVER); + dev->unique = NULL; + dev->unique_len = 0; + } + + /* Clear pid list */ + for (i = 0; i < DRM_HASH_SIZE; i++) { + for (pt = dev->magiclist[i].head; pt; pt = next) { + next = pt->next; + drm_free(pt, sizeof(*pt), DRM_MEM_MAGIC); + } + dev->magiclist[i].head = dev->magiclist[i].tail = NULL; + } + + /* Clear vma list (only built for debugging) */ + if (dev->vmalist) { + for (vma = dev->vmalist; vma; vma = vma_next) { + vma_next = vma->next; + drm_free(vma, sizeof(*vma), DRM_MEM_VMAS); + } + dev->vmalist = NULL; + } + + /* Clear map area information */ + if (dev->maplist) { + for (i = 0; i < dev->map_count; i++) { + map = dev->maplist[i]; + switch (map->type) { + case _DRM_REGISTERS: + case _DRM_FRAME_BUFFER: + drm_ioremapfree(map->handle, map->size, dev); + break; + + case _DRM_SHM: + drm_free_pages((unsigned long)map->handle, + drm_order(map->size) + - PAGE_SHIFT, + DRM_MEM_SAREA); + break; + + default: + break; + }; + + drm_free(map, sizeof(*map), DRM_MEM_MAPS); + } + + drm_free(dev->maplist, + dev->map_count * sizeof(*dev->maplist), + DRM_MEM_MAPS); + dev->maplist = NULL; + dev->map_count = 0; + } + + if (dev->lock.hw_lock) { + dev->lock.hw_lock = NULL; /* SHM removed */ + dev->lock.pid = 0; + wake_up_interruptible(&dev->lock.lock_queue); + } + up(&dev->struct_sem); + + return 0; +} + +drm_device_t **ffb_dev_table; +static int ffb_dev_table_size; + +static void get_ffb_type(ffb_dev_priv_t *ffb_priv, int instance) +{ + volatile unsigned char *strap_bits; + unsigned char val; + + strap_bits = (volatile unsigned char *) + (ffb_priv->card_phys_base + 0x00200000UL); + + /* Don't ask, you have to read the value twice for whatever + * reason to get correct contents. + */ + val = upa_readb(strap_bits); + val = upa_readb(strap_bits); + switch (val & 0x78) { + case (0x0 << 5) | (0x0 << 3): + ffb_priv->ffb_type = ffb1_prototype; + printk("ffb%d: Detected FFB1 pre-FCS prototype\n", instance); + break; + case (0x0 << 5) | (0x1 << 3): + ffb_priv->ffb_type = ffb1_standard; + printk("ffb%d: Detected FFB1\n", instance); + break; + case (0x0 << 5) | (0x3 << 3): + ffb_priv->ffb_type = ffb1_speedsort; + printk("ffb%d: Detected FFB1-SpeedSort\n", instance); + break; + case (0x1 << 5) | (0x0 << 3): + ffb_priv->ffb_type = ffb2_prototype; + printk("ffb%d: Detected FFB2/vertical pre-FCS prototype\n", instance); + break; + case (0x1 << 5) | (0x1 << 3): + ffb_priv->ffb_type = ffb2_vertical; + printk("ffb%d: Detected FFB2/vertical\n", instance); + break; + case (0x1 << 5) | (0x2 << 3): + ffb_priv->ffb_type = ffb2_vertical_plus; + printk("ffb%d: Detected FFB2+/vertical\n", instance); + break; + case (0x2 << 5) | (0x0 << 3): + ffb_priv->ffb_type = ffb2_horizontal; + printk("ffb%d: Detected FFB2/horizontal\n", instance); + break; + case (0x2 << 5) | (0x2 << 3): + ffb_priv->ffb_type = ffb2_horizontal; + printk("ffb%d: Detected FFB2+/horizontal\n", instance); + break; + default: + ffb_priv->ffb_type = ffb2_vertical; + printk("ffb%d: Unknown boardID[%08x], assuming FFB2\n", instance, val); + break; + }; +} + +static void __init ffb_apply_upa_parent_ranges(int parent, struct linux_prom64_registers *regs) +{ + struct linux_prom64_ranges ranges[PROMREG_MAX]; + char name[128]; + int len, i; + + prom_getproperty(parent, "name", name, sizeof(name)); + if (strcmp(name, "upa") != 0) + return; + + len = prom_getproperty(parent, "ranges", (void *) ranges, sizeof(ranges)); + if (len <= 0) + return; + + len /= sizeof(struct linux_prom64_ranges); + for (i = 0; i < len; i++) { + struct linux_prom64_ranges *rng = &ranges[i]; + u64 phys_addr = regs->phys_addr; + + if (phys_addr >= rng->ot_child_base && + phys_addr < (rng->ot_child_base + rng->or_size)) { + regs->phys_addr -= rng->ot_child_base; + regs->phys_addr += rng->ot_parent_base; + return; + } + } + + return; +} + +static int __init ffb_init_one(int prom_node, int parent_node, int instance) +{ + struct linux_prom64_registers regs[2*PROMREG_MAX]; + drm_device_t *dev; + ffb_dev_priv_t *ffb_priv; + int ret, i; + + dev = kmalloc(sizeof(drm_device_t) + sizeof(ffb_dev_priv_t), GFP_KERNEL); + if (!dev) + return -ENOMEM; + + memset(dev, 0, sizeof(*dev)); + spin_lock_init(&dev->count_lock); + sema_init(&dev->struct_sem, 1); + + ffb_priv = (ffb_dev_priv_t *) (dev + 1); + ffb_priv->prom_node = prom_node; + if (prom_getproperty(ffb_priv->prom_node, "reg", + (void *)regs, sizeof(regs)) <= 0) { + kfree(dev); + return -EINVAL; + } + ffb_apply_upa_parent_ranges(parent_node, ®s[0]); + ffb_priv->card_phys_base = regs[0].phys_addr; + ffb_priv->regs = (ffb_fbcPtr) + (regs[0].phys_addr + 0x00600000UL); + get_ffb_type(ffb_priv, instance); + for (i = 0; i < FFB_MAX_CTXS; i++) + ffb_priv->hw_state[i] = NULL; + + ffb_dev_table[instance] = dev; + +#ifdef MODULE + drm_parse_options(ffb); +#endif + + memcpy(&ffb_priv->miscdev, &ffb_misc, sizeof(ffb_misc)); + ret = misc_register(&ffb_priv->miscdev); + if (ret) { + ffb_dev_table[instance] = NULL; + kfree(dev); + return ret; + } + + dev->device = MKDEV(MISC_MAJOR, ffb_priv->miscdev.minor); + dev->name = FFB_NAME; + + drm_mem_init(); + drm_proc_init(dev); + + DRM_INFO("Initialized %s %d.%d.%d %s on minor %d at %016lx\n", + FFB_NAME, + FFB_MAJOR, + FFB_MINOR, + FFB_PATCHLEVEL, + FFB_DATE, + ffb_priv->miscdev.minor, + ffb_priv->card_phys_base); + + return 0; +} + +static int __init ffb_count_siblings(int root) +{ + int node, child, count = 0; + + child = prom_getchild(root); + for (node = prom_searchsiblings(child, "SUNW,ffb"); node; + node = prom_searchsiblings(prom_getsibling(node), "SUNW,ffb")) + count++; + + return count; +} + +static int __init ffb_init_dev_table(void) +{ + int root, total; + + total = ffb_count_siblings(prom_root_node); + root = prom_getchild(prom_root_node); + for (root = prom_searchsiblings(root, "upa"); root; + root = prom_searchsiblings(prom_getsibling(root), "upa")) + total += ffb_count_siblings(root); + + if (!total) + return -ENODEV; + + ffb_dev_table = kmalloc(sizeof(drm_device_t *) * total, GFP_KERNEL); + if (!ffb_dev_table) + return -ENOMEM; + + ffb_dev_table_size = total; + + return 0; +} + +static int __init ffb_scan_siblings(int root, int instance) +{ + int node, child; + + child = prom_getchild(root); + for (node = prom_searchsiblings(child, "SUNW,ffb"); node; + node = prom_searchsiblings(prom_getsibling(node), "SUNW,ffb")) { + ffb_init_one(node, root, instance); + instance++; + } + + return instance; +} + +int __init ffb_init(void) +{ + int root, instance, ret; + + ret = ffb_init_dev_table(); + if (ret) + return ret; + + instance = ffb_scan_siblings(prom_root_node, 0); + + root = prom_getchild(prom_root_node); + for (root = prom_searchsiblings(root, "upa"); root; + root = prom_searchsiblings(prom_getsibling(root), "upa")) + instance = ffb_scan_siblings(root, instance); + + return 0; +} + +void __exit ffb_cleanup(void) +{ + int instance; + + DRM_DEBUG("\n"); + + drm_proc_cleanup(); + for (instance = 0; instance < ffb_dev_table_size; instance++) { + drm_device_t *dev = ffb_dev_table[instance]; + ffb_dev_priv_t *ffb_priv; + + if (!dev) + continue; + + ffb_priv = (ffb_dev_priv_t *) (dev + 1); + if (misc_deregister(&ffb_priv->miscdev)) { + DRM_ERROR("Cannot unload module\n"); + } else { + DRM_INFO("Module unloaded\n"); + } + ffb_takedown(dev); + kfree(dev); + ffb_dev_table[instance] = NULL; + } + kfree(ffb_dev_table); + ffb_dev_table = NULL; + ffb_dev_table_size = 0; +} + +static int ffb_version(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) +{ + drm_version_t version; + int len, ret; + + ret = copy_from_user(&version, (drm_version_t *)arg, sizeof(version)); + if (ret) + return -EFAULT; + + version.version_major = FFB_MAJOR; + version.version_minor = FFB_MINOR; + version.version_patchlevel = FFB_PATCHLEVEL; + + len = strlen(FFB_NAME); + if (len > version.name_len) + len = version.name_len; + version.name_len = len; + if (len && version.name) { + ret = copy_to_user(version.name, FFB_NAME, len); + if (ret) + return -EFAULT; + } + + len = strlen(FFB_DATE); + if (len > version.date_len) + len = version.date_len; + version.date_len = len; + if (len && version.date) { + ret = copy_to_user(version.date, FFB_DATE, len); + if (ret) + return -EFAULT; + } + + len = strlen(FFB_DESC); + if (len > version.desc_len) + len = version.desc_len; + version.desc_len = len; + if (len && version.desc) { + ret = copy_to_user(version.desc, FFB_DESC, len); + if (ret) + return -EFAULT; + } + + ret = copy_to_user((drm_version_t *) arg, &version, sizeof(version)); + if (ret) + ret = -EFAULT; + + return ret; +} + +static int ffb_setup(drm_device_t *dev) +{ + int i; + + atomic_set(&dev->ioctl_count, 0); + atomic_set(&dev->vma_count, 0); + dev->buf_use = 0; + atomic_set(&dev->buf_alloc, 0); + + atomic_set(&dev->total_open, 0); + atomic_set(&dev->total_close, 0); + atomic_set(&dev->total_ioctl, 0); + atomic_set(&dev->total_irq, 0); + atomic_set(&dev->total_ctx, 0); + atomic_set(&dev->total_locks, 0); + atomic_set(&dev->total_unlocks, 0); + atomic_set(&dev->total_contends, 0); + atomic_set(&dev->total_sleeps, 0); + + for (i = 0; i < DRM_HASH_SIZE; i++) { + dev->magiclist[i].head = NULL; + dev->magiclist[i].tail = NULL; + } + + dev->maplist = NULL; + dev->map_count = 0; + dev->vmalist = NULL; + dev->lock.hw_lock = NULL; + init_waitqueue_head(&dev->lock.lock_queue); + dev->queue_count = 0; + dev->queue_reserved = 0; + dev->queue_slots = 0; + dev->queuelist = NULL; + dev->irq = 0; + dev->context_flag = 0; + dev->interrupt_flag = 0; + dev->dma = 0; + dev->dma_flag = 0; + dev->last_context = 0; + dev->last_switch = 0; + dev->last_checked = 0; + init_timer(&dev->timer); + init_waitqueue_head(&dev->context_wait); + + dev->ctx_start = 0; + dev->lck_start = 0; + + dev->buf_rp = dev->buf; + dev->buf_wp = dev->buf; + dev->buf_end = dev->buf + DRM_BSZ; + dev->buf_async = NULL; + init_waitqueue_head(&dev->buf_readers); + init_waitqueue_head(&dev->buf_writers); + + return 0; +} + +static int ffb_open(struct inode *inode, struct file *filp) +{ + drm_device_t *dev; + int minor, i; + int ret = 0; + + minor = MINOR(inode->i_rdev); + for (i = 0; i < ffb_dev_table_size; i++) { + ffb_dev_priv_t *ffb_priv; + + ffb_priv = (ffb_dev_priv_t *) (ffb_dev_table[i] + 1); + + if (ffb_priv->miscdev.minor == minor) + break; + } + + if (i >= ffb_dev_table_size) + return -EINVAL; + + dev = ffb_dev_table[i]; + if (!dev) + return -EINVAL; + + DRM_DEBUG("open_count = %d\n", dev->open_count); + ret = drm_open_helper(inode, filp, dev); + if (!ret) { + atomic_inc(&dev->total_open); + spin_lock(&dev->count_lock); + if (!dev->open_count++) { + spin_unlock(&dev->count_lock); + return ffb_setup(dev); + } + spin_unlock(&dev->count_lock); + } + + return ret; +} + +static int ffb_release(struct inode *inode, struct file *filp) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev; + int ret = 0; + + lock_kernel(); + dev = priv->dev; + DRM_DEBUG("open_count = %d\n", dev->open_count); + if (dev->lock.hw_lock != NULL + && _DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock) + && dev->lock.pid == current->pid) { + ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) (dev + 1); + int context = _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock); + int idx; + + /* We have to free up the rogue hw context state + * holding error or else we will leak it. + */ + idx = context - 1; + if (fpriv->hw_state[idx] != NULL) { + kfree(fpriv->hw_state[idx]); + fpriv->hw_state[idx] = NULL; + } + } + + ret = drm_release(inode, filp); + + if (!ret) { + atomic_inc(&dev->total_close); + spin_lock(&dev->count_lock); + if (!--dev->open_count) { + if (atomic_read(&dev->ioctl_count) || dev->blocked) { + DRM_ERROR("Device busy: %d %d\n", + atomic_read(&dev->ioctl_count), + dev->blocked); + spin_unlock(&dev->count_lock); + unlock_kernel(); + return -EBUSY; + } + spin_unlock(&dev->count_lock); + ret = ffb_takedown(dev); + unlock_kernel(); + return ret; + } + spin_unlock(&dev->count_lock); + } + + unlock_kernel(); + return ret; +} + +static int ffb_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) +{ + int nr = DRM_IOCTL_NR(cmd); + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ioctl_desc_t *ioctl; + drm_ioctl_t *func; + int ret; + + atomic_inc(&dev->ioctl_count); + atomic_inc(&dev->total_ioctl); + ++priv->ioctl_count; + + DRM_DEBUG("pid = %d, cmd = 0x%02x, nr = 0x%02x, dev 0x%x, auth = %d\n", + current->pid, cmd, nr, dev->device, priv->authenticated); + + if (nr >= FFB_IOCTL_COUNT) { + ret = -EINVAL; + } else { + ioctl = &ffb_ioctls[nr]; + func = ioctl->func; + + if (!func) { + DRM_DEBUG("no function\n"); + ret = -EINVAL; + } else if ((ioctl->root_only && !capable(CAP_SYS_ADMIN)) + || (ioctl->auth_needed && !priv->authenticated)) { + ret = -EACCES; + } else { + ret = (func)(inode, filp, cmd, arg); + } + } + + atomic_dec(&dev->ioctl_count); + + return ret; +} + +static int ffb_lock(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + DECLARE_WAITQUEUE(entry, current); + int ret = 0; + drm_lock_t lock; + + ret = copy_from_user(&lock, (drm_lock_t *)arg, sizeof(lock)); + if (ret) + return -EFAULT; + + if (lock.context == DRM_KERNEL_CONTEXT) { + DRM_ERROR("Process %d using kernel context %d\n", + current->pid, lock.context); + return -EINVAL; + } + + DRM_DEBUG("%d (pid %d) requests lock (0x%08x), flags = 0x%08x\n", + lock.context, current->pid, dev->lock.hw_lock->lock, + lock.flags); + + add_wait_queue(&dev->lock.lock_queue, &entry); + for (;;) { + if (!dev->lock.hw_lock) { + /* Device has been unregistered */ + ret = -EINTR; + break; + } + if (drm_lock_take(&dev->lock.hw_lock->lock, + lock.context)) { + dev->lock.pid = current->pid; + dev->lock.lock_time = jiffies; + atomic_inc(&dev->total_locks); + break; /* Got lock */ + } + + /* Contention */ + atomic_inc(&dev->total_sleeps); + current->state = TASK_INTERRUPTIBLE; + current->policy |= SCHED_YIELD; + schedule(); + if (signal_pending(current)) { + ret = -ERESTARTSYS; + break; + } + } + current->state = TASK_RUNNING; + remove_wait_queue(&dev->lock.lock_queue, &entry); + + if (!ret) { + sigemptyset(&dev->sigmask); + sigaddset(&dev->sigmask, SIGSTOP); + sigaddset(&dev->sigmask, SIGTSTP); + sigaddset(&dev->sigmask, SIGTTIN); + sigaddset(&dev->sigmask, SIGTTOU); + dev->sigdata.context = lock.context; + dev->sigdata.lock = dev->lock.hw_lock; + block_all_signals(drm_notifier, &dev->sigdata, &dev->sigmask); + + if (dev->last_context != lock.context) + ffb_context_switch(dev, dev->last_context, lock.context); + } + + DRM_DEBUG("%d %s\n", lock.context, ret ? "interrupted" : "has lock"); + + return ret; +} + +int ffb_unlock(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_lock_t lock; + unsigned int old, new, prev, ctx; + int ret; + + ret = copy_from_user(&lock, (drm_lock_t *)arg, sizeof(lock)); + if (ret) + return -EFAULT; + + if ((ctx = lock.context) == DRM_KERNEL_CONTEXT) { + DRM_ERROR("Process %d using kernel context %d\n", + current->pid, lock.context); + return -EINVAL; + } + + DRM_DEBUG("%d frees lock (%d holds)\n", + lock.context, + _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock)); + atomic_inc(&dev->total_unlocks); + if (_DRM_LOCK_IS_CONT(dev->lock.hw_lock->lock)) + atomic_inc(&dev->total_contends); + + /* We no longer really hold it, but if we are the next + * agent to request it then we should just be able to + * take it immediately and not eat the ioctl. + */ + dev->lock.pid = 0; + { + __volatile__ unsigned int *plock = &dev->lock.hw_lock->lock; + + do { + old = *plock; + new = ctx; + prev = cmpxchg(plock, old, new); + } while (prev != old); + } + + wake_up_interruptible(&dev->lock.lock_queue); + + unblock_all_signals(); + return 0; +} + +extern struct vm_operations_struct drm_vm_ops; +extern struct vm_operations_struct drm_vm_shm_ops; +extern struct vm_operations_struct drm_vm_shm_lock_ops; + +static int ffb_mmap(struct file *filp, struct vm_area_struct *vma) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_map_t *map = NULL; + ffb_dev_priv_t *ffb_priv; + int i, minor; + + DRM_DEBUG("start = 0x%lx, end = 0x%lx, offset = 0x%lx\n", + vma->vm_start, vma->vm_end, VM_OFFSET(vma)); + + minor = MINOR(filp->f_dentry->d_inode->i_rdev); + ffb_priv = NULL; + for (i = 0; i < ffb_dev_table_size; i++) { + ffb_priv = (ffb_dev_priv_t *) (ffb_dev_table[i] + 1); + if (ffb_priv->miscdev.minor == minor) + break; + } + if (i >= ffb_dev_table_size) + return -EINVAL; + + /* We don't support/need dma mappings, so... */ + if (!VM_OFFSET(vma)) + return -EINVAL; + + for (i = 0; i < dev->map_count; i++) { + unsigned long off; + + map = dev->maplist[i]; + + /* Ok, a little hack to make 32-bit apps work. */ + off = (map->offset & 0xffffffff); + if (off == VM_OFFSET(vma)) + break; + } + + if (i >= dev->map_count) + return -EINVAL; + + if (!map || + ((map->flags & _DRM_RESTRICTED) && !capable(CAP_SYS_ADMIN))) + return -EPERM; + + if (map->size != (vma->vm_end - vma->vm_start)) + return -EINVAL; + + /* Set read-only attribute before mappings are created + * so it works for fb/reg maps too. + */ + if (map->flags & _DRM_READ_ONLY) + vma->vm_page_prot = __pgprot(pte_val(pte_wrprotect( + __pte(pgprot_val(vma->vm_page_prot))))); + + switch (map->type) { + case _DRM_FRAME_BUFFER: + /* FALLTHROUGH */ + + case _DRM_REGISTERS: + /* In order to handle 32-bit drm apps/xserver we + * play a trick. The mappings only really specify + * the 32-bit offset from the cards 64-bit base + * address, and we just add in the base here. + */ + vma->vm_flags |= VM_IO; + if (io_remap_page_range(vma->vm_start, + ffb_priv->card_phys_base + VM_OFFSET(vma), + vma->vm_end - vma->vm_start, + vma->vm_page_prot, 0)) + return -EAGAIN; + + vma->vm_ops = &drm_vm_ops; + break; + case _DRM_SHM: + if (map->flags & _DRM_CONTAINS_LOCK) + vma->vm_ops = &drm_vm_shm_lock_ops; + else { + vma->vm_ops = &drm_vm_shm_ops; + vma->vm_private_data = (void *) map; + } + + /* Don't let this area swap. Change when + * DRM_KERNEL advisory is supported. + */ + vma->vm_flags |= VM_LOCKED; + break; + default: + return -EINVAL; /* This should never happen. */ + }; + + vma->vm_flags |= VM_LOCKED | VM_SHM; /* Don't swap */ + + vma->vm_file = filp; /* Needed for drm_vm_open() */ + drm_vm_open(vma); + return 0; +} + +static drm_map_t *ffb_find_map(struct file *filp, unsigned long off) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev; + drm_map_t *map; + int i; + + if (!priv || (dev = priv->dev) == NULL) + return NULL; + + for (i = 0; i < dev->map_count; i++) { + unsigned long uoff; + + map = dev->maplist[i]; + + /* Ok, a little hack to make 32-bit apps work. */ + uoff = (map->offset & 0xffffffff); + if (uoff == off) + return map; + } + return NULL; +} + +static unsigned long ffb_get_unmapped_area(struct file *filp, unsigned long hint, unsigned long len, unsigned long pgoff, unsigned long flags) +{ + drm_map_t *map = ffb_find_map(filp, pgoff << PAGE_SHIFT); + unsigned long addr = -ENOMEM; + + if (!map) + return get_unmapped_area(NULL, hint, len, pgoff, flags); + + if (map->type == _DRM_FRAME_BUFFER || + map->type == _DRM_REGISTERS) { +#ifdef HAVE_ARCH_FB_UNMAPPED_AREA + addr = get_fb_unmapped_area(filp, hint, len, pgoff, flags); +#else + addr = get_unmapped_area(NULL, hint, len, pgoff, flags); +#endif + } else if (map->type == _DRM_SHM && SHMLBA > PAGE_SIZE) { + unsigned long slack = SHMLBA - PAGE_SIZE; + + addr = get_unmapped_area(NULL, hint, len + slack, pgoff, flags); + if (!(addr & ~PAGE_MASK)) { + unsigned long kvirt = (unsigned long) map->handle; + + if ((kvirt & (SHMLBA - 1)) != (addr & (SHMLBA - 1))) { + unsigned long koff, aoff; + + koff = kvirt & (SHMLBA - 1); + aoff = addr & (SHMLBA - 1); + if (koff < aoff) + koff += SHMLBA; + + addr += (koff - aoff); + } + } + } else { + addr = get_unmapped_area(NULL, hint, len, pgoff, flags); + } + + return addr; +} + +module_init(ffb_init); +module_exit(ffb_cleanup); diff -urN linux-2.4.10/drivers/char/drm-4.0/ffb_drv.h linux-2.4.10-lia/drivers/char/drm-4.0/ffb_drv.h --- linux-2.4.10/drivers/char/drm-4.0/ffb_drv.h Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/ffb_drv.h Wed Aug 15 20:52:11 2001 @@ -0,0 +1,276 @@ +/* $Id: ffb_drv.h,v 1.1 2000/06/01 04:24:39 davem Exp $ + * ffb_drv.h: Creator/Creator3D direct rendering driver. + * + * Copyright (C) 2000 David S. Miller (davem@redhat.com) + */ + +/* Auxilliary clips. */ +typedef struct { + volatile unsigned int min; + volatile unsigned int max; +} ffb_auxclip, *ffb_auxclipPtr; + +/* FFB register set. */ +typedef struct _ffb_fbc { + /* Next vertex registers, on the right we list which drawops + * use said register and the logical name the register has in + * that context. + */ /* DESCRIPTION DRAWOP(NAME) */ +/*0x00*/unsigned int pad1[3]; /* Reserved */ +/*0x0c*/volatile unsigned int alpha; /* ALPHA Transparency */ +/*0x10*/volatile unsigned int red; /* RED */ +/*0x14*/volatile unsigned int green; /* GREEN */ +/*0x18*/volatile unsigned int blue; /* BLUE */ +/*0x1c*/volatile unsigned int z; /* DEPTH */ +/*0x20*/volatile unsigned int y; /* Y triangle(DOYF) */ + /* aadot(DYF) */ + /* ddline(DYF) */ + /* aaline(DYF) */ +/*0x24*/volatile unsigned int x; /* X triangle(DOXF) */ + /* aadot(DXF) */ + /* ddline(DXF) */ + /* aaline(DXF) */ +/*0x28*/unsigned int pad2[2]; /* Reserved */ +/*0x30*/volatile unsigned int ryf; /* Y (alias to DOYF) ddline(RYF) */ + /* aaline(RYF) */ + /* triangle(RYF) */ +/*0x34*/volatile unsigned int rxf; /* X ddline(RXF) */ + /* aaline(RXF) */ + /* triangle(RXF) */ +/*0x38*/unsigned int pad3[2]; /* Reserved */ +/*0x40*/volatile unsigned int dmyf; /* Y (alias to DOYF) triangle(DMYF) */ +/*0x44*/volatile unsigned int dmxf; /* X triangle(DMXF) */ +/*0x48*/unsigned int pad4[2]; /* Reserved */ +/*0x50*/volatile unsigned int ebyi; /* Y (alias to RYI) polygon(EBYI) */ +/*0x54*/volatile unsigned int ebxi; /* X polygon(EBXI) */ +/*0x58*/unsigned int pad5[2]; /* Reserved */ +/*0x60*/volatile unsigned int by; /* Y brline(RYI) */ + /* fastfill(OP) */ + /* polygon(YI) */ + /* rectangle(YI) */ + /* bcopy(SRCY) */ + /* vscroll(SRCY) */ +/*0x64*/volatile unsigned int bx; /* X brline(RXI) */ + /* polygon(XI) */ + /* rectangle(XI) */ + /* bcopy(SRCX) */ + /* vscroll(SRCX) */ + /* fastfill(GO) */ +/*0x68*/volatile unsigned int dy; /* destination Y fastfill(DSTY) */ + /* bcopy(DSRY) */ + /* vscroll(DSRY) */ +/*0x6c*/volatile unsigned int dx; /* destination X fastfill(DSTX) */ + /* bcopy(DSTX) */ + /* vscroll(DSTX) */ +/*0x70*/volatile unsigned int bh; /* Y (alias to RYI) brline(DYI) */ + /* dot(DYI) */ + /* polygon(ETYI) */ + /* Height fastfill(H) */ + /* bcopy(H) */ + /* vscroll(H) */ + /* Y count fastfill(NY) */ +/*0x74*/volatile unsigned int bw; /* X dot(DXI) */ + /* brline(DXI) */ + /* polygon(ETXI) */ + /* fastfill(W) */ + /* bcopy(W) */ + /* vscroll(W) */ + /* fastfill(NX) */ +/*0x78*/unsigned int pad6[2]; /* Reserved */ +/*0x80*/unsigned int pad7[32]; /* Reserved */ + + /* Setup Unit's vertex state register */ +/*100*/ volatile unsigned int suvtx; +/*104*/ unsigned int pad8[63]; /* Reserved */ + + /* Frame Buffer Control Registers */ +/*200*/ volatile unsigned int ppc; /* Pixel Processor Control */ +/*204*/ volatile unsigned int wid; /* Current WID */ +/*208*/ volatile unsigned int fg; /* FG data */ +/*20c*/ volatile unsigned int bg; /* BG data */ +/*210*/ volatile unsigned int consty; /* Constant Y */ +/*214*/ volatile unsigned int constz; /* Constant Z */ +/*218*/ volatile unsigned int xclip; /* X Clip */ +/*21c*/ volatile unsigned int dcss; /* Depth Cue Scale Slope */ +/*220*/ volatile unsigned int vclipmin; /* Viewclip XY Min Bounds */ +/*224*/ volatile unsigned int vclipmax; /* Viewclip XY Max Bounds */ +/*228*/ volatile unsigned int vclipzmin; /* Viewclip Z Min Bounds */ +/*22c*/ volatile unsigned int vclipzmax; /* Viewclip Z Max Bounds */ +/*230*/ volatile unsigned int dcsf; /* Depth Cue Scale Front Bound */ +/*234*/ volatile unsigned int dcsb; /* Depth Cue Scale Back Bound */ +/*238*/ volatile unsigned int dczf; /* Depth Cue Z Front */ +/*23c*/ volatile unsigned int dczb; /* Depth Cue Z Back */ +/*240*/ unsigned int pad9; /* Reserved */ +/*244*/ volatile unsigned int blendc; /* Alpha Blend Control */ +/*248*/ volatile unsigned int blendc1; /* Alpha Blend Color 1 */ +/*24c*/ volatile unsigned int blendc2; /* Alpha Blend Color 2 */ +/*250*/ volatile unsigned int fbramitc; /* FB RAM Interleave Test Control */ +/*254*/ volatile unsigned int fbc; /* Frame Buffer Control */ +/*258*/ volatile unsigned int rop; /* Raster OPeration */ +/*25c*/ volatile unsigned int cmp; /* Frame Buffer Compare */ +/*260*/ volatile unsigned int matchab; /* Buffer AB Match Mask */ +/*264*/ volatile unsigned int matchc; /* Buffer C(YZ) Match Mask */ +/*268*/ volatile unsigned int magnab; /* Buffer AB Magnitude Mask */ +/*26c*/ volatile unsigned int magnc; /* Buffer C(YZ) Magnitude Mask */ +/*270*/ volatile unsigned int fbcfg0; /* Frame Buffer Config 0 */ +/*274*/ volatile unsigned int fbcfg1; /* Frame Buffer Config 1 */ +/*278*/ volatile unsigned int fbcfg2; /* Frame Buffer Config 2 */ +/*27c*/ volatile unsigned int fbcfg3; /* Frame Buffer Config 3 */ +/*280*/ volatile unsigned int ppcfg; /* Pixel Processor Config */ +/*284*/ volatile unsigned int pick; /* Picking Control */ +/*288*/ volatile unsigned int fillmode; /* FillMode */ +/*28c*/ volatile unsigned int fbramwac; /* FB RAM Write Address Control */ +/*290*/ volatile unsigned int pmask; /* RGB PlaneMask */ +/*294*/ volatile unsigned int xpmask; /* X PlaneMask */ +/*298*/ volatile unsigned int ypmask; /* Y PlaneMask */ +/*29c*/ volatile unsigned int zpmask; /* Z PlaneMask */ +/*2a0*/ ffb_auxclip auxclip[4]; /* Auxilliary Viewport Clip */ + + /* New 3dRAM III support regs */ +/*2c0*/ volatile unsigned int rawblend2; +/*2c4*/ volatile unsigned int rawpreblend; +/*2c8*/ volatile unsigned int rawstencil; +/*2cc*/ volatile unsigned int rawstencilctl; +/*2d0*/ volatile unsigned int threedram1; +/*2d4*/ volatile unsigned int threedram2; +/*2d8*/ volatile unsigned int passin; +/*2dc*/ volatile unsigned int rawclrdepth; +/*2e0*/ volatile unsigned int rawpmask; +/*2e4*/ volatile unsigned int rawcsrc; +/*2e8*/ volatile unsigned int rawmatch; +/*2ec*/ volatile unsigned int rawmagn; +/*2f0*/ volatile unsigned int rawropblend; +/*2f4*/ volatile unsigned int rawcmp; +/*2f8*/ volatile unsigned int rawwac; +/*2fc*/ volatile unsigned int fbramid; + +/*300*/ volatile unsigned int drawop; /* Draw OPeration */ +/*304*/ unsigned int pad10[2]; /* Reserved */ +/*30c*/ volatile unsigned int lpat; /* Line Pattern control */ +/*310*/ unsigned int pad11; /* Reserved */ +/*314*/ volatile unsigned int fontxy; /* XY Font coordinate */ +/*318*/ volatile unsigned int fontw; /* Font Width */ +/*31c*/ volatile unsigned int fontinc; /* Font Increment */ +/*320*/ volatile unsigned int font; /* Font bits */ +/*324*/ unsigned int pad12[3]; /* Reserved */ +/*330*/ volatile unsigned int blend2; +/*334*/ volatile unsigned int preblend; +/*338*/ volatile unsigned int stencil; +/*33c*/ volatile unsigned int stencilctl; + +/*340*/ unsigned int pad13[4]; /* Reserved */ +/*350*/ volatile unsigned int dcss1; /* Depth Cue Scale Slope 1 */ +/*354*/ volatile unsigned int dcss2; /* Depth Cue Scale Slope 2 */ +/*358*/ volatile unsigned int dcss3; /* Depth Cue Scale Slope 3 */ +/*35c*/ volatile unsigned int widpmask; +/*360*/ volatile unsigned int dcs2; +/*364*/ volatile unsigned int dcs3; +/*368*/ volatile unsigned int dcs4; +/*36c*/ unsigned int pad14; /* Reserved */ +/*370*/ volatile unsigned int dcd2; +/*374*/ volatile unsigned int dcd3; +/*378*/ volatile unsigned int dcd4; +/*37c*/ unsigned int pad15; /* Reserved */ +/*380*/ volatile unsigned int pattern[32]; /* area Pattern */ +/*400*/ unsigned int pad16[8]; /* Reserved */ +/*420*/ volatile unsigned int reset; /* chip RESET */ +/*424*/ unsigned int pad17[247]; /* Reserved */ +/*800*/ volatile unsigned int devid; /* Device ID */ +/*804*/ unsigned int pad18[63]; /* Reserved */ +/*900*/ volatile unsigned int ucsr; /* User Control & Status Register */ +/*904*/ unsigned int pad19[31]; /* Reserved */ +/*980*/ volatile unsigned int mer; /* Mode Enable Register */ +/*984*/ unsigned int pad20[1439]; /* Reserved */ +} ffb_fbc, *ffb_fbcPtr; + +struct ffb_hw_context { + int is_2d_only; + + unsigned int ppc; + unsigned int wid; + unsigned int fg; + unsigned int bg; + unsigned int consty; + unsigned int constz; + unsigned int xclip; + unsigned int dcss; + unsigned int vclipmin; + unsigned int vclipmax; + unsigned int vclipzmin; + unsigned int vclipzmax; + unsigned int dcsf; + unsigned int dcsb; + unsigned int dczf; + unsigned int dczb; + unsigned int blendc; + unsigned int blendc1; + unsigned int blendc2; + unsigned int fbc; + unsigned int rop; + unsigned int cmp; + unsigned int matchab; + unsigned int matchc; + unsigned int magnab; + unsigned int magnc; + unsigned int pmask; + unsigned int xpmask; + unsigned int ypmask; + unsigned int zpmask; + unsigned int auxclip0min; + unsigned int auxclip0max; + unsigned int auxclip1min; + unsigned int auxclip1max; + unsigned int auxclip2min; + unsigned int auxclip2max; + unsigned int auxclip3min; + unsigned int auxclip3max; + unsigned int drawop; + unsigned int lpat; + unsigned int fontxy; + unsigned int fontw; + unsigned int fontinc; + unsigned int area_pattern[32]; + unsigned int ucsr; + unsigned int stencil; + unsigned int stencilctl; + unsigned int dcss1; + unsigned int dcss2; + unsigned int dcss3; + unsigned int dcs2; + unsigned int dcs3; + unsigned int dcs4; + unsigned int dcd2; + unsigned int dcd3; + unsigned int dcd4; + unsigned int mer; +}; + +#define FFB_MAX_CTXS 32 + +enum ffb_chip_type { + ffb1_prototype = 0, /* Early pre-FCS FFB */ + ffb1_standard, /* First FCS FFB, 100Mhz UPA, 66MHz gclk */ + ffb1_speedsort, /* Second FCS FFB, 100Mhz UPA, 75MHz gclk */ + ffb2_prototype, /* Early pre-FCS vertical FFB2 */ + ffb2_vertical, /* First FCS FFB2/vertical, 100Mhz UPA, 100MHZ gclk, + 75(SingleBuffer)/83(DoubleBuffer) MHz fclk */ + ffb2_vertical_plus, /* Second FCS FFB2/vertical, same timings */ + ffb2_horizontal, /* First FCS FFB2/horizontal, same timings as FFB2/vert */ + ffb2_horizontal_plus, /* Second FCS FFB2/horizontal, same timings */ + afb_m3, /* FCS Elite3D, 3 float chips */ + afb_m6 /* FCS Elite3D, 6 float chips */ +}; + +typedef struct ffb_dev_priv { + /* Misc software state. */ + int prom_node; + enum ffb_chip_type ffb_type; + u64 card_phys_base; + struct miscdevice miscdev; + + /* Controller registers. */ + ffb_fbcPtr regs; + + /* Context table. */ + struct ffb_hw_context *hw_state[FFB_MAX_CTXS]; +} ffb_dev_priv_t; diff -urN linux-2.4.10/drivers/char/drm-4.0/fops.c linux-2.4.10-lia/drivers/char/drm-4.0/fops.c --- linux-2.4.10/drivers/char/drm-4.0/fops.c Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/fops.c Wed Aug 15 20:52:11 2001 @@ -0,0 +1,253 @@ +/* fops.c -- File operations for DRM -*- linux-c -*- + * Created: Mon Jan 4 08:58:31 1999 by faith@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rickard E. (Rik) Faith + * Daryll Strauss + * + */ + +#define __NO_VERSION__ +#include "drmP.h" +#include + +/* drm_open is called whenever a process opens /dev/drm. */ + +int drm_open_helper(struct inode *inode, struct file *filp, drm_device_t *dev) +{ + kdev_t minor = MINOR(inode->i_rdev); + drm_file_t *priv; + + if (filp->f_flags & O_EXCL) return -EBUSY; /* No exclusive opens */ + if (!drm_cpu_valid()) return -EINVAL; + + DRM_DEBUG("pid = %d, minor = %d\n", current->pid, minor); + + priv = drm_alloc(sizeof(*priv), DRM_MEM_FILES); + if(priv == NULL) + return -ENOMEM; + memset(priv, 0, sizeof(*priv)); + + filp->private_data = priv; + priv->uid = current->euid; + priv->pid = current->pid; + priv->minor = minor; + priv->dev = dev; + priv->ioctl_count = 0; + priv->authenticated = capable(CAP_SYS_ADMIN); + + down(&dev->struct_sem); + if (!dev->file_last) { + priv->next = NULL; + priv->prev = NULL; + dev->file_first = priv; + dev->file_last = priv; + } else { + priv->next = NULL; + priv->prev = dev->file_last; + dev->file_last->next = priv; + dev->file_last = priv; + } + up(&dev->struct_sem); + + return 0; +} + +int drm_flush(struct file *filp) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + + DRM_DEBUG("pid = %d, device = 0x%x, open_count = %d\n", + current->pid, dev->device, dev->open_count); + return 0; +} + +/* drm_release is called whenever a process closes /dev/drm*. Linux calls + this only if any mappings have been closed. */ + +int drm_release(struct inode *inode, struct file *filp) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + + DRM_DEBUG("pid = %d, device = 0x%x, open_count = %d\n", + current->pid, dev->device, dev->open_count); + + if (dev->lock.hw_lock + && _DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock) + && dev->lock.pid == current->pid) { + DRM_ERROR("Process %d dead, freeing lock for context %d\n", + current->pid, + _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock)); + drm_lock_free(dev, + &dev->lock.hw_lock->lock, + _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock)); + + /* FIXME: may require heavy-handed reset of + hardware at this point, possibly + processed via a callback to the X + server. */ + } + drm_reclaim_buffers(dev, priv->pid); + + drm_fasync(-1, filp, 0); + + down(&dev->struct_sem); + if (priv->prev) priv->prev->next = priv->next; + else dev->file_first = priv->next; + if (priv->next) priv->next->prev = priv->prev; + else dev->file_last = priv->prev; + up(&dev->struct_sem); + + drm_free(priv, sizeof(*priv), DRM_MEM_FILES); + + return 0; +} + +int drm_fasync(int fd, struct file *filp, int on) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + int retcode; + + DRM_DEBUG("fd = %d, device = 0x%x\n", fd, dev->device); + retcode = fasync_helper(fd, filp, on, &dev->buf_async); + if (retcode < 0) return retcode; + return 0; +} + + +/* The drm_read and drm_write_string code (especially that which manages + the circular buffer), is based on Alessandro Rubini's LINUX DEVICE + DRIVERS (Cambridge: O'Reilly, 1998), pages 111-113. */ + +ssize_t drm_read(struct file *filp, char *buf, size_t count, loff_t *off) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + int left; + int avail; + int send; + int cur; + + DRM_DEBUG("%p, %p\n", dev->buf_rp, dev->buf_wp); + + while (dev->buf_rp == dev->buf_wp) { + DRM_DEBUG(" sleeping\n"); + if (filp->f_flags & O_NONBLOCK) { + return -EAGAIN; + } + interruptible_sleep_on(&dev->buf_readers); + if (signal_pending(current)) { + DRM_DEBUG(" interrupted\n"); + return -ERESTARTSYS; + } + DRM_DEBUG(" awake\n"); + } + + left = (dev->buf_rp + DRM_BSZ - dev->buf_wp) % DRM_BSZ; + avail = DRM_BSZ - left; + send = DRM_MIN(avail, count); + + while (send) { + if (dev->buf_wp > dev->buf_rp) { + cur = DRM_MIN(send, dev->buf_wp - dev->buf_rp); + } else { + cur = DRM_MIN(send, dev->buf_end - dev->buf_rp); + } + if (copy_to_user(buf, dev->buf_rp, cur)) + return -EFAULT; + dev->buf_rp += cur; + if (dev->buf_rp == dev->buf_end) dev->buf_rp = dev->buf; + send -= cur; + } + + wake_up_interruptible(&dev->buf_writers); + return DRM_MIN(avail, count);; +} + +int drm_write_string(drm_device_t *dev, const char *s) +{ + int left = (dev->buf_rp + DRM_BSZ - dev->buf_wp) % DRM_BSZ; + int send = strlen(s); + int count; + + DRM_DEBUG("%d left, %d to send (%p, %p)\n", + left, send, dev->buf_rp, dev->buf_wp); + + if (left == 1 || dev->buf_wp != dev->buf_rp) { + DRM_ERROR("Buffer not empty (%d left, wp = %p, rp = %p)\n", + left, + dev->buf_wp, + dev->buf_rp); + } + + while (send) { + if (dev->buf_wp >= dev->buf_rp) { + count = DRM_MIN(send, dev->buf_end - dev->buf_wp); + if (count == left) --count; /* Leave a hole */ + } else { + count = DRM_MIN(send, dev->buf_rp - dev->buf_wp - 1); + } + strncpy(dev->buf_wp, s, count); + dev->buf_wp += count; + if (dev->buf_wp == dev->buf_end) dev->buf_wp = dev->buf; + send -= count; + } + +#if LINUX_VERSION_CODE < 0x020315 && !defined(KILLFASYNCHASTHREEPARAMETERS) + /* The extra parameter to kill_fasync was added in 2.3.21, and is + _not_ present in _stock_ 2.2.14 and 2.2.15. However, some + distributions patch 2.2.x kernels to add this parameter. The + Makefile.linux attempts to detect this addition and defines + KILLFASYNCHASTHREEPARAMETERS if three parameters are found. */ + if (dev->buf_async) kill_fasync(dev->buf_async, SIGIO); +#else + + /* Parameter added in 2.3.21. */ +#if LINUX_VERSION_CODE < 0x020400 + if (dev->buf_async) kill_fasync(dev->buf_async, SIGIO, POLL_IN); +#else + /* Type of first parameter changed in + Linux 2.4.0-test2... */ + if (dev->buf_async) kill_fasync(&dev->buf_async, SIGIO, POLL_IN); +#endif +#endif + DRM_DEBUG("waking\n"); + wake_up_interruptible(&dev->buf_readers); + return 0; +} + +unsigned int drm_poll(struct file *filp, struct poll_table_struct *wait) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + + poll_wait(filp, &dev->buf_readers, wait); + if (dev->buf_wp != dev->buf_rp) return POLLIN | POLLRDNORM; + return 0; +} diff -urN linux-2.4.10/drivers/char/drm-4.0/gamma_dma.c linux-2.4.10-lia/drivers/char/drm-4.0/gamma_dma.c --- linux-2.4.10/drivers/char/drm-4.0/gamma_dma.c Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/gamma_dma.c Wed Aug 15 20:52:11 2001 @@ -0,0 +1,836 @@ +/* gamma_dma.c -- DMA support for GMX 2000 -*- linux-c -*- + * Created: Fri Mar 19 14:30:16 1999 by faith@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rickard E. (Rik) Faith + * + */ + +#define __NO_VERSION__ +#include "drmP.h" +#include "gamma_drv.h" + +#include /* For task queue support */ + + +/* WARNING!!! MAGIC NUMBER!!! The number of regions already added to the + kernel must be specified here. Currently, the number is 2. This must + match the order the X server uses for instantiating register regions , + or must be passed in a new ioctl. */ +#define GAMMA_REG(reg) \ + (2 \ + + ((reg < 0x1000) \ + ? 0 \ + : ((reg < 0x10000) ? 1 : ((reg < 0x11000) ? 2 : 3)))) + +#define GAMMA_OFF(reg) \ + ((reg < 0x1000) \ + ? reg \ + : ((reg < 0x10000) \ + ? (reg - 0x1000) \ + : ((reg < 0x11000) \ + ? (reg - 0x10000) \ + : (reg - 0x11000)))) + +#define GAMMA_BASE(reg) ((unsigned long)dev->maplist[GAMMA_REG(reg)]->handle) +#define GAMMA_ADDR(reg) (GAMMA_BASE(reg) + GAMMA_OFF(reg)) +#define GAMMA_DEREF(reg) *(__volatile__ int *)GAMMA_ADDR(reg) +#define GAMMA_READ(reg) GAMMA_DEREF(reg) +#define GAMMA_WRITE(reg,val) do { GAMMA_DEREF(reg) = val; } while (0) + +#define GAMMA_BROADCASTMASK 0x9378 +#define GAMMA_COMMANDINTENABLE 0x0c48 +#define GAMMA_DMAADDRESS 0x0028 +#define GAMMA_DMACOUNT 0x0030 +#define GAMMA_FILTERMODE 0x8c00 +#define GAMMA_GCOMMANDINTFLAGS 0x0c50 +#define GAMMA_GCOMMANDMODE 0x0c40 +#define GAMMA_GCOMMANDSTATUS 0x0c60 +#define GAMMA_GDELAYTIMER 0x0c38 +#define GAMMA_GDMACONTROL 0x0060 +#define GAMMA_GINTENABLE 0x0808 +#define GAMMA_GINTFLAGS 0x0810 +#define GAMMA_INFIFOSPACE 0x0018 +#define GAMMA_OUTFIFOWORDS 0x0020 +#define GAMMA_OUTPUTFIFO 0x2000 +#define GAMMA_SYNC 0x8c40 +#define GAMMA_SYNC_TAG 0x0188 + +static inline void gamma_dma_dispatch(drm_device_t *dev, unsigned long address, + unsigned long length) +{ + GAMMA_WRITE(GAMMA_DMAADDRESS, virt_to_phys((void *)address)); + while (GAMMA_READ(GAMMA_GCOMMANDSTATUS) != 4) + ; + GAMMA_WRITE(GAMMA_DMACOUNT, length / 4); +} + +static inline void gamma_dma_quiescent_single(drm_device_t *dev) +{ + while (GAMMA_READ(GAMMA_DMACOUNT)) + ; + while (GAMMA_READ(GAMMA_INFIFOSPACE) < 3) + ; + + GAMMA_WRITE(GAMMA_FILTERMODE, 1 << 10); + GAMMA_WRITE(GAMMA_SYNC, 0); + + do { + while (!GAMMA_READ(GAMMA_OUTFIFOWORDS)) + ; + } while (GAMMA_READ(GAMMA_OUTPUTFIFO) != GAMMA_SYNC_TAG); +} + +static inline void gamma_dma_quiescent_dual(drm_device_t *dev) +{ + while (GAMMA_READ(GAMMA_DMACOUNT)) + ; + while (GAMMA_READ(GAMMA_INFIFOSPACE) < 3) + ; + + GAMMA_WRITE(GAMMA_BROADCASTMASK, 3); + + GAMMA_WRITE(GAMMA_FILTERMODE, 1 << 10); + GAMMA_WRITE(GAMMA_SYNC, 0); + + /* Read from first MX */ + do { + while (!GAMMA_READ(GAMMA_OUTFIFOWORDS)) + ; + } while (GAMMA_READ(GAMMA_OUTPUTFIFO) != GAMMA_SYNC_TAG); + + /* Read from second MX */ + do { + while (!GAMMA_READ(GAMMA_OUTFIFOWORDS + 0x10000)) + ; + } while (GAMMA_READ(GAMMA_OUTPUTFIFO + 0x10000) != GAMMA_SYNC_TAG); +} + +static inline void gamma_dma_ready(drm_device_t *dev) +{ + while (GAMMA_READ(GAMMA_DMACOUNT)) + ; +} + +static inline int gamma_dma_is_ready(drm_device_t *dev) +{ + return !GAMMA_READ(GAMMA_DMACOUNT); +} + +static void gamma_dma_service(int irq, void *device, struct pt_regs *regs) +{ + drm_device_t *dev = (drm_device_t *)device; + drm_device_dma_t *dma = dev->dma; + + atomic_inc(&dev->total_irq); + GAMMA_WRITE(GAMMA_GDELAYTIMER, 0xc350/2); /* 0x05S */ + GAMMA_WRITE(GAMMA_GCOMMANDINTFLAGS, 8); + GAMMA_WRITE(GAMMA_GINTFLAGS, 0x2001); + if (gamma_dma_is_ready(dev)) { + /* Free previous buffer */ + if (test_and_set_bit(0, &dev->dma_flag)) { + atomic_inc(&dma->total_missed_free); + return; + } + if (dma->this_buffer) { + drm_free_buffer(dev, dma->this_buffer); + dma->this_buffer = NULL; + } + clear_bit(0, &dev->dma_flag); + + /* Dispatch new buffer */ + queue_task(&dev->tq, &tq_immediate); + mark_bh(IMMEDIATE_BH); + } +} + +/* Only called by gamma_dma_schedule. */ +static int gamma_do_dma(drm_device_t *dev, int locked) +{ + unsigned long address; + unsigned long length; + drm_buf_t *buf; + int retcode = 0; + drm_device_dma_t *dma = dev->dma; +#if DRM_DMA_HISTOGRAM + cycles_t dma_start, dma_stop; +#endif + + if (test_and_set_bit(0, &dev->dma_flag)) { + atomic_inc(&dma->total_missed_dma); + return -EBUSY; + } + +#if DRM_DMA_HISTOGRAM + dma_start = get_cycles(); +#endif + + if (!dma->next_buffer) { + DRM_ERROR("No next_buffer\n"); + clear_bit(0, &dev->dma_flag); + return -EINVAL; + } + + buf = dma->next_buffer; + address = (unsigned long)buf->address; + length = buf->used; + + DRM_DEBUG("context %d, buffer %d (%ld bytes)\n", + buf->context, buf->idx, length); + + if (buf->list == DRM_LIST_RECLAIM) { + drm_clear_next_buffer(dev); + drm_free_buffer(dev, buf); + clear_bit(0, &dev->dma_flag); + return -EINVAL; + } + + if (!length) { + DRM_ERROR("0 length buffer\n"); + drm_clear_next_buffer(dev); + drm_free_buffer(dev, buf); + clear_bit(0, &dev->dma_flag); + return 0; + } + + if (!gamma_dma_is_ready(dev)) { + clear_bit(0, &dev->dma_flag); + return -EBUSY; + } + + if (buf->while_locked) { + if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { + DRM_ERROR("Dispatching buffer %d from pid %d" + " \"while locked\", but no lock held\n", + buf->idx, buf->pid); + } + } else { + if (!locked && !drm_lock_take(&dev->lock.hw_lock->lock, + DRM_KERNEL_CONTEXT)) { + atomic_inc(&dma->total_missed_lock); + clear_bit(0, &dev->dma_flag); + return -EBUSY; + } + } + + if (dev->last_context != buf->context + && !(dev->queuelist[buf->context]->flags + & _DRM_CONTEXT_PRESERVED)) { + /* PRE: dev->last_context != buf->context */ + if (drm_context_switch(dev, dev->last_context, buf->context)) { + drm_clear_next_buffer(dev); + drm_free_buffer(dev, buf); + } + retcode = -EBUSY; + goto cleanup; + + /* POST: we will wait for the context + switch and will dispatch on a later call + when dev->last_context == buf->context. + NOTE WE HOLD THE LOCK THROUGHOUT THIS + TIME! */ + } + + drm_clear_next_buffer(dev); + buf->pending = 1; + buf->waiting = 0; + buf->list = DRM_LIST_PEND; +#if DRM_DMA_HISTOGRAM + buf->time_dispatched = get_cycles(); +#endif + + gamma_dma_dispatch(dev, address, length); + drm_free_buffer(dev, dma->this_buffer); + dma->this_buffer = buf; + + atomic_add(length, &dma->total_bytes); + atomic_inc(&dma->total_dmas); + + if (!buf->while_locked && !dev->context_flag && !locked) { + if (drm_lock_free(dev, &dev->lock.hw_lock->lock, + DRM_KERNEL_CONTEXT)) { + DRM_ERROR("\n"); + } + } +cleanup: + + clear_bit(0, &dev->dma_flag); + +#if DRM_DMA_HISTOGRAM + dma_stop = get_cycles(); + atomic_inc(&dev->histo.dma[drm_histogram_slot(dma_stop - dma_start)]); +#endif + + return retcode; +} + +static void gamma_dma_schedule_timer_wrapper(unsigned long dev) +{ + gamma_dma_schedule((drm_device_t *)dev, 0); +} + +static void gamma_dma_schedule_tq_wrapper(void *dev) +{ + gamma_dma_schedule(dev, 0); +} + +int gamma_dma_schedule(drm_device_t *dev, int locked) +{ + int next; + drm_queue_t *q; + drm_buf_t *buf; + int retcode = 0; + int processed = 0; + int missed; + int expire = 20; + drm_device_dma_t *dma = dev->dma; +#if DRM_DMA_HISTOGRAM + cycles_t schedule_start; +#endif + + if (test_and_set_bit(0, &dev->interrupt_flag)) { + /* Not reentrant */ + atomic_inc(&dma->total_missed_sched); + return -EBUSY; + } + missed = atomic_read(&dma->total_missed_sched); + +#if DRM_DMA_HISTOGRAM + schedule_start = get_cycles(); +#endif + +again: + if (dev->context_flag) { + clear_bit(0, &dev->interrupt_flag); + return -EBUSY; + } + if (dma->next_buffer) { + /* Unsent buffer that was previously + selected, but that couldn't be sent + because the lock could not be obtained + or the DMA engine wasn't ready. Try + again. */ + atomic_inc(&dma->total_tried); + if (!(retcode = gamma_do_dma(dev, locked))) { + atomic_inc(&dma->total_hit); + ++processed; + } + } else { + do { + next = drm_select_queue(dev, + gamma_dma_schedule_timer_wrapper); + if (next >= 0) { + q = dev->queuelist[next]; + buf = drm_waitlist_get(&q->waitlist); + dma->next_buffer = buf; + dma->next_queue = q; + if (buf && buf->list == DRM_LIST_RECLAIM) { + drm_clear_next_buffer(dev); + drm_free_buffer(dev, buf); + } + } + } while (next >= 0 && !dma->next_buffer); + if (dma->next_buffer) { + if (!(retcode = gamma_do_dma(dev, locked))) { + ++processed; + } + } + } + + if (--expire) { + if (missed != atomic_read(&dma->total_missed_sched)) { + atomic_inc(&dma->total_lost); + if (gamma_dma_is_ready(dev)) goto again; + } + if (processed && gamma_dma_is_ready(dev)) { + atomic_inc(&dma->total_lost); + processed = 0; + goto again; + } + } + + clear_bit(0, &dev->interrupt_flag); + +#if DRM_DMA_HISTOGRAM + atomic_inc(&dev->histo.schedule[drm_histogram_slot(get_cycles() + - schedule_start)]); +#endif + return retcode; +} + +static int gamma_dma_priority(drm_device_t *dev, drm_dma_t *d) +{ + unsigned long address; + unsigned long length; + int must_free = 0; + int retcode = 0; + int i; + int idx; + drm_buf_t *buf; + drm_buf_t *last_buf = NULL; + drm_device_dma_t *dma = dev->dma; + DECLARE_WAITQUEUE(entry, current); + + /* Turn off interrupt handling */ + while (test_and_set_bit(0, &dev->interrupt_flag)) { + schedule(); + if (signal_pending(current)) return -EINTR; + } + if (!(d->flags & _DRM_DMA_WHILE_LOCKED)) { + while (!drm_lock_take(&dev->lock.hw_lock->lock, + DRM_KERNEL_CONTEXT)) { + schedule(); + if (signal_pending(current)) { + clear_bit(0, &dev->interrupt_flag); + return -EINTR; + } + } + ++must_free; + } + atomic_inc(&dma->total_prio); + + for (i = 0; i < d->send_count; i++) { + idx = d->send_indices[i]; + if (idx < 0 || idx >= dma->buf_count) { + DRM_ERROR("Index %d (of %d max)\n", + d->send_indices[i], dma->buf_count - 1); + continue; + } + buf = dma->buflist[ idx ]; + if (buf->pid != current->pid) { + DRM_ERROR("Process %d using buffer owned by %d\n", + current->pid, buf->pid); + retcode = -EINVAL; + goto cleanup; + } + if (buf->list != DRM_LIST_NONE) { + DRM_ERROR("Process %d using %d's buffer on list %d\n", + current->pid, buf->pid, buf->list); + retcode = -EINVAL; + goto cleanup; + } + /* This isn't a race condition on + buf->list, since our concern is the + buffer reclaim during the time the + process closes the /dev/drm? handle, so + it can't also be doing DMA. */ + buf->list = DRM_LIST_PRIO; + buf->used = d->send_sizes[i]; + buf->context = d->context; + buf->while_locked = d->flags & _DRM_DMA_WHILE_LOCKED; + address = (unsigned long)buf->address; + length = buf->used; + if (!length) { + DRM_ERROR("0 length buffer\n"); + } + if (buf->pending) { + DRM_ERROR("Sending pending buffer:" + " buffer %d, offset %d\n", + d->send_indices[i], i); + retcode = -EINVAL; + goto cleanup; + } + if (buf->waiting) { + DRM_ERROR("Sending waiting buffer:" + " buffer %d, offset %d\n", + d->send_indices[i], i); + retcode = -EINVAL; + goto cleanup; + } + buf->pending = 1; + + if (dev->last_context != buf->context + && !(dev->queuelist[buf->context]->flags + & _DRM_CONTEXT_PRESERVED)) { + add_wait_queue(&dev->context_wait, &entry); + current->state = TASK_INTERRUPTIBLE; + /* PRE: dev->last_context != buf->context */ + drm_context_switch(dev, dev->last_context, + buf->context); + /* POST: we will wait for the context + switch and will dispatch on a later call + when dev->last_context == buf->context. + NOTE WE HOLD THE LOCK THROUGHOUT THIS + TIME! */ + schedule(); + current->state = TASK_RUNNING; + remove_wait_queue(&dev->context_wait, &entry); + if (signal_pending(current)) { + retcode = -EINTR; + goto cleanup; + } + if (dev->last_context != buf->context) { + DRM_ERROR("Context mismatch: %d %d\n", + dev->last_context, + buf->context); + } + } + +#if DRM_DMA_HISTOGRAM + buf->time_queued = get_cycles(); + buf->time_dispatched = buf->time_queued; +#endif + gamma_dma_dispatch(dev, address, length); + atomic_add(length, &dma->total_bytes); + atomic_inc(&dma->total_dmas); + + if (last_buf) { + drm_free_buffer(dev, last_buf); + } + last_buf = buf; + } + + +cleanup: + if (last_buf) { + gamma_dma_ready(dev); + drm_free_buffer(dev, last_buf); + } + + if (must_free && !dev->context_flag) { + if (drm_lock_free(dev, &dev->lock.hw_lock->lock, + DRM_KERNEL_CONTEXT)) { + DRM_ERROR("\n"); + } + } + clear_bit(0, &dev->interrupt_flag); + return retcode; +} + +static int gamma_dma_send_buffers(drm_device_t *dev, drm_dma_t *d) +{ + DECLARE_WAITQUEUE(entry, current); + drm_buf_t *last_buf = NULL; + int retcode = 0; + drm_device_dma_t *dma = dev->dma; + + if (d->flags & _DRM_DMA_BLOCK) { + last_buf = dma->buflist[d->send_indices[d->send_count-1]]; + add_wait_queue(&last_buf->dma_wait, &entry); + } + + if ((retcode = drm_dma_enqueue(dev, d))) { + if (d->flags & _DRM_DMA_BLOCK) + remove_wait_queue(&last_buf->dma_wait, &entry); + return retcode; + } + + gamma_dma_schedule(dev, 0); + + if (d->flags & _DRM_DMA_BLOCK) { + DRM_DEBUG("%d waiting\n", current->pid); + for (;;) { + current->state = TASK_INTERRUPTIBLE; + if (!last_buf->waiting && !last_buf->pending) + break; /* finished */ + schedule(); + if (signal_pending(current)) { + retcode = -EINTR; /* Can't restart */ + break; + } + } + current->state = TASK_RUNNING; + DRM_DEBUG("%d running\n", current->pid); + remove_wait_queue(&last_buf->dma_wait, &entry); + if (!retcode + || (last_buf->list==DRM_LIST_PEND && !last_buf->pending)) { + if (!waitqueue_active(&last_buf->dma_wait)) { + drm_free_buffer(dev, last_buf); + } + } + if (retcode) { + DRM_ERROR("ctx%d w%d p%d c%d i%d l%d %d/%d\n", + d->context, + last_buf->waiting, + last_buf->pending, + DRM_WAITCOUNT(dev, d->context), + last_buf->idx, + last_buf->list, + last_buf->pid, + current->pid); + } + } + return retcode; +} + +int gamma_dma(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_device_dma_t *dma = dev->dma; + int retcode = 0; + drm_dma_t d; + + if (copy_from_user(&d, (drm_dma_t *)arg, sizeof(d))) + return -EFAULT; + DRM_DEBUG("%d %d: %d send, %d req\n", + current->pid, d.context, d.send_count, d.request_count); + + if (d.context == DRM_KERNEL_CONTEXT || d.context >= dev->queue_slots) { + DRM_ERROR("Process %d using context %d\n", + current->pid, d.context); + return -EINVAL; + } + if (d.send_count < 0 || d.send_count > dma->buf_count) { + DRM_ERROR("Process %d trying to send %d buffers (of %d max)\n", + current->pid, d.send_count, dma->buf_count); + return -EINVAL; + } + if (d.request_count < 0 || d.request_count > dma->buf_count) { + DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", + current->pid, d.request_count, dma->buf_count); + return -EINVAL; + } + + if (d.send_count) { + if (d.flags & _DRM_DMA_PRIORITY) + retcode = gamma_dma_priority(dev, &d); + else + retcode = gamma_dma_send_buffers(dev, &d); + } + + d.granted_count = 0; + + if (!retcode && d.request_count) { + retcode = drm_dma_get_buffers(dev, &d); + } + + DRM_DEBUG("%d returning, granted = %d\n", + current->pid, d.granted_count); + if (copy_to_user((drm_dma_t *)arg, &d, sizeof(d))) + return -EFAULT; + + return retcode; +} + +int gamma_irq_install(drm_device_t *dev, int irq) +{ + int retcode; + + if (!irq) return -EINVAL; + + down(&dev->struct_sem); + if (dev->irq) { + up(&dev->struct_sem); + return -EBUSY; + } + dev->irq = irq; + up(&dev->struct_sem); + + DRM_DEBUG("%d\n", irq); + + dev->context_flag = 0; + dev->interrupt_flag = 0; + dev->dma_flag = 0; + + dev->dma->next_buffer = NULL; + dev->dma->next_queue = NULL; + dev->dma->this_buffer = NULL; + + INIT_LIST_HEAD(&dev->tq.list); + dev->tq.sync = 0; + dev->tq.routine = gamma_dma_schedule_tq_wrapper; + dev->tq.data = dev; + + + /* Before installing handler */ + GAMMA_WRITE(GAMMA_GCOMMANDMODE, 0); + GAMMA_WRITE(GAMMA_GDMACONTROL, 0); + + /* Install handler */ + if ((retcode = request_irq(dev->irq, + gamma_dma_service, + 0, + dev->devname, + dev))) { + down(&dev->struct_sem); + dev->irq = 0; + up(&dev->struct_sem); + return retcode; + } + + /* After installing handler */ + GAMMA_WRITE(GAMMA_GINTENABLE, 0x2001); + GAMMA_WRITE(GAMMA_COMMANDINTENABLE, 0x0008); + GAMMA_WRITE(GAMMA_GDELAYTIMER, 0x39090); + + return 0; +} + +int gamma_irq_uninstall(drm_device_t *dev) +{ + int irq; + + down(&dev->struct_sem); + irq = dev->irq; + dev->irq = 0; + up(&dev->struct_sem); + + if (!irq) return -EINVAL; + + DRM_DEBUG("%d\n", irq); + + GAMMA_WRITE(GAMMA_GDELAYTIMER, 0); + GAMMA_WRITE(GAMMA_COMMANDINTENABLE, 0); + GAMMA_WRITE(GAMMA_GINTENABLE, 0); + free_irq(irq, dev); + + return 0; +} + + +int gamma_control(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_control_t ctl; + int retcode; + + if (copy_from_user(&ctl, (drm_control_t *)arg, sizeof(ctl))) + return -EFAULT; + + switch (ctl.func) { + case DRM_INST_HANDLER: + if ((retcode = gamma_irq_install(dev, ctl.irq))) + return retcode; + break; + case DRM_UNINST_HANDLER: + if ((retcode = gamma_irq_uninstall(dev))) + return retcode; + break; + default: + return -EINVAL; + } + return 0; +} + +int gamma_lock(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + DECLARE_WAITQUEUE(entry, current); + int ret = 0; + drm_lock_t lock; + drm_queue_t *q; +#if DRM_DMA_HISTOGRAM + cycles_t start; + + dev->lck_start = start = get_cycles(); +#endif + + if (copy_from_user(&lock, (drm_lock_t *)arg, sizeof(lock))) + return -EFAULT; + + if (lock.context == DRM_KERNEL_CONTEXT) { + DRM_ERROR("Process %d using kernel context %d\n", + current->pid, lock.context); + return -EINVAL; + } + + DRM_DEBUG("%d (pid %d) requests lock (0x%08x), flags = 0x%08x\n", + lock.context, current->pid, dev->lock.hw_lock->lock, + lock.flags); + + if (lock.context < 0 || lock.context >= dev->queue_count) + return -EINVAL; + q = dev->queuelist[lock.context]; + + ret = drm_flush_block_and_flush(dev, lock.context, lock.flags); + + if (!ret) { + if (_DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock) + != lock.context) { + long j = jiffies - dev->lock.lock_time; + + if (j > 0 && j <= DRM_LOCK_SLICE) { + /* Can't take lock if we just had it and + there is contention. */ + current->state = TASK_INTERRUPTIBLE; + schedule_timeout(j); + } + } + add_wait_queue(&dev->lock.lock_queue, &entry); + for (;;) { + current->state = TASK_INTERRUPTIBLE; + if (!dev->lock.hw_lock) { + /* Device has been unregistered */ + ret = -EINTR; + break; + } + if (drm_lock_take(&dev->lock.hw_lock->lock, + lock.context)) { + dev->lock.pid = current->pid; + dev->lock.lock_time = jiffies; + atomic_inc(&dev->total_locks); + atomic_inc(&q->total_locks); + break; /* Got lock */ + } + + /* Contention */ + atomic_inc(&dev->total_sleeps); + schedule(); + if (signal_pending(current)) { + ret = -ERESTARTSYS; + break; + } + } + current->state = TASK_RUNNING; + remove_wait_queue(&dev->lock.lock_queue, &entry); + } + + drm_flush_unblock(dev, lock.context, lock.flags); /* cleanup phase */ + + if (!ret) { + sigemptyset(&dev->sigmask); + sigaddset(&dev->sigmask, SIGSTOP); + sigaddset(&dev->sigmask, SIGTSTP); + sigaddset(&dev->sigmask, SIGTTIN); + sigaddset(&dev->sigmask, SIGTTOU); + dev->sigdata.context = lock.context; + dev->sigdata.lock = dev->lock.hw_lock; + block_all_signals(drm_notifier, &dev->sigdata, &dev->sigmask); + + if (lock.flags & _DRM_LOCK_READY) + gamma_dma_ready(dev); + if (lock.flags & _DRM_LOCK_QUIESCENT) { + if (gamma_found() == 1) { + gamma_dma_quiescent_single(dev); + } else { + gamma_dma_quiescent_dual(dev); + } + } + } + DRM_DEBUG("%d %s\n", lock.context, ret ? "interrupted" : "has lock"); + +#if DRM_DMA_HISTOGRAM + atomic_inc(&dev->histo.lacq[drm_histogram_slot(get_cycles() - start)]); +#endif + + return ret; +} diff -urN linux-2.4.10/drivers/char/drm-4.0/gamma_drv.c linux-2.4.10-lia/drivers/char/drm-4.0/gamma_drv.c --- linux-2.4.10/drivers/char/drm-4.0/gamma_drv.c Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/gamma_drv.c Mon Aug 20 18:09:34 2001 @@ -0,0 +1,571 @@ +/* gamma.c -- 3dlabs GMX 2000 driver -*- linux-c -*- + * Created: Mon Jan 4 08:58:31 1999 by faith@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rickard E. (Rik) Faith + * + */ + +#include +#include "drmP.h" +#include "gamma_drv.h" + +#ifndef PCI_DEVICE_ID_3DLABS_GAMMA +#define PCI_DEVICE_ID_3DLABS_GAMMA 0x0008 +#endif +#ifndef PCI_DEVICE_ID_3DLABS_MX +#define PCI_DEVICE_ID_3DLABS_MX 0x0006 +#endif + +#define GAMMA_NAME "gamma" +#define GAMMA_DESC "3dlabs GMX 2000" +#define GAMMA_DATE "20000910" +#define GAMMA_MAJOR 1 +#define GAMMA_MINOR 0 +#define GAMMA_PATCHLEVEL 0 + +static drm_device_t gamma_device; + +static struct file_operations gamma_fops = { +#if LINUX_VERSION_CODE >= 0x020400 + /* This started being used during 2.4.0-test */ + owner: THIS_MODULE, +#endif + open: gamma_open, + flush: drm_flush, + release: gamma_release, + ioctl: gamma_ioctl, + mmap: drm_mmap, + read: drm_read, + fasync: drm_fasync, + poll: drm_poll, +}; + +static struct miscdevice gamma_misc = { + minor: MISC_DYNAMIC_MINOR, + name: GAMMA_NAME, + fops: &gamma_fops, +}; + +static drm_ioctl_desc_t gamma_ioctls[] = { + [DRM_IOCTL_NR(DRM_IOCTL_VERSION)] = { gamma_version, 0, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_GET_UNIQUE)] = { drm_getunique, 0, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_GET_MAGIC)] = { drm_getmagic, 0, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_IRQ_BUSID)] = { drm_irq_busid, 0, 1 }, + + [DRM_IOCTL_NR(DRM_IOCTL_SET_UNIQUE)] = { drm_setunique, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_BLOCK)] = { drm_block, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_UNBLOCK)] = { drm_unblock, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_CONTROL)] = { gamma_control, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_AUTH_MAGIC)] = { drm_authmagic, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_ADD_MAP)] = { drm_addmap, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_ADD_BUFS)] = { drm_addbufs, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_MARK_BUFS)] = { drm_markbufs, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_INFO_BUFS)] = { drm_infobufs, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_MAP_BUFS)] = { drm_mapbufs, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_FREE_BUFS)] = { drm_freebufs, 1, 0 }, + + [DRM_IOCTL_NR(DRM_IOCTL_ADD_CTX)] = { drm_addctx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_RM_CTX)] = { drm_rmctx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_MOD_CTX)] = { drm_modctx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_GET_CTX)] = { drm_getctx, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_SWITCH_CTX)] = { drm_switchctx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_NEW_CTX)] = { drm_newctx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_RES_CTX)] = { drm_resctx, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_ADD_DRAW)] = { drm_adddraw, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_RM_DRAW)] = { drm_rmdraw, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_DMA)] = { gamma_dma, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_LOCK)] = { gamma_lock, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_UNLOCK)] = { gamma_unlock, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_FINISH)] = { drm_finish, 1, 0 }, +}; +#define GAMMA_IOCTL_COUNT DRM_ARRAY_SIZE(gamma_ioctls) + +#ifdef MODULE +static char *gamma = NULL; +#endif +static int devices = 0; + +MODULE_AUTHOR("VA Linux Systems, Inc."); +MODULE_DESCRIPTION("3dlabs GMX 2000"); +MODULE_PARM(gamma, "s"); +MODULE_PARM(devices, "i"); +MODULE_PARM_DESC(devices, + "devices=x, where x is the number of MX chips on card\n"); +#ifndef MODULE +/* gamma_options is called by the kernel to parse command-line options + * passed via the boot-loader (e.g., LILO). It calls the insmod option + * routine, drm_parse_options. + */ + + +static int __init gamma_options(char *str) +{ + drm_parse_options(str); + return 1; +} + +__setup("gamma=", gamma_options); +#endif + +static int gamma_setup(drm_device_t *dev) +{ + int i; + + atomic_set(&dev->ioctl_count, 0); + atomic_set(&dev->vma_count, 0); + dev->buf_use = 0; + atomic_set(&dev->buf_alloc, 0); + + drm_dma_setup(dev); + + atomic_set(&dev->total_open, 0); + atomic_set(&dev->total_close, 0); + atomic_set(&dev->total_ioctl, 0); + atomic_set(&dev->total_irq, 0); + atomic_set(&dev->total_ctx, 0); + atomic_set(&dev->total_locks, 0); + atomic_set(&dev->total_unlocks, 0); + atomic_set(&dev->total_contends, 0); + atomic_set(&dev->total_sleeps, 0); + + for (i = 0; i < DRM_HASH_SIZE; i++) { + dev->magiclist[i].head = NULL; + dev->magiclist[i].tail = NULL; + } + dev->maplist = NULL; + dev->map_count = 0; + dev->vmalist = NULL; + dev->lock.hw_lock = NULL; + init_waitqueue_head(&dev->lock.lock_queue); + dev->queue_count = 0; + dev->queue_reserved = 0; + dev->queue_slots = 0; + dev->queuelist = NULL; + dev->irq = 0; + dev->context_flag = 0; + dev->interrupt_flag = 0; + dev->dma_flag = 0; + dev->last_context = 0; + dev->last_switch = 0; + dev->last_checked = 0; + init_timer(&dev->timer); + init_waitqueue_head(&dev->context_wait); +#if DRM_DMA_HISTO + memset(&dev->histo, 0, sizeof(dev->histo)); +#endif + dev->ctx_start = 0; + dev->lck_start = 0; + + dev->buf_rp = dev->buf; + dev->buf_wp = dev->buf; + dev->buf_end = dev->buf + DRM_BSZ; + dev->buf_async = NULL; + init_waitqueue_head(&dev->buf_readers); + init_waitqueue_head(&dev->buf_writers); + + DRM_DEBUG("\n"); + + /* The kernel's context could be created here, but is now created + in drm_dma_enqueue. This is more resource-efficient for + hardware that does not do DMA, but may mean that + drm_select_queue fails between the time the interrupt is + initialized and the time the queues are initialized. */ + + return 0; +} + + +static int gamma_takedown(drm_device_t *dev) +{ + int i; + drm_magic_entry_t *pt, *next; + drm_map_t *map; + drm_vma_entry_t *vma, *vma_next; + + DRM_DEBUG("\n"); + + if (dev->irq) gamma_irq_uninstall(dev); + + down(&dev->struct_sem); + del_timer(&dev->timer); + + if (dev->devname) { + drm_free(dev->devname, strlen(dev->devname)+1, DRM_MEM_DRIVER); + dev->devname = NULL; + } + + if (dev->unique) { + drm_free(dev->unique, strlen(dev->unique)+1, DRM_MEM_DRIVER); + dev->unique = NULL; + dev->unique_len = 0; + } + /* Clear pid list */ + for (i = 0; i < DRM_HASH_SIZE; i++) { + for (pt = dev->magiclist[i].head; pt; pt = next) { + next = pt->next; + drm_free(pt, sizeof(*pt), DRM_MEM_MAGIC); + } + dev->magiclist[i].head = dev->magiclist[i].tail = NULL; + } + + /* Clear vma list (only built for debugging) */ + if (dev->vmalist) { + for (vma = dev->vmalist; vma; vma = vma_next) { + vma_next = vma->next; + drm_free(vma, sizeof(*vma), DRM_MEM_VMAS); + } + dev->vmalist = NULL; + } + + /* Clear map area and mtrr information */ + if (dev->maplist) { + for (i = 0; i < dev->map_count; i++) { + map = dev->maplist[i]; + switch (map->type) { + case _DRM_REGISTERS: + case _DRM_FRAME_BUFFER: +#ifdef CONFIG_MTRR + if (map->mtrr >= 0) { + int retcode; + retcode = mtrr_del(map->mtrr, + map->offset, + map->size); + DRM_DEBUG("mtrr_del = %d\n", retcode); + } +#endif + drm_ioremapfree(map->handle, map->size, dev); + break; + case _DRM_SHM: + drm_free_pages((unsigned long)map->handle, + drm_order(map->size) + - PAGE_SHIFT, + DRM_MEM_SAREA); + break; + case _DRM_AGP: + /* Do nothing here, because this is all + handled in the AGP/GART driver. */ + break; + } + drm_free(map, sizeof(*map), DRM_MEM_MAPS); + } + drm_free(dev->maplist, + dev->map_count * sizeof(*dev->maplist), + DRM_MEM_MAPS); + dev->maplist = NULL; + dev->map_count = 0; + } + + if (dev->queuelist) { + for (i = 0; i < dev->queue_count; i++) { + drm_waitlist_destroy(&dev->queuelist[i]->waitlist); + if (dev->queuelist[i]) { + drm_free(dev->queuelist[i], + sizeof(*dev->queuelist[0]), + DRM_MEM_QUEUES); + dev->queuelist[i] = NULL; + } + } + drm_free(dev->queuelist, + dev->queue_slots * sizeof(*dev->queuelist), + DRM_MEM_QUEUES); + dev->queuelist = NULL; + } + + drm_dma_takedown(dev); + + dev->queue_count = 0; + if (dev->lock.hw_lock) { + dev->lock.hw_lock = NULL; /* SHM removed */ + dev->lock.pid = 0; + wake_up_interruptible(&dev->lock.lock_queue); + } + up(&dev->struct_sem); + + return 0; +} + +int gamma_found(void) +{ + return devices; +} + +int gamma_find_devices(void) +{ + struct pci_dev *d = NULL, *one = NULL, *two = NULL; + + d = pci_find_device(PCI_VENDOR_ID_3DLABS,PCI_DEVICE_ID_3DLABS_GAMMA,d); + if (!d) return 0; + + one = pci_find_device(PCI_VENDOR_ID_3DLABS,PCI_DEVICE_ID_3DLABS_MX,d); + if (!one) return 0; + + /* Make sure it's on the same card, if not - no MX's found */ + if (PCI_SLOT(d->devfn) != PCI_SLOT(one->devfn)) return 0; + + two = pci_find_device(PCI_VENDOR_ID_3DLABS,PCI_DEVICE_ID_3DLABS_MX,one); + if (!two) return 1; + + /* Make sure it's on the same card, if not - only 1 MX found */ + if (PCI_SLOT(d->devfn) != PCI_SLOT(two->devfn)) return 1; + + /* Two MX's found - we don't currently support more than 2 */ + return 2; +} + +/* gamma_init is called via init_module at module load time, or via + * linux/init/main.c (this is not currently supported). */ + +static int __init gamma_init(void) +{ + int retcode; + drm_device_t *dev = &gamma_device; + + DRM_DEBUG("\n"); + + memset((void *)dev, 0, sizeof(*dev)); + dev->count_lock = SPIN_LOCK_UNLOCKED; + sema_init(&dev->struct_sem, 1); + +#ifdef MODULE + drm_parse_options(gamma); +#endif + devices = gamma_find_devices(); + if (devices == 0) return -1; + + if ((retcode = misc_register(&gamma_misc))) { + DRM_ERROR("Cannot register \"%s\"\n", GAMMA_NAME); + return retcode; + } + dev->device = MKDEV(MISC_MAJOR, gamma_misc.minor); + dev->name = GAMMA_NAME; + + drm_mem_init(); + drm_proc_init(dev); + + DRM_INFO("Initialized %s %d.%d.%d %s on minor %d with %d MX devices\n", + GAMMA_NAME, + GAMMA_MAJOR, + GAMMA_MINOR, + GAMMA_PATCHLEVEL, + GAMMA_DATE, + gamma_misc.minor, + devices); + + return 0; +} + +/* gamma_cleanup is called via cleanup_module at module unload time. */ + +static void __exit gamma_cleanup(void) +{ + drm_device_t *dev = &gamma_device; + + DRM_DEBUG("\n"); + + drm_proc_cleanup(); + if (misc_deregister(&gamma_misc)) { + DRM_ERROR("Cannot unload module\n"); + } else { + DRM_INFO("Module unloaded\n"); + } + gamma_takedown(dev); +} + +module_init(gamma_init); +module_exit(gamma_cleanup); + + +int gamma_version(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_version_t version; + int len; + + if (copy_from_user(&version, + (drm_version_t *)arg, + sizeof(version))) + return -EFAULT; + +#define DRM_COPY(name,value) \ + len = strlen(value); \ + if (len > name##_len) len = name##_len; \ + name##_len = strlen(value); \ + if (len && name) { \ + if (copy_to_user(name, value, len)) \ + return -EFAULT; \ + } + + version.version_major = GAMMA_MAJOR; + version.version_minor = GAMMA_MINOR; + version.version_patchlevel = GAMMA_PATCHLEVEL; + + DRM_COPY(version.name, GAMMA_NAME); + DRM_COPY(version.date, GAMMA_DATE); + DRM_COPY(version.desc, GAMMA_DESC); + + if (copy_to_user((drm_version_t *)arg, + &version, + sizeof(version))) + return -EFAULT; + return 0; +} + +int gamma_open(struct inode *inode, struct file *filp) +{ + drm_device_t *dev = &gamma_device; + int retcode = 0; + + DRM_DEBUG("open_count = %d\n", dev->open_count); + if (!(retcode = drm_open_helper(inode, filp, dev))) { +#if LINUX_VERSION_CODE < 0x020333 + MOD_INC_USE_COUNT; /* Needed before Linux 2.3.51 */ +#endif + atomic_inc(&dev->total_open); + spin_lock(&dev->count_lock); + if (!dev->open_count++) { + spin_unlock(&dev->count_lock); + return gamma_setup(dev); + } + spin_unlock(&dev->count_lock); + } + return retcode; +} + +int gamma_release(struct inode *inode, struct file *filp) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev; + int retcode = 0; + + lock_kernel(); + dev = priv->dev; + + DRM_DEBUG("open_count = %d\n", dev->open_count); + if (!(retcode = drm_release(inode, filp))) { +#if LINUX_VERSION_CODE < 0x020333 + MOD_DEC_USE_COUNT; /* Needed before Linux 2.3.51 */ +#endif + atomic_inc(&dev->total_close); + spin_lock(&dev->count_lock); + if (!--dev->open_count) { + if (atomic_read(&dev->ioctl_count) || dev->blocked) { + DRM_ERROR("Device busy: %d %d\n", + atomic_read(&dev->ioctl_count), + dev->blocked); + spin_unlock(&dev->count_lock); + unlock_kernel(); + return -EBUSY; + } + spin_unlock(&dev->count_lock); + unlock_kernel(); + return gamma_takedown(dev); + } + spin_unlock(&dev->count_lock); + } + unlock_kernel(); + return retcode; +} + +/* drm_ioctl is called whenever a process performs an ioctl on /dev/drm. */ + +int gamma_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + int nr = DRM_IOCTL_NR(cmd); + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + int retcode = 0; + drm_ioctl_desc_t *ioctl; + drm_ioctl_t *func; + + atomic_inc(&dev->ioctl_count); + atomic_inc(&dev->total_ioctl); + ++priv->ioctl_count; + + DRM_DEBUG("pid = %d, cmd = 0x%02x, nr = 0x%02x, dev 0x%x, auth = %d\n", + current->pid, cmd, nr, dev->device, priv->authenticated); + + if (nr >= GAMMA_IOCTL_COUNT) { + retcode = -EINVAL; + } else { + ioctl = &gamma_ioctls[nr]; + func = ioctl->func; + + if (!func) { + DRM_DEBUG("no function\n"); + retcode = -EINVAL; + } else if ((ioctl->root_only && !capable(CAP_SYS_ADMIN)) + || (ioctl->auth_needed && !priv->authenticated)) { + retcode = -EACCES; + } else { + retcode = (func)(inode, filp, cmd, arg); + } + } + + atomic_dec(&dev->ioctl_count); + return retcode; +} + + +int gamma_unlock(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_lock_t lock; + + if (copy_from_user(&lock, (drm_lock_t *)arg, sizeof(lock))) + return -EFAULT; + + if (lock.context == DRM_KERNEL_CONTEXT) { + DRM_ERROR("Process %d using kernel context %d\n", + current->pid, lock.context); + return -EINVAL; + } + + DRM_DEBUG("%d frees lock (%d holds)\n", + lock.context, + _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock)); + atomic_inc(&dev->total_unlocks); + if (_DRM_LOCK_IS_CONT(dev->lock.hw_lock->lock)) + atomic_inc(&dev->total_contends); + drm_lock_transfer(dev, &dev->lock.hw_lock->lock, DRM_KERNEL_CONTEXT); + gamma_dma_schedule(dev, 1); + if (!dev->context_flag) { + if (drm_lock_free(dev, &dev->lock.hw_lock->lock, + DRM_KERNEL_CONTEXT)) { + DRM_ERROR("\n"); + } + } +#if DRM_DMA_HISTOGRAM + atomic_inc(&dev->histo.lhld[drm_histogram_slot(get_cycles() + - dev->lck_start)]); +#endif + + unblock_all_signals(); + return 0; +} diff -urN linux-2.4.10/drivers/char/drm-4.0/gamma_drv.h linux-2.4.10-lia/drivers/char/drm-4.0/gamma_drv.h --- linux-2.4.10/drivers/char/drm-4.0/gamma_drv.h Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/gamma_drv.h Wed Aug 15 20:52:11 2001 @@ -0,0 +1,58 @@ +/* gamma_drv.h -- Private header for 3dlabs GMX 2000 driver -*- linux-c -*- + * Created: Mon Jan 4 10:05:05 1999 by faith@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rickard E. (Rik) Faith + * + */ + +#ifndef _GAMMA_DRV_H_ +#define _GAMMA_DRV_H_ + + /* gamma_drv.c */ +extern int gamma_version(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int gamma_open(struct inode *inode, struct file *filp); +extern int gamma_release(struct inode *inode, struct file *filp); +extern int gamma_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int gamma_lock(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int gamma_unlock(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); + + /* gamma_dma.c */ +extern int gamma_dma_schedule(drm_device_t *dev, int locked); +extern int gamma_dma(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int gamma_irq_install(drm_device_t *dev, int irq); +extern int gamma_irq_uninstall(drm_device_t *dev); +extern int gamma_control(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int gamma_find_devices(void); +extern int gamma_found(void); + +#endif diff -urN linux-2.4.10/drivers/char/drm-4.0/i810_bufs.c linux-2.4.10-lia/drivers/char/drm-4.0/i810_bufs.c --- linux-2.4.10/drivers/char/drm-4.0/i810_bufs.c Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/i810_bufs.c Wed Aug 15 20:52:11 2001 @@ -0,0 +1,339 @@ +/* i810_bufs.c -- IOCTLs to manage buffers -*- linux-c -*- + * Created: Thu Jan 6 01:47:26 2000 by jhartmann@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: Rickard E. (Rik) Faith + * Jeff Hartmann + * + */ + +#define __NO_VERSION__ +#include "drmP.h" +#include "i810_drv.h" +#include "linux/un.h" + +int i810_addbufs_agp(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_device_dma_t *dma = dev->dma; + drm_buf_desc_t request; + drm_buf_entry_t *entry; + drm_buf_t *buf; + unsigned long offset; + unsigned long agp_offset; + int count; + int order; + int size; + int alignment; + int page_order; + int total; + int byte_count; + int i; + + if (!dma) return -EINVAL; + + if (copy_from_user(&request, + (drm_buf_desc_t *)arg, + sizeof(request))) + return -EFAULT; + + count = request.count; + order = drm_order(request.size); + size = 1 << order; + agp_offset = request.agp_start; + alignment = (request.flags & _DRM_PAGE_ALIGN) ? PAGE_ALIGN(size) :size; + page_order = order - PAGE_SHIFT > 0 ? order - PAGE_SHIFT : 0; + total = PAGE_SIZE << page_order; + byte_count = 0; + + if (order < DRM_MIN_ORDER || order > DRM_MAX_ORDER) return -EINVAL; + if (dev->queue_count) return -EBUSY; /* Not while in use */ + spin_lock(&dev->count_lock); + if (dev->buf_use) { + spin_unlock(&dev->count_lock); + return -EBUSY; + } + atomic_inc(&dev->buf_alloc); + spin_unlock(&dev->count_lock); + + down(&dev->struct_sem); + entry = &dma->bufs[order]; + if (entry->buf_count) { + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); + return -ENOMEM; /* May only call once for each order */ + } + + if(count < 0 || count > 4096) + { + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); + return -EINVAL; + } + + entry->buflist = drm_alloc(count * sizeof(*entry->buflist), + DRM_MEM_BUFS); + if (!entry->buflist) { + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); + return -ENOMEM; + } + memset(entry->buflist, 0, count * sizeof(*entry->buflist)); + + entry->buf_size = size; + entry->page_order = page_order; + offset = 0; + + while(entry->buf_count < count) { + buf = &entry->buflist[entry->buf_count]; + buf->idx = dma->buf_count + entry->buf_count; + buf->total = alignment; + buf->order = order; + buf->used = 0; + buf->offset = offset; + buf->bus_address = dev->agp->base + agp_offset + offset; + buf->address = (void *)(agp_offset + offset + dev->agp->base); + buf->next = NULL; + buf->waiting = 0; + buf->pending = 0; + init_waitqueue_head(&buf->dma_wait); + buf->pid = 0; + + buf->dev_private = drm_alloc(sizeof(drm_i810_buf_priv_t), + DRM_MEM_BUFS); + buf->dev_priv_size = sizeof(drm_i810_buf_priv_t); + memset(buf->dev_private, 0, sizeof(drm_i810_buf_priv_t)); + +#if DRM_DMA_HISTOGRAM + buf->time_queued = 0; + buf->time_dispatched = 0; + buf->time_completed = 0; + buf->time_freed = 0; +#endif + offset = offset + alignment; + entry->buf_count++; + byte_count += PAGE_SIZE << page_order; + + DRM_DEBUG("buffer %d @ %p\n", + entry->buf_count, buf->address); + } + + dma->buflist = drm_realloc(dma->buflist, + dma->buf_count * sizeof(*dma->buflist), + (dma->buf_count + entry->buf_count) + * sizeof(*dma->buflist), + DRM_MEM_BUFS); + for (i = dma->buf_count; i < dma->buf_count + entry->buf_count; i++) + dma->buflist[i] = &entry->buflist[i - dma->buf_count]; + + dma->buf_count += entry->buf_count; + dma->byte_count += byte_count; + drm_freelist_create(&entry->freelist, entry->buf_count); + for (i = 0; i < entry->buf_count; i++) { + drm_freelist_put(dev, &entry->freelist, &entry->buflist[i]); + } + + up(&dev->struct_sem); + + request.count = entry->buf_count; + request.size = size; + + if (copy_to_user((drm_buf_desc_t *)arg, + &request, + sizeof(request))) + return -EFAULT; + + atomic_dec(&dev->buf_alloc); + dma->flags = _DRM_DMA_USE_AGP; + return 0; +} + +int i810_addbufs(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_buf_desc_t request; + + if (copy_from_user(&request, + (drm_buf_desc_t *)arg, + sizeof(request))) + return -EFAULT; + + if(request.flags & _DRM_AGP_BUFFER) + return i810_addbufs_agp(inode, filp, cmd, arg); + else + return -EINVAL; +} + +int i810_infobufs(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_device_dma_t *dma = dev->dma; + drm_buf_info_t request; + int i; + int count; + + if (!dma) return -EINVAL; + + spin_lock(&dev->count_lock); + if (atomic_read(&dev->buf_alloc)) { + spin_unlock(&dev->count_lock); + return -EBUSY; + } + ++dev->buf_use; /* Can't allocate more after this call */ + spin_unlock(&dev->count_lock); + + if (copy_from_user(&request, + (drm_buf_info_t *)arg, + sizeof(request))) + return -EFAULT; + + for (i = 0, count = 0; i < DRM_MAX_ORDER+1; i++) { + if (dma->bufs[i].buf_count) ++count; + } + + DRM_DEBUG("count = %d\n", count); + + if (request.count >= count) { + for (i = 0, count = 0; i < DRM_MAX_ORDER+1; i++) { + if (dma->bufs[i].buf_count) { + if (copy_to_user(&request.list[count].count, + &dma->bufs[i].buf_count, + sizeof(dma->bufs[0] + .buf_count)) || + copy_to_user(&request.list[count].size, + &dma->bufs[i].buf_size, + sizeof(dma->bufs[0].buf_size)) || + copy_to_user(&request.list[count].low_mark, + &dma->bufs[i] + .freelist.low_mark, + sizeof(dma->bufs[0] + .freelist.low_mark)) || + copy_to_user(&request.list[count] + .high_mark, + &dma->bufs[i] + .freelist.high_mark, + sizeof(dma->bufs[0] + .freelist.high_mark))) + return -EFAULT; + + DRM_DEBUG("%d %d %d %d %d\n", + i, + dma->bufs[i].buf_count, + dma->bufs[i].buf_size, + dma->bufs[i].freelist.low_mark, + dma->bufs[i].freelist.high_mark); + ++count; + } + } + } + request.count = count; + + if (copy_to_user((drm_buf_info_t *)arg, + &request, + sizeof(request))) + return -EFAULT; + + return 0; +} + +int i810_markbufs(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_device_dma_t *dma = dev->dma; + drm_buf_desc_t request; + int order; + drm_buf_entry_t *entry; + + if (!dma) return -EINVAL; + + if (copy_from_user(&request, + (drm_buf_desc_t *)arg, + sizeof(request))) + return -EFAULT; + + DRM_DEBUG("%d, %d, %d\n", + request.size, request.low_mark, request.high_mark); + order = drm_order(request.size); + if (order < DRM_MIN_ORDER || order > DRM_MAX_ORDER) return -EINVAL; + entry = &dma->bufs[order]; + + if (request.low_mark < 0 || request.low_mark > entry->buf_count) + return -EINVAL; + if (request.high_mark < 0 || request.high_mark > entry->buf_count) + return -EINVAL; + + entry->freelist.low_mark = request.low_mark; + entry->freelist.high_mark = request.high_mark; + + return 0; +} + +int i810_freebufs(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_device_dma_t *dma = dev->dma; + drm_buf_free_t request; + int i; + int idx; + drm_buf_t *buf; + + if (!dma) return -EINVAL; + + if (copy_from_user(&request, + (drm_buf_free_t *)arg, + sizeof(request))) + return -EFAULT; + + DRM_DEBUG("%d\n", request.count); + for (i = 0; i < request.count; i++) { + if (copy_from_user(&idx, + &request.list[i], + sizeof(idx))) + return -EFAULT; + if (idx < 0 || idx >= dma->buf_count) { + DRM_ERROR("Index %d (of %d max)\n", + idx, dma->buf_count - 1); + return -EINVAL; + } + buf = dma->buflist[idx]; + if (buf->pid != current->pid) { + DRM_ERROR("Process %d freeing buffer owned by %d\n", + current->pid, buf->pid); + return -EINVAL; + } + drm_free_buffer(dev, buf); + } + + return 0; +} + diff -urN linux-2.4.10/drivers/char/drm-4.0/i810_context.c linux-2.4.10-lia/drivers/char/drm-4.0/i810_context.c --- linux-2.4.10/drivers/char/drm-4.0/i810_context.c Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/i810_context.c Wed Aug 15 20:52:11 2001 @@ -0,0 +1,212 @@ +/* i810_context.c -- IOCTLs for i810 contexts -*- linux-c -*- + * Created: Mon Dec 13 09:51:35 1999 by faith@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: Rickard E. (Rik) Faith + * Jeff Hartmann + * + */ + +#define __NO_VERSION__ +#include "drmP.h" +#include "i810_drv.h" + +static int i810_alloc_queue(drm_device_t *dev) +{ + int temp = drm_ctxbitmap_next(dev); + DRM_DEBUG("i810_alloc_queue: %d\n", temp); + return temp; +} + +int i810_context_switch(drm_device_t *dev, int old, int new) +{ + char buf[64]; + + atomic_inc(&dev->total_ctx); + + if (test_and_set_bit(0, &dev->context_flag)) { + DRM_ERROR("Reentering -- FIXME\n"); + return -EBUSY; + } + +#if DRM_DMA_HISTOGRAM + dev->ctx_start = get_cycles(); +#endif + + DRM_DEBUG("Context switch from %d to %d\n", old, new); + + if (new == dev->last_context) { + clear_bit(0, &dev->context_flag); + return 0; + } + + if (drm_flags & DRM_FLAG_NOCTX) { + i810_context_switch_complete(dev, new); + } else { + sprintf(buf, "C %d %d\n", old, new); + drm_write_string(dev, buf); + } + + return 0; +} + +int i810_context_switch_complete(drm_device_t *dev, int new) +{ + dev->last_context = new; /* PRE/POST: This is the _only_ writer. */ + dev->last_switch = jiffies; + + if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { + DRM_ERROR("Lock isn't held after context switch\n"); + } + + /* If a context switch is ever initiated + when the kernel holds the lock, release + that lock here. */ +#if DRM_DMA_HISTOGRAM + atomic_inc(&dev->histo.ctx[drm_histogram_slot(get_cycles() + - dev->ctx_start)]); + +#endif + clear_bit(0, &dev->context_flag); + wake_up(&dev->context_wait); + + return 0; +} + +int i810_resctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_ctx_res_t res; + drm_ctx_t ctx; + int i; + + DRM_DEBUG("%d\n", DRM_RESERVED_CONTEXTS); + if (copy_from_user(&res, (drm_ctx_res_t *)arg, sizeof(res))) + return -EFAULT; + if (res.count >= DRM_RESERVED_CONTEXTS) { + memset(&ctx, 0, sizeof(ctx)); + for (i = 0; i < DRM_RESERVED_CONTEXTS; i++) { + ctx.handle = i; + if (copy_to_user(&res.contexts[i], + &i, + sizeof(i))) + return -EFAULT; + } + } + res.count = DRM_RESERVED_CONTEXTS; + if (copy_to_user((drm_ctx_res_t *)arg, &res, sizeof(res))) + return -EFAULT; + return 0; +} + +int i810_addctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ctx_t ctx; + + if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx))) + return -EFAULT; + if ((ctx.handle = i810_alloc_queue(dev)) == DRM_KERNEL_CONTEXT) { + /* Skip kernel's context and get a new one. */ + ctx.handle = i810_alloc_queue(dev); + } + if (ctx.handle == -1) { + DRM_DEBUG("Not enough free contexts.\n"); + /* Should this return -EBUSY instead? */ + return -ENOMEM; + } + DRM_DEBUG("%d\n", ctx.handle); + if (copy_to_user((drm_ctx_t *)arg, &ctx, sizeof(ctx))) + return -EFAULT; + return 0; +} + +int i810_modctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + /* This does nothing for the i810 */ + return 0; +} + +int i810_getctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_ctx_t ctx; + + if (copy_from_user(&ctx, (drm_ctx_t*)arg, sizeof(ctx))) + return -EFAULT; + /* This is 0, because we don't hanlde any context flags */ + ctx.flags = 0; + if (copy_to_user((drm_ctx_t*)arg, &ctx, sizeof(ctx))) + return -EFAULT; + return 0; +} + +int i810_switchctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ctx_t ctx; + + if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx))) + return -EFAULT; + DRM_DEBUG("%d\n", ctx.handle); + return i810_context_switch(dev, dev->last_context, ctx.handle); +} + +int i810_newctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ctx_t ctx; + + if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx))) + return -EFAULT; + DRM_DEBUG("%d\n", ctx.handle); + i810_context_switch_complete(dev, ctx.handle); + + return 0; +} + +int i810_rmctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ctx_t ctx; + + if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx))) + return -EFAULT; + DRM_DEBUG("%d\n", ctx.handle); + if(ctx.handle != DRM_KERNEL_CONTEXT) { + drm_ctxbitmap_free(dev, ctx.handle); + } + + return 0; +} diff -urN linux-2.4.10/drivers/char/drm-4.0/i810_dma.c linux-2.4.10-lia/drivers/char/drm-4.0/i810_dma.c --- linux-2.4.10/drivers/char/drm-4.0/i810_dma.c Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/i810_dma.c Mon Aug 20 18:09:34 2001 @@ -0,0 +1,1438 @@ +/* i810_dma.c -- DMA support for the i810 -*- linux-c -*- + * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: Rickard E. (Rik) Faith + * Jeff Hartmann + * Keith Whitwell + * + */ + +#define __NO_VERSION__ +#include "drmP.h" +#include "i810_drv.h" +#include /* For task queue support */ + +/* in case we don't have a 2.3.99-pre6 kernel or later: */ +#ifndef VM_DONTCOPY +#define VM_DONTCOPY 0 +#endif + +#define I810_BUF_FREE 2 +#define I810_BUF_CLIENT 1 +#define I810_BUF_HARDWARE 0 + +#define I810_BUF_UNMAPPED 0 +#define I810_BUF_MAPPED 1 + +#define I810_REG(reg) 2 +#define I810_BASE(reg) ((unsigned long) \ + dev->maplist[I810_REG(reg)]->handle) +#define I810_ADDR(reg) (I810_BASE(reg) + reg) +#define I810_DEREF(reg) *(__volatile__ int *)I810_ADDR(reg) +#define I810_READ(reg) I810_DEREF(reg) +#define I810_WRITE(reg,val) do { I810_DEREF(reg) = val; } while (0) +#define I810_DEREF16(reg) *(__volatile__ u16 *)I810_ADDR(reg) +#define I810_READ16(reg) I810_DEREF16(reg) +#define I810_WRITE16(reg,val) do { I810_DEREF16(reg) = val; } while (0) + +#define RING_LOCALS unsigned int outring, ringmask; volatile char *virt; + +#define BEGIN_LP_RING(n) do { \ + if (I810_VERBOSE) \ + DRM_DEBUG("BEGIN_LP_RING(%d) in %s\n", \ + n, __FUNCTION__); \ + if (dev_priv->ring.space < n*4) \ + i810_wait_ring(dev, n*4); \ + dev_priv->ring.space -= n*4; \ + outring = dev_priv->ring.tail; \ + ringmask = dev_priv->ring.tail_mask; \ + virt = dev_priv->ring.virtual_start; \ +} while (0) + +#define ADVANCE_LP_RING() do { \ + if (I810_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING\n"); \ + dev_priv->ring.tail = outring; \ + I810_WRITE(LP_RING + RING_TAIL, outring); \ +} while(0) + +#define OUT_RING(n) do { \ + if (I810_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \ + *(volatile unsigned int *)(virt + outring) = n; \ + outring += 4; \ + outring &= ringmask; \ +} while (0); + +static inline void i810_print_status_page(drm_device_t *dev) +{ + drm_device_dma_t *dma = dev->dma; + drm_i810_private_t *dev_priv = dev->dev_private; + u32 *temp = (u32 *)dev_priv->hw_status_page; + int i; + + DRM_DEBUG( "hw_status: Interrupt Status : %x\n", temp[0]); + DRM_DEBUG( "hw_status: LpRing Head ptr : %x\n", temp[1]); + DRM_DEBUG( "hw_status: IRing Head ptr : %x\n", temp[2]); + DRM_DEBUG( "hw_status: Reserved : %x\n", temp[3]); + DRM_DEBUG( "hw_status: Driver Counter : %d\n", temp[5]); + for(i = 6; i < dma->buf_count + 6; i++) { + DRM_DEBUG( "buffer status idx : %d used: %d\n", i - 6, temp[i]); + } +} + +static drm_buf_t *i810_freelist_get(drm_device_t *dev) +{ + drm_device_dma_t *dma = dev->dma; + int i; + int used; + + /* Linear search might not be the best solution */ + + for (i = 0; i < dma->buf_count; i++) { + drm_buf_t *buf = dma->buflist[ i ]; + drm_i810_buf_priv_t *buf_priv = buf->dev_private; + /* In use is already a pointer */ + used = cmpxchg(buf_priv->in_use, I810_BUF_FREE, + I810_BUF_CLIENT); + if(used == I810_BUF_FREE) { + return buf; + } + } + return NULL; +} + +/* This should only be called if the buffer is not sent to the hardware + * yet, the hardware updates in use for us once its on the ring buffer. + */ + +static int i810_freelist_put(drm_device_t *dev, drm_buf_t *buf) +{ + drm_i810_buf_priv_t *buf_priv = buf->dev_private; + int used; + + /* In use is already a pointer */ + used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, I810_BUF_FREE); + if(used != I810_BUF_CLIENT) { + DRM_ERROR("Freeing buffer thats not in use : %d\n", buf->idx); + return -EINVAL; + } + + return 0; +} + +static struct file_operations i810_buffer_fops = { + open: i810_open, + flush: drm_flush, + release: i810_release, + ioctl: i810_ioctl, + mmap: i810_mmap_buffers, + read: drm_read, + fasync: drm_fasync, + poll: drm_poll, +}; + +int i810_mmap_buffers(struct file *filp, struct vm_area_struct *vma) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev; + drm_i810_private_t *dev_priv; + drm_buf_t *buf; + drm_i810_buf_priv_t *buf_priv; + + lock_kernel(); + dev = priv->dev; + dev_priv = dev->dev_private; + buf = dev_priv->mmap_buffer; + buf_priv = buf->dev_private; + + vma->vm_flags |= (VM_IO | VM_DONTCOPY); + vma->vm_file = filp; + + buf_priv->currently_mapped = I810_BUF_MAPPED; + unlock_kernel(); + + if (remap_page_range(vma->vm_start, + VM_OFFSET(vma), + vma->vm_end - vma->vm_start, + vma->vm_page_prot)) return -EAGAIN; + return 0; +} + +static int i810_map_buffer(drm_buf_t *buf, struct file *filp) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_i810_buf_priv_t *buf_priv = buf->dev_private; + drm_i810_private_t *dev_priv = dev->dev_private; + struct file_operations *old_fops; + int retcode = 0; + + if(buf_priv->currently_mapped == I810_BUF_MAPPED) return -EINVAL; + + if(VM_DONTCOPY != 0) { + down_write(¤t->mm->mmap_sem); + old_fops = filp->f_op; + filp->f_op = &i810_buffer_fops; + dev_priv->mmap_buffer = buf; + buf_priv->virtual = (void *)do_mmap(filp, 0, buf->total, + PROT_READ|PROT_WRITE, + MAP_SHARED, + buf->bus_address); + dev_priv->mmap_buffer = NULL; + filp->f_op = old_fops; + if ((unsigned long)buf_priv->virtual > -1024UL) { + /* Real error */ + DRM_DEBUG("mmap error\n"); + retcode = (signed int)buf_priv->virtual; + buf_priv->virtual = 0; + } + up_write(¤t->mm->mmap_sem); + } else { + buf_priv->virtual = buf_priv->kernel_virtual; + buf_priv->currently_mapped = I810_BUF_MAPPED; + } + return retcode; +} + +static int i810_unmap_buffer(drm_buf_t *buf) +{ + drm_i810_buf_priv_t *buf_priv = buf->dev_private; + int retcode = 0; + + if(VM_DONTCOPY != 0) { + if(buf_priv->currently_mapped != I810_BUF_MAPPED) + return -EINVAL; + down_write(¤t->mm->mmap_sem); +#if LINUX_VERSION_CODE < 0x020399 + retcode = do_munmap((unsigned long)buf_priv->virtual, + (size_t) buf->total); +#else + retcode = do_munmap(current->mm, + (unsigned long)buf_priv->virtual, + (size_t) buf->total); +#endif + up_write(¤t->mm->mmap_sem); + } + buf_priv->currently_mapped = I810_BUF_UNMAPPED; + buf_priv->virtual = 0; + + return retcode; +} + +static int i810_dma_get_buffer(drm_device_t *dev, drm_i810_dma_t *d, + struct file *filp) +{ + drm_file_t *priv = filp->private_data; + drm_buf_t *buf; + drm_i810_buf_priv_t *buf_priv; + int retcode = 0; + + buf = i810_freelist_get(dev); + if (!buf) { + retcode = -ENOMEM; + DRM_DEBUG("retcode=%d\n", retcode); + return retcode; + } + + retcode = i810_map_buffer(buf, filp); + if(retcode) { + i810_freelist_put(dev, buf); + DRM_DEBUG("mapbuf failed, retcode %d\n", retcode); + return retcode; + } + buf->pid = priv->pid; + buf_priv = buf->dev_private; + d->granted = 1; + d->request_idx = buf->idx; + d->request_size = buf->total; + d->virtual = buf_priv->virtual; + + return retcode; +} + +static unsigned long i810_alloc_page(drm_device_t *dev) +{ + unsigned long address; + + address = __get_free_page(GFP_KERNEL); + if(address == 0UL) + return 0; + + atomic_inc(&virt_to_page(address)->count); + set_bit(PG_locked, &virt_to_page(address)->flags); + + return address; +} + +static void i810_free_page(drm_device_t *dev, unsigned long page) +{ + if(page == 0UL) + return; + + atomic_dec(&virt_to_page(page)->count); + clear_bit(PG_locked, &virt_to_page(page)->flags); + wake_up(&virt_to_page(page)->wait); + free_page(page); + return; +} + +static int i810_dma_cleanup(drm_device_t *dev) +{ + drm_device_dma_t *dma = dev->dma; + + if(dev->dev_private) { + int i; + drm_i810_private_t *dev_priv = + (drm_i810_private_t *) dev->dev_private; + + if(dev_priv->ring.virtual_start) { + drm_ioremapfree((void *) dev_priv->ring.virtual_start, + dev_priv->ring.Size, dev); + } + if(dev_priv->hw_status_page != 0UL) { + i810_free_page(dev, dev_priv->hw_status_page); + /* Need to rewrite hardware status page */ + I810_WRITE(0x02080, 0x1ffff000); + } + drm_free(dev->dev_private, sizeof(drm_i810_private_t), + DRM_MEM_DRIVER); + dev->dev_private = NULL; + + for (i = 0; i < dma->buf_count; i++) { + drm_buf_t *buf = dma->buflist[ i ]; + drm_i810_buf_priv_t *buf_priv = buf->dev_private; + drm_ioremapfree(buf_priv->kernel_virtual, + buf->total, dev); + } + } + return 0; +} + +static int i810_wait_ring(drm_device_t *dev, int n) +{ + drm_i810_private_t *dev_priv = dev->dev_private; + drm_i810_ring_buffer_t *ring = &(dev_priv->ring); + int iters = 0; + unsigned long end; + unsigned int last_head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR; + + end = jiffies + (HZ*3); + while (ring->space < n) { + int i; + + ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR; + ring->space = ring->head - (ring->tail+8); + if (ring->space < 0) ring->space += ring->Size; + + if (ring->head != last_head) + end = jiffies + (HZ*3); + + iters++; + if((signed)(end - jiffies) <= 0) { + DRM_ERROR("space: %d wanted %d\n", ring->space, n); + DRM_ERROR("lockup\n"); + goto out_wait_ring; + } + + for (i = 0 ; i < 2000 ; i++) ; + } + +out_wait_ring: + return iters; +} + +static void i810_kernel_lost_context(drm_device_t *dev) +{ + drm_i810_private_t *dev_priv = dev->dev_private; + drm_i810_ring_buffer_t *ring = &(dev_priv->ring); + + ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR; + ring->tail = I810_READ(LP_RING + RING_TAIL); + ring->space = ring->head - (ring->tail+8); + if (ring->space < 0) ring->space += ring->Size; +} + +static int i810_freelist_init(drm_device_t *dev) +{ + drm_device_dma_t *dma = dev->dma; + drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; + int my_idx = 24; + u32 *hw_status = (u32 *)(dev_priv->hw_status_page + my_idx); + int i; + + if(dma->buf_count > 1019) { + /* Not enough space in the status page for the freelist */ + return -EINVAL; + } + + for (i = 0; i < dma->buf_count; i++) { + drm_buf_t *buf = dma->buflist[ i ]; + drm_i810_buf_priv_t *buf_priv = buf->dev_private; + + buf_priv->in_use = hw_status++; + buf_priv->my_use_idx = my_idx; + my_idx += 4; + + *buf_priv->in_use = I810_BUF_FREE; + + buf_priv->kernel_virtual = drm_ioremap(buf->bus_address, + buf->total, dev); + } + return 0; +} + +static int i810_dma_initialize(drm_device_t *dev, + drm_i810_private_t *dev_priv, + drm_i810_init_t *init) +{ + drm_map_t *sarea_map; + + dev->dev_private = (void *) dev_priv; + memset(dev_priv, 0, sizeof(drm_i810_private_t)); + + if (init->ring_map_idx >= dev->map_count || + init->buffer_map_idx >= dev->map_count) { + i810_dma_cleanup(dev); + DRM_ERROR("ring_map or buffer_map are invalid\n"); + return -EINVAL; + } + + dev_priv->ring_map_idx = init->ring_map_idx; + dev_priv->buffer_map_idx = init->buffer_map_idx; + sarea_map = dev->maplist[0]; + dev_priv->sarea_priv = (drm_i810_sarea_t *) + ((u8 *)sarea_map->handle + + init->sarea_priv_offset); + + atomic_set(&dev_priv->flush_done, 0); + init_waitqueue_head(&dev_priv->flush_queue); + + dev_priv->ring.Start = init->ring_start; + dev_priv->ring.End = init->ring_end; + dev_priv->ring.Size = init->ring_size; + + dev_priv->ring.virtual_start = drm_ioremap(dev->agp->base + + init->ring_start, + init->ring_size, dev); + + dev_priv->ring.tail_mask = dev_priv->ring.Size - 1; + + if (dev_priv->ring.virtual_start == NULL) { + i810_dma_cleanup(dev); + DRM_ERROR("can not ioremap virtual address for" + " ring buffer\n"); + return -ENOMEM; + } + + dev_priv->w = init->w; + dev_priv->h = init->h; + dev_priv->pitch = init->pitch; + dev_priv->back_offset = init->back_offset; + dev_priv->depth_offset = init->depth_offset; + + dev_priv->front_di1 = init->front_offset | init->pitch_bits; + dev_priv->back_di1 = init->back_offset | init->pitch_bits; + dev_priv->zi1 = init->depth_offset | init->pitch_bits; + + + /* Program Hardware Status Page */ + dev_priv->hw_status_page = i810_alloc_page(dev); + memset((void *) dev_priv->hw_status_page, 0, PAGE_SIZE); + if(dev_priv->hw_status_page == 0UL) { + i810_dma_cleanup(dev); + DRM_ERROR("Can not allocate hardware status page\n"); + return -ENOMEM; + } + DRM_DEBUG("hw status page @ %lx\n", dev_priv->hw_status_page); + + I810_WRITE(0x02080, virt_to_bus((void *)dev_priv->hw_status_page)); + DRM_DEBUG("Enabled hardware status page\n"); + + /* Now we need to init our freelist */ + if(i810_freelist_init(dev) != 0) { + i810_dma_cleanup(dev); + DRM_ERROR("Not enough space in the status page for" + " the freelist\n"); + return -ENOMEM; + } + return 0; +} + +int i810_dma_init(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_i810_private_t *dev_priv; + drm_i810_init_t init; + int retcode = 0; + + if (copy_from_user(&init, (drm_i810_init_t *)arg, sizeof(init))) + return -EFAULT; + + switch(init.func) { + case I810_INIT_DMA: + dev_priv = drm_alloc(sizeof(drm_i810_private_t), + DRM_MEM_DRIVER); + if(dev_priv == NULL) return -ENOMEM; + retcode = i810_dma_initialize(dev, dev_priv, &init); + break; + case I810_CLEANUP_DMA: + retcode = i810_dma_cleanup(dev); + break; + default: + retcode = -EINVAL; + break; + } + + return retcode; +} + + + +/* Most efficient way to verify state for the i810 is as it is + * emitted. Non-conformant state is silently dropped. + * + * Use 'volatile' & local var tmp to force the emitted values to be + * identical to the verified ones. + */ +static void i810EmitContextVerified( drm_device_t *dev, + volatile unsigned int *code ) +{ + drm_i810_private_t *dev_priv = dev->dev_private; + int i, j = 0; + unsigned int tmp; + RING_LOCALS; + + BEGIN_LP_RING( I810_CTX_SETUP_SIZE ); + + OUT_RING( GFX_OP_COLOR_FACTOR ); + OUT_RING( code[I810_CTXREG_CF1] ); + + OUT_RING( GFX_OP_STIPPLE ); + OUT_RING( code[I810_CTXREG_ST1] ); + + for ( i = 4 ; i < I810_CTX_SETUP_SIZE ; i++ ) { + tmp = code[i]; + + if ((tmp & (7<<29)) == (3<<29) && + (tmp & (0x1f<<24)) < (0x1d<<24)) + { + OUT_RING( tmp ); + j++; + } + } + + if (j & 1) + OUT_RING( 0 ); + + ADVANCE_LP_RING(); +} + +static void i810EmitTexVerified( drm_device_t *dev, + volatile unsigned int *code ) +{ + drm_i810_private_t *dev_priv = dev->dev_private; + int i, j = 0; + unsigned int tmp; + RING_LOCALS; + + BEGIN_LP_RING( I810_TEX_SETUP_SIZE ); + + OUT_RING( GFX_OP_MAP_INFO ); + OUT_RING( code[I810_TEXREG_MI1] ); + OUT_RING( code[I810_TEXREG_MI2] ); + OUT_RING( code[I810_TEXREG_MI3] ); + + for ( i = 4 ; i < I810_TEX_SETUP_SIZE ; i++ ) { + tmp = code[i]; + + if ((tmp & (7<<29)) == (3<<29) && + (tmp & (0x1f<<24)) < (0x1d<<24)) + { + OUT_RING( tmp ); + j++; + } + } + + if (j & 1) + OUT_RING( 0 ); + + ADVANCE_LP_RING(); +} + + +/* Need to do some additional checking when setting the dest buffer. + */ +static void i810EmitDestVerified( drm_device_t *dev, + volatile unsigned int *code ) +{ + drm_i810_private_t *dev_priv = dev->dev_private; + unsigned int tmp; + RING_LOCALS; + + BEGIN_LP_RING( I810_DEST_SETUP_SIZE + 2 ); + + tmp = code[I810_DESTREG_DI1]; + if (tmp == dev_priv->front_di1 || tmp == dev_priv->back_di1) { + OUT_RING( CMD_OP_DESTBUFFER_INFO ); + OUT_RING( tmp ); + } else + DRM_DEBUG("bad di1 %x (allow %x or %x)\n", + tmp, dev_priv->front_di1, dev_priv->back_di1); + + /* invarient: + */ + OUT_RING( CMD_OP_Z_BUFFER_INFO ); + OUT_RING( dev_priv->zi1 ); + + OUT_RING( GFX_OP_DESTBUFFER_VARS ); + OUT_RING( code[I810_DESTREG_DV1] ); + + OUT_RING( GFX_OP_DRAWRECT_INFO ); + OUT_RING( code[I810_DESTREG_DR1] ); + OUT_RING( code[I810_DESTREG_DR2] ); + OUT_RING( code[I810_DESTREG_DR3] ); + OUT_RING( code[I810_DESTREG_DR4] ); + OUT_RING( 0 ); + + ADVANCE_LP_RING(); +} + + + +static void i810EmitState( drm_device_t *dev ) +{ + drm_i810_private_t *dev_priv = dev->dev_private; + drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; + unsigned int dirty = sarea_priv->dirty; + + if (dirty & I810_UPLOAD_BUFFERS) { + i810EmitDestVerified( dev, sarea_priv->BufferState ); + sarea_priv->dirty &= ~I810_UPLOAD_BUFFERS; + } + + if (dirty & I810_UPLOAD_CTX) { + i810EmitContextVerified( dev, sarea_priv->ContextState ); + sarea_priv->dirty &= ~I810_UPLOAD_CTX; + } + + if (dirty & I810_UPLOAD_TEX0) { + i810EmitTexVerified( dev, sarea_priv->TexState[0] ); + sarea_priv->dirty &= ~I810_UPLOAD_TEX0; + } + + if (dirty & I810_UPLOAD_TEX1) { + i810EmitTexVerified( dev, sarea_priv->TexState[1] ); + sarea_priv->dirty &= ~I810_UPLOAD_TEX1; + } +} + + + +/* need to verify + */ +static void i810_dma_dispatch_clear( drm_device_t *dev, int flags, + unsigned int clear_color, + unsigned int clear_zval ) +{ + drm_i810_private_t *dev_priv = dev->dev_private; + drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; + int nbox = sarea_priv->nbox; + drm_clip_rect_t *pbox = sarea_priv->boxes; + int pitch = dev_priv->pitch; + int cpp = 2; + int i; + RING_LOCALS; + + i810_kernel_lost_context(dev); + + if (nbox > I810_NR_SAREA_CLIPRECTS) + nbox = I810_NR_SAREA_CLIPRECTS; + + for (i = 0 ; i < nbox ; i++, pbox++) { + unsigned int x = pbox->x1; + unsigned int y = pbox->y1; + unsigned int width = (pbox->x2 - x) * cpp; + unsigned int height = pbox->y2 - y; + unsigned int start = y * pitch + x * cpp; + + if (pbox->x1 > pbox->x2 || + pbox->y1 > pbox->y2 || + pbox->x2 > dev_priv->w || + pbox->y2 > dev_priv->h) + continue; + + if ( flags & I810_FRONT ) { + DRM_DEBUG("clear front\n"); + BEGIN_LP_RING( 6 ); + OUT_RING( BR00_BITBLT_CLIENT | + BR00_OP_COLOR_BLT | 0x3 ); + OUT_RING( BR13_SOLID_PATTERN | (0xF0 << 16) | pitch ); + OUT_RING( (height << 16) | width ); + OUT_RING( start ); + OUT_RING( clear_color ); + OUT_RING( 0 ); + ADVANCE_LP_RING(); + } + + if ( flags & I810_BACK ) { + DRM_DEBUG("clear back\n"); + BEGIN_LP_RING( 6 ); + OUT_RING( BR00_BITBLT_CLIENT | + BR00_OP_COLOR_BLT | 0x3 ); + OUT_RING( BR13_SOLID_PATTERN | (0xF0 << 16) | pitch ); + OUT_RING( (height << 16) | width ); + OUT_RING( dev_priv->back_offset + start ); + OUT_RING( clear_color ); + OUT_RING( 0 ); + ADVANCE_LP_RING(); + } + + if ( flags & I810_DEPTH ) { + DRM_DEBUG("clear depth\n"); + BEGIN_LP_RING( 6 ); + OUT_RING( BR00_BITBLT_CLIENT | + BR00_OP_COLOR_BLT | 0x3 ); + OUT_RING( BR13_SOLID_PATTERN | (0xF0 << 16) | pitch ); + OUT_RING( (height << 16) | width ); + OUT_RING( dev_priv->depth_offset + start ); + OUT_RING( clear_zval ); + OUT_RING( 0 ); + ADVANCE_LP_RING(); + } + } +} + +static void i810_dma_dispatch_swap( drm_device_t *dev ) +{ + drm_i810_private_t *dev_priv = dev->dev_private; + drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; + int nbox = sarea_priv->nbox; + drm_clip_rect_t *pbox = sarea_priv->boxes; + int pitch = dev_priv->pitch; + int cpp = 2; + int ofs = dev_priv->back_offset; + int i; + RING_LOCALS; + + DRM_DEBUG("swapbuffers\n"); + + i810_kernel_lost_context(dev); + + if (nbox > I810_NR_SAREA_CLIPRECTS) + nbox = I810_NR_SAREA_CLIPRECTS; + + for (i = 0 ; i < nbox; i++, pbox++) + { + unsigned int w = pbox->x2 - pbox->x1; + unsigned int h = pbox->y2 - pbox->y1; + unsigned int dst = pbox->x1*cpp + pbox->y1*pitch; + unsigned int start = ofs + dst; + + if (pbox->x1 > pbox->x2 || + pbox->y1 > pbox->y2 || + pbox->x2 > dev_priv->w || + pbox->y2 > dev_priv->h) + continue; + + DRM_DEBUG("dispatch swap %d,%d-%d,%d!\n", + pbox[i].x1, pbox[i].y1, + pbox[i].x2, pbox[i].y2); + + BEGIN_LP_RING( 6 ); + OUT_RING( BR00_BITBLT_CLIENT | BR00_OP_SRC_COPY_BLT | 0x4 ); + OUT_RING( pitch | (0xCC << 16)); + OUT_RING( (h << 16) | (w * cpp)); + OUT_RING( dst ); + OUT_RING( pitch ); + OUT_RING( start ); + ADVANCE_LP_RING(); + } +} + + +static void i810_dma_dispatch_vertex(drm_device_t *dev, + drm_buf_t *buf, + int discard, + int used) +{ + drm_i810_private_t *dev_priv = dev->dev_private; + drm_i810_buf_priv_t *buf_priv = buf->dev_private; + drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_clip_rect_t *box = sarea_priv->boxes; + int nbox = sarea_priv->nbox; + unsigned long address = (unsigned long)buf->bus_address; + unsigned long start = address - dev->agp->base; + int i = 0, u; + RING_LOCALS; + + i810_kernel_lost_context(dev); + + if (nbox > I810_NR_SAREA_CLIPRECTS) + nbox = I810_NR_SAREA_CLIPRECTS; + + if (discard) { + u = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, + I810_BUF_HARDWARE); + if(u != I810_BUF_CLIENT) { + DRM_DEBUG("xxxx 2\n"); + } + } + + if (used > 4*1024) + used = 0; + + if (sarea_priv->dirty) + i810EmitState( dev ); + + DRM_DEBUG("dispatch vertex addr 0x%lx, used 0x%x nbox %d\n", + address, used, nbox); + + dev_priv->counter++; + DRM_DEBUG( "dispatch counter : %ld\n", dev_priv->counter); + DRM_DEBUG( "i810_dma_dispatch\n"); + DRM_DEBUG( "start : %lx\n", start); + DRM_DEBUG( "used : %d\n", used); + DRM_DEBUG( "start + used - 4 : %ld\n", start + used - 4); + + if (buf_priv->currently_mapped == I810_BUF_MAPPED) { + *(u32 *)buf_priv->virtual = (GFX_OP_PRIMITIVE | + sarea_priv->vertex_prim | + ((used/4)-2)); + + if (used & 4) { + *(u32 *)((u32)buf_priv->virtual + used) = 0; + used += 4; + } + + i810_unmap_buffer(buf); + } + + if (used) { + do { + if (i < nbox) { + BEGIN_LP_RING(4); + OUT_RING( GFX_OP_SCISSOR | SC_UPDATE_SCISSOR | + SC_ENABLE ); + OUT_RING( GFX_OP_SCISSOR_INFO ); + OUT_RING( box[i].x1 | (box[i].y1<<16) ); + OUT_RING( (box[i].x2-1) | ((box[i].y2-1)<<16) ); + ADVANCE_LP_RING(); + } + + BEGIN_LP_RING(4); + OUT_RING( CMD_OP_BATCH_BUFFER ); + OUT_RING( start | BB1_PROTECTED ); + OUT_RING( start + used - 4 ); + OUT_RING( 0 ); + ADVANCE_LP_RING(); + + } while (++i < nbox); + } + + BEGIN_LP_RING(10); + OUT_RING( CMD_STORE_DWORD_IDX ); + OUT_RING( 20 ); + OUT_RING( dev_priv->counter ); + OUT_RING( 0 ); + + if (discard) { + OUT_RING( CMD_STORE_DWORD_IDX ); + OUT_RING( buf_priv->my_use_idx ); + OUT_RING( I810_BUF_FREE ); + OUT_RING( 0 ); + } + + OUT_RING( CMD_REPORT_HEAD ); + OUT_RING( 0 ); + ADVANCE_LP_RING(); +} + + +/* Interrupts are only for flushing */ +static void i810_dma_service(int irq, void *device, struct pt_regs *regs) +{ + drm_device_t *dev = (drm_device_t *)device; + u16 temp; + + atomic_inc(&dev->total_irq); + temp = I810_READ16(I810REG_INT_IDENTITY_R); + temp = temp & ~(0x6000); + if(temp != 0) I810_WRITE16(I810REG_INT_IDENTITY_R, + temp); /* Clear all interrupts */ + else + return; + + queue_task(&dev->tq, &tq_immediate); + mark_bh(IMMEDIATE_BH); +} + +static void i810_dma_task_queue(void *device) +{ + drm_device_t *dev = (drm_device_t *) device; + drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; + + atomic_set(&dev_priv->flush_done, 1); + wake_up_interruptible(&dev_priv->flush_queue); +} + +int i810_irq_install(drm_device_t *dev, int irq) +{ + int retcode; + u16 temp; + + if (!irq) return -EINVAL; + + down(&dev->struct_sem); + if (dev->irq) { + up(&dev->struct_sem); + return -EBUSY; + } + dev->irq = irq; + up(&dev->struct_sem); + + DRM_DEBUG( "Interrupt Install : %d\n", irq); + DRM_DEBUG("%d\n", irq); + + dev->context_flag = 0; + dev->interrupt_flag = 0; + dev->dma_flag = 0; + + dev->dma->next_buffer = NULL; + dev->dma->next_queue = NULL; + dev->dma->this_buffer = NULL; + + INIT_LIST_HEAD(&dev->tq.list); + dev->tq.sync = 0; + dev->tq.routine = i810_dma_task_queue; + dev->tq.data = dev; + + /* Before installing handler */ + temp = I810_READ16(I810REG_HWSTAM); + temp = temp & 0x6000; + I810_WRITE16(I810REG_HWSTAM, temp); + + temp = I810_READ16(I810REG_INT_MASK_R); + temp = temp & 0x6000; + I810_WRITE16(I810REG_INT_MASK_R, temp); /* Unmask interrupts */ + temp = I810_READ16(I810REG_INT_ENABLE_R); + temp = temp & 0x6000; + I810_WRITE16(I810REG_INT_ENABLE_R, temp); /* Disable all interrupts */ + + /* Install handler */ + if ((retcode = request_irq(dev->irq, + i810_dma_service, + SA_SHIRQ, + dev->devname, + dev))) { + down(&dev->struct_sem); + dev->irq = 0; + up(&dev->struct_sem); + return retcode; + } + temp = I810_READ16(I810REG_INT_ENABLE_R); + temp = temp & 0x6000; + temp = temp | 0x0003; + I810_WRITE16(I810REG_INT_ENABLE_R, + temp); /* Enable bp & user interrupts */ + return 0; +} + +int i810_irq_uninstall(drm_device_t *dev) +{ + int irq; + u16 temp; + + +/* return 0; */ + + down(&dev->struct_sem); + irq = dev->irq; + dev->irq = 0; + up(&dev->struct_sem); + + if (!irq) return -EINVAL; + + DRM_DEBUG( "Interrupt UnInstall: %d\n", irq); + DRM_DEBUG("%d\n", irq); + + temp = I810_READ16(I810REG_INT_IDENTITY_R); + temp = temp & ~(0x6000); + if(temp != 0) I810_WRITE16(I810REG_INT_IDENTITY_R, + temp); /* Clear all interrupts */ + + temp = I810_READ16(I810REG_INT_ENABLE_R); + temp = temp & 0x6000; + I810_WRITE16(I810REG_INT_ENABLE_R, + temp); /* Disable all interrupts */ + + free_irq(irq, dev); + + return 0; +} + +int i810_control(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_control_t ctl; + int retcode; + + DRM_DEBUG( "i810_control\n"); + + if (copy_from_user(&ctl, (drm_control_t *)arg, sizeof(ctl))) + return -EFAULT; + + switch (ctl.func) { + case DRM_INST_HANDLER: + if ((retcode = i810_irq_install(dev, ctl.irq))) + return retcode; + break; + case DRM_UNINST_HANDLER: + if ((retcode = i810_irq_uninstall(dev))) + return retcode; + break; + default: + return -EINVAL; + } + return 0; +} + +static inline void i810_dma_emit_flush(drm_device_t *dev) +{ + drm_i810_private_t *dev_priv = dev->dev_private; + RING_LOCALS; + + i810_kernel_lost_context(dev); + + BEGIN_LP_RING(2); + OUT_RING( CMD_REPORT_HEAD ); + OUT_RING( GFX_OP_USER_INTERRUPT ); + ADVANCE_LP_RING(); + +/* i810_wait_ring( dev, dev_priv->ring.Size - 8 ); */ +/* atomic_set(&dev_priv->flush_done, 1); */ +/* wake_up_interruptible(&dev_priv->flush_queue); */ +} + +static inline void i810_dma_quiescent_emit(drm_device_t *dev) +{ + drm_i810_private_t *dev_priv = dev->dev_private; + RING_LOCALS; + + i810_kernel_lost_context(dev); + + BEGIN_LP_RING(4); + OUT_RING( INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE ); + OUT_RING( CMD_REPORT_HEAD ); + OUT_RING( 0 ); + OUT_RING( GFX_OP_USER_INTERRUPT ); + ADVANCE_LP_RING(); + +/* i810_wait_ring( dev, dev_priv->ring.Size - 8 ); */ +/* atomic_set(&dev_priv->flush_done, 1); */ +/* wake_up_interruptible(&dev_priv->flush_queue); */ +} + +static void i810_dma_quiescent(drm_device_t *dev) +{ + DECLARE_WAITQUEUE(entry, current); + drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; + unsigned long end; + + if(dev_priv == NULL) { + return; + } + atomic_set(&dev_priv->flush_done, 0); + add_wait_queue(&dev_priv->flush_queue, &entry); + end = jiffies + (HZ*3); + + for (;;) { + current->state = TASK_INTERRUPTIBLE; + i810_dma_quiescent_emit(dev); + if (atomic_read(&dev_priv->flush_done) == 1) break; + if((signed)(end - jiffies) <= 0) { + DRM_ERROR("lockup\n"); + break; + } + schedule_timeout(HZ*3); + if (signal_pending(current)) { + break; + } + } + + current->state = TASK_RUNNING; + remove_wait_queue(&dev_priv->flush_queue, &entry); + + return; +} + +static int i810_flush_queue(drm_device_t *dev) +{ + DECLARE_WAITQUEUE(entry, current); + drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; + drm_device_dma_t *dma = dev->dma; + unsigned long end; + int i, ret = 0; + + if(dev_priv == NULL) { + return 0; + } + atomic_set(&dev_priv->flush_done, 0); + add_wait_queue(&dev_priv->flush_queue, &entry); + end = jiffies + (HZ*3); + for (;;) { + current->state = TASK_INTERRUPTIBLE; + i810_dma_emit_flush(dev); + if (atomic_read(&dev_priv->flush_done) == 1) break; + if((signed)(end - jiffies) <= 0) { + DRM_ERROR("lockup\n"); + break; + } + schedule_timeout(HZ*3); + if (signal_pending(current)) { + ret = -EINTR; /* Can't restart */ + break; + } + } + + current->state = TASK_RUNNING; + remove_wait_queue(&dev_priv->flush_queue, &entry); + + + for (i = 0; i < dma->buf_count; i++) { + drm_buf_t *buf = dma->buflist[ i ]; + drm_i810_buf_priv_t *buf_priv = buf->dev_private; + + int used = cmpxchg(buf_priv->in_use, I810_BUF_HARDWARE, + I810_BUF_FREE); + + if (used == I810_BUF_HARDWARE) + DRM_DEBUG("reclaimed from HARDWARE\n"); + if (used == I810_BUF_CLIENT) + DRM_DEBUG("still on client HARDWARE\n"); + } + + return ret; +} + +/* Must be called with the lock held */ +void i810_reclaim_buffers(drm_device_t *dev, pid_t pid) +{ + drm_device_dma_t *dma = dev->dma; + int i; + + if (!dma) return; + if (!dev->dev_private) return; + if (!dma->buflist) return; + + i810_flush_queue(dev); + + for (i = 0; i < dma->buf_count; i++) { + drm_buf_t *buf = dma->buflist[ i ]; + drm_i810_buf_priv_t *buf_priv = buf->dev_private; + + if (buf->pid == pid && buf_priv) { + int used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, + I810_BUF_FREE); + + if (used == I810_BUF_CLIENT) + DRM_DEBUG("reclaimed from client\n"); + if(buf_priv->currently_mapped == I810_BUF_MAPPED) + buf_priv->currently_mapped = I810_BUF_UNMAPPED; + } + } +} + +int i810_lock(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + + DECLARE_WAITQUEUE(entry, current); + int ret = 0; + drm_lock_t lock; + + if (copy_from_user(&lock, (drm_lock_t *)arg, sizeof(lock))) + return -EFAULT; + + if (lock.context == DRM_KERNEL_CONTEXT) { + DRM_ERROR("Process %d using kernel context %d\n", + current->pid, lock.context); + return -EINVAL; + } + + DRM_DEBUG("%d (pid %d) requests lock (0x%08x), flags = 0x%08x\n", + lock.context, current->pid, dev->lock.hw_lock->lock, + lock.flags); + + if (lock.context < 0) { + return -EINVAL; + } + /* Only one queue: + */ + + if (!ret) { + add_wait_queue(&dev->lock.lock_queue, &entry); + for (;;) { + current->state = TASK_INTERRUPTIBLE; + if (!dev->lock.hw_lock) { + /* Device has been unregistered */ + ret = -EINTR; + break; + } + if (drm_lock_take(&dev->lock.hw_lock->lock, + lock.context)) { + dev->lock.pid = current->pid; + dev->lock.lock_time = jiffies; + atomic_inc(&dev->total_locks); + break; /* Got lock */ + } + + /* Contention */ + atomic_inc(&dev->total_sleeps); + DRM_DEBUG("Calling lock schedule\n"); + schedule(); + if (signal_pending(current)) { + ret = -ERESTARTSYS; + break; + } + } + current->state = TASK_RUNNING; + remove_wait_queue(&dev->lock.lock_queue, &entry); + } + + if (!ret) { + sigemptyset(&dev->sigmask); + sigaddset(&dev->sigmask, SIGSTOP); + sigaddset(&dev->sigmask, SIGTSTP); + sigaddset(&dev->sigmask, SIGTTIN); + sigaddset(&dev->sigmask, SIGTTOU); + dev->sigdata.context = lock.context; + dev->sigdata.lock = dev->lock.hw_lock; + block_all_signals(drm_notifier, &dev->sigdata, &dev->sigmask); + + if (lock.flags & _DRM_LOCK_QUIESCENT) { + DRM_DEBUG("_DRM_LOCK_QUIESCENT\n"); + DRM_DEBUG("fred\n"); + i810_dma_quiescent(dev); + } + } + DRM_DEBUG("%d %s\n", lock.context, ret ? "interrupted" : "has lock"); + return ret; +} + +int i810_flush_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + + DRM_DEBUG("i810_flush_ioctl\n"); + if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { + DRM_ERROR("i810_flush_ioctl called without lock held\n"); + return -EINVAL; + } + + i810_flush_queue(dev); + return 0; +} + + +int i810_dma_vertex(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_device_dma_t *dma = dev->dma; + drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; + u32 *hw_status = (u32 *)dev_priv->hw_status_page; + drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *) + dev_priv->sarea_priv; + drm_i810_vertex_t vertex; + + if (copy_from_user(&vertex, (drm_i810_vertex_t *)arg, sizeof(vertex))) + return -EFAULT; + + if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { + DRM_ERROR("i810_dma_vertex called without lock held\n"); + return -EINVAL; + } + + DRM_DEBUG("i810 dma vertex, idx %d used %d discard %d\n", + vertex.idx, vertex.used, vertex.discard); + + if(vertex.idx < 0 || vertex.idx > dma->buf_count) return -EINVAL; + + i810_dma_dispatch_vertex( dev, + dma->buflist[ vertex.idx ], + vertex.discard, vertex.used ); + + atomic_add(vertex.used, &dma->total_bytes); + atomic_inc(&dma->total_dmas); + sarea_priv->last_enqueue = dev_priv->counter-1; + sarea_priv->last_dispatch = (int) hw_status[5]; + + return 0; +} + + + +int i810_clear_bufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_i810_clear_t clear; + + if (copy_from_user(&clear, (drm_i810_clear_t *)arg, sizeof(clear))) + return -EFAULT; + + if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { + DRM_ERROR("i810_clear_bufs called without lock held\n"); + return -EINVAL; + } + + i810_dma_dispatch_clear( dev, clear.flags, + clear.clear_color, + clear.clear_depth ); + return 0; +} + +int i810_swap_bufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + + DRM_DEBUG("i810_swap_bufs\n"); + + if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { + DRM_ERROR("i810_swap_buf called without lock held\n"); + return -EINVAL; + } + + i810_dma_dispatch_swap( dev ); + return 0; +} + +int i810_getage(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; + u32 *hw_status = (u32 *)dev_priv->hw_status_page; + drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *) + dev_priv->sarea_priv; + + sarea_priv->last_dispatch = (int) hw_status[5]; + return 0; +} + +int i810_getbuf(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + int retcode = 0; + drm_i810_dma_t d; + drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; + u32 *hw_status = (u32 *)dev_priv->hw_status_page; + drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *) + dev_priv->sarea_priv; + + DRM_DEBUG("getbuf\n"); + if (copy_from_user(&d, (drm_i810_dma_t *)arg, sizeof(d))) + return -EFAULT; + + if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { + DRM_ERROR("i810_dma called without lock held\n"); + return -EINVAL; + } + + d.granted = 0; + + retcode = i810_dma_get_buffer(dev, &d, filp); + + DRM_DEBUG("i810_dma: %d returning %d, granted = %d\n", + current->pid, retcode, d.granted); + + if (copy_to_user((drm_dma_t *)arg, &d, sizeof(d))) + return -EFAULT; + sarea_priv->last_dispatch = (int) hw_status[5]; + + return retcode; +} + +int i810_copybuf(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_i810_copy_t d; + drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; + u32 *hw_status = (u32 *)dev_priv->hw_status_page; + drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *) + dev_priv->sarea_priv; + drm_buf_t *buf; + drm_i810_buf_priv_t *buf_priv; + drm_device_dma_t *dma = dev->dma; + + if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { + DRM_ERROR("i810_dma called without lock held\n"); + return -EINVAL; + } + + if (copy_from_user(&d, (drm_i810_copy_t *)arg, sizeof(d))) + return -EFAULT; + + if(d.idx < 0 || d.idx > dma->buf_count) return -EINVAL; + buf = dma->buflist[ d.idx ]; + buf_priv = buf->dev_private; + if (buf_priv->currently_mapped != I810_BUF_MAPPED) return -EPERM; + + /* Stopping end users copying their data to the entire kernel + is good.. */ + if (d.used < 0 || d.used > buf->total) + return -EINVAL; + + if (copy_from_user(buf_priv->virtual, d.address, d.used)) + return -EFAULT; + + sarea_priv->last_dispatch = (int) hw_status[5]; + + return 0; +} + +int i810_docopy(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + if(VM_DONTCOPY == 0) return 1; + return 0; +} diff -urN linux-2.4.10/drivers/char/drm-4.0/i810_drm.h linux-2.4.10-lia/drivers/char/drm-4.0/i810_drm.h --- linux-2.4.10/drivers/char/drm-4.0/i810_drm.h Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/i810_drm.h Wed Aug 15 20:52:11 2001 @@ -0,0 +1,194 @@ +#ifndef _I810_DRM_H_ +#define _I810_DRM_H_ + +/* WARNING: These defines must be the same as what the Xserver uses. + * if you change them, you must change the defines in the Xserver. + */ + +#ifndef _I810_DEFINES_ +#define _I810_DEFINES_ + +#define I810_DMA_BUF_ORDER 12 +#define I810_DMA_BUF_SZ (1< + * Jeff Hartmann + * + */ + +#include +#include "drmP.h" +#include "i810_drv.h" + +#define I810_NAME "i810" +#define I810_DESC "Intel I810" +#define I810_DATE "20000928" +#define I810_MAJOR 1 +#define I810_MINOR 1 +#define I810_PATCHLEVEL 0 + +static drm_device_t i810_device; +drm_ctx_t i810_res_ctx; + +static struct file_operations i810_fops = { +#if LINUX_VERSION_CODE >= 0x020400 + /* This started being used during 2.4.0-test */ + owner: THIS_MODULE, +#endif + open: i810_open, + flush: drm_flush, + release: i810_release, + ioctl: i810_ioctl, + mmap: drm_mmap, + read: drm_read, + fasync: drm_fasync, + poll: drm_poll, +}; + +static struct miscdevice i810_misc = { + minor: MISC_DYNAMIC_MINOR, + name: I810_NAME, + fops: &i810_fops, +}; + +static drm_ioctl_desc_t i810_ioctls[] = { + [DRM_IOCTL_NR(DRM_IOCTL_VERSION)] = { i810_version, 0, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_GET_UNIQUE)] = { drm_getunique, 0, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_GET_MAGIC)] = { drm_getmagic, 0, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_IRQ_BUSID)] = { drm_irq_busid, 0, 1 }, + + [DRM_IOCTL_NR(DRM_IOCTL_SET_UNIQUE)] = { drm_setunique, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_BLOCK)] = { drm_block, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_UNBLOCK)] = { drm_unblock, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_CONTROL)] = { i810_control, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_AUTH_MAGIC)] = { drm_authmagic, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_ADD_MAP)] = { drm_addmap, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_ADD_BUFS)] = { i810_addbufs, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_MARK_BUFS)] = { i810_markbufs, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_INFO_BUFS)] = { i810_infobufs, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_FREE_BUFS)] = { i810_freebufs, 1, 0 }, + + [DRM_IOCTL_NR(DRM_IOCTL_ADD_CTX)] = { i810_addctx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_RM_CTX)] = { i810_rmctx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_MOD_CTX)] = { i810_modctx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_GET_CTX)] = { i810_getctx, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_SWITCH_CTX)] = { i810_switchctx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_NEW_CTX)] = { i810_newctx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_RES_CTX)] = { i810_resctx, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_ADD_DRAW)] = { drm_adddraw, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_RM_DRAW)] = { drm_rmdraw, 1, 1 }, + + [DRM_IOCTL_NR(DRM_IOCTL_LOCK)] = { i810_lock, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_UNLOCK)] = { i810_unlock, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_FINISH)] = { drm_finish, 1, 0 }, + + [DRM_IOCTL_NR(DRM_IOCTL_AGP_ACQUIRE)] = { drm_agp_acquire, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_RELEASE)] = { drm_agp_release, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_ENABLE)] = { drm_agp_enable, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_INFO)] = { drm_agp_info, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_ALLOC)] = { drm_agp_alloc, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_FREE)] = { drm_agp_free, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_BIND)] = { drm_agp_bind, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_UNBIND)] = { drm_agp_unbind, 1, 1 }, + + [DRM_IOCTL_NR(DRM_IOCTL_I810_INIT)] = { i810_dma_init, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_I810_VERTEX)] = { i810_dma_vertex, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_I810_CLEAR)] = { i810_clear_bufs, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_I810_FLUSH)] = { i810_flush_ioctl,1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_I810_GETAGE)] = { i810_getage, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_I810_GETBUF)] = { i810_getbuf, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_I810_SWAP)] = { i810_swap_bufs, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_I810_COPY)] = { i810_copybuf, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_I810_DOCOPY)] = { i810_docopy, 1, 0 }, +}; + +#define I810_IOCTL_COUNT DRM_ARRAY_SIZE(i810_ioctls) + +#ifdef MODULE +static char *i810 = NULL; +#endif + +MODULE_AUTHOR("VA Linux Systems, Inc."); +MODULE_DESCRIPTION("Intel I810"); +MODULE_PARM(i810, "s"); + +#ifndef MODULE +/* i810_options is called by the kernel to parse command-line options + * passed via the boot-loader (e.g., LILO). It calls the insmod option + * routine, drm_parse_drm. + */ + +static int __init i810_options(char *str) +{ + drm_parse_options(str); + return 1; +} + +__setup("i810=", i810_options); +#endif + +static int i810_setup(drm_device_t *dev) +{ + int i; + + atomic_set(&dev->ioctl_count, 0); + atomic_set(&dev->vma_count, 0); + dev->buf_use = 0; + atomic_set(&dev->buf_alloc, 0); + + drm_dma_setup(dev); + + atomic_set(&dev->total_open, 0); + atomic_set(&dev->total_close, 0); + atomic_set(&dev->total_ioctl, 0); + atomic_set(&dev->total_irq, 0); + atomic_set(&dev->total_ctx, 0); + atomic_set(&dev->total_locks, 0); + atomic_set(&dev->total_unlocks, 0); + atomic_set(&dev->total_contends, 0); + atomic_set(&dev->total_sleeps, 0); + + for (i = 0; i < DRM_HASH_SIZE; i++) { + dev->magiclist[i].head = NULL; + dev->magiclist[i].tail = NULL; + } + dev->maplist = NULL; + dev->map_count = 0; + dev->vmalist = NULL; + dev->lock.hw_lock = NULL; + init_waitqueue_head(&dev->lock.lock_queue); + dev->queue_count = 0; + dev->queue_reserved = 0; + dev->queue_slots = 0; + dev->queuelist = NULL; + dev->irq = 0; + dev->context_flag = 0; + dev->interrupt_flag = 0; + dev->dma_flag = 0; + dev->last_context = 0; + dev->last_switch = 0; + dev->last_checked = 0; + init_timer(&dev->timer); + init_waitqueue_head(&dev->context_wait); +#if DRM_DMA_HISTO + memset(&dev->histo, 0, sizeof(dev->histo)); +#endif + dev->ctx_start = 0; + dev->lck_start = 0; + + dev->buf_rp = dev->buf; + dev->buf_wp = dev->buf; + dev->buf_end = dev->buf + DRM_BSZ; + dev->buf_async = NULL; + init_waitqueue_head(&dev->buf_readers); + init_waitqueue_head(&dev->buf_writers); + + DRM_DEBUG("\n"); + + /* The kernel's context could be created here, but is now created + in drm_dma_enqueue. This is more resource-efficient for + hardware that does not do DMA, but may mean that + drm_select_queue fails between the time the interrupt is + initialized and the time the queues are initialized. */ + + return 0; +} + + +static int i810_takedown(drm_device_t *dev) +{ + int i; + drm_magic_entry_t *pt, *next; + drm_map_t *map; + drm_vma_entry_t *vma, *vma_next; + + DRM_DEBUG("\n"); + + if (dev->irq) i810_irq_uninstall(dev); + + down(&dev->struct_sem); + del_timer(&dev->timer); + + if (dev->devname) { + drm_free(dev->devname, strlen(dev->devname)+1, DRM_MEM_DRIVER); + dev->devname = NULL; + } + + if (dev->unique) { + drm_free(dev->unique, strlen(dev->unique)+1, DRM_MEM_DRIVER); + dev->unique = NULL; + dev->unique_len = 0; + } + /* Clear pid list */ + for (i = 0; i < DRM_HASH_SIZE; i++) { + for (pt = dev->magiclist[i].head; pt; pt = next) { + next = pt->next; + drm_free(pt, sizeof(*pt), DRM_MEM_MAGIC); + } + dev->magiclist[i].head = dev->magiclist[i].tail = NULL; + } + /* Clear AGP information */ + if (dev->agp) { + drm_agp_mem_t *entry; + drm_agp_mem_t *nexte; + + /* Remove AGP resources, but leave dev->agp + intact until r128_cleanup is called. */ + for (entry = dev->agp->memory; entry; entry = nexte) { + nexte = entry->next; + if (entry->bound) drm_unbind_agp(entry->memory); + drm_free_agp(entry->memory, entry->pages); + drm_free(entry, sizeof(*entry), DRM_MEM_AGPLISTS); + } + dev->agp->memory = NULL; + + if (dev->agp->acquired) _drm_agp_release(); + + dev->agp->acquired = 0; + dev->agp->enabled = 0; + } + /* Clear vma list (only built for debugging) */ + if (dev->vmalist) { + for (vma = dev->vmalist; vma; vma = vma_next) { + vma_next = vma->next; + drm_free(vma, sizeof(*vma), DRM_MEM_VMAS); + } + dev->vmalist = NULL; + } + + /* Clear map area and mtrr information */ + if (dev->maplist) { + for (i = 0; i < dev->map_count; i++) { + map = dev->maplist[i]; + switch (map->type) { + case _DRM_REGISTERS: + case _DRM_FRAME_BUFFER: +#ifdef CONFIG_MTRR + if (map->mtrr >= 0) { + int retcode; + retcode = mtrr_del(map->mtrr, + map->offset, + map->size); + DRM_DEBUG("mtrr_del = %d\n", retcode); + } +#endif + drm_ioremapfree(map->handle, map->size, dev); + break; + case _DRM_SHM: + drm_free_pages((unsigned long)map->handle, + drm_order(map->size) + - PAGE_SHIFT, + DRM_MEM_SAREA); + break; + case _DRM_AGP: + break; + } + drm_free(map, sizeof(*map), DRM_MEM_MAPS); + } + drm_free(dev->maplist, + dev->map_count * sizeof(*dev->maplist), + DRM_MEM_MAPS); + dev->maplist = NULL; + dev->map_count = 0; + } + + if (dev->queuelist) { + for (i = 0; i < dev->queue_count; i++) { + drm_waitlist_destroy(&dev->queuelist[i]->waitlist); + if (dev->queuelist[i]) { + drm_free(dev->queuelist[i], + sizeof(*dev->queuelist[0]), + DRM_MEM_QUEUES); + dev->queuelist[i] = NULL; + } + } + drm_free(dev->queuelist, + dev->queue_slots * sizeof(*dev->queuelist), + DRM_MEM_QUEUES); + dev->queuelist = NULL; + } + + drm_dma_takedown(dev); + + dev->queue_count = 0; + if (dev->lock.hw_lock) { + dev->lock.hw_lock = NULL; /* SHM removed */ + dev->lock.pid = 0; + wake_up_interruptible(&dev->lock.lock_queue); + } + up(&dev->struct_sem); + + return 0; +} + +/* i810_init is called via init_module at module load time, or via + * linux/init/main.c (this is not currently supported). */ + +static int __init i810_init(void) +{ + int retcode; + drm_device_t *dev = &i810_device; + + DRM_DEBUG("\n"); + + memset((void *)dev, 0, sizeof(*dev)); + dev->count_lock = SPIN_LOCK_UNLOCKED; + sema_init(&dev->struct_sem, 1); + +#ifdef MODULE + drm_parse_options(i810); +#endif + DRM_DEBUG("doing misc_register\n"); + if ((retcode = misc_register(&i810_misc))) { + DRM_ERROR("Cannot register \"%s\"\n", I810_NAME); + return retcode; + } + dev->device = MKDEV(MISC_MAJOR, i810_misc.minor); + dev->name = I810_NAME; + + DRM_DEBUG("doing mem init\n"); + drm_mem_init(); + DRM_DEBUG("doing proc init\n"); + drm_proc_init(dev); + DRM_DEBUG("doing agp init\n"); + dev->agp = drm_agp_init(); + if(dev->agp == NULL) { + DRM_INFO("The i810 drm module requires the agpgart module" + " to function correctly\nPlease load the agpgart" + " module before you load the i810 module\n"); + drm_proc_cleanup(); + misc_deregister(&i810_misc); + i810_takedown(dev); + return -ENOMEM; + } + DRM_DEBUG("doing ctxbitmap init\n"); + if((retcode = drm_ctxbitmap_init(dev))) { + DRM_ERROR("Cannot allocate memory for context bitmap.\n"); + drm_proc_cleanup(); + misc_deregister(&i810_misc); + i810_takedown(dev); + return retcode; + } + + DRM_INFO("Initialized %s %d.%d.%d %s on minor %d\n", + I810_NAME, + I810_MAJOR, + I810_MINOR, + I810_PATCHLEVEL, + I810_DATE, + i810_misc.minor); + + return 0; +} + +/* i810_cleanup is called via cleanup_module at module unload time. */ + +static void __exit i810_cleanup(void) +{ + drm_device_t *dev = &i810_device; + + DRM_DEBUG("\n"); + + drm_proc_cleanup(); + if (misc_deregister(&i810_misc)) { + DRM_ERROR("Cannot unload module\n"); + } else { + DRM_INFO("Module unloaded\n"); + } + drm_ctxbitmap_cleanup(dev); + i810_takedown(dev); + if (dev->agp) { + drm_agp_uninit(); + drm_free(dev->agp, sizeof(*dev->agp), DRM_MEM_AGPLISTS); + dev->agp = NULL; + } +} + +module_init(i810_init); +module_exit(i810_cleanup); + + +int i810_version(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_version_t version; + int len; + + if (copy_from_user(&version, + (drm_version_t *)arg, + sizeof(version))) + return -EFAULT; + +#define DRM_COPY(name,value) \ + len = strlen(value); \ + if (len > name##_len) len = name##_len; \ + name##_len = strlen(value); \ + if (len && name) { \ + if (copy_to_user(name, value, len)) \ + return -EFAULT; \ + } + + version.version_major = I810_MAJOR; + version.version_minor = I810_MINOR; + version.version_patchlevel = I810_PATCHLEVEL; + + DRM_COPY(version.name, I810_NAME); + DRM_COPY(version.date, I810_DATE); + DRM_COPY(version.desc, I810_DESC); + + if (copy_to_user((drm_version_t *)arg, + &version, + sizeof(version))) + return -EFAULT; + return 0; +} + +int i810_open(struct inode *inode, struct file *filp) +{ + drm_device_t *dev = &i810_device; + int retcode = 0; + + DRM_DEBUG("open_count = %d\n", dev->open_count); + if (!(retcode = drm_open_helper(inode, filp, dev))) { +#if LINUX_VERSION_CODE < 0x020333 + MOD_INC_USE_COUNT; /* Needed before Linux 2.3.51 */ +#endif + atomic_inc(&dev->total_open); + spin_lock(&dev->count_lock); + if (!dev->open_count++) { + spin_unlock(&dev->count_lock); + return i810_setup(dev); + } + spin_unlock(&dev->count_lock); + } + return retcode; +} + +int i810_release(struct inode *inode, struct file *filp) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev; + int retcode = 0; + + lock_kernel(); + dev = priv->dev; + DRM_DEBUG("pid = %d, device = 0x%x, open_count = %d\n", + current->pid, dev->device, dev->open_count); + + if (dev->lock.hw_lock && _DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock) + && dev->lock.pid == current->pid) { + i810_reclaim_buffers(dev, priv->pid); + DRM_ERROR("Process %d dead, freeing lock for context %d\n", + current->pid, + _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock)); + drm_lock_free(dev, + &dev->lock.hw_lock->lock, + _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock)); + + /* FIXME: may require heavy-handed reset of + hardware at this point, possibly + processed via a callback to the X + server. */ + } else if (dev->lock.hw_lock) { + /* The lock is required to reclaim buffers */ + DECLARE_WAITQUEUE(entry, current); + add_wait_queue(&dev->lock.lock_queue, &entry); + for (;;) { + current->state = TASK_INTERRUPTIBLE; + if (!dev->lock.hw_lock) { + /* Device has been unregistered */ + retcode = -EINTR; + break; + } + if (drm_lock_take(&dev->lock.hw_lock->lock, + DRM_KERNEL_CONTEXT)) { + dev->lock.pid = priv->pid; + dev->lock.lock_time = jiffies; + atomic_inc(&dev->total_locks); + break; /* Got lock */ + } + /* Contention */ + atomic_inc(&dev->total_sleeps); + schedule(); + if (signal_pending(current)) { + retcode = -ERESTARTSYS; + break; + } + } + current->state = TASK_RUNNING; + remove_wait_queue(&dev->lock.lock_queue, &entry); + if(!retcode) { + i810_reclaim_buffers(dev, priv->pid); + drm_lock_free(dev, &dev->lock.hw_lock->lock, + DRM_KERNEL_CONTEXT); + } + } + drm_fasync(-1, filp, 0); + + down(&dev->struct_sem); + if (priv->prev) priv->prev->next = priv->next; + else dev->file_first = priv->next; + if (priv->next) priv->next->prev = priv->prev; + else dev->file_last = priv->prev; + up(&dev->struct_sem); + + drm_free(priv, sizeof(*priv), DRM_MEM_FILES); +#if LINUX_VERSION_CODE < 0x020333 + MOD_DEC_USE_COUNT; /* Needed before Linux 2.3.51 */ +#endif + atomic_inc(&dev->total_close); + spin_lock(&dev->count_lock); + if (!--dev->open_count) { + if (atomic_read(&dev->ioctl_count) || dev->blocked) { + DRM_ERROR("Device busy: %d %d\n", + atomic_read(&dev->ioctl_count), + dev->blocked); + spin_unlock(&dev->count_lock); + unlock_kernel(); + return -EBUSY; + } + spin_unlock(&dev->count_lock); + unlock_kernel(); + return i810_takedown(dev); + } + spin_unlock(&dev->count_lock); + unlock_kernel(); + return retcode; +} + +/* drm_ioctl is called whenever a process performs an ioctl on /dev/drm. */ + +int i810_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + int nr = DRM_IOCTL_NR(cmd); + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + int retcode = 0; + drm_ioctl_desc_t *ioctl; + drm_ioctl_t *func; + + atomic_inc(&dev->ioctl_count); + atomic_inc(&dev->total_ioctl); + ++priv->ioctl_count; + + DRM_DEBUG("pid = %d, cmd = 0x%02x, nr = 0x%02x, dev 0x%x, auth = %d\n", + current->pid, cmd, nr, dev->device, priv->authenticated); + + if (nr >= I810_IOCTL_COUNT) { + retcode = -EINVAL; + } else { + ioctl = &i810_ioctls[nr]; + func = ioctl->func; + + if (!func) { + DRM_DEBUG("no function\n"); + retcode = -EINVAL; + } else if ((ioctl->root_only && !capable(CAP_SYS_ADMIN)) + || (ioctl->auth_needed && !priv->authenticated)) { + retcode = -EACCES; + } else { + retcode = (func)(inode, filp, cmd, arg); + } + } + + atomic_dec(&dev->ioctl_count); + return retcode; +} + +int i810_unlock(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_lock_t lock; + + if (copy_from_user(&lock, (drm_lock_t *)arg, sizeof(lock))) + return -EFAULT; + + if (lock.context == DRM_KERNEL_CONTEXT) { + DRM_ERROR("Process %d using kernel context %d\n", + current->pid, lock.context); + return -EINVAL; + } + + DRM_DEBUG("%d frees lock (%d holds)\n", + lock.context, + _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock)); + atomic_inc(&dev->total_unlocks); + if (_DRM_LOCK_IS_CONT(dev->lock.hw_lock->lock)) + atomic_inc(&dev->total_contends); + drm_lock_transfer(dev, &dev->lock.hw_lock->lock, DRM_KERNEL_CONTEXT); + if (!dev->context_flag) { + if (drm_lock_free(dev, &dev->lock.hw_lock->lock, + DRM_KERNEL_CONTEXT)) { + DRM_ERROR("\n"); + } + } +#if DRM_DMA_HISTOGRAM + atomic_inc(&dev->histo.lhld[drm_histogram_slot(get_cycles() + - dev->lck_start)]); +#endif + + unblock_all_signals(); + return 0; +} diff -urN linux-2.4.10/drivers/char/drm-4.0/i810_drv.h linux-2.4.10-lia/drivers/char/drm-4.0/i810_drv.h --- linux-2.4.10/drivers/char/drm-4.0/i810_drv.h Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/i810_drv.h Wed Aug 15 20:52:11 2001 @@ -0,0 +1,225 @@ +/* i810_drv.h -- Private header for the Matrox g200/g400 driver -*- linux-c -*- + * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: Rickard E. (Rik) Faith + * Jeff Hartmann + * + */ + +#ifndef _I810_DRV_H_ +#define _I810_DRV_H_ + +typedef struct drm_i810_buf_priv { + u32 *in_use; + int my_use_idx; + int currently_mapped; + void *virtual; + void *kernel_virtual; + int map_count; + struct vm_area_struct *vma; +} drm_i810_buf_priv_t; + +typedef struct _drm_i810_ring_buffer{ + int tail_mask; + unsigned long Start; + unsigned long End; + unsigned long Size; + u8 *virtual_start; + int head; + int tail; + int space; +} drm_i810_ring_buffer_t; + +typedef struct drm_i810_private { + int ring_map_idx; + int buffer_map_idx; + + drm_i810_ring_buffer_t ring; + drm_i810_sarea_t *sarea_priv; + + unsigned long hw_status_page; + unsigned long counter; + + atomic_t flush_done; + wait_queue_head_t flush_queue; /* Processes waiting until flush */ + drm_buf_t *mmap_buffer; + + + u32 front_di1, back_di1, zi1; + + int back_offset; + int depth_offset; + int w, h; + int pitch; +} drm_i810_private_t; + + /* i810_drv.c */ +extern int i810_version(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int i810_open(struct inode *inode, struct file *filp); +extern int i810_release(struct inode *inode, struct file *filp); +extern int i810_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int i810_unlock(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); + + /* i810_dma.c */ +extern int i810_dma_schedule(drm_device_t *dev, int locked); +extern int i810_getbuf(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int i810_irq_install(drm_device_t *dev, int irq); +extern int i810_irq_uninstall(drm_device_t *dev); +extern int i810_control(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int i810_lock(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int i810_dma_init(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int i810_flush_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern void i810_reclaim_buffers(drm_device_t *dev, pid_t pid); +extern int i810_getage(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg); +extern int i810_mmap_buffers(struct file *filp, struct vm_area_struct *vma); +extern int i810_copybuf(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int i810_docopy(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); + + /* i810_bufs.c */ +extern int i810_addbufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int i810_infobufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int i810_markbufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int i810_freebufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int i810_addmap(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); + + /* i810_context.c */ +extern int i810_resctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int i810_addctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int i810_modctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int i810_getctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int i810_switchctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int i810_newctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int i810_rmctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); + +extern int i810_context_switch(drm_device_t *dev, int old, int new); +extern int i810_context_switch_complete(drm_device_t *dev, int new); + +#define I810_VERBOSE 0 + + +int i810_dma_vertex(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); + +int i810_swap_bufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); + +int i810_clear_bufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); + +#define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23)) +#define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23)) +#define CMD_REPORT_HEAD (7<<23) +#define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1) +#define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1) + +#define INST_PARSER_CLIENT 0x00000000 +#define INST_OP_FLUSH 0x02000000 +#define INST_FLUSH_MAP_CACHE 0x00000001 + + +#define BB1_START_ADDR_MASK (~0x7) +#define BB1_PROTECTED (1<<0) +#define BB1_UNPROTECTED (0<<0) +#define BB2_END_ADDR_MASK (~0x7) + +#define I810REG_HWSTAM 0x02098 +#define I810REG_INT_IDENTITY_R 0x020a4 +#define I810REG_INT_MASK_R 0x020a8 +#define I810REG_INT_ENABLE_R 0x020a0 + +#define LP_RING 0x2030 +#define HP_RING 0x2040 +#define RING_TAIL 0x00 +#define TAIL_ADDR 0x000FFFF8 +#define RING_HEAD 0x04 +#define HEAD_WRAP_COUNT 0xFFE00000 +#define HEAD_WRAP_ONE 0x00200000 +#define HEAD_ADDR 0x001FFFFC +#define RING_START 0x08 +#define START_ADDR 0x00FFFFF8 +#define RING_LEN 0x0C +#define RING_NR_PAGES 0x000FF000 +#define RING_REPORT_MASK 0x00000006 +#define RING_REPORT_64K 0x00000002 +#define RING_REPORT_128K 0x00000004 +#define RING_NO_REPORT 0x00000000 +#define RING_VALID_MASK 0x00000001 +#define RING_VALID 0x00000001 +#define RING_INVALID 0x00000000 + +#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) +#define SC_UPDATE_SCISSOR (0x1<<1) +#define SC_ENABLE_MASK (0x1<<0) +#define SC_ENABLE (0x1<<0) + +#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) +#define SCI_YMIN_MASK (0xffff<<16) +#define SCI_XMIN_MASK (0xffff<<0) +#define SCI_YMAX_MASK (0xffff<<16) +#define SCI_XMAX_MASK (0xffff<<0) + +#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) +#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) +#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x2) +#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) +#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) +#define GFX_OP_PRIMITIVE ((0x3<<29)|(0x1f<<24)) + +#define CMD_OP_Z_BUFFER_INFO ((0x0<<29)|(0x16<<23)) +#define CMD_OP_DESTBUFFER_INFO ((0x0<<29)|(0x15<<23)) + +#define BR00_BITBLT_CLIENT 0x40000000 +#define BR00_OP_COLOR_BLT 0x10000000 +#define BR00_OP_SRC_COPY_BLT 0x10C00000 +#define BR13_SOLID_PATTERN 0x80000000 + + + +#endif + diff -urN linux-2.4.10/drivers/char/drm-4.0/init.c linux-2.4.10-lia/drivers/char/drm-4.0/init.c --- linux-2.4.10/drivers/char/drm-4.0/init.c Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/init.c Wed Aug 15 20:52:11 2001 @@ -0,0 +1,113 @@ +/* init.c -- Setup/Cleanup for DRM -*- linux-c -*- + * Created: Mon Jan 4 08:58:31 1999 by faith@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rickard E. (Rik) Faith + * + */ + +#define __NO_VERSION__ +#include "drmP.h" + +int drm_flags = 0; + +/* drm_parse_option parses a single option. See description for + drm_parse_options for details. */ + +static void drm_parse_option(char *s) +{ + char *c, *r; + + DRM_DEBUG("\"%s\"\n", s); + if (!s || !*s) return; + for (c = s; *c && *c != ':'; c++); /* find : or \0 */ + if (*c) r = c + 1; else r = NULL; /* remember remainder */ + *c = '\0'; /* terminate */ + if (!strcmp(s, "noctx")) { + drm_flags |= DRM_FLAG_NOCTX; + DRM_INFO("Server-mediated context switching OFF\n"); + return; + } + if (!strcmp(s, "debug")) { + drm_flags |= DRM_FLAG_DEBUG; + DRM_INFO("Debug messages ON\n"); + return; + } + DRM_ERROR("\"%s\" is not a valid option\n", s); + return; +} + +/* drm_parse_options parse the insmod "drm=" options, or the command-line + * options passed to the kernel via LILO. The grammar of the format is as + * follows: + * + * drm ::= 'drm=' option_list + * option_list ::= option [ ';' option_list ] + * option ::= 'device:' major + * | 'debug' + * | 'noctx' + * major ::= INTEGER + * + * Note that 's' contains option_list without the 'drm=' part. + * + * device=major,minor specifies the device number used for /dev/drm + * if major == 0 then the misc device is used + * if major == 0 and minor == 0 then dynamic misc allocation is used + * debug=on specifies that debugging messages will be printk'd + * debug=trace specifies that each function call will be logged via printk + * debug=off turns off all debugging options + * + */ + +void drm_parse_options(char *s) +{ + char *h, *t, *n; + + DRM_DEBUG("\"%s\"\n", s ?: ""); + if (!s || !*s) return; + + for (h = t = n = s; h && *h; h = n) { + for (; *t && *t != ';'; t++); /* find ; or \0 */ + if (*t) n = t + 1; else n = NULL; /* remember next */ + *t = '\0'; /* terminate */ + drm_parse_option(h); /* parse */ + } +} + +/* drm_cpu_valid returns non-zero if the DRI will run on this CPU, and 0 + * otherwise. */ + +int drm_cpu_valid(void) +{ +#if defined(__i386__) + if (boot_cpu_data.x86 == 3) return 0; /* No cmpxchg on a 386 */ +#endif +#if defined(__sparc__) && !defined(__sparc_v9__) + if (1) + return 0; /* No cmpxchg before v9 sparc. */ +#endif + return 1; +} diff -urN linux-2.4.10/drivers/char/drm-4.0/ioctl.c linux-2.4.10-lia/drivers/char/drm-4.0/ioctl.c --- linux-2.4.10/drivers/char/drm-4.0/ioctl.c Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/ioctl.c Wed Aug 15 20:52:11 2001 @@ -0,0 +1,99 @@ +/* ioctl.c -- IOCTL processing for DRM -*- linux-c -*- + * Created: Fri Jan 8 09:01:26 1999 by faith@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rickard E. (Rik) Faith + * + */ + +#define __NO_VERSION__ +#include "drmP.h" + +int drm_irq_busid(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_irq_busid_t p; + struct pci_dev *dev; + + if (copy_from_user(&p, (drm_irq_busid_t *)arg, sizeof(p))) + return -EFAULT; + dev = pci_find_slot(p.busnum, PCI_DEVFN(p.devnum, p.funcnum)); + if (dev) p.irq = dev->irq; + else p.irq = 0; + DRM_DEBUG("%d:%d:%d => IRQ %d\n", + p.busnum, p.devnum, p.funcnum, p.irq); + if (copy_to_user((drm_irq_busid_t *)arg, &p, sizeof(p))) + return -EFAULT; + return 0; +} + +int drm_getunique(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_unique_t u; + + if (copy_from_user(&u, (drm_unique_t *)arg, sizeof(u))) + return -EFAULT; + if (u.unique_len >= dev->unique_len) { + if (copy_to_user(u.unique, dev->unique, dev->unique_len)) + return -EFAULT; + } + u.unique_len = dev->unique_len; + if (copy_to_user((drm_unique_t *)arg, &u, sizeof(u))) + return -EFAULT; + return 0; +} + +int drm_setunique(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_unique_t u; + + if (dev->unique_len || dev->unique) + return -EBUSY; + + if (copy_from_user(&u, (drm_unique_t *)arg, sizeof(u))) + return -EFAULT; + + if (!u.unique_len || u.unique_len > 1024) + return -EINVAL; + + dev->unique_len = u.unique_len; + dev->unique = drm_alloc(u.unique_len + 1, DRM_MEM_DRIVER); + if (copy_from_user(dev->unique, u.unique, dev->unique_len)) + return -EFAULT; + dev->unique[dev->unique_len] = '\0'; + + dev->devname = drm_alloc(strlen(dev->name) + strlen(dev->unique) + 2, + DRM_MEM_DRIVER); + sprintf(dev->devname, "%s@%s", dev->name, dev->unique); + + return 0; +} diff -urN linux-2.4.10/drivers/char/drm-4.0/lists.c linux-2.4.10-lia/drivers/char/drm-4.0/lists.c --- linux-2.4.10/drivers/char/drm-4.0/lists.c Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/lists.c Wed Aug 15 20:52:11 2001 @@ -0,0 +1,218 @@ +/* lists.c -- Buffer list handling routines -*- linux-c -*- + * Created: Mon Apr 19 20:54:22 1999 by faith@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rickard E. (Rik) Faith + * + */ + +#define __NO_VERSION__ +#include "drmP.h" + +int drm_waitlist_create(drm_waitlist_t *bl, int count) +{ + if (bl->count) return -EINVAL; + + bl->count = count; + bl->bufs = drm_alloc((bl->count + 2) * sizeof(*bl->bufs), + DRM_MEM_BUFLISTS); + bl->rp = bl->bufs; + bl->wp = bl->bufs; + bl->end = &bl->bufs[bl->count+1]; + bl->write_lock = SPIN_LOCK_UNLOCKED; + bl->read_lock = SPIN_LOCK_UNLOCKED; + return 0; +} + +int drm_waitlist_destroy(drm_waitlist_t *bl) +{ + if (bl->rp != bl->wp) return -EINVAL; + if (bl->bufs) drm_free(bl->bufs, + (bl->count + 2) * sizeof(*bl->bufs), + DRM_MEM_BUFLISTS); + bl->count = 0; + bl->bufs = NULL; + bl->rp = NULL; + bl->wp = NULL; + bl->end = NULL; + return 0; +} + +int drm_waitlist_put(drm_waitlist_t *bl, drm_buf_t *buf) +{ + int left; + unsigned long flags; + + left = DRM_LEFTCOUNT(bl); + if (!left) { + DRM_ERROR("Overflow while adding buffer %d from pid %d\n", + buf->idx, buf->pid); + return -EINVAL; + } +#if DRM_DMA_HISTOGRAM + buf->time_queued = get_cycles(); +#endif + buf->list = DRM_LIST_WAIT; + + spin_lock_irqsave(&bl->write_lock, flags); + *bl->wp = buf; + if (++bl->wp >= bl->end) bl->wp = bl->bufs; + spin_unlock_irqrestore(&bl->write_lock, flags); + + return 0; +} + +drm_buf_t *drm_waitlist_get(drm_waitlist_t *bl) +{ + drm_buf_t *buf; + unsigned long flags; + + spin_lock_irqsave(&bl->read_lock, flags); + buf = *bl->rp; + if (bl->rp == bl->wp) { + spin_unlock_irqrestore(&bl->read_lock, flags); + return NULL; + } + if (++bl->rp >= bl->end) bl->rp = bl->bufs; + spin_unlock_irqrestore(&bl->read_lock, flags); + + return buf; +} + +int drm_freelist_create(drm_freelist_t *bl, int count) +{ + atomic_set(&bl->count, 0); + bl->next = NULL; + init_waitqueue_head(&bl->waiting); + bl->low_mark = 0; + bl->high_mark = 0; + atomic_set(&bl->wfh, 0); + bl->lock = SPIN_LOCK_UNLOCKED; + ++bl->initialized; + return 0; +} + +int drm_freelist_destroy(drm_freelist_t *bl) +{ + atomic_set(&bl->count, 0); + bl->next = NULL; + return 0; +} + +int drm_freelist_put(drm_device_t *dev, drm_freelist_t *bl, drm_buf_t *buf) +{ + drm_device_dma_t *dma = dev->dma; + + if (!dma) { + DRM_ERROR("No DMA support\n"); + return 1; + } + + if (buf->waiting || buf->pending || buf->list == DRM_LIST_FREE) { + DRM_ERROR("Freed buffer %d: w%d, p%d, l%d\n", + buf->idx, buf->waiting, buf->pending, buf->list); + } + if (!bl) return 1; +#if DRM_DMA_HISTOGRAM + buf->time_freed = get_cycles(); + drm_histogram_compute(dev, buf); +#endif + buf->list = DRM_LIST_FREE; + + spin_lock(&bl->lock); + buf->next = bl->next; + bl->next = buf; + spin_unlock(&bl->lock); + + atomic_inc(&bl->count); + if (atomic_read(&bl->count) > dma->buf_count) { + DRM_ERROR("%d of %d buffers free after addition of %d\n", + atomic_read(&bl->count), dma->buf_count, buf->idx); + return 1; + } + /* Check for high water mark */ + if (atomic_read(&bl->wfh) && atomic_read(&bl->count)>=bl->high_mark) { + atomic_set(&bl->wfh, 0); + wake_up_interruptible(&bl->waiting); + } + return 0; +} + +static drm_buf_t *drm_freelist_try(drm_freelist_t *bl) +{ + drm_buf_t *buf; + + if (!bl) return NULL; + + /* Get buffer */ + spin_lock(&bl->lock); + if (!bl->next) { + spin_unlock(&bl->lock); + return NULL; + } + buf = bl->next; + bl->next = bl->next->next; + spin_unlock(&bl->lock); + + atomic_dec(&bl->count); + buf->next = NULL; + buf->list = DRM_LIST_NONE; + if (buf->waiting || buf->pending) { + DRM_ERROR("Free buffer %d: w%d, p%d, l%d\n", + buf->idx, buf->waiting, buf->pending, buf->list); + } + + return buf; +} + +drm_buf_t *drm_freelist_get(drm_freelist_t *bl, int block) +{ + drm_buf_t *buf = NULL; + DECLARE_WAITQUEUE(entry, current); + + if (!bl || !bl->initialized) return NULL; + + /* Check for low water mark */ + if (atomic_read(&bl->count) <= bl->low_mark) /* Became low */ + atomic_set(&bl->wfh, 1); + if (atomic_read(&bl->wfh)) { + if (block) { + add_wait_queue(&bl->waiting, &entry); + for (;;) { + current->state = TASK_INTERRUPTIBLE; + if (!atomic_read(&bl->wfh) + && (buf = drm_freelist_try(bl))) break; + schedule(); + if (signal_pending(current)) break; + } + current->state = TASK_RUNNING; + remove_wait_queue(&bl->waiting, &entry); + } + return buf; + } + + return drm_freelist_try(bl); +} diff -urN linux-2.4.10/drivers/char/drm-4.0/lock.c linux-2.4.10-lia/drivers/char/drm-4.0/lock.c --- linux-2.4.10/drivers/char/drm-4.0/lock.c Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/lock.c Wed Aug 15 20:52:11 2001 @@ -0,0 +1,252 @@ +/* lock.c -- IOCTLs for locking -*- linux-c -*- + * Created: Tue Feb 2 08:37:54 1999 by faith@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rickard E. (Rik) Faith + * + */ + +#define __NO_VERSION__ +#include "drmP.h" + +int drm_block(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + DRM_DEBUG("\n"); + return 0; +} + +int drm_unblock(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + DRM_DEBUG("\n"); + return 0; +} + +int drm_lock_take(__volatile__ unsigned int *lock, unsigned int context) +{ + unsigned int old, new, prev; + + do { + old = *lock; + if (old & _DRM_LOCK_HELD) new = old | _DRM_LOCK_CONT; + else new = context | _DRM_LOCK_HELD; + prev = cmpxchg(lock, old, new); + } while (prev != old); + if (_DRM_LOCKING_CONTEXT(old) == context) { + if (old & _DRM_LOCK_HELD) { + if (context != DRM_KERNEL_CONTEXT) { + DRM_ERROR("%d holds heavyweight lock\n", + context); + } + return 0; + } + } + if (new == (context | _DRM_LOCK_HELD)) { + /* Have lock */ + return 1; + } + return 0; +} + +/* This takes a lock forcibly and hands it to context. Should ONLY be used + inside *_unlock to give lock to kernel before calling *_dma_schedule. */ +int drm_lock_transfer(drm_device_t *dev, + __volatile__ unsigned int *lock, unsigned int context) +{ + unsigned int old, new, prev; + + dev->lock.pid = 0; + do { + old = *lock; + new = context | _DRM_LOCK_HELD; + prev = cmpxchg(lock, old, new); + } while (prev != old); + return 1; +} + +int drm_lock_free(drm_device_t *dev, + __volatile__ unsigned int *lock, unsigned int context) +{ + unsigned int old, new, prev; + pid_t pid = dev->lock.pid; + + dev->lock.pid = 0; + do { + old = *lock; + new = 0; + prev = cmpxchg(lock, old, new); + } while (prev != old); + if (_DRM_LOCK_IS_HELD(old) && _DRM_LOCKING_CONTEXT(old) != context) { + DRM_ERROR("%d freed heavyweight lock held by %d (pid %d)\n", + context, + _DRM_LOCKING_CONTEXT(old), + pid); + return 1; + } + wake_up_interruptible(&dev->lock.lock_queue); + return 0; +} + +static int drm_flush_queue(drm_device_t *dev, int context) +{ + DECLARE_WAITQUEUE(entry, current); + int ret = 0; + drm_queue_t *q = dev->queuelist[context]; + + DRM_DEBUG("\n"); + + atomic_inc(&q->use_count); + if (atomic_read(&q->use_count) > 1) { + atomic_inc(&q->block_write); + add_wait_queue(&q->flush_queue, &entry); + atomic_inc(&q->block_count); + for (;;) { + current->state = TASK_INTERRUPTIBLE; + if (!DRM_BUFCOUNT(&q->waitlist)) break; + schedule(); + if (signal_pending(current)) { + ret = -EINTR; /* Can't restart */ + break; + } + } + atomic_dec(&q->block_count); + current->state = TASK_RUNNING; + remove_wait_queue(&q->flush_queue, &entry); + } + atomic_dec(&q->use_count); + atomic_inc(&q->total_flushed); + + /* NOTE: block_write is still incremented! + Use drm_flush_unlock_queue to decrement. */ + return ret; +} + +static int drm_flush_unblock_queue(drm_device_t *dev, int context) +{ + drm_queue_t *q = dev->queuelist[context]; + + DRM_DEBUG("\n"); + + atomic_inc(&q->use_count); + if (atomic_read(&q->use_count) > 1) { + if (atomic_read(&q->block_write)) { + atomic_dec(&q->block_write); + wake_up_interruptible(&q->write_queue); + } + } + atomic_dec(&q->use_count); + return 0; +} + +int drm_flush_block_and_flush(drm_device_t *dev, int context, + drm_lock_flags_t flags) +{ + int ret = 0; + int i; + + DRM_DEBUG("\n"); + + if (flags & _DRM_LOCK_FLUSH) { + ret = drm_flush_queue(dev, DRM_KERNEL_CONTEXT); + if (!ret) ret = drm_flush_queue(dev, context); + } + if (flags & _DRM_LOCK_FLUSH_ALL) { + for (i = 0; !ret && i < dev->queue_count; i++) { + ret = drm_flush_queue(dev, i); + } + } + return ret; +} + +int drm_flush_unblock(drm_device_t *dev, int context, drm_lock_flags_t flags) +{ + int ret = 0; + int i; + + DRM_DEBUG("\n"); + + if (flags & _DRM_LOCK_FLUSH) { + ret = drm_flush_unblock_queue(dev, DRM_KERNEL_CONTEXT); + if (!ret) ret = drm_flush_unblock_queue(dev, context); + } + if (flags & _DRM_LOCK_FLUSH_ALL) { + for (i = 0; !ret && i < dev->queue_count; i++) { + ret = drm_flush_unblock_queue(dev, i); + } + } + + return ret; +} + +int drm_finish(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + int ret = 0; + drm_lock_t lock; + + DRM_DEBUG("\n"); + + if (copy_from_user(&lock, (drm_lock_t *)arg, sizeof(lock))) + return -EFAULT; + ret = drm_flush_block_and_flush(dev, lock.context, lock.flags); + drm_flush_unblock(dev, lock.context, lock.flags); + return ret; +} + +/* If we get here, it means that the process has called DRM_IOCTL_LOCK + without calling DRM_IOCTL_UNLOCK. + + If the lock is not held, then let the signal proceed as usual. + + If the lock is held, then set the contended flag and keep the signal + blocked. + + + Return 1 if the signal should be delivered normally. + Return 0 if the signal should be blocked. */ + +int drm_notifier(void *priv) +{ + drm_sigdata_t *s = (drm_sigdata_t *)priv; + unsigned int old, new, prev; + + + /* Allow signal delivery if lock isn't held */ + if (!_DRM_LOCK_IS_HELD(s->lock->lock) + || _DRM_LOCKING_CONTEXT(s->lock->lock) != s->context) return 1; + + /* Otherwise, set flag to force call to + drmUnlock */ + do { + old = s->lock->lock; + new = old | _DRM_LOCK_CONT; + prev = cmpxchg(&s->lock->lock, old, new); + } while (prev != old); + return 0; +} diff -urN linux-2.4.10/drivers/char/drm-4.0/memory.c linux-2.4.10-lia/drivers/char/drm-4.0/memory.c --- linux-2.4.10/drivers/char/drm-4.0/memory.c Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/memory.c Mon Aug 20 18:09:34 2001 @@ -0,0 +1,486 @@ +/* memory.c -- Memory management wrappers for DRM -*- linux-c -*- + * Created: Thu Feb 4 14:00:34 1999 by faith@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rickard E. (Rik) Faith + * + */ + +#define __NO_VERSION__ +#include +#include "drmP.h" +#include + +typedef struct drm_mem_stats { + const char *name; + int succeed_count; + int free_count; + int fail_count; + unsigned long bytes_allocated; + unsigned long bytes_freed; +} drm_mem_stats_t; + +static spinlock_t drm_mem_lock = SPIN_LOCK_UNLOCKED; +static unsigned long drm_ram_available = 0; /* In pages */ +static unsigned long drm_ram_used = 0; +static drm_mem_stats_t drm_mem_stats[] = { + [DRM_MEM_DMA] = { "dmabufs" }, + [DRM_MEM_SAREA] = { "sareas" }, + [DRM_MEM_DRIVER] = { "driver" }, + [DRM_MEM_MAGIC] = { "magic" }, + [DRM_MEM_IOCTLS] = { "ioctltab" }, + [DRM_MEM_MAPS] = { "maplist" }, + [DRM_MEM_VMAS] = { "vmalist" }, + [DRM_MEM_BUFS] = { "buflist" }, + [DRM_MEM_SEGS] = { "seglist" }, + [DRM_MEM_PAGES] = { "pagelist" }, + [DRM_MEM_FILES] = { "files" }, + [DRM_MEM_QUEUES] = { "queues" }, + [DRM_MEM_CMDS] = { "commands" }, + [DRM_MEM_MAPPINGS] = { "mappings" }, + [DRM_MEM_BUFLISTS] = { "buflists" }, + [DRM_MEM_AGPLISTS] = { "agplist" }, + [DRM_MEM_TOTALAGP] = { "totalagp" }, + [DRM_MEM_BOUNDAGP] = { "boundagp" }, + [DRM_MEM_CTXBITMAP] = { "ctxbitmap"}, + { NULL, 0, } /* Last entry must be null */ +}; + +void drm_mem_init(void) +{ + drm_mem_stats_t *mem; + struct sysinfo si; + + for (mem = drm_mem_stats; mem->name; ++mem) { + mem->succeed_count = 0; + mem->free_count = 0; + mem->fail_count = 0; + mem->bytes_allocated = 0; + mem->bytes_freed = 0; + } + + si_meminfo(&si); +#if LINUX_VERSION_CODE < 0x020317 + /* Changed to page count in 2.3.23 */ + drm_ram_available = si.totalram >> PAGE_SHIFT; +#else + drm_ram_available = si.totalram; +#endif + drm_ram_used = 0; +} + +/* drm_mem_info is called whenever a process reads /dev/drm/mem. */ + +static int _drm_mem_info(char *buf, char **start, off_t offset, int len, + int *eof, void *data) +{ + drm_mem_stats_t *pt; + + if (offset > 0) return 0; /* no partial requests */ + len = 0; + *eof = 1; + DRM_PROC_PRINT(" total counts " + " | outstanding \n"); + DRM_PROC_PRINT("type alloc freed fail bytes freed" + " | allocs bytes\n\n"); + DRM_PROC_PRINT("%-9.9s %5d %5d %4d %10lu kB |\n", + "system", 0, 0, 0, + drm_ram_available << (PAGE_SHIFT - 10)); + DRM_PROC_PRINT("%-9.9s %5d %5d %4d %10lu kB |\n", + "locked", 0, 0, 0, drm_ram_used >> 10); + DRM_PROC_PRINT("\n"); + for (pt = drm_mem_stats; pt->name; pt++) { + DRM_PROC_PRINT("%-9.9s %5d %5d %4d %10lu %10lu | %6d %10ld\n", + pt->name, + pt->succeed_count, + pt->free_count, + pt->fail_count, + pt->bytes_allocated, + pt->bytes_freed, + pt->succeed_count - pt->free_count, + (long)pt->bytes_allocated + - (long)pt->bytes_freed); + } + + return len; +} + +int drm_mem_info(char *buf, char **start, off_t offset, int len, + int *eof, void *data) +{ + int ret; + + spin_lock(&drm_mem_lock); + ret = _drm_mem_info(buf, start, offset, len, eof, data); + spin_unlock(&drm_mem_lock); + return ret; +} + +void *drm_alloc(size_t size, int area) +{ + void *pt; + + if (!size) { + DRM_MEM_ERROR(area, "Allocating 0 bytes\n"); + return NULL; + } + + if (!(pt = kmalloc(size, GFP_KERNEL))) { + spin_lock(&drm_mem_lock); + ++drm_mem_stats[area].fail_count; + spin_unlock(&drm_mem_lock); + return NULL; + } + spin_lock(&drm_mem_lock); + ++drm_mem_stats[area].succeed_count; + drm_mem_stats[area].bytes_allocated += size; + spin_unlock(&drm_mem_lock); + return pt; +} + +void *drm_realloc(void *oldpt, size_t oldsize, size_t size, int area) +{ + void *pt; + + if (!(pt = drm_alloc(size, area))) return NULL; + if (oldpt && oldsize) { + memcpy(pt, oldpt, oldsize); + drm_free(oldpt, oldsize, area); + } + return pt; +} + +char *drm_strdup(const char *s, int area) +{ + char *pt; + int length = s ? strlen(s) : 0; + + if (!(pt = drm_alloc(length+1, area))) return NULL; + strcpy(pt, s); + return pt; +} + +void drm_strfree(const char *s, int area) +{ + unsigned int size; + + if (!s) return; + + size = 1 + (s ? strlen(s) : 0); + drm_free((void *)s, size, area); +} + +void drm_free(void *pt, size_t size, int area) +{ + int alloc_count; + int free_count; + + if (!pt) DRM_MEM_ERROR(area, "Attempt to free NULL pointer\n"); + else kfree(pt); + spin_lock(&drm_mem_lock); + drm_mem_stats[area].bytes_freed += size; + free_count = ++drm_mem_stats[area].free_count; + alloc_count = drm_mem_stats[area].succeed_count; + spin_unlock(&drm_mem_lock); + if (free_count > alloc_count) { + DRM_MEM_ERROR(area, "Excess frees: %d frees, %d allocs\n", + free_count, alloc_count); + } +} + +unsigned long drm_alloc_pages(int order, int area) +{ + unsigned long address; + unsigned long bytes = PAGE_SIZE << order; + unsigned long addr; + unsigned int sz; + + spin_lock(&drm_mem_lock); + if ((drm_ram_used >> PAGE_SHIFT) + > (DRM_RAM_PERCENT * drm_ram_available) / 100) { + spin_unlock(&drm_mem_lock); + return 0; + } + spin_unlock(&drm_mem_lock); + + address = __get_free_pages(GFP_KERNEL, order); + if (!address) { + spin_lock(&drm_mem_lock); + ++drm_mem_stats[area].fail_count; + spin_unlock(&drm_mem_lock); + return 0; + } + spin_lock(&drm_mem_lock); + ++drm_mem_stats[area].succeed_count; + drm_mem_stats[area].bytes_allocated += bytes; + drm_ram_used += bytes; + spin_unlock(&drm_mem_lock); + + + /* Zero outside the lock */ + memset((void *)address, 0, bytes); + + /* Reserve */ + for (addr = address, sz = bytes; + sz > 0; + addr += PAGE_SIZE, sz -= PAGE_SIZE) { +#if LINUX_VERSION_CODE >= 0x020400 + /* Argument type changed in 2.4.0-test6/pre8 */ + mem_map_reserve(virt_to_page(addr)); +#else + mem_map_reserve(MAP_NR(addr)); +#endif + } + + return address; +} + +void drm_free_pages(unsigned long address, int order, int area) +{ + unsigned long bytes = PAGE_SIZE << order; + int alloc_count; + int free_count; + unsigned long addr; + unsigned int sz; + + if (!address) { + DRM_MEM_ERROR(area, "Attempt to free address 0\n"); + } else { + /* Unreserve */ + for (addr = address, sz = bytes; + sz > 0; + addr += PAGE_SIZE, sz -= PAGE_SIZE) { +#if LINUX_VERSION_CODE >= 0x020400 + /* Argument type changed in 2.4.0-test6/pre8 */ + mem_map_unreserve(virt_to_page(addr)); +#else + mem_map_unreserve(MAP_NR(addr)); +#endif + } + free_pages(address, order); + } + + spin_lock(&drm_mem_lock); + free_count = ++drm_mem_stats[area].free_count; + alloc_count = drm_mem_stats[area].succeed_count; + drm_mem_stats[area].bytes_freed += bytes; + drm_ram_used -= bytes; + spin_unlock(&drm_mem_lock); + if (free_count > alloc_count) { + DRM_MEM_ERROR(area, + "Excess frees: %d frees, %d allocs\n", + free_count, alloc_count); + } +} + +void *drm_ioremap(unsigned long offset, unsigned long size, drm_device_t *dev) +{ + void *pt; + + if (!size) { + DRM_MEM_ERROR(DRM_MEM_MAPPINGS, + "Mapping 0 bytes at 0x%08lx\n", offset); + return NULL; + } + + if(dev->agp->cant_use_aperture == 0) { + goto standard_ioremap; + } else { + drm_map_t *map = NULL; + int i; + + for(i = 0; i < dev->map_count; i++) { + map = dev->maplist[i]; + if (!map) continue; + if (map->offset <= offset && + (map->offset + map->size) >= (offset + size)) + break; + } + + if(map && map->type == _DRM_AGP) { + struct drm_agp_mem *agpmem; + + for(agpmem = dev->agp->memory; agpmem; + agpmem = agpmem->next) { + if(agpmem->bound <= offset && + (agpmem->bound + (agpmem->pages + << PAGE_SHIFT)) >= (offset + size)) + break; + } + + if(agpmem == NULL) + goto standard_ioremap; + + pt = agpmem->memory->vmptr + (offset - agpmem->bound); + goto ioremap_success; + } else { + goto standard_ioremap; + } + } + +standard_ioremap: + if (!(pt = ioremap(offset, size))) { + spin_lock(&drm_mem_lock); + ++drm_mem_stats[DRM_MEM_MAPPINGS].fail_count; + spin_unlock(&drm_mem_lock); + return NULL; + } + +ioremap_success: + spin_lock(&drm_mem_lock); + ++drm_mem_stats[DRM_MEM_MAPPINGS].succeed_count; + drm_mem_stats[DRM_MEM_MAPPINGS].bytes_allocated += size; + spin_unlock(&drm_mem_lock); + return pt; +} + +void drm_ioremapfree(void *pt, unsigned long size, drm_device_t *dev) +{ + int alloc_count; + int free_count; + + if (!pt) + DRM_MEM_ERROR(DRM_MEM_MAPPINGS, + "Attempt to free NULL pointer\n"); + else if(dev->agp->cant_use_aperture == 0) + iounmap(pt); + + spin_lock(&drm_mem_lock); + drm_mem_stats[DRM_MEM_MAPPINGS].bytes_freed += size; + free_count = ++drm_mem_stats[DRM_MEM_MAPPINGS].free_count; + alloc_count = drm_mem_stats[DRM_MEM_MAPPINGS].succeed_count; + spin_unlock(&drm_mem_lock); + if (free_count > alloc_count) { + DRM_MEM_ERROR(DRM_MEM_MAPPINGS, + "Excess frees: %d frees, %d allocs\n", + free_count, alloc_count); + } +} + +#if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE) +agp_memory *drm_alloc_agp(int pages, u32 type) +{ + agp_memory *handle; + + if (!pages) { + DRM_MEM_ERROR(DRM_MEM_TOTALAGP, "Allocating 0 pages\n"); + return NULL; + } + + if ((handle = drm_agp_allocate_memory(pages, type))) { + spin_lock(&drm_mem_lock); + ++drm_mem_stats[DRM_MEM_TOTALAGP].succeed_count; + drm_mem_stats[DRM_MEM_TOTALAGP].bytes_allocated + += pages << PAGE_SHIFT; + spin_unlock(&drm_mem_lock); + return handle; + } + spin_lock(&drm_mem_lock); + ++drm_mem_stats[DRM_MEM_TOTALAGP].fail_count; + spin_unlock(&drm_mem_lock); + return NULL; +} + +int drm_free_agp(agp_memory *handle, int pages) +{ + int alloc_count; + int free_count; + int retval = -EINVAL; + + if (!handle) { + DRM_MEM_ERROR(DRM_MEM_TOTALAGP, + "Attempt to free NULL AGP handle\n"); + return retval;; + } + + if (drm_agp_free_memory(handle)) { + spin_lock(&drm_mem_lock); + free_count = ++drm_mem_stats[DRM_MEM_TOTALAGP].free_count; + alloc_count = drm_mem_stats[DRM_MEM_TOTALAGP].succeed_count; + drm_mem_stats[DRM_MEM_TOTALAGP].bytes_freed + += pages << PAGE_SHIFT; + spin_unlock(&drm_mem_lock); + if (free_count > alloc_count) { + DRM_MEM_ERROR(DRM_MEM_TOTALAGP, + "Excess frees: %d frees, %d allocs\n", + free_count, alloc_count); + } + return 0; + } + return retval; +} + +int drm_bind_agp(agp_memory *handle, unsigned int start) +{ + int retcode = -EINVAL; + + if (!handle) { + DRM_MEM_ERROR(DRM_MEM_BOUNDAGP, + "Attempt to bind NULL AGP handle\n"); + return retcode; + } + + if (!(retcode = drm_agp_bind_memory(handle, start))) { + spin_lock(&drm_mem_lock); + ++drm_mem_stats[DRM_MEM_BOUNDAGP].succeed_count; + drm_mem_stats[DRM_MEM_BOUNDAGP].bytes_allocated + += handle->page_count << PAGE_SHIFT; + spin_unlock(&drm_mem_lock); + return retcode; + } + spin_lock(&drm_mem_lock); + ++drm_mem_stats[DRM_MEM_BOUNDAGP].fail_count; + spin_unlock(&drm_mem_lock); + return retcode; +} + +int drm_unbind_agp(agp_memory *handle) +{ + int alloc_count; + int free_count; + int retcode = -EINVAL; + + if (!handle) { + DRM_MEM_ERROR(DRM_MEM_BOUNDAGP, + "Attempt to unbind NULL AGP handle\n"); + return retcode; + } + + if ((retcode = drm_agp_unbind_memory(handle))) return retcode; + spin_lock(&drm_mem_lock); + free_count = ++drm_mem_stats[DRM_MEM_BOUNDAGP].free_count; + alloc_count = drm_mem_stats[DRM_MEM_BOUNDAGP].succeed_count; + drm_mem_stats[DRM_MEM_BOUNDAGP].bytes_freed + += handle->page_count << PAGE_SHIFT; + spin_unlock(&drm_mem_lock); + if (free_count > alloc_count) { + DRM_MEM_ERROR(DRM_MEM_BOUNDAGP, + "Excess frees: %d frees, %d allocs\n", + free_count, alloc_count); + } + return retcode; +} +#endif diff -urN linux-2.4.10/drivers/char/drm-4.0/mga_bufs.c linux-2.4.10-lia/drivers/char/drm-4.0/mga_bufs.c --- linux-2.4.10/drivers/char/drm-4.0/mga_bufs.c Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/mga_bufs.c Wed Aug 15 20:52:11 2001 @@ -0,0 +1,629 @@ +/* mga_bufs.c -- IOCTLs to manage buffers -*- linux-c -*- + * Created: Thu Jan 6 01:47:26 2000 by jhartmann@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: Rickard E. (Rik) Faith + * Jeff Hartmann + * + */ + +#define __NO_VERSION__ +#include "drmP.h" +#include "mga_drv.h" +#include "linux/un.h" + + +int mga_addbufs_agp(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_device_dma_t *dma = dev->dma; + drm_buf_desc_t request; + drm_buf_entry_t *entry; + drm_buf_t *buf; + unsigned long offset; + unsigned long agp_offset; + int count; + int order; + int size; + int alignment; + int page_order; + int total; + int byte_count; + int i; + + if (!dma) return -EINVAL; + + if (copy_from_user(&request, + (drm_buf_desc_t *)arg, + sizeof(request))) + return -EFAULT; + + count = request.count; + order = drm_order(request.size); + size = 1 << order; + agp_offset = request.agp_start; + alignment = (request.flags & _DRM_PAGE_ALIGN) ? PAGE_ALIGN(size):size; + page_order = order - PAGE_SHIFT > 0 ? order - PAGE_SHIFT : 0; + total = PAGE_SIZE << page_order; + byte_count = 0; + + DRM_DEBUG("count: %d\n", count); + DRM_DEBUG("order: %d\n", order); + DRM_DEBUG("size: %d\n", size); + DRM_DEBUG("agp_offset: %ld\n", agp_offset); + DRM_DEBUG("alignment: %d\n", alignment); + DRM_DEBUG("page_order: %d\n", page_order); + DRM_DEBUG("total: %d\n", total); + DRM_DEBUG("byte_count: %d\n", byte_count); + + if (order < DRM_MIN_ORDER || order > DRM_MAX_ORDER) return -EINVAL; + if (dev->queue_count) return -EBUSY; /* Not while in use */ + spin_lock(&dev->count_lock); + if (dev->buf_use) { + spin_unlock(&dev->count_lock); + return -EBUSY; + } + atomic_inc(&dev->buf_alloc); + spin_unlock(&dev->count_lock); + + down(&dev->struct_sem); + entry = &dma->bufs[order]; + if (entry->buf_count) { + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); + return -ENOMEM; /* May only call once for each order */ + } + + /* This isnt neccessarily a good limit, but we have to stop a dumb + 32 bit overflow problem below */ + + if ( count < 0 || count > 4096) + { + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); + return -EINVAL; + } + + entry->buflist = drm_alloc(count * sizeof(*entry->buflist), + DRM_MEM_BUFS); + if (!entry->buflist) { + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); + return -ENOMEM; + } + memset(entry->buflist, 0, count * sizeof(*entry->buflist)); + + entry->buf_size = size; + entry->page_order = page_order; + offset = 0; + + + while(entry->buf_count < count) { + buf = &entry->buflist[entry->buf_count]; + buf->idx = dma->buf_count + entry->buf_count; + buf->total = alignment; + buf->order = order; + buf->used = 0; + + buf->offset = offset; /* Hrm */ + buf->bus_address = dev->agp->base + agp_offset + offset; + buf->address = (void *)(agp_offset + offset + dev->agp->base); + buf->next = NULL; + buf->waiting = 0; + buf->pending = 0; + init_waitqueue_head(&buf->dma_wait); + buf->pid = 0; + + buf->dev_private = drm_alloc(sizeof(drm_mga_buf_priv_t), + DRM_MEM_BUFS); + buf->dev_priv_size = sizeof(drm_mga_buf_priv_t); + +#if DRM_DMA_HISTOGRAM + buf->time_queued = 0; + buf->time_dispatched = 0; + buf->time_completed = 0; + buf->time_freed = 0; +#endif + offset = offset + alignment; + entry->buf_count++; + byte_count += PAGE_SIZE << page_order; + } + + dma->buflist = drm_realloc(dma->buflist, + dma->buf_count * sizeof(*dma->buflist), + (dma->buf_count + entry->buf_count) + * sizeof(*dma->buflist), + DRM_MEM_BUFS); + for (i = dma->buf_count; i < dma->buf_count + entry->buf_count; i++) + dma->buflist[i] = &entry->buflist[i - dma->buf_count]; + + dma->buf_count += entry->buf_count; + + DRM_DEBUG("dma->buf_count : %d\n", dma->buf_count); + + dma->byte_count += byte_count; + + DRM_DEBUG("entry->buf_count : %d\n", entry->buf_count); + + drm_freelist_create(&entry->freelist, entry->buf_count); + for (i = 0; i < entry->buf_count; i++) { + drm_freelist_put(dev, &entry->freelist, &entry->buflist[i]); + } + + up(&dev->struct_sem); + + request.count = entry->buf_count; + request.size = size; + + if (copy_to_user((drm_buf_desc_t *)arg, + &request, + sizeof(request))) + return -EFAULT; + + atomic_dec(&dev->buf_alloc); + + DRM_DEBUG("count: %d\n", count); + DRM_DEBUG("order: %d\n", order); + DRM_DEBUG("size: %d\n", size); + DRM_DEBUG("agp_offset: %ld\n", agp_offset); + DRM_DEBUG("alignment: %d\n", alignment); + DRM_DEBUG("page_order: %d\n", page_order); + DRM_DEBUG("total: %d\n", total); + DRM_DEBUG("byte_count: %d\n", byte_count); + + dma->flags = _DRM_DMA_USE_AGP; + + DRM_DEBUG("dma->flags : %x\n", dma->flags); + + return 0; +} + +int mga_addbufs_pci(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_device_dma_t *dma = dev->dma; + drm_buf_desc_t request; + int count; + int order; + int size; + int total; + int page_order; + drm_buf_entry_t *entry; + unsigned long page; + drm_buf_t *buf; + int alignment; + unsigned long offset; + int i; + int byte_count; + int page_count; + + if (!dma) return -EINVAL; + + if (copy_from_user(&request, + (drm_buf_desc_t *)arg, + sizeof(request))) + return -EFAULT; + + count = request.count; + order = drm_order(request.size); + size = 1 << order; + + DRM_DEBUG("count = %d, size = %d (%d), order = %d, queue_count = %d\n", + request.count, request.size, size, order, dev->queue_count); + + if (order < DRM_MIN_ORDER || order > DRM_MAX_ORDER) return -EINVAL; + if (dev->queue_count) return -EBUSY; /* Not while in use */ + + alignment = (request.flags & _DRM_PAGE_ALIGN) ? PAGE_ALIGN(size):size; + page_order = order - PAGE_SHIFT > 0 ? order - PAGE_SHIFT : 0; + total = PAGE_SIZE << page_order; + + spin_lock(&dev->count_lock); + if (dev->buf_use) { + spin_unlock(&dev->count_lock); + return -EBUSY; + } + atomic_inc(&dev->buf_alloc); + spin_unlock(&dev->count_lock); + + down(&dev->struct_sem); + entry = &dma->bufs[order]; + if (entry->buf_count) { + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); + return -ENOMEM; /* May only call once for each order */ + } + + if(count < 0 || count > 4096) + { + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); + return -EINVAL; + } + + entry->buflist = drm_alloc(count * sizeof(*entry->buflist), + DRM_MEM_BUFS); + if (!entry->buflist) { + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); + return -ENOMEM; + } + memset(entry->buflist, 0, count * sizeof(*entry->buflist)); + + entry->seglist = drm_alloc(count * sizeof(*entry->seglist), + DRM_MEM_SEGS); + if (!entry->seglist) { + drm_free(entry->buflist, + count * sizeof(*entry->buflist), + DRM_MEM_BUFS); + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); + return -ENOMEM; + } + memset(entry->seglist, 0, count * sizeof(*entry->seglist)); + + dma->pagelist = drm_realloc(dma->pagelist, + dma->page_count * sizeof(*dma->pagelist), + (dma->page_count + (count << page_order)) + * sizeof(*dma->pagelist), + DRM_MEM_PAGES); + DRM_DEBUG("pagelist: %d entries\n", + dma->page_count + (count << page_order)); + + + entry->buf_size = size; + entry->page_order = page_order; + byte_count = 0; + page_count = 0; + while (entry->buf_count < count) { + if (!(page = drm_alloc_pages(page_order, DRM_MEM_DMA))) break; + entry->seglist[entry->seg_count++] = page; + for (i = 0; i < (1 << page_order); i++) { + DRM_DEBUG("page %d @ 0x%08lx\n", + dma->page_count + page_count, + page + PAGE_SIZE * i); + dma->pagelist[dma->page_count + page_count++] + = page + PAGE_SIZE * i; + } + for (offset = 0; + offset + size <= total && entry->buf_count < count; + offset += alignment, ++entry->buf_count) { + buf = &entry->buflist[entry->buf_count]; + buf->idx = dma->buf_count + entry->buf_count; + buf->total = alignment; + buf->order = order; + buf->used = 0; + buf->offset = (dma->byte_count + byte_count + offset); + buf->address = (void *)(page + offset); + buf->next = NULL; + buf->waiting = 0; + buf->pending = 0; + init_waitqueue_head(&buf->dma_wait); + buf->pid = 0; +#if DRM_DMA_HISTOGRAM + buf->time_queued = 0; + buf->time_dispatched = 0; + buf->time_completed = 0; + buf->time_freed = 0; +#endif + DRM_DEBUG("buffer %d @ %p\n", + entry->buf_count, buf->address); + } + byte_count += PAGE_SIZE << page_order; + } + + dma->buflist = drm_realloc(dma->buflist, + dma->buf_count * sizeof(*dma->buflist), + (dma->buf_count + entry->buf_count) + * sizeof(*dma->buflist), + DRM_MEM_BUFS); + for (i = dma->buf_count; i < dma->buf_count + entry->buf_count; i++) + dma->buflist[i] = &entry->buflist[i - dma->buf_count]; + + dma->buf_count += entry->buf_count; + dma->seg_count += entry->seg_count; + dma->page_count += entry->seg_count << page_order; + dma->byte_count += PAGE_SIZE * (entry->seg_count << page_order); + + drm_freelist_create(&entry->freelist, entry->buf_count); + for (i = 0; i < entry->buf_count; i++) { + drm_freelist_put(dev, &entry->freelist, &entry->buflist[i]); + } + + up(&dev->struct_sem); + + request.count = entry->buf_count; + request.size = size; + + if (copy_to_user((drm_buf_desc_t *)arg, + &request, + sizeof(request))) + return -EFAULT; + + atomic_dec(&dev->buf_alloc); + return 0; +} + +int mga_addbufs(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_buf_desc_t request; + + if (copy_from_user(&request, + (drm_buf_desc_t *)arg, + sizeof(request))) + return -EFAULT; + + if(request.flags & _DRM_AGP_BUFFER) + return mga_addbufs_agp(inode, filp, cmd, arg); + else + return mga_addbufs_pci(inode, filp, cmd, arg); +} + +int mga_infobufs(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_device_dma_t *dma = dev->dma; + drm_buf_info_t request; + int i; + int count; + + if (!dma) return -EINVAL; + + spin_lock(&dev->count_lock); + if (atomic_read(&dev->buf_alloc)) { + spin_unlock(&dev->count_lock); + return -EBUSY; + } + ++dev->buf_use; /* Can't allocate more after this call */ + spin_unlock(&dev->count_lock); + + if (copy_from_user(&request, + (drm_buf_info_t *)arg, + sizeof(request))) + return -EFAULT; + + for (i = 0, count = 0; i < DRM_MAX_ORDER+1; i++) { + if (dma->bufs[i].buf_count) ++count; + } + + if (request.count >= count) { + for (i = 0, count = 0; i < DRM_MAX_ORDER+1; i++) { + if (dma->bufs[i].buf_count) { + if (copy_to_user(&request.list[count].count, + &dma->bufs[i].buf_count, + sizeof(dma->bufs[0] + .buf_count)) || + copy_to_user(&request.list[count].size, + &dma->bufs[i].buf_size, + sizeof(dma->bufs[0].buf_size)) || + copy_to_user(&request.list[count].low_mark, + &dma->bufs[i] + .freelist.low_mark, + sizeof(dma->bufs[0] + .freelist.low_mark)) || + copy_to_user(&request.list[count] + .high_mark, + &dma->bufs[i] + .freelist.high_mark, + sizeof(dma->bufs[0] + .freelist.high_mark))) + return -EFAULT; + ++count; + } + } + } + request.count = count; + + if (copy_to_user((drm_buf_info_t *)arg, + &request, + sizeof(request))) + return -EFAULT; + + return 0; +} + +int mga_markbufs(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_device_dma_t *dma = dev->dma; + drm_buf_desc_t request; + int order; + drm_buf_entry_t *entry; + + if (!dma) return -EINVAL; + + if (copy_from_user(&request, (drm_buf_desc_t *)arg, sizeof(request))) + return -EFAULT; + + order = drm_order(request.size); + if (order < DRM_MIN_ORDER || order > DRM_MAX_ORDER) return -EINVAL; + entry = &dma->bufs[order]; + + if (request.low_mark < 0 || request.low_mark > entry->buf_count) + return -EINVAL; + if (request.high_mark < 0 || request.high_mark > entry->buf_count) + return -EINVAL; + + entry->freelist.low_mark = request.low_mark; + entry->freelist.high_mark = request.high_mark; + + return 0; +} + +int mga_freebufs(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_device_dma_t *dma = dev->dma; + drm_buf_free_t request; + int i; + int idx; + drm_buf_t *buf; + + if (!dma) return -EINVAL; + + if (copy_from_user(&request, + (drm_buf_free_t *)arg, + sizeof(request))) + return -EFAULT; + + for (i = 0; i < request.count; i++) { + if (copy_from_user(&idx, + &request.list[i], + sizeof(idx))) + return -EFAULT; + if (idx < 0 || idx >= dma->buf_count) { + DRM_ERROR("Index %d (of %d max)\n", + idx, dma->buf_count - 1); + return -EINVAL; + } + buf = dma->buflist[idx]; + if (buf->pid != current->pid) { + DRM_ERROR("Process %d freeing buffer owned by %d\n", + current->pid, buf->pid); + return -EINVAL; + } + drm_free_buffer(dev, buf); + } + + return 0; +} + +int mga_mapbufs(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_device_dma_t *dma = dev->dma; + int retcode = 0; + const int zero = 0; + unsigned long virtual; + unsigned long address; + drm_buf_map_t request; + int i; + + if (!dma) return -EINVAL; + + spin_lock(&dev->count_lock); + if (atomic_read(&dev->buf_alloc)) { + spin_unlock(&dev->count_lock); + return -EBUSY; + } + ++dev->buf_use; /* Can't allocate more after this call */ + spin_unlock(&dev->count_lock); + + if (copy_from_user(&request, + (drm_buf_map_t *)arg, + sizeof(request))) + return -EFAULT; + + if (request.count >= dma->buf_count) { + if(dma->flags & _DRM_DMA_USE_AGP) { + drm_mga_private_t *dev_priv = dev->dev_private; + drm_map_t *map = NULL; + + map = dev->maplist[dev_priv->buffer_map_idx]; + if (!map) { + retcode = -EINVAL; + goto done; + } + + DRM_DEBUG("map->offset : %lx\n", map->offset); + DRM_DEBUG("map->size : %lx\n", map->size); + DRM_DEBUG("map->type : %d\n", map->type); + DRM_DEBUG("map->flags : %x\n", map->flags); + DRM_DEBUG("map->handle : %p\n", map->handle); + DRM_DEBUG("map->mtrr : %d\n", map->mtrr); + down_write(¤t->mm->mmap_sem); + virtual = do_mmap(filp, 0, map->size, + PROT_READ|PROT_WRITE, + MAP_SHARED, + (unsigned long)map->offset); + up_write(¤t->mm->mmap_sem); + } else { + down_write(¤t->mm->mmap_sem); + virtual = do_mmap(filp, 0, dma->byte_count, + PROT_READ|PROT_WRITE, MAP_SHARED, 0); + up_write(¤t->mm->mmap_sem); + } + if (virtual > -1024UL) { + /* Real error */ + DRM_DEBUG("mmap error\n"); + retcode = (signed long)virtual; + goto done; + } + request.virtual = (void *)virtual; + + for (i = 0; i < dma->buf_count; i++) { + if (copy_to_user(&request.list[i].idx, + &dma->buflist[i]->idx, + sizeof(request.list[0].idx))) { + retcode = -EFAULT; + goto done; + } + if (copy_to_user(&request.list[i].total, + &dma->buflist[i]->total, + sizeof(request.list[0].total))) { + retcode = -EFAULT; + goto done; + } + if (copy_to_user(&request.list[i].used, + &zero, + sizeof(zero))) { + retcode = -EFAULT; + goto done; + } + address = virtual + dma->buflist[i]->offset; + if (copy_to_user(&request.list[i].address, + &address, + sizeof(address))) { + retcode = -EFAULT; + goto done; + } + } + } + done: + request.count = dma->buf_count; + DRM_DEBUG("%d buffers, retcode = %d\n", request.count, retcode); + + if (copy_to_user((drm_buf_map_t *)arg, + &request, + sizeof(request))) + return -EFAULT; + + DRM_DEBUG("retcode : %d\n", retcode); + + return retcode; +} diff -urN linux-2.4.10/drivers/char/drm-4.0/mga_context.c linux-2.4.10-lia/drivers/char/drm-4.0/mga_context.c --- linux-2.4.10/drivers/char/drm-4.0/mga_context.c Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/mga_context.c Wed Aug 15 20:52:11 2001 @@ -0,0 +1,209 @@ +/* mga_context.c -- IOCTLs for mga contexts -*- linux-c -*- + * Created: Mon Dec 13 09:51:35 1999 by faith@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Author: Rickard E. (Rik) Faith + * Jeff Hartmann + * + */ + +#define __NO_VERSION__ +#include "drmP.h" +#include "mga_drv.h" + +static int mga_alloc_queue(drm_device_t *dev) +{ + return drm_ctxbitmap_next(dev); +} + +int mga_context_switch(drm_device_t *dev, int old, int new) +{ + char buf[64]; + + atomic_inc(&dev->total_ctx); + + if (test_and_set_bit(0, &dev->context_flag)) { + DRM_ERROR("Reentering -- FIXME\n"); + return -EBUSY; + } + +#if DRM_DMA_HISTOGRAM + dev->ctx_start = get_cycles(); +#endif + + DRM_DEBUG("Context switch from %d to %d\n", old, new); + + if (new == dev->last_context) { + clear_bit(0, &dev->context_flag); + return 0; + } + + if (drm_flags & DRM_FLAG_NOCTX) { + mga_context_switch_complete(dev, new); + } else { + sprintf(buf, "C %d %d\n", old, new); + drm_write_string(dev, buf); + } + + return 0; +} + +int mga_context_switch_complete(drm_device_t *dev, int new) +{ + dev->last_context = new; /* PRE/POST: This is the _only_ writer. */ + dev->last_switch = jiffies; + + if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { + DRM_ERROR("Lock isn't held after context switch\n"); + } + + /* If a context switch is ever initiated + when the kernel holds the lock, release + that lock here. */ +#if DRM_DMA_HISTOGRAM + atomic_inc(&dev->histo.ctx[drm_histogram_slot(get_cycles() + - dev->ctx_start)]); + +#endif + clear_bit(0, &dev->context_flag); + wake_up(&dev->context_wait); + + return 0; +} + +int mga_resctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_ctx_res_t res; + drm_ctx_t ctx; + int i; + + if (copy_from_user(&res, (drm_ctx_res_t *)arg, sizeof(res))) + return -EFAULT; + if (res.count >= DRM_RESERVED_CONTEXTS) { + memset(&ctx, 0, sizeof(ctx)); + for (i = 0; i < DRM_RESERVED_CONTEXTS; i++) { + ctx.handle = i; + if (copy_to_user(&res.contexts[i], + &i, + sizeof(i))) + return -EFAULT; + } + } + res.count = DRM_RESERVED_CONTEXTS; + if (copy_to_user((drm_ctx_res_t *)arg, &res, sizeof(res))) + return -EFAULT; + return 0; +} + +int mga_addctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ctx_t ctx; + + if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx))) + return -EFAULT; + if ((ctx.handle = mga_alloc_queue(dev)) == DRM_KERNEL_CONTEXT) { + /* Skip kernel's context and get a new one. */ + ctx.handle = mga_alloc_queue(dev); + } + if (ctx.handle == -1) { + return -ENOMEM; + } + DRM_DEBUG("%d\n", ctx.handle); + if (copy_to_user((drm_ctx_t *)arg, &ctx, sizeof(ctx))) + return -EFAULT; + return 0; +} + +int mga_modctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + /* This does nothing for the mga */ + return 0; +} + +int mga_getctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_ctx_t ctx; + + if (copy_from_user(&ctx, (drm_ctx_t*)arg, sizeof(ctx))) + return -EFAULT; + /* This is 0, because we don't hanlde any context flags */ + ctx.flags = 0; + if (copy_to_user((drm_ctx_t*)arg, &ctx, sizeof(ctx))) + return -EFAULT; + return 0; +} + +int mga_switchctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ctx_t ctx; + + if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx))) + return -EFAULT; + DRM_DEBUG("%d\n", ctx.handle); + return mga_context_switch(dev, dev->last_context, ctx.handle); +} + +int mga_newctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ctx_t ctx; + + if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx))) + return -EFAULT; + DRM_DEBUG("%d\n", ctx.handle); + mga_context_switch_complete(dev, ctx.handle); + + return 0; +} + +int mga_rmctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ctx_t ctx; + + if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx))) + return -EFAULT; + DRM_DEBUG("%d\n", ctx.handle); + if(ctx.handle == DRM_KERNEL_CONTEXT+1) priv->remove_auth_on_close = 1; + + if(ctx.handle != DRM_KERNEL_CONTEXT) { + drm_ctxbitmap_free(dev, ctx.handle); + } + + return 0; +} diff -urN linux-2.4.10/drivers/char/drm-4.0/mga_dma.c linux-2.4.10-lia/drivers/char/drm-4.0/mga_dma.c --- linux-2.4.10/drivers/char/drm-4.0/mga_dma.c Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/mga_dma.c Mon Aug 20 18:09:34 2001 @@ -0,0 +1,1059 @@ +/* mga_dma.c -- DMA support for mga g200/g400 -*- linux-c -*- + * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: Rickard E. (Rik) Faith + * Jeff Hartmann + * Keith Whitwell + * + */ + +#define __NO_VERSION__ +#include "drmP.h" +#include "mga_drv.h" + +#include /* For task queue support */ + +#define MGA_REG(reg) 2 +#define MGA_BASE(reg) ((unsigned long) \ + ((drm_device_t *)dev)->maplist[MGA_REG(reg)]->handle) +#define MGA_ADDR(reg) (MGA_BASE(reg) + reg) +#define MGA_DEREF(reg) *(__volatile__ int *)MGA_ADDR(reg) +#define MGA_READ(reg) MGA_DEREF(reg) +#define MGA_WRITE(reg,val) do { MGA_DEREF(reg) = val; } while (0) + +#define PDEA_pagpxfer_enable 0x2 + +static int mga_flush_queue(drm_device_t *dev); + +static unsigned long mga_alloc_page(drm_device_t *dev) +{ + unsigned long address; + + address = __get_free_page(GFP_KERNEL); + if(address == 0UL) { + return 0; + } + atomic_inc(&virt_to_page(address)->count); + set_bit(PG_reserved, &virt_to_page(address)->flags); + + return address; +} + +static void mga_free_page(drm_device_t *dev, unsigned long page) +{ + if(!page) return; + atomic_dec(&virt_to_page(page)->count); + clear_bit(PG_reserved, &virt_to_page(page)->flags); + free_page(page); + return; +} + +static void mga_delay(void) +{ + return; +} + +/* These are two age tags that will never be sent to + * the hardware */ +#define MGA_BUF_USED 0xffffffff +#define MGA_BUF_FREE 0 + +static int mga_freelist_init(drm_device_t *dev) +{ + drm_device_dma_t *dma = dev->dma; + drm_buf_t *buf; + drm_mga_buf_priv_t *buf_priv; + drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; + drm_mga_freelist_t *item; + int i; + + dev_priv->head = drm_alloc(sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER); + if(dev_priv->head == NULL) return -ENOMEM; + memset(dev_priv->head, 0, sizeof(drm_mga_freelist_t)); + dev_priv->head->age = MGA_BUF_USED; + + for (i = 0; i < dma->buf_count; i++) { + buf = dma->buflist[ i ]; + buf_priv = buf->dev_private; + item = drm_alloc(sizeof(drm_mga_freelist_t), + DRM_MEM_DRIVER); + if(item == NULL) return -ENOMEM; + memset(item, 0, sizeof(drm_mga_freelist_t)); + item->age = MGA_BUF_FREE; + item->prev = dev_priv->head; + item->next = dev_priv->head->next; + if(dev_priv->head->next != NULL) + dev_priv->head->next->prev = item; + if(item->next == NULL) dev_priv->tail = item; + item->buf = buf; + buf_priv->my_freelist = item; + buf_priv->discard = 0; + buf_priv->dispatched = 0; + dev_priv->head->next = item; + } + + return 0; +} + +static void mga_freelist_cleanup(drm_device_t *dev) +{ + drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; + drm_mga_freelist_t *item; + drm_mga_freelist_t *prev; + + item = dev_priv->head; + while(item) { + prev = item; + item = item->next; + drm_free(prev, sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER); + } + + dev_priv->head = dev_priv->tail = NULL; +} + +/* Frees dispatch lock */ +static inline void mga_dma_quiescent(drm_device_t *dev) +{ + drm_device_dma_t *dma = dev->dma; + drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + unsigned long end; + int i; + + DRM_DEBUG("dispatch_status = 0x%02lx\n", dev_priv->dispatch_status); + end = jiffies + (HZ*3); + while(1) { + if(!test_and_set_bit(MGA_IN_DISPATCH, + &dev_priv->dispatch_status)) { + break; + } + if((signed)(end - jiffies) <= 0) { + DRM_ERROR("irqs: %d wanted %d\n", + atomic_read(&dev->total_irq), + atomic_read(&dma->total_lost)); + DRM_ERROR("lockup: dispatch_status = 0x%02lx," + " jiffies = %lu, end = %lu\n", + dev_priv->dispatch_status, jiffies, end); + return; + } + for (i = 0 ; i < 2000 ; i++) mga_delay(); + } + end = jiffies + (HZ*3); + DRM_DEBUG("quiescent status : %x\n", MGA_READ(MGAREG_STATUS)); + while((MGA_READ(MGAREG_STATUS) & 0x00030001) != 0x00020000) { + if((signed)(end - jiffies) <= 0) { + DRM_ERROR("irqs: %d wanted %d\n", + atomic_read(&dev->total_irq), + atomic_read(&dma->total_lost)); + DRM_ERROR("lockup\n"); + clear_bit(MGA_IN_DISPATCH, &dev_priv->dispatch_status); + return; + } + for (i = 0 ; i < 2000 ; i++) mga_delay(); + } + sarea_priv->dirty |= MGA_DMA_FLUSH; + + clear_bit(MGA_IN_DISPATCH, &dev_priv->dispatch_status); + DRM_DEBUG("exit, dispatch_status = 0x%02lx\n", + dev_priv->dispatch_status); +} + +static void mga_reset_freelist(drm_device_t *dev) +{ + drm_device_dma_t *dma = dev->dma; + drm_buf_t *buf; + drm_mga_buf_priv_t *buf_priv; + int i; + + for (i = 0; i < dma->buf_count; i++) { + buf = dma->buflist[ i ]; + buf_priv = buf->dev_private; + buf_priv->my_freelist->age = MGA_BUF_FREE; + } +} + +/* Least recently used : + * These operations are not atomic b/c they are protected by the + * hardware lock */ + +drm_buf_t *mga_freelist_get(drm_device_t *dev) +{ + DECLARE_WAITQUEUE(entry, current); + drm_mga_private_t *dev_priv = + (drm_mga_private_t *) dev->dev_private; + drm_mga_freelist_t *prev; + drm_mga_freelist_t *next; + static int failed = 0; + int return_null = 0; + + if(failed >= 1000 && dev_priv->tail->age >= dev_priv->last_prim_age) { + DRM_DEBUG("Waiting on freelist," + " tail->age = %d, last_prim_age= %d\n", + dev_priv->tail->age, + dev_priv->last_prim_age); + add_wait_queue(&dev_priv->buf_queue, &entry); + set_bit(MGA_IN_GETBUF, &dev_priv->dispatch_status); + for (;;) { + current->state = TASK_INTERRUPTIBLE; + mga_dma_schedule(dev, 0); + if(dev_priv->tail->age < dev_priv->last_prim_age) + break; + atomic_inc(&dev->total_sleeps); + schedule(); + if (signal_pending(current)) { + ++return_null; + break; + } + } + clear_bit(MGA_IN_GETBUF, &dev_priv->dispatch_status); + current->state = TASK_RUNNING; + remove_wait_queue(&dev_priv->buf_queue, &entry); + if (return_null) return NULL; + } + + if(dev_priv->tail->age < dev_priv->last_prim_age) { + prev = dev_priv->tail->prev; + next = dev_priv->tail; + prev->next = NULL; + next->prev = next->next = NULL; + dev_priv->tail = prev; + next->age = MGA_BUF_USED; + failed = 0; + return next->buf; + } + + failed++; + return NULL; +} + +int mga_freelist_put(drm_device_t *dev, drm_buf_t *buf) +{ + drm_mga_private_t *dev_priv = + (drm_mga_private_t *) dev->dev_private; + drm_mga_buf_priv_t *buf_priv = buf->dev_private; + drm_mga_freelist_t *prev; + drm_mga_freelist_t *head; + drm_mga_freelist_t *next; + + if(buf_priv->my_freelist->age == MGA_BUF_USED) { + /* Discarded buffer, put it on the tail */ + next = buf_priv->my_freelist; + next->age = MGA_BUF_FREE; + prev = dev_priv->tail; + prev->next = next; + next->prev = prev; + next->next = NULL; + dev_priv->tail = next; + } else { + /* Normally aged buffer, put it on the head + 1, + * as the real head is a sentinal element + */ + next = buf_priv->my_freelist; + head = dev_priv->head; + prev = head->next; + head->next = next; + prev->prev = next; + next->prev = head; + next->next = prev; + } + + return 0; +} + +static int mga_init_primary_bufs(drm_device_t *dev, drm_mga_init_t *init) +{ + drm_mga_private_t *dev_priv = dev->dev_private; + drm_mga_prim_buf_t *prim_buffer; + int i, temp, size_of_buf; + int offset = init->reserved_map_agpstart; + + dev_priv->primary_size = ((init->primary_size + PAGE_SIZE - 1) / + PAGE_SIZE) * PAGE_SIZE; + size_of_buf = dev_priv->primary_size / MGA_NUM_PRIM_BUFS; + dev_priv->warp_ucode_size = init->warp_ucode_size; + dev_priv->prim_bufs = drm_alloc(sizeof(drm_mga_prim_buf_t *) * + (MGA_NUM_PRIM_BUFS + 1), + DRM_MEM_DRIVER); + if(dev_priv->prim_bufs == NULL) { + DRM_ERROR("Unable to allocate memory for prim_buf\n"); + return -ENOMEM; + } + memset(dev_priv->prim_bufs, + 0, sizeof(drm_mga_prim_buf_t *) * (MGA_NUM_PRIM_BUFS + 1)); + + temp = init->warp_ucode_size + dev_priv->primary_size; + temp = ((temp + PAGE_SIZE - 1) / PAGE_SIZE) * PAGE_SIZE; + + dev_priv->ioremap = drm_ioremap(dev->agp->base + offset, + temp, dev); + if(dev_priv->ioremap == NULL) { + DRM_ERROR("Ioremap failed\n"); + return -ENOMEM; + } + init_waitqueue_head(&dev_priv->wait_queue); + + for(i = 0; i < MGA_NUM_PRIM_BUFS; i++) { + prim_buffer = drm_alloc(sizeof(drm_mga_prim_buf_t), + DRM_MEM_DRIVER); + if(prim_buffer == NULL) return -ENOMEM; + memset(prim_buffer, 0, sizeof(drm_mga_prim_buf_t)); + prim_buffer->phys_head = offset + dev->agp->base; + prim_buffer->current_dma_ptr = + prim_buffer->head = + (u32 *) (dev_priv->ioremap + + offset - + init->reserved_map_agpstart); + prim_buffer->num_dwords = 0; + prim_buffer->max_dwords = size_of_buf / sizeof(u32); + prim_buffer->max_dwords -= 5; /* Leave room for the softrap */ + prim_buffer->sec_used = 0; + prim_buffer->idx = i; + prim_buffer->prim_age = i + 1; + offset = offset + size_of_buf; + dev_priv->prim_bufs[i] = prim_buffer; + } + dev_priv->current_prim_idx = 0; + dev_priv->next_prim = + dev_priv->last_prim = + dev_priv->current_prim = + dev_priv->prim_bufs[0]; + dev_priv->next_prim_age = 2; + dev_priv->last_prim_age = 1; + set_bit(MGA_BUF_IN_USE, &dev_priv->current_prim->buffer_status); + return 0; +} + +void mga_fire_primary(drm_device_t *dev, drm_mga_prim_buf_t *prim) +{ + drm_mga_private_t *dev_priv = dev->dev_private; + drm_device_dma_t *dma = dev->dma; + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + int use_agp = PDEA_pagpxfer_enable; + unsigned long end; + int i; + int next_idx; + PRIMLOCALS; + + dev_priv->last_prim = prim; + + /* We never check for overflow, b/c there is always room */ + PRIMPTR(prim); + if(num_dwords <= 0) { + DRM_ERROR("num_dwords == 0 when dispatched\n"); + goto out_prim_wait; + } + PRIMOUTREG( MGAREG_DMAPAD, 0); + PRIMOUTREG( MGAREG_DMAPAD, 0); + PRIMOUTREG( MGAREG_DMAPAD, 0); + PRIMOUTREG( MGAREG_SOFTRAP, 0); + PRIMFINISH(prim); + + end = jiffies + (HZ*3); + if(sarea_priv->dirty & MGA_DMA_FLUSH) { + while((MGA_READ(MGAREG_STATUS) & 0x00030001) != 0x00020000) { + if((signed)(end - jiffies) <= 0) { + DRM_ERROR("irqs: %d wanted %d\n", + atomic_read(&dev->total_irq), + atomic_read(&dma->total_lost)); + DRM_ERROR("lockup (flush)\n"); + goto out_prim_wait; + } + + for (i = 0 ; i < 4096 ; i++) mga_delay(); + } + sarea_priv->dirty &= ~(MGA_DMA_FLUSH); + } else { + while((MGA_READ(MGAREG_STATUS) & 0x00020001) != 0x00020000) { + if((signed)(end - jiffies) <= 0) { + DRM_ERROR("irqs: %d wanted %d\n", + atomic_read(&dev->total_irq), + atomic_read(&dma->total_lost)); + DRM_ERROR("lockup (wait)\n"); + goto out_prim_wait; + } + + for (i = 0 ; i < 4096 ; i++) mga_delay(); + } + } + + mga_flush_write_combine(); + atomic_inc(&dev_priv->pending_bufs); + MGA_WRITE(MGAREG_PRIMADDRESS, phys_head | TT_GENERAL); + MGA_WRITE(MGAREG_PRIMEND, (phys_head + num_dwords * 4) | use_agp); + prim->num_dwords = 0; + sarea_priv->last_enqueue = prim->prim_age; + + next_idx = prim->idx + 1; + if(next_idx >= MGA_NUM_PRIM_BUFS) + next_idx = 0; + + dev_priv->next_prim = dev_priv->prim_bufs[next_idx]; + return; + + out_prim_wait: + prim->num_dwords = 0; + prim->sec_used = 0; + clear_bit(MGA_BUF_IN_USE, &prim->buffer_status); + wake_up_interruptible(&dev_priv->wait_queue); + clear_bit(MGA_BUF_SWAP_PENDING, &prim->buffer_status); + clear_bit(MGA_IN_DISPATCH, &dev_priv->dispatch_status); +} + +int mga_advance_primary(drm_device_t *dev) +{ + DECLARE_WAITQUEUE(entry, current); + drm_mga_private_t *dev_priv = dev->dev_private; + drm_mga_prim_buf_t *prim_buffer; + drm_device_dma_t *dma = dev->dma; + int next_prim_idx; + int ret = 0; + + /* This needs to reset the primary buffer if available, + * we should collect stats on how many times it bites + * it's tail */ + + next_prim_idx = dev_priv->current_prim_idx + 1; + if(next_prim_idx >= MGA_NUM_PRIM_BUFS) + next_prim_idx = 0; + prim_buffer = dev_priv->prim_bufs[next_prim_idx]; + set_bit(MGA_IN_WAIT, &dev_priv->dispatch_status); + + /* In use is cleared in interrupt handler */ + + if(test_and_set_bit(MGA_BUF_IN_USE, &prim_buffer->buffer_status)) { + add_wait_queue(&dev_priv->wait_queue, &entry); + for (;;) { + current->state = TASK_INTERRUPTIBLE; + mga_dma_schedule(dev, 0); + if(!test_and_set_bit(MGA_BUF_IN_USE, + &prim_buffer->buffer_status)) + break; + atomic_inc(&dev->total_sleeps); + atomic_inc(&dma->total_missed_sched); + schedule(); + if (signal_pending(current)) { + ret = -ERESTARTSYS; + break; + } + } + current->state = TASK_RUNNING; + remove_wait_queue(&dev_priv->wait_queue, &entry); + if(ret) return ret; + } + clear_bit(MGA_IN_WAIT, &dev_priv->dispatch_status); + + /* This primary buffer is now free to use */ + prim_buffer->current_dma_ptr = prim_buffer->head; + prim_buffer->num_dwords = 0; + prim_buffer->sec_used = 0; + prim_buffer->prim_age = dev_priv->next_prim_age++; + if(prim_buffer->prim_age == 0 || prim_buffer->prim_age == 0xffffffff) { + mga_flush_queue(dev); + mga_dma_quiescent(dev); + mga_reset_freelist(dev); + prim_buffer->prim_age = (dev_priv->next_prim_age += 2); + } + + /* Reset all buffer status stuff */ + clear_bit(MGA_BUF_NEEDS_OVERFLOW, &prim_buffer->buffer_status); + clear_bit(MGA_BUF_FORCE_FIRE, &prim_buffer->buffer_status); + clear_bit(MGA_BUF_SWAP_PENDING, &prim_buffer->buffer_status); + + dev_priv->current_prim = prim_buffer; + dev_priv->current_prim_idx = next_prim_idx; + return 0; +} + +/* More dynamic performance decisions */ +static inline int mga_decide_to_fire(drm_device_t *dev) +{ + drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; + + if(test_bit(MGA_BUF_FORCE_FIRE, &dev_priv->next_prim->buffer_status)) { + return 1; + } + + if (test_bit(MGA_IN_GETBUF, &dev_priv->dispatch_status) && + dev_priv->next_prim->num_dwords) { + return 1; + } + + if (test_bit(MGA_IN_FLUSH, &dev_priv->dispatch_status) && + dev_priv->next_prim->num_dwords) { + return 1; + } + + if(atomic_read(&dev_priv->pending_bufs) <= MGA_NUM_PRIM_BUFS - 1) { + if(test_bit(MGA_BUF_SWAP_PENDING, + &dev_priv->next_prim->buffer_status)) { + return 1; + } + } + + if(atomic_read(&dev_priv->pending_bufs) <= MGA_NUM_PRIM_BUFS / 2) { + if(dev_priv->next_prim->sec_used >= MGA_DMA_BUF_NR / 8) { + return 1; + } + } + + if(atomic_read(&dev_priv->pending_bufs) >= MGA_NUM_PRIM_BUFS / 2) { + if(dev_priv->next_prim->sec_used >= MGA_DMA_BUF_NR / 4) { + return 1; + } + } + + return 0; +} + +int mga_dma_schedule(drm_device_t *dev, int locked) +{ + drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; + int retval = 0; + + if (!dev_priv) return -EBUSY; + + if (test_and_set_bit(0, &dev->dma_flag)) { + retval = -EBUSY; + goto sch_out_wakeup; + } + + if(test_bit(MGA_IN_FLUSH, &dev_priv->dispatch_status) || + test_bit(MGA_IN_WAIT, &dev_priv->dispatch_status) || + test_bit(MGA_IN_GETBUF, &dev_priv->dispatch_status)) { + locked = 1; + } + + if (!locked && + !drm_lock_take(&dev->lock.hw_lock->lock, DRM_KERNEL_CONTEXT)) { + clear_bit(0, &dev->dma_flag); + retval = -EBUSY; + goto sch_out_wakeup; + } + + if(!test_and_set_bit(MGA_IN_DISPATCH, &dev_priv->dispatch_status)) { + /* Fire dma buffer */ + if(mga_decide_to_fire(dev)) { + clear_bit(MGA_BUF_FORCE_FIRE, + &dev_priv->next_prim->buffer_status); + if(dev_priv->current_prim == dev_priv->next_prim) { + /* Schedule overflow for a later time */ + set_bit(MGA_BUF_NEEDS_OVERFLOW, + &dev_priv->next_prim->buffer_status); + } + mga_fire_primary(dev, dev_priv->next_prim); + } else { + clear_bit(MGA_IN_DISPATCH, &dev_priv->dispatch_status); + } + } + + if (!locked) { + if (drm_lock_free(dev, &dev->lock.hw_lock->lock, + DRM_KERNEL_CONTEXT)) { + DRM_ERROR("\n"); + } + } + + clear_bit(0, &dev->dma_flag); + +sch_out_wakeup: + if(test_bit(MGA_IN_FLUSH, &dev_priv->dispatch_status) && + atomic_read(&dev_priv->pending_bufs) == 0) { + /* Everything has been processed by the hardware */ + clear_bit(MGA_IN_FLUSH, &dev_priv->dispatch_status); + wake_up_interruptible(&dev_priv->flush_queue); + } + + if(test_bit(MGA_IN_GETBUF, &dev_priv->dispatch_status) + && dev_priv->tail->age < dev_priv->last_prim_age) + wake_up_interruptible(&dev_priv->buf_queue); + + return retval; +} + +static void mga_dma_service(int irq, void *device, struct pt_regs *regs) +{ + drm_device_t *dev = (drm_device_t *)device; + drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; + drm_mga_prim_buf_t *last_prim_buffer; + + atomic_inc(&dev->total_irq); + if((MGA_READ(MGAREG_STATUS) & 0x00000001) != 0x00000001) return; + MGA_WRITE(MGAREG_ICLEAR, 0x00000001); + last_prim_buffer = dev_priv->last_prim; + last_prim_buffer->num_dwords = 0; + last_prim_buffer->sec_used = 0; + dev_priv->sarea_priv->last_dispatch = + dev_priv->last_prim_age = last_prim_buffer->prim_age; + clear_bit(MGA_BUF_IN_USE, &last_prim_buffer->buffer_status); + clear_bit(MGA_BUF_SWAP_PENDING, &last_prim_buffer->buffer_status); + clear_bit(MGA_IN_DISPATCH, &dev_priv->dispatch_status); + atomic_dec(&dev_priv->pending_bufs); + queue_task(&dev->tq, &tq_immediate); + mark_bh(IMMEDIATE_BH); + wake_up_interruptible(&dev_priv->wait_queue); +} + +static void mga_dma_task_queue(void *device) +{ + mga_dma_schedule((drm_device_t *)device, 0); +} + +int mga_dma_cleanup(drm_device_t *dev) +{ + if(dev->dev_private) { + drm_mga_private_t *dev_priv = + (drm_mga_private_t *) dev->dev_private; + + if (dev->irq) mga_flush_queue(dev); + mga_dma_quiescent(dev); + + if(dev_priv->ioremap) { + int temp = (dev_priv->warp_ucode_size + + dev_priv->primary_size + + PAGE_SIZE - 1) / PAGE_SIZE * PAGE_SIZE; + + drm_ioremapfree((void *) dev_priv->ioremap, temp, dev); + } + if(dev_priv->status_page != NULL) { + iounmap(dev_priv->status_page); + } + if(dev_priv->real_status_page != 0UL) { + mga_free_page(dev, dev_priv->real_status_page); + } + if(dev_priv->prim_bufs != NULL) { + int i; + for(i = 0; i < MGA_NUM_PRIM_BUFS; i++) { + if(dev_priv->prim_bufs[i] != NULL) { + drm_free(dev_priv->prim_bufs[i], + sizeof(drm_mga_prim_buf_t), + DRM_MEM_DRIVER); + } + } + drm_free(dev_priv->prim_bufs, sizeof(void *) * + (MGA_NUM_PRIM_BUFS + 1), + DRM_MEM_DRIVER); + } + if(dev_priv->head != NULL) { + mga_freelist_cleanup(dev); + } + + + drm_free(dev->dev_private, sizeof(drm_mga_private_t), + DRM_MEM_DRIVER); + dev->dev_private = NULL; + } + + return 0; +} + +static int mga_dma_initialize(drm_device_t *dev, drm_mga_init_t *init) { + drm_mga_private_t *dev_priv; + drm_map_t *sarea_map = NULL; + + dev_priv = drm_alloc(sizeof(drm_mga_private_t), DRM_MEM_DRIVER); + if(dev_priv == NULL) return -ENOMEM; + dev->dev_private = (void *) dev_priv; + + memset(dev_priv, 0, sizeof(drm_mga_private_t)); + + if((init->reserved_map_idx >= dev->map_count) || + (init->buffer_map_idx >= dev->map_count)) { + mga_dma_cleanup(dev); + return -EINVAL; + } + + dev_priv->reserved_map_idx = init->reserved_map_idx; + dev_priv->buffer_map_idx = init->buffer_map_idx; + sarea_map = dev->maplist[0]; + dev_priv->sarea_priv = (drm_mga_sarea_t *) + ((u8 *)sarea_map->handle + + init->sarea_priv_offset); + + /* Scale primary size to the next page */ + dev_priv->chipset = init->chipset; + dev_priv->frontOffset = init->frontOffset; + dev_priv->backOffset = init->backOffset; + dev_priv->depthOffset = init->depthOffset; + dev_priv->textureOffset = init->textureOffset; + dev_priv->textureSize = init->textureSize; + dev_priv->cpp = init->cpp; + dev_priv->sgram = init->sgram; + dev_priv->stride = init->stride; + + dev_priv->mAccess = init->mAccess; + init_waitqueue_head(&dev_priv->flush_queue); + init_waitqueue_head(&dev_priv->buf_queue); + dev_priv->WarpPipe = 0xff000000; + dev_priv->vertexsize = 0; + + DRM_DEBUG("chipset=%d ucode_size=%d backOffset=%x depthOffset=%x\n", + dev_priv->chipset, dev_priv->warp_ucode_size, + dev_priv->backOffset, dev_priv->depthOffset); + DRM_DEBUG("cpp: %d sgram: %d stride: %d maccess: %x\n", + dev_priv->cpp, dev_priv->sgram, dev_priv->stride, + dev_priv->mAccess); + + memcpy(&dev_priv->WarpIndex, &init->WarpIndex, + sizeof(drm_mga_warp_index_t) * MGA_MAX_WARP_PIPES); + + if(mga_init_primary_bufs(dev, init) != 0) { + DRM_ERROR("Can not initialize primary buffers\n"); + mga_dma_cleanup(dev); + return -ENOMEM; + } + dev_priv->real_status_page = mga_alloc_page(dev); + if(dev_priv->real_status_page == 0UL) { + mga_dma_cleanup(dev); + DRM_ERROR("Can not allocate status page\n"); + return -ENOMEM; + } + + dev_priv->status_page = + ioremap_nocache(virt_to_bus((void *)dev_priv->real_status_page), + PAGE_SIZE); + + if(dev_priv->status_page == NULL) { + mga_dma_cleanup(dev); + DRM_ERROR("Can not remap status page\n"); + return -ENOMEM; + } + + /* Write status page when secend or softrap occurs + * + * Disable this on ia64 on the off chance that real status page will be + * above 4GB. + */ +#if defined(__ia64__) + MGA_WRITE(MGAREG_PRIMPTR, + virt_to_bus((void *)dev_priv->real_status_page)); +#else + MGA_WRITE(MGAREG_PRIMPTR, + virt_to_bus((void *)dev_priv->real_status_page) | 0x00000003); +#endif + + /* Private is now filled in, initialize the hardware */ + { + PRIMLOCALS; + PRIMGETPTR( dev_priv ); + + PRIMOUTREG(MGAREG_DMAPAD, 0); + PRIMOUTREG(MGAREG_DMAPAD, 0); + PRIMOUTREG(MGAREG_DWGSYNC, 0x0100); + PRIMOUTREG(MGAREG_SOFTRAP, 0); + /* Poll for the first buffer to insure that + * the status register will be correct + */ + + mga_flush_write_combine(); + MGA_WRITE(MGAREG_PRIMADDRESS, phys_head | TT_GENERAL); + + MGA_WRITE(MGAREG_PRIMEND, ((phys_head + num_dwords * 4) | + PDEA_pagpxfer_enable)); + + while(MGA_READ(MGAREG_DWGSYNC) != 0x0100) ; + } + + if(mga_freelist_init(dev) != 0) { + DRM_ERROR("Could not initialize freelist\n"); + mga_dma_cleanup(dev); + return -ENOMEM; + } + return 0; +} + +int mga_dma_init(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_mga_init_t init; + + if (copy_from_user(&init, (drm_mga_init_t *)arg, sizeof(init))) + return -EFAULT; + + switch(init.func) { + case MGA_INIT_DMA: + return mga_dma_initialize(dev, &init); + case MGA_CLEANUP_DMA: + return mga_dma_cleanup(dev); + } + + return -EINVAL; +} + +int mga_irq_install(drm_device_t *dev, int irq) +{ + int retcode; + + if (!irq) return -EINVAL; + + down(&dev->struct_sem); + if (dev->irq) { + up(&dev->struct_sem); + return -EBUSY; + } + dev->irq = irq; + up(&dev->struct_sem); + + DRM_DEBUG("install irq handler %d\n", irq); + + dev->context_flag = 0; + dev->interrupt_flag = 0; + dev->dma_flag = 0; + dev->dma->next_buffer = NULL; + dev->dma->next_queue = NULL; + dev->dma->this_buffer = NULL; + INIT_LIST_HEAD(&dev->tq.list); + dev->tq.sync = 0; + dev->tq.routine = mga_dma_task_queue; + dev->tq.data = dev; + + /* Before installing handler */ + MGA_WRITE(MGAREG_IEN, 0); + /* Install handler */ + if ((retcode = request_irq(dev->irq, + mga_dma_service, + SA_SHIRQ, + dev->devname, + dev))) { + down(&dev->struct_sem); + dev->irq = 0; + up(&dev->struct_sem); + return retcode; + } + /* After installing handler */ + MGA_WRITE(MGAREG_ICLEAR, 0x00000001); + MGA_WRITE(MGAREG_IEN, 0x00000001); + return 0; +} + +int mga_irq_uninstall(drm_device_t *dev) +{ + int irq; + + down(&dev->struct_sem); + irq = dev->irq; + dev->irq = 0; + up(&dev->struct_sem); + + if (!irq) return -EINVAL; + DRM_DEBUG("remove irq handler %d\n", irq); + MGA_WRITE(MGAREG_ICLEAR, 0x00000001); + MGA_WRITE(MGAREG_IEN, 0); + free_irq(irq, dev); + return 0; +} + +int mga_control(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_control_t ctl; + + if (copy_from_user(&ctl, (drm_control_t *)arg, sizeof(ctl))) + return -EFAULT; + + switch (ctl.func) { + case DRM_INST_HANDLER: + return mga_irq_install(dev, ctl.irq); + case DRM_UNINST_HANDLER: + return mga_irq_uninstall(dev); + default: + return -EINVAL; + } +} + +static int mga_flush_queue(drm_device_t *dev) +{ + DECLARE_WAITQUEUE(entry, current); + drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; + int ret = 0; + + if(!dev_priv) return 0; + + if(dev_priv->next_prim->num_dwords != 0) { + add_wait_queue(&dev_priv->flush_queue, &entry); + if (test_bit(MGA_IN_FLUSH, &dev_priv->dispatch_status)) + DRM_ERROR("Incorrect mga_flush_queue logic\n"); + set_bit(MGA_IN_FLUSH, &dev_priv->dispatch_status); + mga_dma_schedule(dev, 0); + for (;;) { + current->state = TASK_INTERRUPTIBLE; + if (!test_bit(MGA_IN_FLUSH, + &dev_priv->dispatch_status)) + break; + atomic_inc(&dev->total_sleeps); + schedule(); + if (signal_pending(current)) { + ret = -EINTR; /* Can't restart */ + clear_bit(MGA_IN_FLUSH, + &dev_priv->dispatch_status); + break; + } + } + current->state = TASK_RUNNING; + remove_wait_queue(&dev_priv->flush_queue, &entry); + } + return ret; +} + +/* Must be called with the lock held */ +void mga_reclaim_buffers(drm_device_t *dev, pid_t pid) +{ + drm_device_dma_t *dma = dev->dma; + int i; + + if (!dma) return; + if(dev->dev_private == NULL) return; + if(dma->buflist == NULL) return; + + DRM_DEBUG("buf_count=%d\n", dma->buf_count); + + mga_flush_queue(dev); + + for (i = 0; i < dma->buf_count; i++) { + drm_buf_t *buf = dma->buflist[ i ]; + drm_mga_buf_priv_t *buf_priv = buf->dev_private; + + /* Only buffers that need to get reclaimed ever + * get set to free + */ + if (buf->pid == pid && buf_priv) { + if(buf_priv->my_freelist->age == MGA_BUF_USED) + buf_priv->my_freelist->age = MGA_BUF_FREE; + } + } +} + +int mga_lock(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + DECLARE_WAITQUEUE(entry, current); + int ret = 0; + drm_lock_t lock; + + if (copy_from_user(&lock, (drm_lock_t *)arg, sizeof(lock))) + return -EFAULT; + + if (lock.context == DRM_KERNEL_CONTEXT) { + DRM_ERROR("Process %d using kernel context %d\n", + current->pid, lock.context); + return -EINVAL; + } + + if (lock.context < 0) return -EINVAL; + + /* Only one queue: + */ + + if (!ret) { + add_wait_queue(&dev->lock.lock_queue, &entry); + for (;;) { + current->state = TASK_INTERRUPTIBLE; + if (!dev->lock.hw_lock) { + /* Device has been unregistered */ + ret = -EINTR; + break; + } + if (drm_lock_take(&dev->lock.hw_lock->lock, + lock.context)) { + dev->lock.pid = current->pid; + dev->lock.lock_time = jiffies; + atomic_inc(&dev->total_locks); + break; /* Got lock */ + } + + /* Contention */ + atomic_inc(&dev->total_sleeps); + schedule(); + if (signal_pending(current)) { + ret = -ERESTARTSYS; + break; + } + } + current->state = TASK_RUNNING; + remove_wait_queue(&dev->lock.lock_queue, &entry); + } + + if (!ret) { + sigemptyset(&dev->sigmask); + sigaddset(&dev->sigmask, SIGSTOP); + sigaddset(&dev->sigmask, SIGTSTP); + sigaddset(&dev->sigmask, SIGTTIN); + sigaddset(&dev->sigmask, SIGTTOU); + dev->sigdata.context = lock.context; + dev->sigdata.lock = dev->lock.hw_lock; + block_all_signals(drm_notifier, &dev->sigdata, &dev->sigmask); + + if (lock.flags & _DRM_LOCK_QUIESCENT) { + DRM_DEBUG("_DRM_LOCK_QUIESCENT\n"); + mga_flush_queue(dev); + mga_dma_quiescent(dev); + } + } + + if (ret) DRM_DEBUG("%d %s\n", lock.context, + ret ? "interrupted" : "has lock"); + return ret; +} + +int mga_flush_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_lock_t lock; + drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; + + if (copy_from_user(&lock, (drm_lock_t *)arg, sizeof(lock))) + return -EFAULT; + + if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { + DRM_ERROR("lock not held\n"); + return -EINVAL; + } + + if(lock.flags & _DRM_LOCK_FLUSH || lock.flags & _DRM_LOCK_FLUSH_ALL) { + drm_mga_prim_buf_t *temp_buf; + + temp_buf = dev_priv->current_prim; + + if(temp_buf && temp_buf->num_dwords) { + set_bit(MGA_BUF_FORCE_FIRE, &temp_buf->buffer_status); + mga_advance_primary(dev); + } + mga_dma_schedule(dev, 1); + } + if(lock.flags & _DRM_LOCK_QUIESCENT) { + mga_flush_queue(dev); + mga_dma_quiescent(dev); + } + + return 0; +} diff -urN linux-2.4.10/drivers/char/drm-4.0/mga_drm.h linux-2.4.10-lia/drivers/char/drm-4.0/mga_drm.h --- linux-2.4.10/drivers/char/drm-4.0/mga_drm.h Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/mga_drm.h Wed Aug 15 20:52:11 2001 @@ -0,0 +1,274 @@ +/* mga_drm.h -- Public header for the Matrox g200/g400 driver -*- linux-c -*- + * Created: Tue Jan 25 01:50:01 1999 by jhartmann@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: Jeff Hartmann + * Keith Whitwell + * + */ + +#ifndef _MGA_DRM_H_ +#define _MGA_DRM_H_ + +/* WARNING: If you change any of these defines, make sure to change the + * defines in the Xserver file (xf86drmMga.h) + */ +#ifndef _MGA_DEFINES_ +#define _MGA_DEFINES_ + +#define MGA_F 0x1 /* fog */ +#define MGA_A 0x2 /* alpha */ +#define MGA_S 0x4 /* specular */ +#define MGA_T2 0x8 /* multitexture */ + +#define MGA_WARP_TGZ 0 +#define MGA_WARP_TGZF (MGA_F) +#define MGA_WARP_TGZA (MGA_A) +#define MGA_WARP_TGZAF (MGA_F|MGA_A) +#define MGA_WARP_TGZS (MGA_S) +#define MGA_WARP_TGZSF (MGA_S|MGA_F) +#define MGA_WARP_TGZSA (MGA_S|MGA_A) +#define MGA_WARP_TGZSAF (MGA_S|MGA_F|MGA_A) +#define MGA_WARP_T2GZ (MGA_T2) +#define MGA_WARP_T2GZF (MGA_T2|MGA_F) +#define MGA_WARP_T2GZA (MGA_T2|MGA_A) +#define MGA_WARP_T2GZAF (MGA_T2|MGA_A|MGA_F) +#define MGA_WARP_T2GZS (MGA_T2|MGA_S) +#define MGA_WARP_T2GZSF (MGA_T2|MGA_S|MGA_F) +#define MGA_WARP_T2GZSA (MGA_T2|MGA_S|MGA_A) +#define MGA_WARP_T2GZSAF (MGA_T2|MGA_S|MGA_F|MGA_A) + +#define MGA_MAX_G400_PIPES 16 +#define MGA_MAX_G200_PIPES 8 /* no multitex */ +#define MGA_MAX_WARP_PIPES MGA_MAX_G400_PIPES + +#define MGA_CARD_TYPE_G200 1 +#define MGA_CARD_TYPE_G400 2 + +#define MGA_FRONT 0x1 +#define MGA_BACK 0x2 +#define MGA_DEPTH 0x4 + +/* 3d state excluding texture units: + */ +#define MGA_CTXREG_DSTORG 0 /* validated */ +#define MGA_CTXREG_MACCESS 1 +#define MGA_CTXREG_PLNWT 2 +#define MGA_CTXREG_DWGCTL 3 +#define MGA_CTXREG_ALPHACTRL 4 +#define MGA_CTXREG_FOGCOLOR 5 +#define MGA_CTXREG_WFLAG 6 +#define MGA_CTXREG_TDUAL0 7 +#define MGA_CTXREG_TDUAL1 8 +#define MGA_CTXREG_FCOL 9 +#define MGA_CTXREG_STENCIL 10 +#define MGA_CTXREG_STENCILCTL 11 +#define MGA_CTX_SETUP_SIZE 12 + +/* 2d state + */ +#define MGA_2DREG_PITCH 0 +#define MGA_2D_SETUP_SIZE 1 + +/* Each texture unit has a state: + */ +#define MGA_TEXREG_CTL 0 +#define MGA_TEXREG_CTL2 1 +#define MGA_TEXREG_FILTER 2 +#define MGA_TEXREG_BORDERCOL 3 +#define MGA_TEXREG_ORG 4 /* validated */ +#define MGA_TEXREG_ORG1 5 +#define MGA_TEXREG_ORG2 6 +#define MGA_TEXREG_ORG3 7 +#define MGA_TEXREG_ORG4 8 +#define MGA_TEXREG_WIDTH 9 +#define MGA_TEXREG_HEIGHT 10 +#define MGA_TEX_SETUP_SIZE 11 + +/* What needs to be changed for the current vertex dma buffer? + */ +#define MGA_UPLOAD_CTX 0x1 +#define MGA_UPLOAD_TEX0 0x2 +#define MGA_UPLOAD_TEX1 0x4 +#define MGA_UPLOAD_PIPE 0x8 +#define MGA_UPLOAD_TEX0IMAGE 0x10 /* handled client-side */ +#define MGA_UPLOAD_TEX1IMAGE 0x20 /* handled client-side */ +#define MGA_UPLOAD_2D 0x40 +#define MGA_WAIT_AGE 0x80 /* handled client-side */ +#define MGA_UPLOAD_CLIPRECTS 0x100 /* handled client-side */ +#define MGA_DMA_FLUSH 0x200 /* set when someone gets the lock + quiescent */ + +/* 32 buffers of 64k each, total 2 meg. + */ +#define MGA_DMA_BUF_ORDER 16 +#define MGA_DMA_BUF_SZ (1< + * Jeff Hartmann + * + * + */ + +#include +#include "drmP.h" +#include "mga_drv.h" + +#define MGA_NAME "mga" +#define MGA_DESC "Matrox G200/G400" +#define MGA_DATE "20000928" +#define MGA_MAJOR 2 +#define MGA_MINOR 0 +#define MGA_PATCHLEVEL 1 + +static drm_device_t mga_device; +drm_ctx_t mga_res_ctx; + +static struct file_operations mga_fops = { +#if LINUX_VERSION_CODE >= 0x020400 + /* This started being used during 2.4.0-test */ + owner: THIS_MODULE, +#endif + open: mga_open, + flush: drm_flush, + release: mga_release, + ioctl: mga_ioctl, + mmap: drm_mmap, + read: drm_read, + fasync: drm_fasync, + poll: drm_poll, +}; + +static struct miscdevice mga_misc = { + minor: MISC_DYNAMIC_MINOR, + name: MGA_NAME, + fops: &mga_fops, +}; + +static drm_ioctl_desc_t mga_ioctls[] = { + [DRM_IOCTL_NR(DRM_IOCTL_VERSION)] = { mga_version, 0, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_GET_UNIQUE)] = { drm_getunique, 0, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_GET_MAGIC)] = { drm_getmagic, 0, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_IRQ_BUSID)] = { drm_irq_busid, 0, 1 }, + + [DRM_IOCTL_NR(DRM_IOCTL_SET_UNIQUE)] = { drm_setunique, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_BLOCK)] = { drm_block, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_UNBLOCK)] = { drm_unblock, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_CONTROL)] = { mga_control, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_AUTH_MAGIC)] = { drm_authmagic, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_ADD_MAP)] = { drm_addmap, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_ADD_BUFS)] = { mga_addbufs, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_MARK_BUFS)] = { mga_markbufs, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_INFO_BUFS)] = { mga_infobufs, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_MAP_BUFS)] = { mga_mapbufs, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_FREE_BUFS)] = { mga_freebufs, 1, 0 }, + + [DRM_IOCTL_NR(DRM_IOCTL_ADD_CTX)] = { mga_addctx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_RM_CTX)] = { mga_rmctx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_MOD_CTX)] = { mga_modctx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_GET_CTX)] = { mga_getctx, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_SWITCH_CTX)] = { mga_switchctx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_NEW_CTX)] = { mga_newctx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_RES_CTX)] = { mga_resctx, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_ADD_DRAW)] = { drm_adddraw, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_RM_DRAW)] = { drm_rmdraw, 1, 1 }, + + [DRM_IOCTL_NR(DRM_IOCTL_DMA)] = { mga_dma, 1, 0 }, + + [DRM_IOCTL_NR(DRM_IOCTL_LOCK)] = { mga_lock, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_UNLOCK)] = { mga_unlock, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_FINISH)] = { drm_finish, 1, 0 }, + + [DRM_IOCTL_NR(DRM_IOCTL_AGP_ACQUIRE)] = { drm_agp_acquire, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_RELEASE)] = { drm_agp_release, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_ENABLE)] = { drm_agp_enable, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_INFO)] = { drm_agp_info, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_ALLOC)] = { drm_agp_alloc, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_FREE)] = { drm_agp_free, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_BIND)] = { drm_agp_bind, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_UNBIND)] = { drm_agp_unbind, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_MGA_INIT)] = { mga_dma_init, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_MGA_SWAP)] = { mga_swap_bufs, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_MGA_CLEAR)] = { mga_clear_bufs, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_MGA_ILOAD)] = { mga_iload, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_MGA_VERTEX)] = { mga_vertex, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_MGA_FLUSH)] = { mga_flush_ioctl, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_MGA_INDICES)] = { mga_indices, 1, 0 }, +}; + +#define MGA_IOCTL_COUNT DRM_ARRAY_SIZE(mga_ioctls) + +#ifdef MODULE +static char *mga = NULL; +#endif + +MODULE_AUTHOR("VA Linux Systems, Inc."); +MODULE_DESCRIPTION("Matrox G200/G400"); +MODULE_PARM(mga, "s"); + +#ifndef MODULE +/* mga_options is called by the kernel to parse command-line options passed + * via the boot-loader (e.g., LILO). It calls the insmod option routine, + * drm_parse_drm. + */ + +static int __init mga_options(char *str) +{ + drm_parse_options(str); + return 1; +} + +__setup("mga=", mga_options); +#endif + +static int mga_setup(drm_device_t *dev) +{ + int i; + + atomic_set(&dev->ioctl_count, 0); + atomic_set(&dev->vma_count, 0); + dev->buf_use = 0; + atomic_set(&dev->buf_alloc, 0); + + drm_dma_setup(dev); + + atomic_set(&dev->total_open, 0); + atomic_set(&dev->total_close, 0); + atomic_set(&dev->total_ioctl, 0); + atomic_set(&dev->total_irq, 0); + atomic_set(&dev->total_ctx, 0); + atomic_set(&dev->total_locks, 0); + atomic_set(&dev->total_unlocks, 0); + atomic_set(&dev->total_contends, 0); + atomic_set(&dev->total_sleeps, 0); + + for (i = 0; i < DRM_HASH_SIZE; i++) { + dev->magiclist[i].head = NULL; + dev->magiclist[i].tail = NULL; + } + dev->maplist = NULL; + dev->map_count = 0; + dev->vmalist = NULL; + dev->lock.hw_lock = NULL; + init_waitqueue_head(&dev->lock.lock_queue); + dev->queue_count = 0; + dev->queue_reserved = 0; + dev->queue_slots = 0; + dev->queuelist = NULL; + dev->irq = 0; + dev->context_flag = 0; + dev->interrupt_flag = 0; + dev->dma_flag = 0; + dev->last_context = 0; + dev->last_switch = 0; + dev->last_checked = 0; + init_timer(&dev->timer); + init_waitqueue_head(&dev->context_wait); + + dev->ctx_start = 0; + dev->lck_start = 0; + + dev->buf_rp = dev->buf; + dev->buf_wp = dev->buf; + dev->buf_end = dev->buf + DRM_BSZ; + dev->buf_async = NULL; + init_waitqueue_head(&dev->buf_readers); + init_waitqueue_head(&dev->buf_writers); + + DRM_DEBUG("\n"); + + /* The kernel's context could be created here, but is now created + in drm_dma_enqueue. This is more resource-efficient for + hardware that does not do DMA, but may mean that + drm_select_queue fails between the time the interrupt is + initialized and the time the queues are initialized. */ + + return 0; +} + + +static int mga_takedown(drm_device_t *dev) +{ + int i; + drm_magic_entry_t *pt, *next; + drm_map_t *map; + drm_vma_entry_t *vma, *vma_next; + + DRM_DEBUG("\n"); + + if (dev->dev_private) mga_dma_cleanup(dev); + if (dev->irq) mga_irq_uninstall(dev); + + down(&dev->struct_sem); + del_timer(&dev->timer); + + if (dev->devname) { + drm_free(dev->devname, strlen(dev->devname)+1, DRM_MEM_DRIVER); + dev->devname = NULL; + } + + if (dev->unique) { + drm_free(dev->unique, strlen(dev->unique)+1, DRM_MEM_DRIVER); + dev->unique = NULL; + dev->unique_len = 0; + } + /* Clear pid list */ + for (i = 0; i < DRM_HASH_SIZE; i++) { + for (pt = dev->magiclist[i].head; pt; pt = next) { + next = pt->next; + drm_free(pt, sizeof(*pt), DRM_MEM_MAGIC); + } + dev->magiclist[i].head = dev->magiclist[i].tail = NULL; + } + /* Clear AGP information */ + if (dev->agp) { + drm_agp_mem_t *entry; + drm_agp_mem_t *nexte; + + /* Remove AGP resources, but leave dev->agp + intact until cleanup is called. */ + for (entry = dev->agp->memory; entry; entry = nexte) { + nexte = entry->next; + if (entry->bound) drm_unbind_agp(entry->memory); + drm_free_agp(entry->memory, entry->pages); + drm_free(entry, sizeof(*entry), DRM_MEM_AGPLISTS); + } + dev->agp->memory = NULL; + + if (dev->agp->acquired) _drm_agp_release(); + + dev->agp->acquired = 0; + dev->agp->enabled = 0; + } + /* Clear vma list (only built for debugging) */ + if (dev->vmalist) { + for (vma = dev->vmalist; vma; vma = vma_next) { + vma_next = vma->next; + drm_free(vma, sizeof(*vma), DRM_MEM_VMAS); + } + dev->vmalist = NULL; + } + + /* Clear map area and mtrr information */ + if (dev->maplist) { + for (i = 0; i < dev->map_count; i++) { + map = dev->maplist[i]; + switch (map->type) { + case _DRM_REGISTERS: + case _DRM_FRAME_BUFFER: +#ifdef CONFIG_MTRR + if (map->mtrr >= 0) { + int retcode; + retcode = mtrr_del(map->mtrr, + map->offset, + map->size); + DRM_DEBUG("mtrr_del = %d\n", retcode); + } +#endif + drm_ioremapfree(map->handle, map->size, dev); + break; + case _DRM_SHM: + drm_free_pages((unsigned long)map->handle, + drm_order(map->size) + - PAGE_SHIFT, + DRM_MEM_SAREA); + break; + case _DRM_AGP: + break; + } + drm_free(map, sizeof(*map), DRM_MEM_MAPS); + } + drm_free(dev->maplist, + dev->map_count * sizeof(*dev->maplist), + DRM_MEM_MAPS); + dev->maplist = NULL; + dev->map_count = 0; + } + + if (dev->queuelist) { + for (i = 0; i < dev->queue_count; i++) { + drm_waitlist_destroy(&dev->queuelist[i]->waitlist); + if (dev->queuelist[i]) { + drm_free(dev->queuelist[i], + sizeof(*dev->queuelist[0]), + DRM_MEM_QUEUES); + dev->queuelist[i] = NULL; + } + } + drm_free(dev->queuelist, + dev->queue_slots * sizeof(*dev->queuelist), + DRM_MEM_QUEUES); + dev->queuelist = NULL; + } + + drm_dma_takedown(dev); + + dev->queue_count = 0; + if (dev->lock.hw_lock) { + dev->lock.hw_lock = NULL; /* SHM removed */ + dev->lock.pid = 0; + wake_up_interruptible(&dev->lock.lock_queue); + } + up(&dev->struct_sem); + + return 0; +} + +/* mga_init is called via init_module at module load time, or via + * linux/init/main.c (this is not currently supported). */ + +static int __init mga_init(void) +{ + int retcode; + drm_device_t *dev = &mga_device; + + DRM_DEBUG("\n"); + + memset((void *)dev, 0, sizeof(*dev)); + dev->count_lock = SPIN_LOCK_UNLOCKED; + sema_init(&dev->struct_sem, 1); + +#ifdef MODULE + drm_parse_options(mga); +#endif + if ((retcode = misc_register(&mga_misc))) { + DRM_ERROR("Cannot register \"%s\"\n", MGA_NAME); + return retcode; + } + dev->device = MKDEV(MISC_MAJOR, mga_misc.minor); + dev->name = MGA_NAME; + + drm_mem_init(); + drm_proc_init(dev); + dev->agp = drm_agp_init(); + if(dev->agp == NULL) { + DRM_INFO("The mga drm module requires the agpgart module" + " to function correctly\nPlease load the agpgart" + " module before you load the mga module\n"); + drm_proc_cleanup(); + misc_deregister(&mga_misc); + mga_takedown(dev); + return -ENOMEM; + } +#ifdef CONFIG_MTRR + dev->agp->agp_mtrr = mtrr_add(dev->agp->agp_info.aper_base, + dev->agp->agp_info.aper_size * 1024 * 1024, + MTRR_TYPE_WRCOMB, + 1); +#endif + if((retcode = drm_ctxbitmap_init(dev))) { + DRM_ERROR("Cannot allocate memory for context bitmap.\n"); + drm_proc_cleanup(); + misc_deregister(&mga_misc); + mga_takedown(dev); + return retcode; + } + + DRM_INFO("Initialized %s %d.%d.%d %s on minor %d\n", + MGA_NAME, + MGA_MAJOR, + MGA_MINOR, + MGA_PATCHLEVEL, + MGA_DATE, + mga_misc.minor); + + return 0; +} + +/* mga_cleanup is called via cleanup_module at module unload time. */ + +static void __exit mga_cleanup(void) +{ + drm_device_t *dev = &mga_device; + + DRM_DEBUG("\n"); + + drm_proc_cleanup(); + if (misc_deregister(&mga_misc)) { + DRM_ERROR("Cannot unload module\n"); + } else { + DRM_INFO("Module unloaded\n"); + } + drm_ctxbitmap_cleanup(dev); +#ifdef CONFIG_MTRR + if(dev->agp && dev->agp->agp_mtrr) { + int retval; + retval = mtrr_del(dev->agp->agp_mtrr, + dev->agp->agp_info.aper_base, + dev->agp->agp_info.aper_size * 1024*1024); + DRM_DEBUG("mtrr_del = %d\n", retval); + } +#endif + + mga_takedown(dev); + if (dev->agp) { + drm_agp_uninit(); + drm_free(dev->agp, sizeof(*dev->agp), DRM_MEM_AGPLISTS); + dev->agp = NULL; + } +} + +module_init(mga_init); +module_exit(mga_cleanup); + + +int mga_version(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_version_t version; + int len; + + if (copy_from_user(&version, + (drm_version_t *)arg, + sizeof(version))) + return -EFAULT; + +#define DRM_COPY(name,value) \ + len = strlen(value); \ + if (len > name##_len) len = name##_len; \ + name##_len = strlen(value); \ + if (len && name) { \ + if (copy_to_user(name, value, len)) \ + return -EFAULT; \ + } + + version.version_major = MGA_MAJOR; + version.version_minor = MGA_MINOR; + version.version_patchlevel = MGA_PATCHLEVEL; + + DRM_COPY(version.name, MGA_NAME); + DRM_COPY(version.date, MGA_DATE); + DRM_COPY(version.desc, MGA_DESC); + + if (copy_to_user((drm_version_t *)arg, + &version, + sizeof(version))) + return -EFAULT; + return 0; +} + +int mga_open(struct inode *inode, struct file *filp) +{ + drm_device_t *dev = &mga_device; + int retcode = 0; + + DRM_DEBUG("open_count = %d\n", dev->open_count); + if (!(retcode = drm_open_helper(inode, filp, dev))) { +#if LINUX_VERSION_CODE < 0x020333 + MOD_INC_USE_COUNT; /* Needed before Linux 2.3.51 */ +#endif + atomic_inc(&dev->total_open); + spin_lock(&dev->count_lock); + if (!dev->open_count++) { + spin_unlock(&dev->count_lock); + return mga_setup(dev); + } + spin_unlock(&dev->count_lock); + } + return retcode; +} + +int mga_release(struct inode *inode, struct file *filp) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev; + int retcode = 0; + + lock_kernel(); + dev = priv->dev; + DRM_DEBUG("pid = %d, device = 0x%x, open_count = %d\n", + current->pid, dev->device, dev->open_count); + + if (dev->lock.hw_lock && _DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock) + && dev->lock.pid == current->pid) { + mga_reclaim_buffers(dev, priv->pid); + DRM_INFO("Process %d dead (ctx %d, d_s = 0x%02lx)\n", + current->pid, + _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock), + dev->dev_private ? + ((drm_mga_private_t *)dev->dev_private) + ->dispatch_status + : 0); + + if (dev->dev_private) + ((drm_mga_private_t *)dev->dev_private) + ->dispatch_status &= MGA_IN_DISPATCH; + + drm_lock_free(dev, + &dev->lock.hw_lock->lock, + _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock)); + } else if (dev->lock.hw_lock) { + /* The lock is required to reclaim buffers */ + DECLARE_WAITQUEUE(entry, current); + add_wait_queue(&dev->lock.lock_queue, &entry); + for (;;) { + current->state = TASK_INTERRUPTIBLE; + if (!dev->lock.hw_lock) { + /* Device has been unregistered */ + retcode = -EINTR; + break; + } + if (drm_lock_take(&dev->lock.hw_lock->lock, + DRM_KERNEL_CONTEXT)) { + dev->lock.pid = priv->pid; + dev->lock.lock_time = jiffies; + atomic_inc(&dev->total_locks); + break; /* Got lock */ + } + /* Contention */ + atomic_inc(&dev->total_sleeps); + schedule(); + if (signal_pending(current)) { + retcode = -ERESTARTSYS; + break; + } + } + current->state = TASK_RUNNING; + remove_wait_queue(&dev->lock.lock_queue, &entry); + if(!retcode) { + mga_reclaim_buffers(dev, priv->pid); + if (dev->dev_private) + ((drm_mga_private_t *)dev->dev_private) + ->dispatch_status &= MGA_IN_DISPATCH; + drm_lock_free(dev, &dev->lock.hw_lock->lock, + DRM_KERNEL_CONTEXT); + } + } + drm_fasync(-1, filp, 0); + + down(&dev->struct_sem); + if (priv->remove_auth_on_close == 1) { + drm_file_t *temp = dev->file_first; + while(temp) { + temp->authenticated = 0; + temp = temp->next; + } + } + if (priv->prev) priv->prev->next = priv->next; + else dev->file_first = priv->next; + if (priv->next) priv->next->prev = priv->prev; + else dev->file_last = priv->prev; + up(&dev->struct_sem); + + drm_free(priv, sizeof(*priv), DRM_MEM_FILES); +#if LINUX_VERSION_CODE < 0x020333 + MOD_DEC_USE_COUNT; /* Needed before Linux 2.3.51 */ +#endif + atomic_inc(&dev->total_close); + spin_lock(&dev->count_lock); + if (!--dev->open_count) { + if (atomic_read(&dev->ioctl_count) || dev->blocked) { + DRM_ERROR("Device busy: %d %d\n", + atomic_read(&dev->ioctl_count), + dev->blocked); + spin_unlock(&dev->count_lock); + unlock_kernel(); + return -EBUSY; + } + spin_unlock(&dev->count_lock); + unlock_kernel(); + return mga_takedown(dev); + } + spin_unlock(&dev->count_lock); + unlock_kernel(); + return retcode; +} + + +/* drm_ioctl is called whenever a process performs an ioctl on /dev/drm. */ + +int mga_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + int nr = DRM_IOCTL_NR(cmd); + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + int retcode = 0; + drm_ioctl_desc_t *ioctl; + drm_ioctl_t *func; + + atomic_inc(&dev->ioctl_count); + atomic_inc(&dev->total_ioctl); + ++priv->ioctl_count; + + if (nr >= MGA_IOCTL_COUNT) { + retcode = -EINVAL; + } else { + ioctl = &mga_ioctls[nr]; + func = ioctl->func; + + if (!func) { + DRM_DEBUG("no function: pid = %d, cmd = 0x%02x," + " nr = 0x%02x, dev 0x%x, auth = %d\n", + current->pid, cmd, nr, dev->device, + priv->authenticated); + retcode = -EINVAL; + } else if ((ioctl->root_only && !capable(CAP_SYS_ADMIN)) + || (ioctl->auth_needed && !priv->authenticated)) { + retcode = -EACCES; + } else { + retcode = (func)(inode, filp, cmd, arg); + } + } + + atomic_dec(&dev->ioctl_count); + return retcode; +} + +int mga_unlock(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_lock_t lock; + + if (copy_from_user(&lock, (drm_lock_t *)arg, sizeof(lock))) + return -EFAULT; + + if (lock.context == DRM_KERNEL_CONTEXT) { + DRM_ERROR("Process %d using kernel context %d\n", + current->pid, lock.context); + return -EINVAL; + } + + atomic_inc(&dev->total_unlocks); + if (_DRM_LOCK_IS_CONT(dev->lock.hw_lock->lock)) + atomic_inc(&dev->total_contends); + drm_lock_transfer(dev, &dev->lock.hw_lock->lock, DRM_KERNEL_CONTEXT); + mga_dma_schedule(dev, 1); + + if (drm_lock_free(dev, &dev->lock.hw_lock->lock, + DRM_KERNEL_CONTEXT)) DRM_ERROR("\n"); + + unblock_all_signals(); + return 0; +} diff -urN linux-2.4.10/drivers/char/drm-4.0/mga_drv.h linux-2.4.10-lia/drivers/char/drm-4.0/mga_drv.h --- linux-2.4.10/drivers/char/drm-4.0/mga_drv.h Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/mga_drv.h Wed Aug 15 20:52:12 2001 @@ -0,0 +1,520 @@ +/* mga_drv.h -- Private header for the Matrox g200/g400 driver -*- linux-c -*- + * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: Rickard E. (Rik) Faith + * Jeff Hartmann + * + */ + +#ifndef _MGA_DRV_H_ +#define _MGA_DRV_H_ + +#define MGA_BUF_IN_USE 0 +#define MGA_BUF_SWAP_PENDING 1 +#define MGA_BUF_FORCE_FIRE 2 +#define MGA_BUF_NEEDS_OVERFLOW 3 + +typedef struct { + long buffer_status; /* long req'd for set_bit() --RR */ + int num_dwords; + int max_dwords; + u32 *current_dma_ptr; + u32 *head; + u32 phys_head; + unsigned int prim_age; + int sec_used; + int idx; +} drm_mga_prim_buf_t; + +typedef struct _drm_mga_freelist { + __volatile__ unsigned int age; + drm_buf_t *buf; + struct _drm_mga_freelist *next; + struct _drm_mga_freelist *prev; +} drm_mga_freelist_t; + +#define MGA_IN_DISPATCH 0 +#define MGA_IN_FLUSH 1 +#define MGA_IN_WAIT 2 +#define MGA_IN_GETBUF 3 + +typedef struct _drm_mga_private { + long dispatch_status; /* long req'd for set_bit() --RR */ + unsigned int next_prim_age; + __volatile__ unsigned int last_prim_age; + int reserved_map_idx; + int buffer_map_idx; + drm_mga_sarea_t *sarea_priv; + int primary_size; + int warp_ucode_size; + int chipset; + unsigned int frontOffset; + unsigned int backOffset; + unsigned int depthOffset; + unsigned int textureOffset; + unsigned int textureSize; + int cpp; + unsigned int stride; + int sgram; + int use_agp; + drm_mga_warp_index_t WarpIndex[MGA_MAX_G400_PIPES]; + unsigned int WarpPipe; + unsigned int vertexsize; + atomic_t pending_bufs; + void *status_page; + unsigned long real_status_page; + u8 *ioremap; + drm_mga_prim_buf_t **prim_bufs; + drm_mga_prim_buf_t *next_prim; + drm_mga_prim_buf_t *last_prim; + drm_mga_prim_buf_t *current_prim; + int current_prim_idx; + drm_mga_freelist_t *head; + drm_mga_freelist_t *tail; + wait_queue_head_t flush_queue; /* Processes waiting until flush */ + wait_queue_head_t wait_queue; /* Processes waiting until interrupt */ + wait_queue_head_t buf_queue; /* Processes waiting for a free buf */ + /* Some validated register values: + */ + u32 mAccess; +} drm_mga_private_t; + + /* mga_drv.c */ +extern int mga_version(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int mga_open(struct inode *inode, struct file *filp); +extern int mga_release(struct inode *inode, struct file *filp); +extern int mga_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int mga_unlock(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); + + /* mga_dma.c */ +extern int mga_dma_schedule(drm_device_t *dev, int locked); +extern int mga_dma(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int mga_irq_install(drm_device_t *dev, int irq); +extern int mga_irq_uninstall(drm_device_t *dev); +extern int mga_control(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int mga_lock(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); + +/* mga_dma_init does init and release */ +extern int mga_dma_init(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int mga_dma_cleanup(drm_device_t *dev); +extern int mga_flush_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern unsigned int mga_create_sync_tag(drm_device_t *dev); +extern drm_buf_t *mga_freelist_get(drm_device_t *dev); +extern int mga_freelist_put(drm_device_t *dev, drm_buf_t *buf); +extern int mga_advance_primary(drm_device_t *dev); +extern void mga_reclaim_buffers(drm_device_t *dev, pid_t pid); + + + /* mga_bufs.c */ +extern int mga_addbufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int mga_infobufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int mga_markbufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int mga_freebufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int mga_mapbufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int mga_addmap(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); + /* mga_state.c */ +extern int mga_clear_bufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int mga_swap_bufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int mga_iload(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int mga_vertex(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int mga_indices(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); + /* mga_context.c */ +extern int mga_resctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int mga_addctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int mga_modctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int mga_getctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int mga_switchctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int mga_newctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int mga_rmctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); + +extern int mga_context_switch(drm_device_t *dev, int old, int new); +extern int mga_context_switch_complete(drm_device_t *dev, int new); + +#define mga_flush_write_combine() mb() + +typedef enum { + TT_GENERAL, + TT_BLIT, + TT_VECTOR, + TT_VERTEX +} transferType_t; + +typedef struct { + drm_mga_freelist_t *my_freelist; + int discard; + int dispatched; +} drm_mga_buf_priv_t; + +#define DWGREG0 0x1c00 +#define DWGREG0_END 0x1dff +#define DWGREG1 0x2c00 +#define DWGREG1_END 0x2dff + +#define ISREG0(r) (r >= DWGREG0 && r <= DWGREG0_END) +#define ADRINDEX0(r) (u8)((r - DWGREG0) >> 2) +#define ADRINDEX1(r) (u8)(((r - DWGREG1) >> 2) | 0x80) +#define ADRINDEX(r) (ISREG0(r) ? ADRINDEX0(r) : ADRINDEX1(r)) + +#define MGA_VERBOSE 0 +#define MGA_NUM_PRIM_BUFS 8 + +#define PRIMLOCALS u8 tempIndex[4]; u32 *dma_ptr; u32 phys_head; \ + int outcount, num_dwords + +#define PRIM_OVERFLOW(dev, dev_priv, length) do { \ + drm_mga_prim_buf_t *tmp_buf = \ + dev_priv->prim_bufs[dev_priv->current_prim_idx]; \ + if( test_bit(MGA_BUF_NEEDS_OVERFLOW, &tmp_buf->buffer_status)) { \ + mga_advance_primary(dev); \ + mga_dma_schedule(dev, 1); \ + tmp_buf = dev_priv->prim_bufs[dev_priv->current_prim_idx]; \ + } else if( tmp_buf->max_dwords - tmp_buf->num_dwords < length || \ + tmp_buf->sec_used > MGA_DMA_BUF_NR/2) { \ + set_bit(MGA_BUF_FORCE_FIRE, &tmp_buf->buffer_status); \ + mga_advance_primary(dev); \ + mga_dma_schedule(dev, 1); \ + tmp_buf = dev_priv->prim_bufs[dev_priv->current_prim_idx]; \ + } \ + if(MGA_VERBOSE) \ + DRM_DEBUG("PRIMGETPTR in %s\n", __FUNCTION__); \ + dma_ptr = tmp_buf->current_dma_ptr; \ + num_dwords = tmp_buf->num_dwords; \ + phys_head = tmp_buf->phys_head; \ + outcount = 0; \ +} while(0) + +#define PRIMGETPTR(dev_priv) do { \ + drm_mga_prim_buf_t *tmp_buf = \ + dev_priv->prim_bufs[dev_priv->current_prim_idx]; \ + if(MGA_VERBOSE) \ + DRM_DEBUG("PRIMGETPTR in %s\n", __FUNCTION__); \ + dma_ptr = tmp_buf->current_dma_ptr; \ + num_dwords = tmp_buf->num_dwords; \ + phys_head = tmp_buf->phys_head; \ + outcount = 0; \ +} while(0) + +#define PRIMPTR(prim_buf) do { \ + if(MGA_VERBOSE) \ + DRM_DEBUG("PRIMPTR in %s\n", __FUNCTION__); \ + dma_ptr = prim_buf->current_dma_ptr; \ + num_dwords = prim_buf->num_dwords; \ + phys_head = prim_buf->phys_head; \ + outcount = 0; \ +} while(0) + +#define PRIMFINISH(prim_buf) do { \ + if (MGA_VERBOSE) { \ + DRM_DEBUG( "PRIMFINISH in %s\n", __FUNCTION__); \ + if (outcount & 3) \ + DRM_DEBUG(" --- truncation\n"); \ + } \ + prim_buf->num_dwords = num_dwords; \ + prim_buf->current_dma_ptr = dma_ptr; \ +} while(0) + +#define PRIMADVANCE(dev_priv) do { \ +drm_mga_prim_buf_t *tmp_buf = \ + dev_priv->prim_bufs[dev_priv->current_prim_idx]; \ + if (MGA_VERBOSE) { \ + DRM_DEBUG("PRIMADVANCE in %s\n", __FUNCTION__); \ + if (outcount & 3) \ + DRM_DEBUG(" --- truncation\n"); \ + } \ + tmp_buf->num_dwords = num_dwords; \ + tmp_buf->current_dma_ptr = dma_ptr; \ +} while (0) + +#define PRIMUPDATE(dev_priv) do { \ + drm_mga_prim_buf_t *tmp_buf = \ + dev_priv->prim_bufs[dev_priv->current_prim_idx]; \ + tmp_buf->sec_used++; \ +} while (0) + +#define AGEBUF(dev_priv, buf_priv) do { \ + drm_mga_prim_buf_t *tmp_buf = \ + dev_priv->prim_bufs[dev_priv->current_prim_idx]; \ + buf_priv->my_freelist->age = tmp_buf->prim_age; \ +} while (0) + + +#define PRIMOUTREG(reg, val) do { \ + tempIndex[outcount]=ADRINDEX(reg); \ + dma_ptr[1+outcount] = val; \ + if (MGA_VERBOSE) \ + DRM_DEBUG(" PRIMOUT %d: 0x%x -- 0x%x\n", \ + num_dwords + 1 + outcount, ADRINDEX(reg), val); \ + if( ++outcount == 4) { \ + outcount = 0; \ + dma_ptr[0] = *(u32 *)tempIndex; \ + dma_ptr+=5; \ + num_dwords += 5; \ + } \ +}while (0) + +/* A reduced set of the mga registers. + */ + +#define MGAREG_MGA_EXEC 0x0100 +#define MGAREG_ALPHACTRL 0x2c7c +#define MGAREG_AR0 0x1c60 +#define MGAREG_AR1 0x1c64 +#define MGAREG_AR2 0x1c68 +#define MGAREG_AR3 0x1c6c +#define MGAREG_AR4 0x1c70 +#define MGAREG_AR5 0x1c74 +#define MGAREG_AR6 0x1c78 +#define MGAREG_CXBNDRY 0x1c80 +#define MGAREG_CXLEFT 0x1ca0 +#define MGAREG_CXRIGHT 0x1ca4 +#define MGAREG_DMAPAD 0x1c54 +#define MGAREG_DSTORG 0x2cb8 +#define MGAREG_DWGCTL 0x1c00 +#define MGAREG_DWGSYNC 0x2c4c +#define MGAREG_FCOL 0x1c24 +#define MGAREG_FIFOSTATUS 0x1e10 +#define MGAREG_FOGCOL 0x1cf4 +#define MGAREG_FXBNDRY 0x1c84 +#define MGAREG_FXLEFT 0x1ca8 +#define MGAREG_FXRIGHT 0x1cac +#define MGAREG_ICLEAR 0x1e18 +#define MGAREG_IEN 0x1e1c +#define MGAREG_LEN 0x1c5c +#define MGAREG_MACCESS 0x1c04 +#define MGAREG_PITCH 0x1c8c +#define MGAREG_PLNWT 0x1c1c +#define MGAREG_PRIMADDRESS 0x1e58 +#define MGAREG_PRIMEND 0x1e5c +#define MGAREG_PRIMPTR 0x1e50 +#define MGAREG_SECADDRESS 0x2c40 +#define MGAREG_SECEND 0x2c44 +#define MGAREG_SETUPADDRESS 0x2cd0 +#define MGAREG_SETUPEND 0x2cd4 +#define MGAREG_SOFTRAP 0x2c48 +#define MGAREG_SRCORG 0x2cb4 +#define MGAREG_STATUS 0x1e14 +#define MGAREG_STENCIL 0x2cc8 +#define MGAREG_STENCILCTL 0x2ccc +#define MGAREG_TDUALSTAGE0 0x2cf8 +#define MGAREG_TDUALSTAGE1 0x2cfc +#define MGAREG_TEXBORDERCOL 0x2c5c +#define MGAREG_TEXCTL 0x2c30 +#define MGAREG_TEXCTL2 0x2c3c +#define MGAREG_TEXFILTER 0x2c58 +#define MGAREG_TEXHEIGHT 0x2c2c +#define MGAREG_TEXORG 0x2c24 +#define MGAREG_TEXORG1 0x2ca4 +#define MGAREG_TEXORG2 0x2ca8 +#define MGAREG_TEXORG3 0x2cac +#define MGAREG_TEXORG4 0x2cb0 +#define MGAREG_TEXTRANS 0x2c34 +#define MGAREG_TEXTRANSHIGH 0x2c38 +#define MGAREG_TEXWIDTH 0x2c28 +#define MGAREG_WACCEPTSEQ 0x1dd4 +#define MGAREG_WCODEADDR 0x1e6c +#define MGAREG_WFLAG 0x1dc4 +#define MGAREG_WFLAG1 0x1de0 +#define MGAREG_WFLAGNB 0x1e64 +#define MGAREG_WFLAGNB1 0x1e08 +#define MGAREG_WGETMSB 0x1dc8 +#define MGAREG_WIADDR 0x1dc0 +#define MGAREG_WIADDR2 0x1dd8 +#define MGAREG_WMISC 0x1e70 +#define MGAREG_WVRTXSZ 0x1dcc +#define MGAREG_YBOT 0x1c9c +#define MGAREG_YDST 0x1c90 +#define MGAREG_YDSTLEN 0x1c88 +#define MGAREG_YDSTORG 0x1c94 +#define MGAREG_YTOP 0x1c98 +#define MGAREG_ZORG 0x1c0c + +/* Warp registers */ +#define MGAREG_WR0 0x2d00 +#define MGAREG_WR1 0x2d04 +#define MGAREG_WR2 0x2d08 +#define MGAREG_WR3 0x2d0c +#define MGAREG_WR4 0x2d10 +#define MGAREG_WR5 0x2d14 +#define MGAREG_WR6 0x2d18 +#define MGAREG_WR7 0x2d1c +#define MGAREG_WR8 0x2d20 +#define MGAREG_WR9 0x2d24 +#define MGAREG_WR10 0x2d28 +#define MGAREG_WR11 0x2d2c +#define MGAREG_WR12 0x2d30 +#define MGAREG_WR13 0x2d34 +#define MGAREG_WR14 0x2d38 +#define MGAREG_WR15 0x2d3c +#define MGAREG_WR16 0x2d40 +#define MGAREG_WR17 0x2d44 +#define MGAREG_WR18 0x2d48 +#define MGAREG_WR19 0x2d4c +#define MGAREG_WR20 0x2d50 +#define MGAREG_WR21 0x2d54 +#define MGAREG_WR22 0x2d58 +#define MGAREG_WR23 0x2d5c +#define MGAREG_WR24 0x2d60 +#define MGAREG_WR25 0x2d64 +#define MGAREG_WR26 0x2d68 +#define MGAREG_WR27 0x2d6c +#define MGAREG_WR28 0x2d70 +#define MGAREG_WR29 0x2d74 +#define MGAREG_WR30 0x2d78 +#define MGAREG_WR31 0x2d7c +#define MGAREG_WR32 0x2d80 +#define MGAREG_WR33 0x2d84 +#define MGAREG_WR34 0x2d88 +#define MGAREG_WR35 0x2d8c +#define MGAREG_WR36 0x2d90 +#define MGAREG_WR37 0x2d94 +#define MGAREG_WR38 0x2d98 +#define MGAREG_WR39 0x2d9c +#define MGAREG_WR40 0x2da0 +#define MGAREG_WR41 0x2da4 +#define MGAREG_WR42 0x2da8 +#define MGAREG_WR43 0x2dac +#define MGAREG_WR44 0x2db0 +#define MGAREG_WR45 0x2db4 +#define MGAREG_WR46 0x2db8 +#define MGAREG_WR47 0x2dbc +#define MGAREG_WR48 0x2dc0 +#define MGAREG_WR49 0x2dc4 +#define MGAREG_WR50 0x2dc8 +#define MGAREG_WR51 0x2dcc +#define MGAREG_WR52 0x2dd0 +#define MGAREG_WR53 0x2dd4 +#define MGAREG_WR54 0x2dd8 +#define MGAREG_WR55 0x2ddc +#define MGAREG_WR56 0x2de0 +#define MGAREG_WR57 0x2de4 +#define MGAREG_WR58 0x2de8 +#define MGAREG_WR59 0x2dec +#define MGAREG_WR60 0x2df0 +#define MGAREG_WR61 0x2df4 +#define MGAREG_WR62 0x2df8 +#define MGAREG_WR63 0x2dfc + +#define PDEA_pagpxfer_enable 0x2 + +#define WIA_wmode_suspend 0x0 +#define WIA_wmode_start 0x3 +#define WIA_wagp_agp 0x4 + +#define DC_opcod_line_open 0x0 +#define DC_opcod_autoline_open 0x1 +#define DC_opcod_line_close 0x2 +#define DC_opcod_autoline_close 0x3 +#define DC_opcod_trap 0x4 +#define DC_opcod_texture_trap 0x6 +#define DC_opcod_bitblt 0x8 +#define DC_opcod_iload 0x9 +#define DC_atype_rpl 0x0 +#define DC_atype_rstr 0x10 +#define DC_atype_zi 0x30 +#define DC_atype_blk 0x40 +#define DC_atype_i 0x70 +#define DC_linear_xy 0x0 +#define DC_linear_linear 0x80 +#define DC_zmode_nozcmp 0x0 +#define DC_zmode_ze 0x200 +#define DC_zmode_zne 0x300 +#define DC_zmode_zlt 0x400 +#define DC_zmode_zlte 0x500 +#define DC_zmode_zgt 0x600 +#define DC_zmode_zgte 0x700 +#define DC_solid_disable 0x0 +#define DC_solid_enable 0x800 +#define DC_arzero_disable 0x0 +#define DC_arzero_enable 0x1000 +#define DC_sgnzero_disable 0x0 +#define DC_sgnzero_enable 0x2000 +#define DC_shftzero_disable 0x0 +#define DC_shftzero_enable 0x4000 +#define DC_bop_SHIFT 16 +#define DC_trans_SHIFT 20 +#define DC_bltmod_bmonolef 0x0 +#define DC_bltmod_bmonowf 0x8000000 +#define DC_bltmod_bplan 0x2000000 +#define DC_bltmod_bfcol 0x4000000 +#define DC_bltmod_bu32bgr 0x6000000 +#define DC_bltmod_bu32rgb 0xe000000 +#define DC_bltmod_bu24bgr 0x16000000 +#define DC_bltmod_bu24rgb 0x1e000000 +#define DC_pattern_disable 0x0 +#define DC_pattern_enable 0x20000000 +#define DC_transc_disable 0x0 +#define DC_transc_enable 0x40000000 +#define DC_clipdis_disable 0x0 +#define DC_clipdis_enable 0x80000000 + + +#define SETADD_mode_vertlist 0x0 + + +#define MGA_CLEAR_CMD (DC_opcod_trap | DC_arzero_enable | \ + DC_sgnzero_enable | DC_shftzero_enable | \ + (0xC << DC_bop_SHIFT) | DC_clipdis_enable | \ + DC_solid_enable | DC_transc_enable) + + +#define MGA_COPY_CMD (DC_opcod_bitblt | DC_atype_rpl | DC_linear_xy | \ + DC_solid_disable | DC_arzero_disable | \ + DC_sgnzero_enable | DC_shftzero_enable | \ + (0xC << DC_bop_SHIFT) | DC_bltmod_bfcol | \ + DC_pattern_disable | DC_transc_disable | \ + DC_clipdis_enable) \ + +#define MGA_FLUSH_CMD (DC_opcod_texture_trap | (0xF << DC_trans_SHIFT) |\ + DC_arzero_enable | DC_sgnzero_enable | \ + DC_atype_i) + +#endif diff -urN linux-2.4.10/drivers/char/drm-4.0/mga_state.c linux-2.4.10-lia/drivers/char/drm-4.0/mga_state.c --- linux-2.4.10/drivers/char/drm-4.0/mga_state.c Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/mga_state.c Wed Aug 15 20:52:12 2001 @@ -0,0 +1,1017 @@ +/* mga_state.c -- State support for mga g200/g400 -*- linux-c -*- + * Created: Thu Jan 27 02:53:43 2000 by jhartmann@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: Jeff Hartmann + * Keith Whitwell + * + */ + +#define __NO_VERSION__ +#include "drmP.h" +#include "mga_drv.h" +#include "drm.h" + +/* If you change the functions to set state, PLEASE + * change these values + */ + +#define MGAEMITCLIP_SIZE 10 +#define MGAEMITCTX_SIZE 20 +#define MGAG200EMITTEX_SIZE 20 +#define MGAG400EMITTEX0_SIZE 30 +#define MGAG400EMITTEX1_SIZE 25 +#define MGAG400EMITPIPE_SIZE 50 +#define MGAG200EMITPIPE_SIZE 15 + +#define MAX_STATE_SIZE ((MGAEMITCLIP_SIZE * MGA_NR_SAREA_CLIPRECTS) + \ + MGAEMITCTX_SIZE + MGAG400EMITTEX0_SIZE + \ + MGAG400EMITTEX1_SIZE + MGAG400EMITPIPE_SIZE) + +static void mgaEmitClipRect(drm_mga_private_t * dev_priv, + drm_clip_rect_t * box) +{ + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + unsigned int *regs = sarea_priv->ContextState; + PRIMLOCALS; + + /* This takes 10 dwords */ + PRIMGETPTR(dev_priv); + + /* Force reset of dwgctl on G400 (eliminates clip disable bit) */ + if (dev_priv->chipset == MGA_CARD_TYPE_G400) { +#if 0 + PRIMOUTREG(MGAREG_DMAPAD, 0); + PRIMOUTREG(MGAREG_DWGSYNC, 0); + PRIMOUTREG(MGAREG_DWGSYNC, 0); + PRIMOUTREG(MGAREG_DWGCTL, regs[MGA_CTXREG_DWGCTL]); +#else + PRIMOUTREG(MGAREG_DWGCTL, regs[MGA_CTXREG_DWGCTL]); + PRIMOUTREG(MGAREG_LEN + MGAREG_MGA_EXEC, 0x80000000); + PRIMOUTREG(MGAREG_DWGCTL, regs[MGA_CTXREG_DWGCTL]); + PRIMOUTREG(MGAREG_LEN + MGAREG_MGA_EXEC, 0x80000000); +#endif + } + PRIMOUTREG(MGAREG_DMAPAD, 0); + PRIMOUTREG(MGAREG_CXBNDRY, ((box->x2) << 16) | (box->x1)); + PRIMOUTREG(MGAREG_YTOP, box->y1 * dev_priv->stride / dev_priv->cpp); + PRIMOUTREG(MGAREG_YBOT, box->y2 * dev_priv->stride / dev_priv->cpp); + + PRIMADVANCE(dev_priv); +} + +static void mgaEmitContext(drm_mga_private_t * dev_priv) +{ + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + unsigned int *regs = sarea_priv->ContextState; + PRIMLOCALS; + + /* This takes a max of 20 dwords */ + PRIMGETPTR(dev_priv); + + PRIMOUTREG(MGAREG_DSTORG, regs[MGA_CTXREG_DSTORG]); + PRIMOUTREG(MGAREG_MACCESS, regs[MGA_CTXREG_MACCESS]); + PRIMOUTREG(MGAREG_PLNWT, regs[MGA_CTXREG_PLNWT]); + PRIMOUTREG(MGAREG_DWGCTL, regs[MGA_CTXREG_DWGCTL]); + + PRIMOUTREG(MGAREG_ALPHACTRL, regs[MGA_CTXREG_ALPHACTRL]); + PRIMOUTREG(MGAREG_FOGCOL, regs[MGA_CTXREG_FOGCOLOR]); + PRIMOUTREG(MGAREG_WFLAG, regs[MGA_CTXREG_WFLAG]); + PRIMOUTREG(MGAREG_ZORG, dev_priv->depthOffset); /* invarient */ + + if (dev_priv->chipset == MGA_CARD_TYPE_G400) { + PRIMOUTREG(MGAREG_WFLAG1, regs[MGA_CTXREG_WFLAG]); + PRIMOUTREG(MGAREG_TDUALSTAGE0, regs[MGA_CTXREG_TDUAL0]); + PRIMOUTREG(MGAREG_TDUALSTAGE1, regs[MGA_CTXREG_TDUAL1]); + PRIMOUTREG(MGAREG_FCOL, regs[MGA_CTXREG_FCOL]); + + PRIMOUTREG(MGAREG_STENCIL, regs[MGA_CTXREG_STENCIL]); + PRIMOUTREG(MGAREG_STENCILCTL, regs[MGA_CTXREG_STENCILCTL]); + PRIMOUTREG(MGAREG_DMAPAD, 0); + PRIMOUTREG(MGAREG_DMAPAD, 0); + } else { + PRIMOUTREG(MGAREG_FCOL, regs[MGA_CTXREG_FCOL]); + PRIMOUTREG(MGAREG_DMAPAD, 0); + PRIMOUTREG(MGAREG_DMAPAD, 0); + PRIMOUTREG(MGAREG_DMAPAD, 0); + } + + PRIMADVANCE(dev_priv); +} + +static void mgaG200EmitTex(drm_mga_private_t * dev_priv) +{ + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + unsigned int *regs = sarea_priv->TexState[0]; + PRIMLOCALS; + + PRIMGETPTR(dev_priv); + + /* This takes 20 dwords */ + + PRIMOUTREG(MGAREG_TEXCTL2, regs[MGA_TEXREG_CTL2]); + PRIMOUTREG(MGAREG_TEXCTL, regs[MGA_TEXREG_CTL]); + PRIMOUTREG(MGAREG_TEXFILTER, regs[MGA_TEXREG_FILTER]); + PRIMOUTREG(MGAREG_TEXBORDERCOL, regs[MGA_TEXREG_BORDERCOL]); + + PRIMOUTREG(MGAREG_TEXORG, regs[MGA_TEXREG_ORG]); + PRIMOUTREG(MGAREG_TEXORG1, regs[MGA_TEXREG_ORG1]); + PRIMOUTREG(MGAREG_TEXORG2, regs[MGA_TEXREG_ORG2]); + PRIMOUTREG(MGAREG_TEXORG3, regs[MGA_TEXREG_ORG3]); + + PRIMOUTREG(MGAREG_TEXORG4, regs[MGA_TEXREG_ORG4]); + PRIMOUTREG(MGAREG_TEXWIDTH, regs[MGA_TEXREG_WIDTH]); + PRIMOUTREG(MGAREG_TEXHEIGHT, regs[MGA_TEXREG_HEIGHT]); + PRIMOUTREG(MGAREG_WR24, regs[MGA_TEXREG_WIDTH]); + + PRIMOUTREG(MGAREG_WR34, regs[MGA_TEXREG_HEIGHT]); + PRIMOUTREG(MGAREG_TEXTRANS, 0xffff); + PRIMOUTREG(MGAREG_TEXTRANSHIGH, 0xffff); + PRIMOUTREG(MGAREG_DMAPAD, 0); + + PRIMADVANCE(dev_priv); +} + +#define TMC_dualtex_enable 0x80 + +static void mgaG400EmitTex0(drm_mga_private_t * dev_priv) +{ + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + unsigned int *regs = sarea_priv->TexState[0]; + PRIMLOCALS; + + PRIMGETPTR(dev_priv); + + /* This takes 30 dwords */ + + PRIMOUTREG(MGAREG_TEXCTL2, regs[MGA_TEXREG_CTL2] | 0x00008000); + PRIMOUTREG(MGAREG_TEXCTL, regs[MGA_TEXREG_CTL]); + PRIMOUTREG(MGAREG_TEXFILTER, regs[MGA_TEXREG_FILTER]); + PRIMOUTREG(MGAREG_TEXBORDERCOL, regs[MGA_TEXREG_BORDERCOL]); + + PRIMOUTREG(MGAREG_TEXORG, regs[MGA_TEXREG_ORG]); + PRIMOUTREG(MGAREG_TEXORG1, regs[MGA_TEXREG_ORG1]); + PRIMOUTREG(MGAREG_TEXORG2, regs[MGA_TEXREG_ORG2]); + PRIMOUTREG(MGAREG_TEXORG3, regs[MGA_TEXREG_ORG3]); + + PRIMOUTREG(MGAREG_TEXORG4, regs[MGA_TEXREG_ORG4]); + PRIMOUTREG(MGAREG_TEXWIDTH, regs[MGA_TEXREG_WIDTH]); + PRIMOUTREG(MGAREG_TEXHEIGHT, regs[MGA_TEXREG_HEIGHT]); + PRIMOUTREG(MGAREG_WR49, 0); + + PRIMOUTREG(MGAREG_WR57, 0); + PRIMOUTREG(MGAREG_WR53, 0); + PRIMOUTREG(MGAREG_WR61, 0); + PRIMOUTREG(MGAREG_WR52, 0x40); + + PRIMOUTREG(MGAREG_WR60, 0x40); + PRIMOUTREG(MGAREG_WR54, regs[MGA_TEXREG_WIDTH] | 0x40); + PRIMOUTREG(MGAREG_WR62, regs[MGA_TEXREG_HEIGHT] | 0x40); + PRIMOUTREG(MGAREG_DMAPAD, 0); + + PRIMOUTREG(MGAREG_DMAPAD, 0); + PRIMOUTREG(MGAREG_DMAPAD, 0); + PRIMOUTREG(MGAREG_TEXTRANS, 0xffff); + PRIMOUTREG(MGAREG_TEXTRANSHIGH, 0xffff); + + PRIMADVANCE(dev_priv); +} + +#define TMC_map1_enable 0x80000000 + +static void mgaG400EmitTex1(drm_mga_private_t * dev_priv) +{ + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + unsigned int *regs = sarea_priv->TexState[1]; + PRIMLOCALS; + + PRIMGETPTR(dev_priv); + + /* This takes 25 dwords */ + + PRIMOUTREG(MGAREG_TEXCTL2, + regs[MGA_TEXREG_CTL2] | TMC_map1_enable | 0x00008000); + PRIMOUTREG(MGAREG_TEXCTL, regs[MGA_TEXREG_CTL]); + PRIMOUTREG(MGAREG_TEXFILTER, regs[MGA_TEXREG_FILTER]); + PRIMOUTREG(MGAREG_TEXBORDERCOL, regs[MGA_TEXREG_BORDERCOL]); + + PRIMOUTREG(MGAREG_TEXORG, regs[MGA_TEXREG_ORG]); + PRIMOUTREG(MGAREG_TEXORG1, regs[MGA_TEXREG_ORG1]); + PRIMOUTREG(MGAREG_TEXORG2, regs[MGA_TEXREG_ORG2]); + PRIMOUTREG(MGAREG_TEXORG3, regs[MGA_TEXREG_ORG3]); + + PRIMOUTREG(MGAREG_TEXORG4, regs[MGA_TEXREG_ORG4]); + PRIMOUTREG(MGAREG_TEXWIDTH, regs[MGA_TEXREG_WIDTH]); + PRIMOUTREG(MGAREG_TEXHEIGHT, regs[MGA_TEXREG_HEIGHT]); + PRIMOUTREG(MGAREG_WR49, 0); + + PRIMOUTREG(MGAREG_WR57, 0); + PRIMOUTREG(MGAREG_WR53, 0); + PRIMOUTREG(MGAREG_WR61, 0); + PRIMOUTREG(MGAREG_WR52, regs[MGA_TEXREG_WIDTH] | 0x40); + + PRIMOUTREG(MGAREG_WR60, regs[MGA_TEXREG_HEIGHT] | 0x40); + PRIMOUTREG(MGAREG_TEXTRANS, 0xffff); + PRIMOUTREG(MGAREG_TEXTRANSHIGH, 0xffff); + PRIMOUTREG(MGAREG_TEXCTL2, regs[MGA_TEXREG_CTL2] | 0x00008000); + + PRIMADVANCE(dev_priv); +} + +#define MAGIC_FPARAM_HEX_VALUE 0x46480000 +/* This is the hex value of 12800.0f which is a magic value we must + * set in wr56. + */ + +static void mgaG400EmitPipe(drm_mga_private_t * dev_priv) +{ + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + unsigned int pipe = sarea_priv->WarpPipe; + PRIMLOCALS; + + PRIMGETPTR(dev_priv); + + /* This takes 50 dwords */ + + /* Establish vertex size. + */ + PRIMOUTREG(MGAREG_WIADDR2, WIA_wmode_suspend); + PRIMOUTREG(MGAREG_DMAPAD, 0); + PRIMOUTREG(MGAREG_DMAPAD, 0); + PRIMOUTREG(MGAREG_DMAPAD, 0); + + if (pipe & MGA_T2) { + PRIMOUTREG(MGAREG_WVRTXSZ, 0x00001e09); + PRIMOUTREG(MGAREG_DMAPAD, 0); + PRIMOUTREG(MGAREG_DMAPAD, 0); + PRIMOUTREG(MGAREG_DMAPAD, 0); + + PRIMOUTREG(MGAREG_WACCEPTSEQ, 0); + PRIMOUTREG(MGAREG_WACCEPTSEQ, 0); + PRIMOUTREG(MGAREG_WACCEPTSEQ, 0); + PRIMOUTREG(MGAREG_WACCEPTSEQ, 0x1e000000); + } else { + if (dev_priv->WarpPipe & MGA_T2) { + /* Flush the WARP pipe */ + PRIMOUTREG(MGAREG_YDST, 0); + PRIMOUTREG(MGAREG_FXLEFT, 0); + PRIMOUTREG(MGAREG_FXRIGHT, 1); + PRIMOUTREG(MGAREG_DWGCTL, MGA_FLUSH_CMD); + + PRIMOUTREG(MGAREG_LEN + MGAREG_MGA_EXEC, 1); + PRIMOUTREG(MGAREG_DWGSYNC, 0x7000); + PRIMOUTREG(MGAREG_TEXCTL2, 0x00008000); + PRIMOUTREG(MGAREG_LEN + MGAREG_MGA_EXEC, 0); + + PRIMOUTREG(MGAREG_TEXCTL2, 0x80 | 0x00008000); + PRIMOUTREG(MGAREG_LEN + MGAREG_MGA_EXEC, 0); + PRIMOUTREG(MGAREG_TEXCTL2, 0x00008000); + PRIMOUTREG(MGAREG_DMAPAD, 0); + } + + PRIMOUTREG(MGAREG_WVRTXSZ, 0x00001807); + PRIMOUTREG(MGAREG_DMAPAD, 0); + PRIMOUTREG(MGAREG_DMAPAD, 0); + PRIMOUTREG(MGAREG_DMAPAD, 0); + + PRIMOUTREG(MGAREG_WACCEPTSEQ, 0); + PRIMOUTREG(MGAREG_WACCEPTSEQ, 0); + PRIMOUTREG(MGAREG_WACCEPTSEQ, 0); + PRIMOUTREG(MGAREG_WACCEPTSEQ, 0x18000000); + } + + PRIMOUTREG(MGAREG_WFLAG, 0); + PRIMOUTREG(MGAREG_WFLAG1, 0); + PRIMOUTREG(MGAREG_WR56, MAGIC_FPARAM_HEX_VALUE); + PRIMOUTREG(MGAREG_DMAPAD, 0); + + PRIMOUTREG(MGAREG_WR49, 0); /* Tex stage 0 */ + PRIMOUTREG(MGAREG_WR57, 0); /* Tex stage 0 */ + PRIMOUTREG(MGAREG_WR53, 0); /* Tex stage 1 */ + PRIMOUTREG(MGAREG_WR61, 0); /* Tex stage 1 */ + + PRIMOUTREG(MGAREG_WR54, 0x40); /* Tex stage 0 : w */ + PRIMOUTREG(MGAREG_WR62, 0x40); /* Tex stage 0 : h */ + PRIMOUTREG(MGAREG_WR52, 0x40); /* Tex stage 1 : w */ + PRIMOUTREG(MGAREG_WR60, 0x40); /* Tex stage 1 : h */ + + /* Dma pading required due to hw bug */ + PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff); + PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff); + PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff); + PRIMOUTREG(MGAREG_WIADDR2, + (u32) (dev_priv->WarpIndex[pipe]. + phys_addr | WIA_wmode_start | WIA_wagp_agp)); + PRIMADVANCE(dev_priv); +} + +static void mgaG200EmitPipe(drm_mga_private_t * dev_priv) +{ + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + unsigned int pipe = sarea_priv->WarpPipe; + PRIMLOCALS; + + PRIMGETPTR(dev_priv); + + /* This takes 15 dwords */ + + PRIMOUTREG(MGAREG_WIADDR, WIA_wmode_suspend); + PRIMOUTREG(MGAREG_WVRTXSZ, 7); + PRIMOUTREG(MGAREG_WFLAG, 0); + PRIMOUTREG(MGAREG_WR24, 0); /* tex w/h */ + + PRIMOUTREG(MGAREG_WR25, 0x100); + PRIMOUTREG(MGAREG_WR34, 0); /* tex w/h */ + PRIMOUTREG(MGAREG_WR42, 0xFFFF); + PRIMOUTREG(MGAREG_WR60, 0xFFFF); + + /* Dma pading required due to hw bug */ + PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff); + PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff); + PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff); + PRIMOUTREG(MGAREG_WIADDR, + (u32) (dev_priv->WarpIndex[pipe]. + phys_addr | WIA_wmode_start | WIA_wagp_agp)); + + PRIMADVANCE( dev_priv ); +} + +static void mgaEmitState(drm_mga_private_t * dev_priv) +{ + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + unsigned int dirty = sarea_priv->dirty; + + if (dev_priv->chipset == MGA_CARD_TYPE_G400) { + int multitex = sarea_priv->WarpPipe & MGA_T2; + + if (sarea_priv->WarpPipe != dev_priv->WarpPipe) { + mgaG400EmitPipe(dev_priv); + dev_priv->WarpPipe = sarea_priv->WarpPipe; + } + + if (dirty & MGA_UPLOAD_CTX) { + mgaEmitContext(dev_priv); + sarea_priv->dirty &= ~MGA_UPLOAD_CTX; + } + + if (dirty & MGA_UPLOAD_TEX0) { + mgaG400EmitTex0(dev_priv); + sarea_priv->dirty &= ~MGA_UPLOAD_TEX0; + } + + if ((dirty & MGA_UPLOAD_TEX1) && multitex) { + mgaG400EmitTex1(dev_priv); + sarea_priv->dirty &= ~MGA_UPLOAD_TEX1; + } + } else { + if (sarea_priv->WarpPipe != dev_priv->WarpPipe) { + mgaG200EmitPipe(dev_priv); + dev_priv->WarpPipe = sarea_priv->WarpPipe; + } + + if (dirty & MGA_UPLOAD_CTX) { + mgaEmitContext(dev_priv); + sarea_priv->dirty &= ~MGA_UPLOAD_CTX; + } + + if (dirty & MGA_UPLOAD_TEX0) { + mgaG200EmitTex(dev_priv); + sarea_priv->dirty &= ~MGA_UPLOAD_TEX0; + } + } +} + +/* Disallow all write destinations except the front and backbuffer. + */ +static int mgaVerifyContext(drm_mga_private_t * dev_priv) +{ + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + unsigned int *regs = sarea_priv->ContextState; + + if (regs[MGA_CTXREG_DSTORG] != dev_priv->frontOffset && + regs[MGA_CTXREG_DSTORG] != dev_priv->backOffset) { + DRM_DEBUG("BAD DSTORG: %x (front %x, back %x)\n\n", + regs[MGA_CTXREG_DSTORG], dev_priv->frontOffset, + dev_priv->backOffset); + regs[MGA_CTXREG_DSTORG] = 0; + return -1; + } + + return 0; +} + +/* Disallow texture reads from PCI space. + */ +static int mgaVerifyTex(drm_mga_private_t * dev_priv, int unit) +{ + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + + if ((sarea_priv->TexState[unit][MGA_TEXREG_ORG] & 0x3) == 0x1) { + DRM_DEBUG("BAD TEXREG_ORG: %x, unit %d\n", + sarea_priv->TexState[unit][MGA_TEXREG_ORG], + unit); + sarea_priv->TexState[unit][MGA_TEXREG_ORG] = 0; + return -1; + } + + return 0; +} + +static int mgaVerifyState(drm_mga_private_t * dev_priv) +{ + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + unsigned int dirty = sarea_priv->dirty; + int rv = 0; + + if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS) + sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS; + + if (dirty & MGA_UPLOAD_CTX) + rv |= mgaVerifyContext(dev_priv); + + if (dirty & MGA_UPLOAD_TEX0) + rv |= mgaVerifyTex(dev_priv, 0); + + if (dev_priv->chipset == MGA_CARD_TYPE_G400) { + if (dirty & MGA_UPLOAD_TEX1) + rv |= mgaVerifyTex(dev_priv, 1); + + if (dirty & MGA_UPLOAD_PIPE) + rv |= (sarea_priv->WarpPipe > MGA_MAX_G400_PIPES); + } else { + if (dirty & MGA_UPLOAD_PIPE) + rv |= (sarea_priv->WarpPipe > MGA_MAX_G200_PIPES); + } + + return rv == 0; +} + +static int mgaVerifyIload(drm_mga_private_t * dev_priv, + unsigned long bus_address, + unsigned int dstOrg, int length) +{ + if (dstOrg < dev_priv->textureOffset || + dstOrg + length > + (dev_priv->textureOffset + dev_priv->textureSize)) { + return -EINVAL; + } + if (length % 64) { + return -EINVAL; + } + return 0; +} + +/* This copies a 64 byte aligned agp region to the frambuffer + * with a standard blit, the ioctl needs to do checking */ + +static void mga_dma_dispatch_tex_blit(drm_device_t * dev, + unsigned long bus_address, + int length, unsigned int destOrg) +{ + drm_mga_private_t *dev_priv = dev->dev_private; + int use_agp = PDEA_pagpxfer_enable | 0x00000001; + u16 y2; + PRIMLOCALS; + + y2 = length / 64; + + PRIM_OVERFLOW(dev, dev_priv, 30); + + PRIMOUTREG(MGAREG_DSTORG, destOrg); + PRIMOUTREG(MGAREG_MACCESS, 0x00000000); + PRIMOUTREG(MGAREG_SRCORG, (u32) bus_address | use_agp); + PRIMOUTREG(MGAREG_AR5, 64); + + PRIMOUTREG(MGAREG_PITCH, 64); + PRIMOUTREG(MGAREG_DMAPAD, 0); + PRIMOUTREG(MGAREG_DMAPAD, 0); + PRIMOUTREG(MGAREG_DWGCTL, MGA_COPY_CMD); + + PRIMOUTREG(MGAREG_AR0, 63); + PRIMOUTREG(MGAREG_AR3, 0); + PRIMOUTREG(MGAREG_FXBNDRY, (63 << 16)); + PRIMOUTREG(MGAREG_YDSTLEN + MGAREG_MGA_EXEC, y2); + + PRIMOUTREG(MGAREG_DMAPAD, 0); + PRIMOUTREG(MGAREG_SRCORG, 0); + PRIMOUTREG(MGAREG_PITCH, dev_priv->stride / dev_priv->cpp); + PRIMOUTREG(MGAREG_DWGSYNC, 0x7000); + PRIMADVANCE(dev_priv); +} + +static void mga_dma_dispatch_vertex(drm_device_t * dev, drm_buf_t * buf) +{ + drm_mga_private_t *dev_priv = dev->dev_private; + drm_mga_buf_priv_t *buf_priv = buf->dev_private; + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + unsigned long address = (unsigned long) buf->bus_address; + int length = buf->used; + int use_agp = PDEA_pagpxfer_enable; + int i = 0; + PRIMLOCALS; + + if (buf->used) { + /* WARNING: if you change any of the state functions verify + * these numbers (Overestimating this doesn't hurt). + */ + buf_priv->dispatched = 1; + PRIM_OVERFLOW(dev, dev_priv, + (MAX_STATE_SIZE + (5 * MGA_NR_SAREA_CLIPRECTS))); + mgaEmitState(dev_priv); + +#if 0 + length = dev_priv->vertexsize * 3 * 4; +#endif + + do { + if (i < sarea_priv->nbox) { + mgaEmitClipRect(dev_priv, + &sarea_priv->boxes[i]); + } + + PRIMGETPTR(dev_priv); + PRIMOUTREG(MGAREG_DMAPAD, 0); + PRIMOUTREG(MGAREG_DMAPAD, 0); + PRIMOUTREG(MGAREG_SECADDRESS, + ((u32) address) | TT_VERTEX); + PRIMOUTREG(MGAREG_SECEND, + (((u32) (address + length)) | use_agp)); + PRIMADVANCE(dev_priv); + } while (++i < sarea_priv->nbox); + } + if (buf_priv->discard) { + if (buf_priv->dispatched == 1) + AGEBUF(dev_priv, buf_priv); + buf_priv->dispatched = 0; + mga_freelist_put(dev, buf); + } + + +} + + +static void mga_dma_dispatch_indices(drm_device_t * dev, + drm_buf_t * buf, + unsigned int start, unsigned int end) +{ + drm_mga_private_t *dev_priv = dev->dev_private; + drm_mga_buf_priv_t *buf_priv = buf->dev_private; + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + unsigned int address = (unsigned int) buf->bus_address; + int use_agp = PDEA_pagpxfer_enable; + int i = 0; + PRIMLOCALS; + + if (start != end) { + /* WARNING: if you change any of the state functions verify + * these numbers (Overestimating this doesn't hurt). + */ + buf_priv->dispatched = 1; + PRIM_OVERFLOW(dev, dev_priv, + (MAX_STATE_SIZE + (5 * MGA_NR_SAREA_CLIPRECTS))); + mgaEmitState(dev_priv); + + do { + if (i < sarea_priv->nbox) { + mgaEmitClipRect(dev_priv, + &sarea_priv->boxes[i]); + } + + PRIMGETPTR(dev_priv); + PRIMOUTREG(MGAREG_DMAPAD, 0); + PRIMOUTREG(MGAREG_DMAPAD, 0); + PRIMOUTREG(MGAREG_SETUPADDRESS, + ((address + start) | + SETADD_mode_vertlist)); + PRIMOUTREG(MGAREG_SETUPEND, + ((address + end) | use_agp)); +/* ((address + start + 12) | use_agp)); */ + PRIMADVANCE(dev_priv); + } while (++i < sarea_priv->nbox); + } + if (buf_priv->discard) { + if (buf_priv->dispatched == 1) + AGEBUF(dev_priv, buf_priv); + buf_priv->dispatched = 0; + mga_freelist_put(dev, buf); + } +} + + +static void mga_dma_dispatch_clear(drm_device_t * dev, int flags, + unsigned int clear_color, + unsigned int clear_zval, + unsigned int clear_colormask, + unsigned int clear_depthmask) +{ + drm_mga_private_t *dev_priv = dev->dev_private; + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + unsigned int *regs = sarea_priv->ContextState; + int nbox = sarea_priv->nbox; + drm_clip_rect_t *pbox = sarea_priv->boxes; + unsigned int cmd; + int i; + PRIMLOCALS; + + if (dev_priv->sgram) + cmd = MGA_CLEAR_CMD | DC_atype_blk; + else + cmd = MGA_CLEAR_CMD | DC_atype_rstr; + + PRIM_OVERFLOW(dev, dev_priv, 35 * MGA_NR_SAREA_CLIPRECTS); + + for (i = 0; i < nbox; i++) { + unsigned int height = pbox[i].y2 - pbox[i].y1; + + if (flags & MGA_FRONT) { + PRIMOUTREG(MGAREG_DMAPAD, 0); + PRIMOUTREG(MGAREG_PLNWT, clear_colormask); + PRIMOUTREG(MGAREG_YDSTLEN, + (pbox[i].y1 << 16) | height); + PRIMOUTREG(MGAREG_FXBNDRY, + (pbox[i].x2 << 16) | pbox[i].x1); + + PRIMOUTREG(MGAREG_DMAPAD, 0); + PRIMOUTREG(MGAREG_FCOL, clear_color); + PRIMOUTREG(MGAREG_DSTORG, dev_priv->frontOffset); + PRIMOUTREG(MGAREG_DWGCTL + MGAREG_MGA_EXEC, cmd); + } + + if (flags & MGA_BACK) { + PRIMOUTREG(MGAREG_DMAPAD, 0); + PRIMOUTREG(MGAREG_PLNWT, clear_colormask); + PRIMOUTREG(MGAREG_YDSTLEN, + (pbox[i].y1 << 16) | height); + PRIMOUTREG(MGAREG_FXBNDRY, + (pbox[i].x2 << 16) | pbox[i].x1); + + PRIMOUTREG(MGAREG_DMAPAD, 0); + PRIMOUTREG(MGAREG_FCOL, clear_color); + PRIMOUTREG(MGAREG_DSTORG, dev_priv->backOffset); + PRIMOUTREG(MGAREG_DWGCTL + MGAREG_MGA_EXEC, cmd); + } + + if (flags & MGA_DEPTH) { + PRIMOUTREG(MGAREG_DMAPAD, 0); + PRIMOUTREG(MGAREG_PLNWT, clear_depthmask); + PRIMOUTREG(MGAREG_YDSTLEN, + (pbox[i].y1 << 16) | height); + PRIMOUTREG(MGAREG_FXBNDRY, + (pbox[i].x2 << 16) | pbox[i].x1); + + PRIMOUTREG(MGAREG_DMAPAD, 0); + PRIMOUTREG(MGAREG_FCOL, clear_zval); + PRIMOUTREG(MGAREG_DSTORG, dev_priv->depthOffset); + PRIMOUTREG(MGAREG_DWGCTL + MGAREG_MGA_EXEC, cmd); + } + } + + /* Force reset of DWGCTL */ + PRIMOUTREG(MGAREG_DMAPAD, 0); + PRIMOUTREG(MGAREG_DMAPAD, 0); + PRIMOUTREG(MGAREG_DMAPAD, 0); + PRIMOUTREG(MGAREG_DWGCTL, regs[MGA_CTXREG_DWGCTL]); + PRIMADVANCE(dev_priv); +} + +static void mga_dma_dispatch_swap(drm_device_t * dev) +{ + drm_mga_private_t *dev_priv = dev->dev_private; + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + unsigned int *regs = sarea_priv->ContextState; + int nbox = sarea_priv->nbox; + drm_clip_rect_t *pbox = sarea_priv->boxes; + int i; + int pixel_stride = dev_priv->stride / dev_priv->cpp; + + PRIMLOCALS; + + PRIM_OVERFLOW(dev, dev_priv, (MGA_NR_SAREA_CLIPRECTS * 5) + 20); + + PRIMOUTREG(MGAREG_DMAPAD, 0); + PRIMOUTREG(MGAREG_DMAPAD, 0); + PRIMOUTREG(MGAREG_DWGSYNC, 0x7100); + PRIMOUTREG(MGAREG_DWGSYNC, 0x7000); + + PRIMOUTREG(MGAREG_DSTORG, dev_priv->frontOffset); + PRIMOUTREG(MGAREG_MACCESS, dev_priv->mAccess); + PRIMOUTREG(MGAREG_SRCORG, dev_priv->backOffset); + PRIMOUTREG(MGAREG_AR5, pixel_stride); + + PRIMOUTREG(MGAREG_DMAPAD, 0); + PRIMOUTREG(MGAREG_DMAPAD, 0); + PRIMOUTREG(MGAREG_DMAPAD, 0); + PRIMOUTREG(MGAREG_DWGCTL, MGA_COPY_CMD); + + for (i = 0; i < nbox; i++) { + unsigned int h = pbox[i].y2 - pbox[i].y1; + unsigned int start = pbox[i].y1 * pixel_stride; + + PRIMOUTREG(MGAREG_AR0, start + pbox[i].x2 - 1); + PRIMOUTREG(MGAREG_AR3, start + pbox[i].x1); + PRIMOUTREG(MGAREG_FXBNDRY, + pbox[i].x1 | ((pbox[i].x2 - 1) << 16)); + PRIMOUTREG(MGAREG_YDSTLEN + MGAREG_MGA_EXEC, + (pbox[i].y1 << 16) | h); + } + + /* Force reset of DWGCTL */ + PRIMOUTREG(MGAREG_DMAPAD, 0); + PRIMOUTREG(MGAREG_DMAPAD, 0); + PRIMOUTREG(MGAREG_SRCORG, 0); + PRIMOUTREG(MGAREG_DWGCTL, regs[MGA_CTXREG_DWGCTL]); + + PRIMADVANCE(dev_priv); +} + +int mga_clear_bufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_mga_private_t *dev_priv = + (drm_mga_private_t *) dev->dev_private; + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_mga_clear_t clear; + + if (copy_from_user(&clear, (drm_mga_clear_t *) arg, sizeof(clear))) + return -EFAULT; + + if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { + DRM_ERROR("mga_clear_bufs called without lock held\n"); + return -EINVAL; + } + + if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS) + sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS; + + /* Make sure we restore the 3D state next time. + */ + dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CTX; + mga_dma_dispatch_clear(dev, clear.flags, + clear.clear_color, + clear.clear_depth, + clear.clear_color_mask, + clear.clear_depth_mask); + PRIMUPDATE(dev_priv); + mga_flush_write_combine(); + mga_dma_schedule(dev, 1); + return 0; +} + +int mga_swap_bufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_mga_private_t *dev_priv = + (drm_mga_private_t *) dev->dev_private; + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + + if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { + DRM_ERROR("mga_swap_bufs called without lock held\n"); + return -EINVAL; + } + + if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS) + sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS; + + /* Make sure we restore the 3D state next time. + */ + dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CTX; + mga_dma_dispatch_swap(dev); + PRIMUPDATE(dev_priv); + set_bit(MGA_BUF_SWAP_PENDING, + &dev_priv->current_prim->buffer_status); + mga_flush_write_combine(); + mga_dma_schedule(dev, 1); + return 0; +} + +int mga_iload(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_device_dma_t *dma = dev->dma; + drm_mga_private_t *dev_priv = + (drm_mga_private_t *) dev->dev_private; + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_buf_t *buf; + drm_mga_buf_priv_t *buf_priv; + drm_mga_iload_t iload; + unsigned long bus_address; + + if (copy_from_user(&iload, (drm_mga_iload_t *) arg, sizeof(iload))) + return -EFAULT; + + if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { + DRM_ERROR("mga_iload called without lock held\n"); + return -EINVAL; + } + + if(iload.idx < 0 || iload.idx > dma->buf_count) return -EINVAL; + buf = dma->buflist[iload.idx]; + buf_priv = buf->dev_private; + bus_address = buf->bus_address; + + if (mgaVerifyIload(dev_priv, + bus_address, iload.destOrg, iload.length)) { + mga_freelist_put(dev, buf); + return -EINVAL; + } + + sarea_priv->dirty |= MGA_UPLOAD_CTX; + + mga_dma_dispatch_tex_blit(dev, bus_address, iload.length, + iload.destOrg); + AGEBUF(dev_priv, buf_priv); + buf_priv->discard = 1; + mga_freelist_put(dev, buf); + mga_flush_write_combine(); + mga_dma_schedule(dev, 1); + return 0; +} + +int mga_vertex(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_mga_private_t *dev_priv = + (drm_mga_private_t *) dev->dev_private; + drm_device_dma_t *dma = dev->dma; + drm_buf_t *buf; + drm_mga_buf_priv_t *buf_priv; + drm_mga_vertex_t vertex; + + if (copy_from_user(&vertex, (drm_mga_vertex_t *) arg, sizeof(vertex))) + return -EFAULT; + + if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { + DRM_ERROR("mga_vertex called without lock held\n"); + return -EINVAL; + } + + if(vertex.idx < 0 || vertex.idx > dma->buf_count) return -EINVAL; + + buf = dma->buflist[vertex.idx]; + buf_priv = buf->dev_private; + + buf->used = vertex.used; + buf_priv->discard = vertex.discard; + + if (!mgaVerifyState(dev_priv)) { + if (vertex.discard) { + if (buf_priv->dispatched == 1) + AGEBUF(dev_priv, buf_priv); + buf_priv->dispatched = 0; + mga_freelist_put(dev, buf); + } + return -EINVAL; + } + + mga_dma_dispatch_vertex(dev, buf); + + PRIMUPDATE(dev_priv); + mga_flush_write_combine(); + mga_dma_schedule(dev, 1); + return 0; +} + + +int mga_indices(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_mga_private_t *dev_priv = + (drm_mga_private_t *) dev->dev_private; + drm_device_dma_t *dma = dev->dma; + drm_buf_t *buf; + drm_mga_buf_priv_t *buf_priv; + drm_mga_indices_t indices; + + if (copy_from_user(&indices, + (drm_mga_indices_t *)arg, sizeof(indices))) + return -EFAULT; + + if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { + DRM_ERROR("mga_indices called without lock held\n"); + return -EINVAL; + } + + if(indices.idx < 0 || indices.idx > dma->buf_count) return -EINVAL; + buf = dma->buflist[indices.idx]; + buf_priv = buf->dev_private; + + buf_priv->discard = indices.discard; + + if (!mgaVerifyState(dev_priv)) { + if (indices.discard) { + if (buf_priv->dispatched == 1) + AGEBUF(dev_priv, buf_priv); + buf_priv->dispatched = 0; + mga_freelist_put(dev, buf); + } + return -EINVAL; + } + + mga_dma_dispatch_indices(dev, buf, indices.start, indices.end); + + PRIMUPDATE(dev_priv); + mga_flush_write_combine(); + mga_dma_schedule(dev, 1); + return 0; +} + + + +static int mga_dma_get_buffers(drm_device_t * dev, drm_dma_t * d) +{ + int i; + drm_buf_t *buf; + + for (i = d->granted_count; i < d->request_count; i++) { + buf = mga_freelist_get(dev); + if (!buf) + break; + buf->pid = current->pid; + if (copy_to_user(&d->request_indices[i], + &buf->idx, sizeof(buf->idx))) + return -EFAULT; + if (copy_to_user(&d->request_sizes[i], + &buf->total, sizeof(buf->total))) + return -EFAULT; + ++d->granted_count; + } + return 0; +} + +int mga_dma(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_device_dma_t *dma = dev->dma; + int retcode = 0; + drm_dma_t d; + + if (copy_from_user(&d, (drm_dma_t *) arg, sizeof(d))) + return -EFAULT; + + if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { + DRM_ERROR("mga_dma called without lock held\n"); + return -EINVAL; + } + + /* Please don't send us buffers. + */ + if (d.send_count != 0) { + DRM_ERROR + ("Process %d trying to send %d buffers via drmDMA\n", + current->pid, d.send_count); + return -EINVAL; + } + + /* We'll send you buffers. + */ + if (d.request_count < 0 || d.request_count > dma->buf_count) { + DRM_ERROR + ("Process %d trying to get %d buffers (of %d max)\n", + current->pid, d.request_count, dma->buf_count); + return -EINVAL; + } + + d.granted_count = 0; + + if (d.request_count) { + retcode = mga_dma_get_buffers(dev, &d); + } + + if (copy_to_user((drm_dma_t *) arg, &d, sizeof(d))) + return -EFAULT; + return retcode; +} diff -urN linux-2.4.10/drivers/char/drm-4.0/proc.c linux-2.4.10-lia/drivers/char/drm-4.0/proc.c --- linux-2.4.10/drivers/char/drm-4.0/proc.c Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/proc.c Wed Aug 15 20:52:12 2001 @@ -0,0 +1,578 @@ +/* proc.c -- /proc support for DRM -*- linux-c -*- + * Created: Mon Jan 11 09:48:47 1999 by faith@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rickard E. (Rik) Faith + */ + +#define __NO_VERSION__ +#include "drmP.h" + +static struct proc_dir_entry *drm_root = NULL; +static struct proc_dir_entry *drm_dev_root = NULL; +static char drm_slot_name[64]; + +static int drm_name_info(char *buf, char **start, off_t offset, + int len, int *eof, void *data); +static int drm_vm_info(char *buf, char **start, off_t offset, + int len, int *eof, void *data); +static int drm_clients_info(char *buf, char **start, off_t offset, + int len, int *eof, void *data); +static int drm_queues_info(char *buf, char **start, off_t offset, + int len, int *eof, void *data); +static int drm_bufs_info(char *buf, char **start, off_t offset, + int len, int *eof, void *data); +#if DRM_DEBUG_CODE +static int drm_vma_info(char *buf, char **start, off_t offset, + int len, int *eof, void *data); +#endif +#if DRM_DMA_HISTOGRAM +static int drm_histo_info(char *buf, char **start, off_t offset, + int len, int *eof, void *data); +#endif + +struct drm_proc_list { + const char *name; + int (*f)(char *, char **, off_t, int, int *, void *); +} drm_proc_list[] = { + { "name", drm_name_info }, + { "mem", drm_mem_info }, + { "vm", drm_vm_info }, + { "clients", drm_clients_info }, + { "queues", drm_queues_info }, + { "bufs", drm_bufs_info }, +#if DRM_DEBUG_CODE + { "vma", drm_vma_info }, +#endif +#if DRM_DMA_HISTOGRAM + { "histo", drm_histo_info }, +#endif +}; +#define DRM_PROC_ENTRIES (sizeof(drm_proc_list)/sizeof(drm_proc_list[0])) + +int drm_proc_init(drm_device_t *dev) +{ + struct proc_dir_entry *ent; + int i, j; + + drm_root = create_proc_entry("dri", S_IFDIR, NULL); + if (!drm_root) { + DRM_ERROR("Cannot create /proc/dri\n"); + return -1; + } + + /* Instead of doing this search, we should + add some global support for /proc/dri. */ + for (i = 0; i < 8; i++) { + sprintf(drm_slot_name, "dri/%d", i); + drm_dev_root = create_proc_entry(drm_slot_name, S_IFDIR, NULL); + if (!drm_dev_root) { + DRM_ERROR("Cannot create /proc/%s\n", drm_slot_name); + remove_proc_entry("dri", NULL); + break; + } + if (drm_dev_root->nlink == 2) break; + drm_dev_root = NULL; + } + if (!drm_dev_root) { + DRM_ERROR("Cannot find slot in /proc/dri\n"); + return -1; + } + + for (i = 0; i < DRM_PROC_ENTRIES; i++) { + ent = create_proc_entry(drm_proc_list[i].name, + S_IFREG|S_IRUGO, drm_dev_root); + if (!ent) { + DRM_ERROR("Cannot create /proc/%s/%s\n", + drm_slot_name, drm_proc_list[i].name); + for (j = 0; j < i; j++) + remove_proc_entry(drm_proc_list[i].name, + drm_dev_root); + remove_proc_entry(drm_slot_name, NULL); + remove_proc_entry("dri", NULL); + return -1; + } + ent->read_proc = drm_proc_list[i].f; + ent->data = dev; + } + + return 0; +} + + +int drm_proc_cleanup(void) +{ + int i; + + if (drm_root) { + if (drm_dev_root) { + for (i = 0; i < DRM_PROC_ENTRIES; i++) { + remove_proc_entry(drm_proc_list[i].name, + drm_dev_root); + } + remove_proc_entry(drm_slot_name, NULL); + } + remove_proc_entry("dri", NULL); + remove_proc_entry(DRM_NAME, NULL); + } + drm_root = drm_dev_root = NULL; + return 0; +} + +static int drm_name_info(char *buf, char **start, off_t offset, int len, + int *eof, void *data) +{ + drm_device_t *dev = (drm_device_t *)data; + + if (offset > 0) return 0; /* no partial requests */ + len = 0; + *eof = 1; + + if (dev->unique) { + DRM_PROC_PRINT("%s 0x%x %s\n", + dev->name, dev->device, dev->unique); + } else { + DRM_PROC_PRINT("%s 0x%x\n", dev->name, dev->device); + } + return len; +} + +static int _drm_vm_info(char *buf, char **start, off_t offset, int len, + int *eof, void *data) +{ + drm_device_t *dev = (drm_device_t *)data; + drm_map_t *map; + /* Hardcoded from _DRM_FRAME_BUFFER, + _DRM_REGISTERS, _DRM_SHM, and + _DRM_AGP. */ + const char *types[] = { "FB", "REG", "SHM", "AGP" }; + const char *type; + int i; + + if (offset > 0) return 0; /* no partial requests */ + len = 0; + *eof = 1; + DRM_PROC_PRINT("slot offset size type flags " + "address mtrr\n\n"); + for (i = 0; i < dev->map_count; i++) { + map = dev->maplist[i]; + if (map->type < 0 || map->type > 3) type = "??"; + else type = types[map->type]; + DRM_PROC_PRINT("%4d 0x%08lx 0x%08lx %4.4s 0x%02x 0x%08lx ", + i, + map->offset, + map->size, + type, + map->flags, + (unsigned long)map->handle); + if (map->mtrr < 0) { + DRM_PROC_PRINT("none\n"); + } else { + DRM_PROC_PRINT("%4d\n", map->mtrr); + } + } + + return len; +} + +static int drm_vm_info(char *buf, char **start, off_t offset, int len, + int *eof, void *data) +{ + drm_device_t *dev = (drm_device_t *)data; + int ret; + + down(&dev->struct_sem); + ret = _drm_vm_info(buf, start, offset, len, eof, data); + up(&dev->struct_sem); + return ret; +} + + +static int _drm_queues_info(char *buf, char **start, off_t offset, int len, + int *eof, void *data) +{ + drm_device_t *dev = (drm_device_t *)data; + int i; + drm_queue_t *q; + + if (offset > 0) return 0; /* no partial requests */ + len = 0; + *eof = 1; + DRM_PROC_PRINT(" ctx/flags use fin" + " blk/rw/rwf wait flushed queued" + " locks\n\n"); + for (i = 0; i < dev->queue_count; i++) { + q = dev->queuelist[i]; + atomic_inc(&q->use_count); + DRM_PROC_PRINT_RET(atomic_dec(&q->use_count), + "%5d/0x%03x %5d %5d" + " %5d/%c%c/%c%c%c %5Zd %10d %10d %10d\n", + i, + q->flags, + atomic_read(&q->use_count), + atomic_read(&q->finalization), + atomic_read(&q->block_count), + atomic_read(&q->block_read) ? 'r' : '-', + atomic_read(&q->block_write) ? 'w' : '-', + waitqueue_active(&q->read_queue) ? 'r':'-', + waitqueue_active(&q->write_queue) ? 'w':'-', + waitqueue_active(&q->flush_queue) ? 'f':'-', + DRM_BUFCOUNT(&q->waitlist), + atomic_read(&q->total_flushed), + atomic_read(&q->total_queued), + atomic_read(&q->total_locks)); + atomic_dec(&q->use_count); + } + + return len; +} + +static int drm_queues_info(char *buf, char **start, off_t offset, int len, + int *eof, void *data) +{ + drm_device_t *dev = (drm_device_t *)data; + int ret; + + down(&dev->struct_sem); + ret = _drm_queues_info(buf, start, offset, len, eof, data); + up(&dev->struct_sem); + return ret; +} + +/* drm_bufs_info is called whenever a process reads + /dev/drm//bufs. */ + +static int _drm_bufs_info(char *buf, char **start, off_t offset, int len, + int *eof, void *data) +{ + drm_device_t *dev = (drm_device_t *)data; + drm_device_dma_t *dma = dev->dma; + int i; + + if (!dma) return 0; + if (offset > 0) return 0; /* no partial requests */ + len = 0; + *eof = 1; + DRM_PROC_PRINT(" o size count free segs pages kB\n\n"); + for (i = 0; i <= DRM_MAX_ORDER; i++) { + if (dma->bufs[i].buf_count) + DRM_PROC_PRINT("%2d %8d %5d %5d %5d %5d %5ld\n", + i, + dma->bufs[i].buf_size, + dma->bufs[i].buf_count, + atomic_read(&dma->bufs[i] + .freelist.count), + dma->bufs[i].seg_count, + dma->bufs[i].seg_count + *(1 << dma->bufs[i].page_order), + (dma->bufs[i].seg_count + * (1 << dma->bufs[i].page_order)) + * PAGE_SIZE / 1024); + } + DRM_PROC_PRINT("\n"); + for (i = 0; i < dma->buf_count; i++) { + if (i && !(i%32)) DRM_PROC_PRINT("\n"); + DRM_PROC_PRINT(" %d", dma->buflist[i]->list); + } + DRM_PROC_PRINT("\n"); + + return len; +} + +static int drm_bufs_info(char *buf, char **start, off_t offset, int len, + int *eof, void *data) +{ + drm_device_t *dev = (drm_device_t *)data; + int ret; + + down(&dev->struct_sem); + ret = _drm_bufs_info(buf, start, offset, len, eof, data); + up(&dev->struct_sem); + return ret; +} + + +static int _drm_clients_info(char *buf, char **start, off_t offset, int len, + int *eof, void *data) +{ + drm_device_t *dev = (drm_device_t *)data; + drm_file_t *priv; + + if (offset > 0) return 0; /* no partial requests */ + len = 0; + *eof = 1; + DRM_PROC_PRINT("a dev pid uid magic ioctls\n\n"); + for (priv = dev->file_first; priv; priv = priv->next) { + DRM_PROC_PRINT("%c %3d %5d %5d %10u %10lu\n", + priv->authenticated ? 'y' : 'n', + priv->minor, + priv->pid, + priv->uid, + priv->magic, + priv->ioctl_count); + } + + return len; +} + +static int drm_clients_info(char *buf, char **start, off_t offset, int len, + int *eof, void *data) +{ + drm_device_t *dev = (drm_device_t *)data; + int ret; + + down(&dev->struct_sem); + ret = _drm_clients_info(buf, start, offset, len, eof, data); + up(&dev->struct_sem); + return ret; +} + +#if DRM_DEBUG_CODE + +#define DRM_VMA_VERBOSE 0 + +static int _drm_vma_info(char *buf, char **start, off_t offset, int len, + int *eof, void *data) +{ + drm_device_t *dev = (drm_device_t *)data; + drm_vma_entry_t *pt; + struct vm_area_struct *vma; +#if DRM_VMA_VERBOSE + unsigned long i; + unsigned long address; + pgd_t *pgd; + pmd_t *pmd; + pte_t *pte; +#endif +#if defined(__i386__) + unsigned int pgprot; +#endif + + if (offset > 0) return 0; /* no partial requests */ + len = 0; + *eof = 1; + DRM_PROC_PRINT("vma use count: %d, high_memory = %p, 0x%08lx\n", + atomic_read(&dev->vma_count), + high_memory, virt_to_phys(high_memory)); + for (pt = dev->vmalist; pt; pt = pt->next) { + if (!(vma = pt->vma)) continue; + DRM_PROC_PRINT("\n%5d 0x%08lx-0x%08lx %c%c%c%c%c%c 0x%08lx", + pt->pid, + vma->vm_start, + vma->vm_end, + vma->vm_flags & VM_READ ? 'r' : '-', + vma->vm_flags & VM_WRITE ? 'w' : '-', + vma->vm_flags & VM_EXEC ? 'x' : '-', + vma->vm_flags & VM_MAYSHARE ? 's' : 'p', + vma->vm_flags & VM_LOCKED ? 'l' : '-', + vma->vm_flags & VM_IO ? 'i' : '-', + VM_OFFSET(vma)); + +#if defined(__i386__) + pgprot = pgprot_val(vma->vm_page_prot); + DRM_PROC_PRINT(" %c%c%c%c%c%c%c%c%c", + pgprot & _PAGE_PRESENT ? 'p' : '-', + pgprot & _PAGE_RW ? 'w' : 'r', + pgprot & _PAGE_USER ? 'u' : 's', + pgprot & _PAGE_PWT ? 't' : 'b', + pgprot & _PAGE_PCD ? 'u' : 'c', + pgprot & _PAGE_ACCESSED ? 'a' : '-', + pgprot & _PAGE_DIRTY ? 'd' : '-', + pgprot & _PAGE_PSE ? 'm' : 'k', + pgprot & _PAGE_GLOBAL ? 'g' : 'l' ); +#endif + DRM_PROC_PRINT("\n"); +#if 0 + for (i = vma->vm_start; i < vma->vm_end; i += PAGE_SIZE) { + pgd = pgd_offset(vma->vm_mm, i); + pmd = pmd_offset(pgd, i); + pte = pte_offset(pmd, i); + if (pte_present(*pte)) { + address = __pa(pte_page(*pte)) + + (i & (PAGE_SIZE-1)); + DRM_PROC_PRINT(" 0x%08lx -> 0x%08lx" + " %c%c%c%c%c\n", + i, + address, + pte_read(*pte) ? 'r' : '-', + pte_write(*pte) ? 'w' : '-', + pte_exec(*pte) ? 'x' : '-', + pte_dirty(*pte) ? 'd' : '-', + pte_young(*pte) ? 'a' : '-' ); + } else { + DRM_PROC_PRINT(" 0x%08lx\n", i); + } + } +#endif + } + + return len; +} + +static int drm_vma_info(char *buf, char **start, off_t offset, int len, + int *eof, void *data) +{ + drm_device_t *dev = (drm_device_t *)data; + int ret; + + down(&dev->struct_sem); + ret = _drm_vma_info(buf, start, offset, len, eof, data); + up(&dev->struct_sem); + return ret; +} +#endif + + +#if DRM_DMA_HISTOGRAM +static int _drm_histo_info(char *buf, char **start, off_t offset, int len, + int *eof, void *data) +{ + drm_device_t *dev = (drm_device_t *)data; + drm_device_dma_t *dma = dev->dma; + int i; + unsigned long slot_value = DRM_DMA_HISTOGRAM_INITIAL; + unsigned long prev_value = 0; + drm_buf_t *buffer; + + if (offset > 0) return 0; /* no partial requests */ + len = 0; + *eof = 1; + + DRM_PROC_PRINT("general statistics:\n"); + DRM_PROC_PRINT("total %10u\n", atomic_read(&dev->histo.total)); + DRM_PROC_PRINT("open %10u\n", atomic_read(&dev->total_open)); + DRM_PROC_PRINT("close %10u\n", atomic_read(&dev->total_close)); + DRM_PROC_PRINT("ioctl %10u\n", atomic_read(&dev->total_ioctl)); + DRM_PROC_PRINT("irq %10u\n", atomic_read(&dev->total_irq)); + DRM_PROC_PRINT("ctx %10u\n", atomic_read(&dev->total_ctx)); + + DRM_PROC_PRINT("\nlock statistics:\n"); + DRM_PROC_PRINT("locks %10u\n", atomic_read(&dev->total_locks)); + DRM_PROC_PRINT("unlocks %10u\n", atomic_read(&dev->total_unlocks)); + DRM_PROC_PRINT("contends %10u\n", atomic_read(&dev->total_contends)); + DRM_PROC_PRINT("sleeps %10u\n", atomic_read(&dev->total_sleeps)); + + + if (dma) { + DRM_PROC_PRINT("\ndma statistics:\n"); + DRM_PROC_PRINT("prio %10u\n", + atomic_read(&dma->total_prio)); + DRM_PROC_PRINT("bytes %10u\n", + atomic_read(&dma->total_bytes)); + DRM_PROC_PRINT("dmas %10u\n", + atomic_read(&dma->total_dmas)); + DRM_PROC_PRINT("missed:\n"); + DRM_PROC_PRINT(" dma %10u\n", + atomic_read(&dma->total_missed_dma)); + DRM_PROC_PRINT(" lock %10u\n", + atomic_read(&dma->total_missed_lock)); + DRM_PROC_PRINT(" free %10u\n", + atomic_read(&dma->total_missed_free)); + DRM_PROC_PRINT(" sched %10u\n", + atomic_read(&dma->total_missed_sched)); + DRM_PROC_PRINT("tried %10u\n", + atomic_read(&dma->total_tried)); + DRM_PROC_PRINT("hit %10u\n", + atomic_read(&dma->total_hit)); + DRM_PROC_PRINT("lost %10u\n", + atomic_read(&dma->total_lost)); + + buffer = dma->next_buffer; + if (buffer) { + DRM_PROC_PRINT("next_buffer %7d\n", buffer->idx); + } else { + DRM_PROC_PRINT("next_buffer none\n"); + } + buffer = dma->this_buffer; + if (buffer) { + DRM_PROC_PRINT("this_buffer %7d\n", buffer->idx); + } else { + DRM_PROC_PRINT("this_buffer none\n"); + } + } + + + DRM_PROC_PRINT("\nvalues:\n"); + if (dev->lock.hw_lock) { + DRM_PROC_PRINT("lock 0x%08x\n", + dev->lock.hw_lock->lock); + } else { + DRM_PROC_PRINT("lock none\n"); + } + DRM_PROC_PRINT("context_flag 0x%08lx\n", dev->context_flag); + DRM_PROC_PRINT("interrupt_flag 0x%08lx\n", dev->interrupt_flag); + DRM_PROC_PRINT("dma_flag 0x%08lx\n", dev->dma_flag); + + DRM_PROC_PRINT("queue_count %10d\n", dev->queue_count); + DRM_PROC_PRINT("last_context %10d\n", dev->last_context); + DRM_PROC_PRINT("last_switch %10lu\n", dev->last_switch); + DRM_PROC_PRINT("last_checked %10d\n", dev->last_checked); + + + DRM_PROC_PRINT("\n q2d d2c c2f" + " q2c q2f dma sch" + " ctx lacq lhld\n\n"); + for (i = 0; i < DRM_DMA_HISTOGRAM_SLOTS; i++) { + DRM_PROC_PRINT("%s %10lu %10u %10u %10u %10u %10u" + " %10u %10u %10u %10u %10u\n", + i == DRM_DMA_HISTOGRAM_SLOTS - 1 ? ">=" : "< ", + i == DRM_DMA_HISTOGRAM_SLOTS - 1 + ? prev_value : slot_value , + + atomic_read(&dev->histo + .queued_to_dispatched[i]), + atomic_read(&dev->histo + .dispatched_to_completed[i]), + atomic_read(&dev->histo + .completed_to_freed[i]), + + atomic_read(&dev->histo + .queued_to_completed[i]), + atomic_read(&dev->histo + .queued_to_freed[i]), + atomic_read(&dev->histo.dma[i]), + atomic_read(&dev->histo.schedule[i]), + atomic_read(&dev->histo.ctx[i]), + atomic_read(&dev->histo.lacq[i]), + atomic_read(&dev->histo.lhld[i])); + prev_value = slot_value; + slot_value = DRM_DMA_HISTOGRAM_NEXT(slot_value); + } + return len; +} + +static int drm_histo_info(char *buf, char **start, off_t offset, int len, + int *eof, void *data) +{ + drm_device_t *dev = (drm_device_t *)data; + int ret; + + down(&dev->struct_sem); + ret = _drm_histo_info(buf, start, offset, len, eof, data); + up(&dev->struct_sem); + return ret; +} +#endif diff -urN linux-2.4.10/drivers/char/drm-4.0/r128_bufs.c linux-2.4.10-lia/drivers/char/drm-4.0/r128_bufs.c --- linux-2.4.10/drivers/char/drm-4.0/r128_bufs.c Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/r128_bufs.c Wed Aug 15 20:52:12 2001 @@ -0,0 +1,319 @@ +/* r128_bufs.c -- IOCTLs to manage buffers -*- linux-c -*- + * Created: Wed Apr 12 16:19:08 2000 by kevin@precisioninsight.com + * + * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: Kevin E. Martin + * Rickard E. (Rik) Faith + * Jeff Hartmann + * + */ + +#define __NO_VERSION__ +#include +#include "drmP.h" +#include "r128_drv.h" +#include "linux/un.h" + + +#if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE) +int r128_addbufs_agp(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_device_dma_t *dma = dev->dma; + drm_buf_desc_t request; + drm_buf_entry_t *entry; + drm_buf_t *buf; + unsigned long offset; + unsigned long agp_offset; + int count; + int order; + int size; + int alignment; + int page_order; + int total; + int byte_count; + int i; + + if (!dma) return -EINVAL; + + if (copy_from_user(&request, + (drm_buf_desc_t *)arg, + sizeof(request))) + return -EFAULT; + + count = request.count; + order = drm_order(request.size); + size = 1 << order; + + alignment = (request.flags & _DRM_PAGE_ALIGN) ? PAGE_ALIGN(size):size; + page_order = order - PAGE_SHIFT > 0 ? order - PAGE_SHIFT : 0; + total = PAGE_SIZE << page_order; + + byte_count = 0; + agp_offset = dev->agp->base + request.agp_start; + + DRM_DEBUG("count: %d\n", count); + DRM_DEBUG("order: %d\n", order); + DRM_DEBUG("size: %d\n", size); + DRM_DEBUG("agp_offset: %ld\n", agp_offset); + DRM_DEBUG("alignment: %d\n", alignment); + DRM_DEBUG("page_order: %d\n", page_order); + DRM_DEBUG("total: %d\n", total); + + if (order < DRM_MIN_ORDER || order > DRM_MAX_ORDER) return -EINVAL; + if (dev->queue_count) return -EBUSY; /* Not while in use */ + + spin_lock(&dev->count_lock); + if (dev->buf_use) { + spin_unlock(&dev->count_lock); + return -EBUSY; + } + atomic_inc(&dev->buf_alloc); + spin_unlock(&dev->count_lock); + + down(&dev->struct_sem); + entry = &dma->bufs[order]; + if (entry->buf_count) { + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); + return -ENOMEM; /* May only call once for each order */ + } + + /* Might be a poor limit, but take that up with XFree86 + if its a problem */ + + if(count < 0 || count > 4096) + { + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); + return -EINVAL; + } + + entry->buflist = drm_alloc(count * sizeof(*entry->buflist), + DRM_MEM_BUFS); + if (!entry->buflist) { + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); + return -ENOMEM; + } + memset(entry->buflist, 0, count * sizeof(*entry->buflist)); + + entry->buf_size = size; + entry->page_order = page_order; + offset = 0; + + for (offset = 0; + entry->buf_count < count; + offset += alignment, ++entry->buf_count) { + buf = &entry->buflist[entry->buf_count]; + buf->idx = dma->buf_count + entry->buf_count; + buf->total = alignment; + buf->order = order; + buf->used = 0; + buf->offset = (dma->byte_count + offset); + buf->address = (void *)(agp_offset + offset); + buf->next = NULL; + buf->waiting = 0; + buf->pending = 0; + init_waitqueue_head(&buf->dma_wait); + buf->pid = 0; + + buf->dev_priv_size = sizeof(drm_r128_buf_priv_t); + buf->dev_private = drm_alloc(sizeof(drm_r128_buf_priv_t), + DRM_MEM_BUFS); + memset(buf->dev_private, 0, buf->dev_priv_size); + +#if DRM_DMA_HISTOGRAM + buf->time_queued = 0; + buf->time_dispatched = 0; + buf->time_completed = 0; + buf->time_freed = 0; +#endif + + byte_count += PAGE_SIZE << page_order; + + DRM_DEBUG("buffer %d @ %p\n", + entry->buf_count, buf->address); + } + + DRM_DEBUG("byte_count: %d\n", byte_count); + + dma->buflist = drm_realloc(dma->buflist, + dma->buf_count * sizeof(*dma->buflist), + (dma->buf_count + entry->buf_count) + * sizeof(*dma->buflist), + DRM_MEM_BUFS); + for (i = dma->buf_count; i < dma->buf_count + entry->buf_count; i++) + dma->buflist[i] = &entry->buflist[i - dma->buf_count]; + + dma->buf_count += entry->buf_count; + dma->byte_count += byte_count; + + drm_freelist_create(&entry->freelist, entry->buf_count); + for (i = 0; i < entry->buf_count; i++) { + drm_freelist_put(dev, &entry->freelist, &entry->buflist[i]); + } + + up(&dev->struct_sem); + + request.count = entry->buf_count; + request.size = size; + + if (copy_to_user((drm_buf_desc_t *)arg, + &request, + sizeof(request))) + return -EFAULT; + + dma->flags = _DRM_DMA_USE_AGP; + + atomic_dec(&dev->buf_alloc); + return 0; +} +#endif + +int r128_addbufs(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_r128_private_t *dev_priv = dev->dev_private; + drm_buf_desc_t request; + + if (!dev_priv || dev_priv->is_pci) return -EINVAL; + + if (copy_from_user(&request, + (drm_buf_desc_t *)arg, + sizeof(request))) + return -EFAULT; + +#if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE) + if (request.flags & _DRM_AGP_BUFFER) + return r128_addbufs_agp(inode, filp, cmd, arg); + else +#endif + return -EINVAL; +} + +int r128_mapbufs(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_r128_private_t *dev_priv = dev->dev_private; + drm_device_dma_t *dma = dev->dma; + int retcode = 0; + const int zero = 0; + unsigned long virtual; + unsigned long address; + drm_buf_map_t request; + int i; + + if (!dma || !dev_priv || dev_priv->is_pci) return -EINVAL; + + DRM_DEBUG("\n"); + + spin_lock(&dev->count_lock); + if (atomic_read(&dev->buf_alloc)) { + spin_unlock(&dev->count_lock); + return -EBUSY; + } + ++dev->buf_use; /* Can't allocate more after this call */ + spin_unlock(&dev->count_lock); + + if (copy_from_user(&request, + (drm_buf_map_t *)arg, + sizeof(request))) + return -EFAULT; + + if (request.count >= dma->buf_count) { + if (dma->flags & _DRM_DMA_USE_AGP) { + drm_map_t *map; + + map = dev_priv->buffers; + if (!map) { + retcode = -EINVAL; + goto done; + } + + down_write(¤t->mm->mmap_sem); + virtual = do_mmap(filp, 0, map->size, + PROT_READ|PROT_WRITE, + MAP_SHARED, + (unsigned long)map->offset); + up_write(¤t->mm->mmap_sem); + } else { + down_write(¤t->mm->mmap_sem); + virtual = do_mmap(filp, 0, dma->byte_count, + PROT_READ|PROT_WRITE, MAP_SHARED, 0); + up_write(¤t->mm->mmap_sem); + } + if (virtual > -1024UL) { + /* Real error */ + retcode = (signed long)virtual; + goto done; + } + request.virtual = (void *)virtual; + + for (i = 0; i < dma->buf_count; i++) { + if (copy_to_user(&request.list[i].idx, + &dma->buflist[i]->idx, + sizeof(request.list[0].idx))) { + retcode = -EFAULT; + goto done; + } + if (copy_to_user(&request.list[i].total, + &dma->buflist[i]->total, + sizeof(request.list[0].total))) { + retcode = -EFAULT; + goto done; + } + if (copy_to_user(&request.list[i].used, + &zero, + sizeof(zero))) { + retcode = -EFAULT; + goto done; + } + address = virtual + dma->buflist[i]->offset; + if (copy_to_user(&request.list[i].address, + &address, + sizeof(address))) { + retcode = -EFAULT; + goto done; + } + } + } + done: + request.count = dma->buf_count; + DRM_DEBUG("%d buffers, retcode = %d\n", request.count, retcode); + + if (copy_to_user((drm_buf_map_t *)arg, + &request, + sizeof(request))) + return -EFAULT; + + return retcode; +} diff -urN linux-2.4.10/drivers/char/drm-4.0/r128_cce.c linux-2.4.10-lia/drivers/char/drm-4.0/r128_cce.c --- linux-2.4.10/drivers/char/drm-4.0/r128_cce.c Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/r128_cce.c Mon Aug 20 18:09:34 2001 @@ -0,0 +1,1305 @@ +/* r128_cce.c -- ATI Rage 128 driver -*- linux-c -*- + * Created: Wed Apr 5 19:24:19 2000 by kevin@precisioninsight.com + * + * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Gareth Hughes + * + */ + +#define __NO_VERSION__ +#include "drmP.h" +#include "r128_drv.h" + +#include /* For task queue support */ +#include + + +/* FIXME: Temporary CCE packet buffer */ +u32 r128_cce_buffer[(1 << 14)] __attribute__ ((aligned (32))); + +/* CCE microcode (from ATI) */ +static u32 r128_cce_microcode[] = { + 0, 276838400, 0, 268449792, 2, 142, 2, 145, 0, 1076765731, 0, + 1617039951, 0, 774592877, 0, 1987540286, 0, 2307490946U, 0, + 599558925, 0, 589505315, 0, 596487092, 0, 589505315, 1, + 11544576, 1, 206848, 1, 311296, 1, 198656, 2, 912273422, 11, + 262144, 0, 0, 1, 33559837, 1, 7438, 1, 14809, 1, 6615, 12, 28, + 1, 6614, 12, 28, 2, 23, 11, 18874368, 0, 16790922, 1, 409600, 9, + 30, 1, 147854772, 16, 420483072, 3, 8192, 0, 10240, 1, 198656, + 1, 15630, 1, 51200, 10, 34858, 9, 42, 1, 33559823, 2, 10276, 1, + 15717, 1, 15718, 2, 43, 1, 15936948, 1, 570480831, 1, 14715071, + 12, 322123831, 1, 33953125, 12, 55, 1, 33559908, 1, 15718, 2, + 46, 4, 2099258, 1, 526336, 1, 442623, 4, 4194365, 1, 509952, 1, + 459007, 3, 0, 12, 92, 2, 46, 12, 176, 1, 15734, 1, 206848, 1, + 18432, 1, 133120, 1, 100670734, 1, 149504, 1, 165888, 1, + 15975928, 1, 1048576, 6, 3145806, 1, 15715, 16, 2150645232U, 2, + 268449859, 2, 10307, 12, 176, 1, 15734, 1, 15735, 1, 15630, 1, + 15631, 1, 5253120, 6, 3145810, 16, 2150645232U, 1, 15864, 2, 82, + 1, 343310, 1, 1064207, 2, 3145813, 1, 15728, 1, 7817, 1, 15729, + 3, 15730, 12, 92, 2, 98, 1, 16168, 1, 16167, 1, 16002, 1, 16008, + 1, 15974, 1, 15975, 1, 15990, 1, 15976, 1, 15977, 1, 15980, 0, + 15981, 1, 10240, 1, 5253120, 1, 15720, 1, 198656, 6, 110, 1, + 180224, 1, 103824738, 2, 112, 2, 3145839, 0, 536885440, 1, + 114880, 14, 125, 12, 206975, 1, 33559995, 12, 198784, 0, + 33570236, 1, 15803, 0, 15804, 3, 294912, 1, 294912, 3, 442370, + 1, 11544576, 0, 811612160, 1, 12593152, 1, 11536384, 1, + 14024704, 7, 310382726, 0, 10240, 1, 14796, 1, 14797, 1, 14793, + 1, 14794, 0, 14795, 1, 268679168, 1, 9437184, 1, 268449792, 1, + 198656, 1, 9452827, 1, 1075854602, 1, 1075854603, 1, 557056, 1, + 114880, 14, 159, 12, 198784, 1, 1109409213, 12, 198783, 1, + 1107312059, 12, 198784, 1, 1109409212, 2, 162, 1, 1075854781, 1, + 1073757627, 1, 1075854780, 1, 540672, 1, 10485760, 6, 3145894, + 16, 274741248, 9, 168, 3, 4194304, 3, 4209949, 0, 0, 0, 256, 14, + 174, 1, 114857, 1, 33560007, 12, 176, 0, 10240, 1, 114858, 1, + 33560018, 1, 114857, 3, 33560007, 1, 16008, 1, 114874, 1, + 33560360, 1, 114875, 1, 33560154, 0, 15963, 0, 256, 0, 4096, 1, + 409611, 9, 188, 0, 10240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + + +#define DO_REMAP(_m, _d) (_m)->handle = drm_ioremap((_m)->offset, \ + (_m)->size, (_d)) + +#define DO_REMAPFREE(_m, _d) \ + do { \ + if ((_m)->handle && (_m)->size) \ + drm_ioremapfree((_m)->handle, (_m)->size, (_d)); \ + } while (0) + +#define DO_FIND_MAP(_m, _o) \ + do { \ + int _i; \ + for (_i = 0; _i < dev->map_count; _i++) { \ + if (dev->maplist[_i]->offset == _o) { \ + _m = dev->maplist[_i]; \ + break; \ + } \ + } \ + } while (0) + + +int R128_READ_PLL(drm_device_t *dev, int addr) +{ + drm_r128_private_t *dev_priv = dev->dev_private; + + R128_WRITE8(R128_CLOCK_CNTL_INDEX, addr & 0x1f); + return R128_READ(R128_CLOCK_CNTL_DATA); +} + +#if 0 +static void r128_status( drm_r128_private_t *dev_priv ) +{ + printk( "GUI_STAT = 0x%08x\n", + (unsigned int)R128_READ( R128_GUI_STAT ) ); + printk( "PM4_STAT = 0x%08x\n", + (unsigned int)R128_READ( R128_PM4_STAT ) ); + printk( "PM4_BUFFER_DL_WPTR = 0x%08x\n", + (unsigned int)R128_READ( R128_PM4_BUFFER_DL_WPTR ) ); + printk( "PM4_BUFFER_DL_RPTR = 0x%08x\n", + (unsigned int)R128_READ( R128_PM4_BUFFER_DL_RPTR ) ); + printk( "PM4_MICRO_CNTL = 0x%08x\n", + (unsigned int)R128_READ( R128_PM4_MICRO_CNTL ) ); + printk( "PM4_BUFFER_CNTL = 0x%08x\n", + (unsigned int)R128_READ( R128_PM4_BUFFER_CNTL ) ); +} +#endif + + +/* ================================================================ + * Engine, FIFO control + */ + +static int r128_do_pixcache_flush( drm_r128_private_t *dev_priv ) +{ + u32 tmp; + int i; + + tmp = R128_READ( R128_PC_NGUI_CTLSTAT ) | R128_PC_FLUSH_ALL; + R128_WRITE( R128_PC_NGUI_CTLSTAT, tmp ); + + for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { + if ( !(R128_READ( R128_PC_NGUI_CTLSTAT ) & R128_PC_BUSY) ) { + return 0; + } + udelay( 1 ); + } + + DRM_ERROR( "%s failed!\n", __FUNCTION__ ); + return -EBUSY; +} + +static int r128_do_wait_for_fifo( drm_r128_private_t *dev_priv, int entries ) +{ + int i; + + for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { + int slots = R128_READ( R128_GUI_STAT ) & R128_GUI_FIFOCNT_MASK; + if ( slots >= entries ) return 0; + udelay( 1 ); + } + + DRM_ERROR( "%s failed!\n", __FUNCTION__ ); + return -EBUSY; +} + +static int r128_do_wait_for_idle( drm_r128_private_t *dev_priv ) +{ + int i, ret; + + ret = r128_do_wait_for_fifo( dev_priv, 64 ); + if ( !ret ) return ret; + + for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { + if ( !(R128_READ( R128_GUI_STAT ) & R128_GUI_ACTIVE) ) { + r128_do_pixcache_flush( dev_priv ); + return 0; + } + udelay( 1 ); + } + + DRM_ERROR( "%s failed!\n", __FUNCTION__ ); + return -EBUSY; +} + + +/* ================================================================ + * CCE control, initialization + */ + +/* Load the microcode for the CCE */ +static void r128_cce_load_microcode( drm_r128_private_t *dev_priv ) +{ + int i; + + r128_do_wait_for_idle( dev_priv ); + + R128_WRITE( R128_PM4_MICROCODE_ADDR, 0 ); + for ( i = 0 ; i < 256 ; i++ ) { + R128_WRITE( R128_PM4_MICROCODE_DATAH, + r128_cce_microcode[i * 2] ); + R128_WRITE( R128_PM4_MICROCODE_DATAL, + r128_cce_microcode[i * 2 + 1] ); + } +} + +/* Flush any pending commands to the CCE. This should only be used just + * prior to a wait for idle, as it informs the engine that the command + * stream is ending. + */ +static void r128_do_cce_flush( drm_r128_private_t *dev_priv ) +{ + u32 tmp; + + tmp = R128_READ( R128_PM4_BUFFER_DL_WPTR ) | R128_PM4_BUFFER_DL_DONE; + R128_WRITE( R128_PM4_BUFFER_DL_WPTR, tmp ); +} + +/* Wait for the CCE to go idle. + */ +static int r128_do_cce_idle( drm_r128_private_t *dev_priv ) +{ + int i; + + for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { +#ifndef CONFIG_AGP_I460 + if ( *dev_priv->ring.head == dev_priv->ring.tail ) { +#else + /* + * XXX - this is (I think) a 460GX specific hack + * + * When doing texturing, ring.tail sometimes gets ahead of + * PM4_BUFFER_DL_WPTR by 2; consequently, the card processes + * its whole quota of instructions and *ring.head is still 2 + * short of ring.tail. Work around this for now in lieu of + * a better solution. + */ + if ( (*dev_priv->ring.head == dev_priv->ring.tail) || + ((dev_priv->ring.tail - *dev_priv->ring.head) == 2) ) { +#endif + int pm4stat = R128_READ( R128_PM4_STAT ); + if ( ( (pm4stat & R128_PM4_FIFOCNT_MASK) >= + dev_priv->cce_fifo_size ) && + !(pm4stat & (R128_PM4_BUSY | + R128_PM4_GUI_ACTIVE)) ) { + return r128_do_pixcache_flush( dev_priv ); + } + } + udelay( 1 ); + } + +#if 0 + DRM_ERROR( "failed!\n" ); + r128_status( dev_priv ); +#endif + return -EBUSY; +} + +/* Start the Concurrent Command Engine. + */ +static void r128_do_cce_start( drm_r128_private_t *dev_priv ) +{ + r128_do_wait_for_idle( dev_priv ); + + R128_WRITE( R128_PM4_BUFFER_CNTL, + dev_priv->cce_mode | dev_priv->ring.size_l2qw ); + R128_READ( R128_PM4_BUFFER_ADDR ); /* as per the sample code */ + R128_WRITE( R128_PM4_MICRO_CNTL, R128_PM4_MICRO_FREERUN ); + + dev_priv->cce_running = 1; +} + +/* Reset the Concurrent Command Engine. This will not flush any pending + * commangs, so you must wait for the CCE command stream to complete + * before calling this routine. + */ +static void r128_do_cce_reset( drm_r128_private_t *dev_priv ) +{ + R128_WRITE( R128_PM4_BUFFER_DL_WPTR, 0 ); + R128_WRITE( R128_PM4_BUFFER_DL_RPTR, 0 ); + *dev_priv->ring.head = 0; + dev_priv->ring.tail = 0; +} + +/* Stop the Concurrent Command Engine. This will not flush any pending + * commangs, so you must flush the command stream and wait for the CCE + * to go idle before calling this routine. + */ +static void r128_do_cce_stop( drm_r128_private_t *dev_priv ) +{ + R128_WRITE( R128_PM4_MICRO_CNTL, 0 ); + R128_WRITE( R128_PM4_BUFFER_CNTL, R128_PM4_NONPM4 ); + + dev_priv->cce_running = 0; +} + +/* Reset the engine. This will stop the CCE if it is running. + */ +static int r128_do_engine_reset( drm_device_t *dev ) +{ + drm_r128_private_t *dev_priv = dev->dev_private; + u32 clock_cntl_index, mclk_cntl, gen_reset_cntl; + + r128_do_pixcache_flush( dev_priv ); + + clock_cntl_index = R128_READ( R128_CLOCK_CNTL_INDEX ); + mclk_cntl = R128_READ_PLL( dev, R128_MCLK_CNTL ); + + R128_WRITE_PLL( R128_MCLK_CNTL, + mclk_cntl | R128_FORCE_GCP | R128_FORCE_PIPE3D_CP ); + + gen_reset_cntl = R128_READ( R128_GEN_RESET_CNTL ); + + /* Taken from the sample code - do not change */ + R128_WRITE( R128_GEN_RESET_CNTL, + gen_reset_cntl | R128_SOFT_RESET_GUI ); + R128_READ( R128_GEN_RESET_CNTL ); + R128_WRITE( R128_GEN_RESET_CNTL, + gen_reset_cntl & ~R128_SOFT_RESET_GUI ); + R128_READ( R128_GEN_RESET_CNTL ); + + R128_WRITE_PLL( R128_MCLK_CNTL, mclk_cntl ); + R128_WRITE( R128_CLOCK_CNTL_INDEX, clock_cntl_index ); + R128_WRITE( R128_GEN_RESET_CNTL, gen_reset_cntl ); + + /* Reset the CCE ring */ + r128_do_cce_reset( dev_priv ); + + /* The CCE is no longer running after an engine reset */ + dev_priv->cce_running = 0; + + /* Reset any pending vertex, indirect buffers */ + r128_freelist_reset( dev ); + + return 0; +} + +static void r128_cce_init_ring_buffer( drm_device_t *dev ) +{ + drm_r128_private_t *dev_priv = dev->dev_private; + u32 ring_start; + u32 tmp; + + /* The manual (p. 2) says this address is in "VM space". This + * means it's an offset from the start of AGP space. + */ + ring_start = dev_priv->cce_ring->offset - dev->agp->base; + R128_WRITE( R128_PM4_BUFFER_OFFSET, ring_start | R128_AGP_OFFSET ); + + R128_WRITE( R128_PM4_BUFFER_DL_WPTR, 0 ); + R128_WRITE( R128_PM4_BUFFER_DL_RPTR, 0 ); + +#if defined(CONFIG_AGP_I460) && defined(__ia64__) + /* + * XXX - This is a 460GX specific hack + * + * We have to hack this right now. 460GX isn't claiming PCI writes + * from the card into the AGP aperture. Because of this, we have + * to get space outside of the aperture for RPTR_ADDR. + */ + if(dev->agp->agp_info.chipset == INTEL_460GX) { + dev_priv->ring.head = (void *) + __get_free_page(GFP_KERNEL | GFP_DMA); + atomic_inc(&virt_to_page(dev_priv->ring.head)->count); + set_bit(PG_locked, &virt_to_page(dev_priv->ring.head)->flags); + dev_priv->ring.head = __va(dev_priv->ring.head); + + *dev_priv->ring.head = 0; + R128_WRITE(R128_PM4_BUFFER_DL_RPTR_ADDR, + __pa(dev_priv->ring.head)); + } else { +#else + /* DL_RPTR_ADDR is a physical address in AGP space. */ + *dev_priv->ring.head = 0; + R128_WRITE( R128_PM4_BUFFER_DL_RPTR_ADDR, + dev_priv->ring_rptr->offset ); +#endif +#if defined(CONFIG_AGP_I460) && defined(__ia64__) + } +#endif + + /* Set watermark control */ + R128_WRITE( R128_PM4_BUFFER_WM_CNTL, + ((R128_WATERMARK_L/4) << R128_WMA_SHIFT) + | ((R128_WATERMARK_M/4) << R128_WMB_SHIFT) + | ((R128_WATERMARK_N/4) << R128_WMC_SHIFT) + | ((R128_WATERMARK_K/64) << R128_WB_WM_SHIFT) ); + + /* Force read. Why? Because it's in the examples... */ + R128_READ( R128_PM4_BUFFER_ADDR ); + + /* Turn on bus mastering */ + tmp = R128_READ( R128_BUS_CNTL ) & ~R128_BUS_MASTER_DIS; + R128_WRITE( R128_BUS_CNTL, tmp ); +} + +static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init ) +{ + drm_r128_private_t *dev_priv; + int i; + + dev_priv = drm_alloc( sizeof(drm_r128_private_t), DRM_MEM_DRIVER ); + if ( dev_priv == NULL ) + return -ENOMEM; + dev->dev_private = (void *)dev_priv; + + memset( dev_priv, 0, sizeof(drm_r128_private_t) ); + + dev_priv->is_pci = init->is_pci; + + /* GH: We don't support PCI cards until PCI GART is implemented. + * Fail here so we can remove all checks for PCI cards around + * the CCE ring code. + */ + if ( dev_priv->is_pci ) { + drm_free( dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER ); + dev->dev_private = NULL; + return -EINVAL; + } + + dev_priv->usec_timeout = init->usec_timeout; + if ( dev_priv->usec_timeout < 1 || + dev_priv->usec_timeout > R128_MAX_USEC_TIMEOUT ) { + drm_free( dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER ); + dev->dev_private = NULL; + return -EINVAL; + } + + dev_priv->cce_mode = init->cce_mode; + dev_priv->cce_secure = init->cce_secure; + + /* GH: Simple idle check. + */ + atomic_set( &dev_priv->idle_count, 0 ); + + /* We don't support anything other than bus-mastering ring mode, + * but the ring can be in either AGP or PCI space for the ring + * read pointer. + */ + if ( ( init->cce_mode != R128_PM4_192BM ) && + ( init->cce_mode != R128_PM4_128BM_64INDBM ) && + ( init->cce_mode != R128_PM4_64BM_128INDBM ) && + ( init->cce_mode != R128_PM4_64BM_64VCBM_64INDBM ) ) { + drm_free( dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER ); + dev->dev_private = NULL; + return -EINVAL; + } + + switch ( init->cce_mode ) { + case R128_PM4_NONPM4: + dev_priv->cce_fifo_size = 0; + break; + case R128_PM4_192PIO: + case R128_PM4_192BM: + dev_priv->cce_fifo_size = 192; + break; + case R128_PM4_128PIO_64INDBM: + case R128_PM4_128BM_64INDBM: + dev_priv->cce_fifo_size = 128; + break; + case R128_PM4_64PIO_128INDBM: + case R128_PM4_64BM_128INDBM: + case R128_PM4_64PIO_64VCBM_64INDBM: + case R128_PM4_64BM_64VCBM_64INDBM: + case R128_PM4_64PIO_64VCPIO_64INDPIO: + dev_priv->cce_fifo_size = 64; + break; + } + + dev_priv->fb_bpp = init->fb_bpp; + dev_priv->front_offset = init->front_offset; + dev_priv->front_pitch = init->front_pitch; + dev_priv->back_offset = init->back_offset; + dev_priv->back_pitch = init->back_pitch; + + dev_priv->depth_bpp = init->depth_bpp; + dev_priv->depth_offset = init->depth_offset; + dev_priv->depth_pitch = init->depth_pitch; + dev_priv->span_offset = init->span_offset; + + dev_priv->front_pitch_offset_c = (((dev_priv->front_pitch/8) << 21) | + (dev_priv->front_offset >> 5)); + dev_priv->back_pitch_offset_c = (((dev_priv->back_pitch/8) << 21) | + (dev_priv->back_offset >> 5)); + dev_priv->depth_pitch_offset_c = (((dev_priv->depth_pitch/8) << 21) | + (dev_priv->depth_offset >> 5) | + R128_DST_TILE); + dev_priv->span_pitch_offset_c = (((dev_priv->depth_pitch/8) << 21) | + (dev_priv->span_offset >> 5)); + + /* FIXME: We want multiple shared areas, including one shared + * only by the X Server and kernel module. + */ + for ( i = 0 ; i < dev->map_count ; i++ ) { + if ( dev->maplist[i]->type == _DRM_SHM ) { + dev_priv->sarea = dev->maplist[i]; + break; + } + } + + DO_FIND_MAP( dev_priv->fb, init->fb_offset ); + DO_FIND_MAP( dev_priv->mmio, init->mmio_offset ); + DO_FIND_MAP( dev_priv->cce_ring, init->ring_offset ); + DO_FIND_MAP( dev_priv->ring_rptr, init->ring_rptr_offset ); + DO_FIND_MAP( dev_priv->buffers, init->buffers_offset ); + + if ( !dev_priv->is_pci ) { + DO_FIND_MAP( dev_priv->agp_textures, + init->agp_textures_offset ); + } + + dev_priv->sarea_priv = + (drm_r128_sarea_t *)((u8 *)dev_priv->sarea->handle + + init->sarea_priv_offset); + + DO_REMAP( dev_priv->cce_ring, dev ); + DO_REMAP( dev_priv->ring_rptr, dev ); + DO_REMAP( dev_priv->buffers, dev ); +#if 0 + if ( !dev_priv->is_pci ) { + DO_REMAP( dev_priv->agp_textures, dev ); + } +#endif + + dev_priv->ring.head = ((__volatile__ u32 *) + dev_priv->ring_rptr->handle); + + dev_priv->ring.start = (u32 *)dev_priv->cce_ring->handle; + dev_priv->ring.end = ((u32 *)dev_priv->cce_ring->handle + + init->ring_size / sizeof(u32)); + dev_priv->ring.size = init->ring_size; + dev_priv->ring.size_l2qw = drm_order( init->ring_size / 8 ); + + dev_priv->ring.tail_mask = + (dev_priv->ring.size / sizeof(u32)) - 1; + + dev_priv->sarea_priv->last_frame = 0; + R128_WRITE( R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame ); + + dev_priv->sarea_priv->last_dispatch = 0; + R128_WRITE( R128_LAST_DISPATCH_REG, + dev_priv->sarea_priv->last_dispatch ); + + r128_cce_init_ring_buffer( dev ); + r128_cce_load_microcode( dev_priv ); + r128_do_engine_reset( dev ); + + return 0; +} + +static int r128_do_cleanup_cce( drm_device_t *dev ) +{ + if ( dev->dev_private ) { + drm_r128_private_t *dev_priv = dev->dev_private; + + DO_REMAPFREE( dev_priv->cce_ring, dev ); + DO_REMAPFREE( dev_priv->ring_rptr, dev ); + DO_REMAPFREE( dev_priv->buffers, dev ); +#if 0 + if ( !dev_priv->is_pci ) { + DO_REMAPFREE( dev_priv->agp_textures, dev ); + } +#endif + +#if defined(CONFIG_AGP_I460) && defined(__ia64__) + /* + * Free the page we grabbed for RPTR_ADDR + */ + if(dev->agp->agp_info.chipset == INTEL_460GX) { + atomic_dec(&virt_to_page(dev_priv->ring.head)->count); + clear_bit(PG_locked, + &virt_to_page(dev_priv->ring.head)->flags); + wake_up(&virt_to_page(dev_priv->ring.head)->wait); + free_page((unsigned long) dev_priv->ring.head); + } +#endif + + drm_free( dev->dev_private, sizeof(drm_r128_private_t), + DRM_MEM_DRIVER ); + dev->dev_private = NULL; + } + + return 0; +} + +int r128_cce_init( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_r128_init_t init; + + if ( copy_from_user( &init, (drm_r128_init_t *)arg, sizeof(init) ) ) + return -EFAULT; + + switch ( init.func ) { + case R128_INIT_CCE: + return r128_do_init_cce( dev, &init ); + case R128_CLEANUP_CCE: + return r128_do_cleanup_cce( dev ); + } + + return -EINVAL; +} + +int r128_cce_start( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_r128_private_t *dev_priv = dev->dev_private; + DRM_DEBUG( "%s\n", __FUNCTION__ ); + + if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || + dev->lock.pid != current->pid ) { + DRM_ERROR( "%s called without lock held\n", __FUNCTION__ ); + return -EINVAL; + } + if ( dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4 ) { + DRM_DEBUG( "%s while CCE running\n", __FUNCTION__ ); + return 0; + } + + r128_do_cce_start( dev_priv ); + + return 0; +} + +/* Stop the CCE. The engine must have been idled before calling this + * routine. + */ +int r128_cce_stop( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_r128_private_t *dev_priv = dev->dev_private; + drm_r128_cce_stop_t stop; + int ret; + DRM_DEBUG( "%s\n", __FUNCTION__ ); + + if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || + dev->lock.pid != current->pid ) { + DRM_ERROR( "%s called without lock held\n", __FUNCTION__ ); + return -EINVAL; + } + + if ( copy_from_user( &stop, (drm_r128_init_t *)arg, sizeof(stop) ) ) + return -EFAULT; + + /* Flush any pending CCE commands. This ensures any outstanding + * commands are exectuted by the engine before we turn it off. + */ + if ( stop.flush ) { + r128_do_cce_flush( dev_priv ); + } + + /* If we fail to make the engine go idle, we return an error + * code so that the DRM ioctl wrapper can try again. + */ + if ( stop.idle ) { + ret = r128_do_cce_idle( dev_priv ); + if ( ret < 0 ) return ret; + } + + /* Finally, we can turn off the CCE. If the engine isn't idle, + * we will get some dropped triangles as they won't be fully + * rendered before the CCE is shut down. + */ + r128_do_cce_stop( dev_priv ); + + /* Reset the engine */ + r128_do_engine_reset( dev ); + + return 0; +} + +/* Just reset the CCE ring. Called as part of an X Server engine reset. + */ +int r128_cce_reset( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_r128_private_t *dev_priv = dev->dev_private; + DRM_DEBUG( "%s\n", __FUNCTION__ ); + + if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || + dev->lock.pid != current->pid ) { + DRM_ERROR( "%s called without lock held\n", __FUNCTION__ ); + return -EINVAL; + } + if ( !dev_priv ) { + DRM_DEBUG( "%s called before init done\n", __FUNCTION__ ); + return -EINVAL; + } + + r128_do_cce_reset( dev_priv ); + + /* The CCE is no longer running after an engine reset */ + dev_priv->cce_running = 0; + + return 0; +} + +int r128_cce_idle( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_r128_private_t *dev_priv = dev->dev_private; + DRM_DEBUG( "%s\n", __FUNCTION__ ); + + if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || + dev->lock.pid != current->pid ) { + DRM_ERROR( "%s called without lock held\n", __FUNCTION__ ); + return -EINVAL; + } + + if ( dev_priv->cce_running ) { + r128_do_cce_flush( dev_priv ); + } + + return r128_do_cce_idle( dev_priv ); +} + +int r128_engine_reset( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + DRM_DEBUG( "%s\n", __FUNCTION__ ); + + if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || + dev->lock.pid != current->pid ) { + DRM_ERROR( "%s called without lock held\n", __FUNCTION__ ); + return -EINVAL; + } + + return r128_do_engine_reset( dev ); +} + + +/* ================================================================ + * Freelist management + */ +#define R128_BUFFER_USED 0xffffffff +#define R128_BUFFER_FREE 0 + +#if 0 +static int r128_freelist_init( drm_device_t *dev ) +{ + drm_device_dma_t *dma = dev->dma; + drm_r128_private_t *dev_priv = dev->dev_private; + drm_buf_t *buf; + drm_r128_buf_priv_t *buf_priv; + drm_r128_freelist_t *entry; + int i; + + dev_priv->head = drm_alloc( sizeof(drm_r128_freelist_t), + DRM_MEM_DRIVER ); + if ( dev_priv->head == NULL ) + return -ENOMEM; + + memset( dev_priv->head, 0, sizeof(drm_r128_freelist_t) ); + dev_priv->head->age = R128_BUFFER_USED; + + for ( i = 0 ; i < dma->buf_count ; i++ ) { + buf = dma->buflist[i]; + buf_priv = buf->dev_private; + + entry = drm_alloc( sizeof(drm_r128_freelist_t), + DRM_MEM_DRIVER ); + if ( !entry ) return -ENOMEM; + + entry->age = R128_BUFFER_FREE; + entry->buf = buf; + entry->prev = dev_priv->head; + entry->next = dev_priv->head->next; + if ( !entry->next ) + dev_priv->tail = entry; + + buf_priv->discard = 0; + buf_priv->dispatched = 0; + buf_priv->list_entry = entry; + + dev_priv->head->next = entry; + + if ( dev_priv->head->next ) + dev_priv->head->next->prev = entry; + } + + return 0; + +} +#endif + +drm_buf_t *r128_freelist_get( drm_device_t *dev ) +{ + drm_device_dma_t *dma = dev->dma; + drm_r128_private_t *dev_priv = dev->dev_private; + drm_r128_buf_priv_t *buf_priv; + drm_buf_t *buf; + int i, t; + + /* FIXME: Optimize -- use freelist code */ + + for ( i = 0 ; i < dma->buf_count ; i++ ) { + buf = dma->buflist[i]; + buf_priv = buf->dev_private; + if ( buf->pid == 0 ) + return buf; + } + + for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) { + u32 done_age = R128_READ( R128_LAST_DISPATCH_REG ); + + for ( i = 0 ; i < dma->buf_count ; i++ ) { + buf = dma->buflist[i]; + buf_priv = buf->dev_private; + if ( buf->pending && buf_priv->age <= done_age ) { + /* The buffer has been processed, so it + * can now be used. + */ + buf->pending = 0; + return buf; + } + } + udelay( 1 ); + } + + DRM_ERROR( "returning NULL!\n" ); + return NULL; +} + +void r128_freelist_reset( drm_device_t *dev ) +{ + drm_device_dma_t *dma = dev->dma; + int i; + + for ( i = 0 ; i < dma->buf_count ; i++ ) { + drm_buf_t *buf = dma->buflist[i]; + drm_r128_buf_priv_t *buf_priv = buf->dev_private; + buf_priv->age = 0; + } +} + + +/* ================================================================ + * CCE packet submission + */ + +int r128_wait_ring( drm_r128_private_t *dev_priv, int n ) +{ + drm_r128_ring_buffer_t *ring = &dev_priv->ring; + int i; + + for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { + ring->space = *ring->head - ring->tail; + if ( ring->space <= 0 ) + ring->space += ring->size; + + if ( ring->space >= n ) + return 0; + + udelay( 1 ); + } + + return -EBUSY; +} + +void r128_update_ring_snapshot( drm_r128_private_t *dev_priv ) +{ + drm_r128_ring_buffer_t *ring = &dev_priv->ring; + + ring->space = *ring->head - ring->tail; +#if R128_PERFORMANCE_BOXES + if ( ring->space == 0 ) + atomic_inc( &dev_priv->idle_count ); +#endif + if ( ring->space <= 0 ) + ring->space += ring->size; +} + +#if 0 +static int r128_verify_command( drm_r128_private_t *dev_priv, + u32 cmd, int *size ) +{ + int writing = 1; + + *size = 0; + + switch ( cmd & R128_CCE_PACKET_MASK ) { + case R128_CCE_PACKET0: + if ( (cmd & R128_CCE_PACKET0_REG_MASK) <= (0x1004 >> 2) && + (cmd & R128_CCE_PACKET0_REG_MASK) != + (R128_PM4_VC_FPU_SETUP >> 2) ) { + writing = 0; + } + *size = ((cmd & R128_CCE_PACKET_COUNT_MASK) >> 16) + 2; + break; + + case R128_CCE_PACKET1: + if ( (cmd & R128_CCE_PACKET1_REG0_MASK) <= (0x1004 >> 2) && + (cmd & R128_CCE_PACKET1_REG0_MASK) != + (R128_PM4_VC_FPU_SETUP >> 2) ) { + writing = 0; + } + if ( (cmd & R128_CCE_PACKET1_REG1_MASK) <= (0x1004 << 9) && + (cmd & R128_CCE_PACKET1_REG1_MASK) != + (R128_PM4_VC_FPU_SETUP << 9) ) { + writing = 0; + } + *size = 3; + break; + + case R128_CCE_PACKET2: + break; + + case R128_CCE_PACKET3: + *size = ((cmd & R128_CCE_PACKET_COUNT_MASK) >> 16) + 2; + break; + + } + + return writing; +} + +static int r128_submit_packet_ring_secure( drm_r128_private_t *dev_priv, + u32 *commands, int *count ) +{ +#if 0 + int write = dev_priv->sarea_priv->ring_write; + int *write_ptr = dev_priv->ring_start + write; + int c = *count; + u32 tmp = 0; + int psize = 0; + int writing = 1; + int timeout; + + while ( c > 0 ) { + tmp = *commands++; + if ( !psize ) { + writing = r128_verify_command( dev_priv, tmp, &psize ); + } + psize--; + + if ( writing ) { + write++; + *write_ptr++ = tmp; + } + if ( write >= dev_priv->ring_entries ) { + write = 0; + write_ptr = dev_priv->ring_start; + } + timeout = 0; + while ( write == *dev_priv->ring_read_ptr ) { + R128_READ( R128_PM4_BUFFER_DL_RPTR ); + if ( timeout++ >= dev_priv->usec_timeout ) + return -EBUSY; + udelay( 1 ); + } + c--; + } + + if ( write < 32 ) { + memcpy( dev_priv->ring_end, + dev_priv->ring_start, + write * sizeof(u32) ); + } + + /* Make sure WC cache has been flushed */ + r128_flush_write_combine(); + + dev_priv->sarea_priv->ring_write = write; + R128_WRITE( R128_PM4_BUFFER_DL_WPTR, write ); + + *count = 0; +#endif + return 0; +} + +static int r128_submit_packet_ring_insecure( drm_r128_private_t *dev_priv, + u32 *commands, int *count ) +{ +#if 0 + int write = dev_priv->sarea_priv->ring_write; + int *write_ptr = dev_priv->ring_start + write; + int c = *count; + int timeout; + + while ( c > 0 ) { + write++; + *write_ptr++ = *commands++; + if ( write >= dev_priv->ring_entries ) { + write = 0; + write_ptr = dev_priv->ring_start; + } + + timeout = 0; + while ( write == *dev_priv->ring_read_ptr ) { + R128_READ( R128_PM4_BUFFER_DL_RPTR ); + if ( timeout++ >= dev_priv->usec_timeout ) + return -EBUSY; + udelay( 1 ); + } + c--; + } + + if ( write < 32 ) { + memcpy( dev_priv->ring_end, + dev_priv->ring_start, + write * sizeof(u32) ); + } + + /* Make sure WC cache has been flushed */ + r128_flush_write_combine(); + + dev_priv->sarea_priv->ring_write = write; + R128_WRITE( R128_PM4_BUFFER_DL_WPTR, write ); + + *count = 0; +#endif + return 0; +} +#endif + +/* Internal packet submission routine. This uses the insecure versions + * of the packet submission functions, and thus should only be used for + * packets generated inside the kernel module. + */ +int r128_do_submit_packet( drm_r128_private_t *dev_priv, + u32 *buffer, int count ) +{ + int c = count; + int ret = 0; + +#if 0 + int left = 0; + + if ( c >= dev_priv->ring_entries ) { + c = dev_priv->ring_entries - 1; + left = count - c; + } + + /* Since this is only used by the kernel we can use the + * insecure ring buffer submit packet routine. + */ + ret = r128_submit_packet_ring_insecure( dev_priv, buffer, &c ); + c += left; +#endif + + return ( ret < 0 ) ? ret : c; +} + +/* External packet submission routine. This uses the secure versions + * by default, and can thus submit packets received from user space. + */ +int r128_cce_packet( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_r128_private_t *dev_priv = dev->dev_private; + drm_r128_packet_t packet; + u32 *buffer; + int c; + int size; + int ret = 0; + +#if 0 + /* GH: Disable packet submission for now. + */ + return -EINVAL; +#endif + + if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || + dev->lock.pid != current->pid ) { + DRM_ERROR( "r128_submit_packet called without lock held\n" ); + return -EINVAL; + } + + if ( copy_from_user( &packet, (drm_r128_packet_t *)arg, + sizeof(packet) ) ) + return -EFAULT; + +#if 0 + c = packet.count; + size = c * sizeof(*buffer); + + { + int left = 0; + + if ( c >= dev_priv->ring_entries ) { + c = dev_priv->ring_entries - 1; + size = c * sizeof(*buffer); + left = packet.count - c; + } + + buffer = kmalloc( size, 0 ); + if ( buffer == NULL) + return -ENOMEM; + if ( copy_from_user( buffer, packet.buffer, size ) ) + return -EFAULT; + + if ( dev_priv->cce_secure ) { + ret = r128_submit_packet_ring_secure( dev_priv, + buffer, &c ); + } else { + ret = r128_submit_packet_ring_insecure( dev_priv, + buffer, &c ); + } + c += left; + } + + kfree( buffer ); +#else + c = 0; +#endif + + packet.count = c; + if ( copy_to_user( (drm_r128_packet_t *)arg, &packet, + sizeof(packet) ) ) + return -EFAULT; + + if ( ret ) { + return ret; + } else if ( c > 0 ) { + return -EAGAIN; + } + return 0; +} + +#if 0 +static int r128_send_vertbufs( drm_device_t *dev, drm_r128_vertex_t *v ) +{ + drm_device_dma_t *dma = dev->dma; + drm_r128_private_t *dev_priv = dev->dev_private; + drm_r128_buf_priv_t *buf_priv; + drm_buf_t *buf; + int i, ret; + RING_LOCALS; + + /* Make sure we have valid data */ + for (i = 0; i < v->send_count; i++) { + int idx = v->send_indices[i]; + + if (idx < 0 || idx >= dma->buf_count) { + DRM_ERROR("Index %d (of %d max)\n", + idx, dma->buf_count - 1); + return -EINVAL; + } + buf = dma->buflist[idx]; + if (buf->pid != current->pid) { + DRM_ERROR("Process %d using buffer owned by %d\n", + current->pid, buf->pid); + return -EINVAL; + } + if (buf->pending) { + DRM_ERROR("Sending pending buffer:" + " buffer %d, offset %d\n", + v->send_indices[i], i); + return -EINVAL; + } + } + + /* Wait for idle, if we've wrapped to make sure that all pending + buffers have been processed */ + if (dev_priv->submit_age == R128_MAX_VBUF_AGE) { + if ((ret = r128_do_cce_idle(dev)) < 0) return ret; + dev_priv->submit_age = 0; + r128_freelist_reset(dev); + } + + /* Make sure WC cache has been flushed (if in PIO mode) */ + if (!dev_priv->cce_is_bm_mode) r128_flush_write_combine(); + + /* FIXME: Add support for sending vertex buffer to the CCE here + instead of in client code. The v->prim holds the primitive + type that should be drawn. Loop over the list buffers in + send_indices[] and submit a packet for each VB. + + This will require us to loop over the clip rects here as + well, which implies that we extend the kernel driver to allow + cliprects to be stored here. Note that the cliprects could + possibly come from the X server instead of the client, but + this will require additional changes to the DRI to allow for + this optimization. */ + + /* Submit a CCE packet that writes submit_age to R128_VB_AGE_REG */ +#if 0 + cce_buffer[0] = R128CCE0(R128_CCE_PACKET0, R128_VB_AGE_REG, 0); + cce_buffer[1] = dev_priv->submit_age; + + if ((ret = r128_do_submit_packet(dev, cce_buffer, 2)) < 0) { + /* Until we add support for sending VBs to the CCE in + this routine, we can recover from this error. After + we add that support, we won't be able to easily + recover, so we will probably have to implement + another mechanism for handling timeouts from packets + submitted directly by the kernel. */ + return ret; + } +#else + BEGIN_RING( 2 ); + + OUT_RING( CCE_PACKET0( R128_VB_AGE_REG, 0 ) ); + OUT_RING( dev_priv->submit_age ); + + ADVANCE_RING(); +#endif + /* Now that the submit packet request has succeeded, we can mark + the buffers as pending */ + for (i = 0; i < v->send_count; i++) { + buf = dma->buflist[v->send_indices[i]]; + buf->pending = 1; + + buf_priv = buf->dev_private; + buf_priv->age = dev_priv->submit_age; + } + + dev_priv->submit_age++; + + return 0; +} +#endif + + + + +static int r128_cce_get_buffers( drm_device_t *dev, drm_dma_t *d ) +{ + int i; + drm_buf_t *buf; + + for ( i = d->granted_count ; i < d->request_count ; i++ ) { + buf = r128_freelist_get( dev ); + if ( !buf ) return -EAGAIN; + + buf->pid = current->pid; + + if ( copy_to_user( &d->request_indices[i], &buf->idx, + sizeof(buf->idx) ) ) + return -EFAULT; + if ( copy_to_user( &d->request_sizes[i], &buf->total, + sizeof(buf->total) ) ) + return -EFAULT; + + d->granted_count++; + } + return 0; +} + +int r128_cce_buffers( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_device_dma_t *dma = dev->dma; + int ret = 0; + drm_dma_t d; + + if ( copy_from_user( &d, (drm_dma_t *) arg, sizeof(d) ) ) + return -EFAULT; + + if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || + dev->lock.pid != current->pid ) { + DRM_ERROR( "%s called without lock held\n", __FUNCTION__ ); + return -EINVAL; + } + + /* Please don't send us buffers. + */ + if ( d.send_count != 0 ) { + DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n", + current->pid, d.send_count ); + return -EINVAL; + } + + /* We'll send you buffers. + */ + if ( d.request_count < 0 || d.request_count > dma->buf_count ) { + DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n", + current->pid, d.request_count, dma->buf_count ); + return -EINVAL; + } + + d.granted_count = 0; + + if ( d.request_count ) { + ret = r128_cce_get_buffers( dev, &d ); + } + + if ( copy_to_user( (drm_dma_t *) arg, &d, sizeof(d) ) ) + return -EFAULT; + + return ret; +} diff -urN linux-2.4.10/drivers/char/drm-4.0/r128_context.c linux-2.4.10-lia/drivers/char/drm-4.0/r128_context.c --- linux-2.4.10/drivers/char/drm-4.0/r128_context.c Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/r128_context.c Wed Aug 15 20:52:12 2001 @@ -0,0 +1,217 @@ +/* r128_context.c -- IOCTLs for r128 contexts -*- linux-c -*- + * Created: Mon Dec 13 09:51:35 1999 by faith@precisioninsight.com + * + * Copyright 1999, 2000 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Author: Rickard E. (Rik) Faith + * + */ + +#define __NO_VERSION__ +#include "drmP.h" +#include "r128_drv.h" + +extern drm_ctx_t r128_res_ctx; + +static int r128_alloc_queue(drm_device_t *dev) +{ + return drm_ctxbitmap_next(dev); +} + +int r128_context_switch(drm_device_t *dev, int old, int new) +{ + char buf[64]; + + atomic_inc(&dev->total_ctx); + + if (test_and_set_bit(0, &dev->context_flag)) { + DRM_ERROR("Reentering -- FIXME\n"); + return -EBUSY; + } + +#if DRM_DMA_HISTOGRAM + dev->ctx_start = get_cycles(); +#endif + + DRM_DEBUG("Context switch from %d to %d\n", old, new); + + if (new == dev->last_context) { + clear_bit(0, &dev->context_flag); + return 0; + } + + if (drm_flags & DRM_FLAG_NOCTX) { + r128_context_switch_complete(dev, new); + } else { + sprintf(buf, "C %d %d\n", old, new); + drm_write_string(dev, buf); + } + + return 0; +} + +int r128_context_switch_complete(drm_device_t *dev, int new) +{ + dev->last_context = new; /* PRE/POST: This is the _only_ writer. */ + dev->last_switch = jiffies; + + if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { + DRM_ERROR("Lock isn't held after context switch\n"); + } + + /* If a context switch is ever initiated + when the kernel holds the lock, release + that lock here. */ +#if DRM_DMA_HISTOGRAM + atomic_inc(&dev->histo.ctx[drm_histogram_slot(get_cycles() + - dev->ctx_start)]); + +#endif + clear_bit(0, &dev->context_flag); + wake_up(&dev->context_wait); + + return 0; +} + + +int r128_resctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_ctx_res_t res; + drm_ctx_t ctx; + int i; + + DRM_DEBUG("%d\n", DRM_RESERVED_CONTEXTS); + if (copy_from_user(&res, (drm_ctx_res_t *)arg, sizeof(res))) + return -EFAULT; + if (res.count >= DRM_RESERVED_CONTEXTS) { + memset(&ctx, 0, sizeof(ctx)); + for (i = 0; i < DRM_RESERVED_CONTEXTS; i++) { + ctx.handle = i; + if (copy_to_user(&res.contexts[i], + &i, + sizeof(i))) + return -EFAULT; + } + } + res.count = DRM_RESERVED_CONTEXTS; + if (copy_to_user((drm_ctx_res_t *)arg, &res, sizeof(res))) + return -EFAULT; + return 0; +} + + +int r128_addctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ctx_t ctx; + + if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx))) + return -EFAULT; + if ((ctx.handle = r128_alloc_queue(dev)) == DRM_KERNEL_CONTEXT) { + /* Skip kernel's context and get a new one. */ + ctx.handle = r128_alloc_queue(dev); + } + DRM_DEBUG("%d\n", ctx.handle); + if (ctx.handle == -1) { + DRM_DEBUG("Not enough free contexts.\n"); + /* Should this return -EBUSY instead? */ + return -ENOMEM; + } + + if (copy_to_user((drm_ctx_t *)arg, &ctx, sizeof(ctx))) + return -EFAULT; + return 0; +} + +int r128_modctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_ctx_t ctx; + + if (copy_from_user(&ctx, (drm_ctx_t*)arg, sizeof(ctx))) + return -EFAULT; + if (ctx.flags==_DRM_CONTEXT_PRESERVED) + r128_res_ctx.handle=ctx.handle; + return 0; +} + +int r128_getctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_ctx_t ctx; + + if (copy_from_user(&ctx, (drm_ctx_t*)arg, sizeof(ctx))) + return -EFAULT; + /* This is 0, because we don't hanlde any context flags */ + ctx.flags = 0; + if (copy_to_user((drm_ctx_t*)arg, &ctx, sizeof(ctx))) + return -EFAULT; + return 0; +} + +int r128_switchctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ctx_t ctx; + + if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx))) + return -EFAULT; + DRM_DEBUG("%d\n", ctx.handle); + return r128_context_switch(dev, dev->last_context, ctx.handle); +} + +int r128_newctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ctx_t ctx; + + if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx))) + return -EFAULT; + DRM_DEBUG("%d\n", ctx.handle); + r128_context_switch_complete(dev, ctx.handle); + + return 0; +} + +int r128_rmctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ctx_t ctx; + + if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx))) + return -EFAULT; + DRM_DEBUG("%d\n", ctx.handle); + drm_ctxbitmap_free(dev, ctx.handle); + + return 0; +} diff -urN linux-2.4.10/drivers/char/drm-4.0/r128_drm.h linux-2.4.10-lia/drivers/char/drm-4.0/r128_drm.h --- linux-2.4.10/drivers/char/drm-4.0/r128_drm.h Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/r128_drm.h Wed Aug 15 20:52:12 2001 @@ -0,0 +1,272 @@ +/* r128_drm.h -- Public header for the r128 driver -*- linux-c -*- + * Created: Wed Apr 5 19:24:19 2000 by kevin@precisioninsight.com + * + * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Kevin E. Martin + * Gareth Hughes + * + */ + +#ifndef _R128_DRM_H_ +#define _R128_DRM_H_ + +/* WARNING: If you change any of these defines, make sure to change the + * defines in the X server file (r128_sarea.h) + */ +#ifndef __R128_SAREA_DEFINES__ +#define __R128_SAREA_DEFINES__ + +/* What needs to be changed for the current vertex buffer? + */ +#define R128_UPLOAD_CONTEXT 0x001 +#define R128_UPLOAD_SETUP 0x002 +#define R128_UPLOAD_TEX0 0x004 +#define R128_UPLOAD_TEX1 0x008 +#define R128_UPLOAD_TEX0IMAGES 0x010 +#define R128_UPLOAD_TEX1IMAGES 0x020 +#define R128_UPLOAD_CORE 0x040 +#define R128_UPLOAD_MASKS 0x080 +#define R128_UPLOAD_WINDOW 0x100 +#define R128_UPLOAD_CLIPRECTS 0x200 /* handled client-side */ +#define R128_REQUIRE_QUIESCENCE 0x400 +#define R128_UPLOAD_ALL 0x7ff + +#define R128_FRONT 0x1 +#define R128_BACK 0x2 +#define R128_DEPTH 0x4 + +/* Primitive types + */ +#define R128_POINTS 0x1 +#define R128_LINES 0x2 +#define R128_LINE_STRIP 0x3 +#define R128_TRIANGLES 0x4 +#define R128_TRIANGLE_FAN 0x5 +#define R128_TRIANGLE_STRIP 0x6 + +/* Vertex/indirect buffer size + */ +#if 1 +#define R128_BUFFER_SIZE 16384 +#else +#define R128_BUFFER_SIZE (128 * 1024) +#endif + +/* Byte offsets for indirect buffer data + */ +#define R128_INDEX_PRIM_OFFSET 20 +#define R128_HOSTDATA_BLIT_OFFSET 32 + +/* 2048x2048 @ 32bpp texture requires this many indirect buffers + */ +#define R128_MAX_BLIT_BUFFERS ((2048 * 2048 * 4) / R128_BUFFER_SIZE) + +/* Keep these small for testing. + */ +#define R128_NR_SAREA_CLIPRECTS 12 + +/* There are 2 heaps (local/AGP). Each region within a heap is a + * minimum of 64k, and there are at most 64 of them per heap. + */ +#define R128_LOCAL_TEX_HEAP 0 +#define R128_AGP_TEX_HEAP 1 +#define R128_NR_TEX_HEAPS 2 +#define R128_NR_TEX_REGIONS 64 +#define R128_LOG_TEX_GRANULARITY 16 + +#define R128_NR_CONTEXT_REGS 12 +#define R128_TEX_MAXLEVELS 11 + +#endif /* __R128_SAREA_DEFINES__ */ + +typedef struct { + /* Context state - can be written in one large chunk */ + unsigned int dst_pitch_offset_c; + unsigned int dp_gui_master_cntl_c; + unsigned int sc_top_left_c; + unsigned int sc_bottom_right_c; + unsigned int z_offset_c; + unsigned int z_pitch_c; + unsigned int z_sten_cntl_c; + unsigned int tex_cntl_c; + unsigned int misc_3d_state_cntl_reg; + unsigned int texture_clr_cmp_clr_c; + unsigned int texture_clr_cmp_msk_c; + unsigned int fog_color_c; + + /* Texture state */ + unsigned int tex_size_pitch_c; + unsigned int constant_color_c; + + /* Setup state */ + unsigned int pm4_vc_fpu_setup; + unsigned int setup_cntl; + + /* Mask state */ + unsigned int dp_write_mask; + unsigned int sten_ref_mask_c; + unsigned int plane_3d_mask_c; + + /* Window state */ + unsigned int window_xy_offset; + + /* Core state */ + unsigned int scale_3d_cntl; +} drm_r128_context_regs_t; + +/* Setup registers for each texture unit */ +typedef struct { + unsigned int tex_cntl; + unsigned int tex_combine_cntl; + unsigned int tex_size_pitch; + unsigned int tex_offset[R128_TEX_MAXLEVELS]; + unsigned int tex_border_color; +} drm_r128_texture_regs_t; + + +typedef struct drm_tex_region { + unsigned char next, prev; + unsigned char in_use; + int age; +} drm_tex_region_t; + +typedef struct drm_r128_sarea { + /* The channel for communication of state information to the kernel + * on firing a vertex buffer. + */ + drm_r128_context_regs_t context_state; + drm_r128_texture_regs_t tex_state[R128_NR_TEX_HEAPS]; + unsigned int dirty; + unsigned int vertsize; + unsigned int vc_format; + + /* The current cliprects, or a subset thereof. + */ + drm_clip_rect_t boxes[R128_NR_SAREA_CLIPRECTS]; + unsigned int nbox; + + /* Counters for client-side throttling of rendering clients. + */ + unsigned int last_frame; + unsigned int last_dispatch; + + drm_tex_region_t tex_list[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS+1]; + int tex_age[R128_NR_TEX_HEAPS]; + int ctx_owner; +} drm_r128_sarea_t; + + +/* WARNING: If you change any of these defines, make sure to change the + * defines in the Xserver file (xf86drmR128.h) + */ +typedef struct drm_r128_init { + enum { + R128_INIT_CCE = 0x01, + R128_CLEANUP_CCE = 0x02 + } func; + int sarea_priv_offset; + int is_pci; + int cce_mode; + int cce_secure; + int ring_size; + int usec_timeout; + + unsigned int fb_bpp; + unsigned int front_offset, front_pitch; + unsigned int back_offset, back_pitch; + unsigned int depth_bpp; + unsigned int depth_offset, depth_pitch; + unsigned int span_offset; + + unsigned int fb_offset; + unsigned int mmio_offset; + unsigned int ring_offset; + unsigned int ring_rptr_offset; + unsigned int buffers_offset; + unsigned int agp_textures_offset; +} drm_r128_init_t; + +typedef struct drm_r128_cce_stop { + int flush; + int idle; +} drm_r128_cce_stop_t; + +typedef struct drm_r128_clear { + unsigned int flags; + int x, y, w, h; + unsigned int clear_color; + unsigned int clear_depth; +} drm_r128_clear_t; + +typedef struct drm_r128_vertex { + int prim; + int idx; /* Index of vertex buffer */ + int count; /* Number of vertices in buffer */ + int discard; /* Client finished with buffer? */ +} drm_r128_vertex_t; + +typedef struct drm_r128_indices { + int prim; + int idx; + int start; + int end; + int discard; /* Client finished with buffer? */ +} drm_r128_indices_t; + +typedef struct drm_r128_blit { + int idx; + int pitch; + int offset; + int format; + unsigned short x, y; + unsigned short width, height; +} drm_r128_blit_t; + +typedef struct drm_r128_depth { + enum { + R128_WRITE_SPAN = 0x01, + R128_WRITE_PIXELS = 0x02, + R128_READ_SPAN = 0x03, + R128_READ_PIXELS = 0x04 + } func; + int n; + int *x; + int *y; + unsigned int *buffer; + unsigned char *mask; +} drm_r128_depth_t; + +typedef struct drm_r128_stipple { + unsigned int *mask; +} drm_r128_stipple_t; + +typedef struct drm_r128_packet { + unsigned int *buffer; + int count; + int flags; +} drm_r128_packet_t; + +#endif diff -urN linux-2.4.10/drivers/char/drm-4.0/r128_drv.c linux-2.4.10-lia/drivers/char/drm-4.0/r128_drv.c --- linux-2.4.10/drivers/char/drm-4.0/r128_drv.c Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/r128_drv.c Mon Aug 20 18:09:34 2001 @@ -0,0 +1,699 @@ +/* r128_drv.c -- ATI Rage 128 driver -*- linux-c -*- + * Created: Mon Dec 13 09:47:27 1999 by faith@precisioninsight.com + * + * Copyright 1999, 2000 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rickard E. (Rik) Faith + * Kevin E. Martin + * Gareth Hughes + * + */ + +#include +#include "drmP.h" +#include "r128_drv.h" + +#define R128_NAME "r128" +#define R128_DESC "ATI Rage 128" +#define R128_DATE "20001215" +#define R128_MAJOR 2 +#define R128_MINOR 1 +#define R128_PATCHLEVEL 2 + +static drm_device_t r128_device; +drm_ctx_t r128_res_ctx; + +static struct file_operations r128_fops = { +#if LINUX_VERSION_CODE >= 0x020400 + /* This started being used during 2.4.0-test */ + owner: THIS_MODULE, +#endif + open: r128_open, + flush: drm_flush, + release: r128_release, + ioctl: r128_ioctl, + mmap: drm_mmap, + read: drm_read, + fasync: drm_fasync, + poll: drm_poll, +}; + +static struct miscdevice r128_misc = { + minor: MISC_DYNAMIC_MINOR, + name: R128_NAME, + fops: &r128_fops, +}; + +static drm_ioctl_desc_t r128_ioctls[] = { + [DRM_IOCTL_NR(DRM_IOCTL_VERSION)] = { r128_version, 0, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_GET_UNIQUE)] = { drm_getunique, 0, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_GET_MAGIC)] = { drm_getmagic, 0, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_IRQ_BUSID)] = { drm_irq_busid, 0, 1 }, + + [DRM_IOCTL_NR(DRM_IOCTL_SET_UNIQUE)] = { drm_setunique, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_BLOCK)] = { drm_block, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_UNBLOCK)] = { drm_unblock, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_AUTH_MAGIC)] = { drm_authmagic, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_ADD_MAP)] = { drm_addmap, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_ADD_BUFS)] = { r128_addbufs, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_MARK_BUFS)] = { drm_markbufs, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_INFO_BUFS)] = { drm_infobufs, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_MAP_BUFS)] = { r128_mapbufs, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_FREE_BUFS)] = { drm_freebufs, 1, 0 }, + + [DRM_IOCTL_NR(DRM_IOCTL_ADD_CTX)] = { r128_addctx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_RM_CTX)] = { r128_rmctx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_MOD_CTX)] = { r128_modctx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_GET_CTX)] = { r128_getctx, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_SWITCH_CTX)] = { r128_switchctx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_NEW_CTX)] = { r128_newctx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_RES_CTX)] = { r128_resctx, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_ADD_DRAW)] = { drm_adddraw, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_RM_DRAW)] = { drm_rmdraw, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_DMA)] = { r128_cce_buffers, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_LOCK)] = { r128_lock, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_UNLOCK)] = { r128_unlock, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_FINISH)] = { drm_finish, 1, 0 }, + +#if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE) + [DRM_IOCTL_NR(DRM_IOCTL_AGP_ACQUIRE)] = { drm_agp_acquire, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_RELEASE)] = { drm_agp_release, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_ENABLE)] = { drm_agp_enable, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_INFO)] = { drm_agp_info, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_ALLOC)] = { drm_agp_alloc, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_FREE)] = { drm_agp_free, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_BIND)] = { drm_agp_bind, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_UNBIND)] = { drm_agp_unbind, 1, 1 }, +#endif + + [DRM_IOCTL_NR(DRM_IOCTL_R128_INIT)] = { r128_cce_init, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_R128_CCE_START)] = { r128_cce_start, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_R128_CCE_STOP)] = { r128_cce_stop, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_R128_CCE_RESET)] = { r128_cce_reset, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_R128_CCE_IDLE)] = { r128_cce_idle, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_R128_RESET)] = { r128_engine_reset, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_R128_SWAP)] = { r128_cce_swap, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_R128_CLEAR)] = { r128_cce_clear, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_R128_VERTEX)] = { r128_cce_vertex, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_R128_INDICES)] = { r128_cce_indices, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_R128_BLIT)] = { r128_cce_blit, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_R128_DEPTH)] = { r128_cce_depth, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_R128_STIPPLE)] = { r128_cce_stipple, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_R128_PACKET)] = { r128_cce_packet, 1, 0 }, +}; +#define R128_IOCTL_COUNT DRM_ARRAY_SIZE(r128_ioctls) + +#ifdef MODULE +static char *r128 = NULL; +#endif + +MODULE_AUTHOR("VA Linux Systems, Inc."); +MODULE_DESCRIPTION("r128"); +MODULE_PARM(r128, "s"); + +#ifndef MODULE +/* r128_options is called by the kernel to parse command-line options + * passed via the boot-loader (e.g., LILO). It calls the insmod option + * routine, drm_parse_drm. + */ + +static int __init r128_options(char *str) +{ + drm_parse_options(str); + return 1; +} + +__setup("r128=", r128_options); +#endif + +static int r128_setup(drm_device_t *dev) +{ + int i; + + atomic_set(&dev->ioctl_count, 0); + atomic_set(&dev->vma_count, 0); + dev->buf_use = 0; + atomic_set(&dev->buf_alloc, 0); + + drm_dma_setup(dev); + + atomic_set(&dev->total_open, 0); + atomic_set(&dev->total_close, 0); + atomic_set(&dev->total_ioctl, 0); + atomic_set(&dev->total_irq, 0); + atomic_set(&dev->total_ctx, 0); + atomic_set(&dev->total_locks, 0); + atomic_set(&dev->total_unlocks, 0); + atomic_set(&dev->total_contends, 0); + atomic_set(&dev->total_sleeps, 0); + + for (i = 0; i < DRM_HASH_SIZE; i++) { + dev->magiclist[i].head = NULL; + dev->magiclist[i].tail = NULL; + } + dev->maplist = NULL; + dev->map_count = 0; + dev->vmalist = NULL; + dev->lock.hw_lock = NULL; + init_waitqueue_head(&dev->lock.lock_queue); + dev->queue_count = 0; + dev->queue_reserved = 0; + dev->queue_slots = 0; + dev->queuelist = NULL; + dev->irq = 0; + dev->context_flag = 0; + dev->interrupt_flag = 0; + dev->dma_flag = 0; + dev->last_context = 0; + dev->last_switch = 0; + dev->last_checked = 0; + init_timer(&dev->timer); + init_waitqueue_head(&dev->context_wait); + + dev->ctx_start = 0; + dev->lck_start = 0; + + dev->buf_rp = dev->buf; + dev->buf_wp = dev->buf; + dev->buf_end = dev->buf + DRM_BSZ; + dev->buf_async = NULL; + init_waitqueue_head(&dev->buf_readers); + init_waitqueue_head(&dev->buf_writers); + + r128_res_ctx.handle=-1; + + DRM_DEBUG("\n"); + + /* The kernel's context could be created here, but is now created + in drm_dma_enqueue. This is more resource-efficient for + hardware that does not do DMA, but may mean that + drm_select_queue fails between the time the interrupt is + initialized and the time the queues are initialized. */ + + return 0; +} + + +static int r128_takedown(drm_device_t *dev) +{ + int i; + drm_magic_entry_t *pt, *next; + drm_map_t *map; + drm_vma_entry_t *vma, *vma_next; + + DRM_DEBUG("\n"); + + down(&dev->struct_sem); + del_timer(&dev->timer); + + if (dev->devname) { + drm_free(dev->devname, strlen(dev->devname)+1, DRM_MEM_DRIVER); + dev->devname = NULL; + } + + if (dev->unique) { + drm_free(dev->unique, strlen(dev->unique)+1, DRM_MEM_DRIVER); + dev->unique = NULL; + dev->unique_len = 0; + } + /* Clear pid list */ + for (i = 0; i < DRM_HASH_SIZE; i++) { + for (pt = dev->magiclist[i].head; pt; pt = next) { + next = pt->next; + drm_free(pt, sizeof(*pt), DRM_MEM_MAGIC); + } + dev->magiclist[i].head = dev->magiclist[i].tail = NULL; + } + +#if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE) + /* Clear AGP information */ + if (dev->agp) { + drm_agp_mem_t *entry; + drm_agp_mem_t *nexte; + + /* Remove AGP resources, but leave dev->agp + intact until r128_cleanup is called. */ + for (entry = dev->agp->memory; entry; entry = nexte) { + nexte = entry->next; + if (entry->bound) drm_unbind_agp(entry->memory); + drm_free_agp(entry->memory, entry->pages); + drm_free(entry, sizeof(*entry), DRM_MEM_AGPLISTS); + } + dev->agp->memory = NULL; + + if (dev->agp->acquired) _drm_agp_release(); + + dev->agp->acquired = 0; + dev->agp->enabled = 0; + } +#endif + + /* Clear vma list (only built for debugging) */ + if (dev->vmalist) { + for (vma = dev->vmalist; vma; vma = vma_next) { + vma_next = vma->next; + drm_free(vma, sizeof(*vma), DRM_MEM_VMAS); + } + dev->vmalist = NULL; + } + + /* Clear map area and mtrr information */ + if (dev->maplist) { + for (i = 0; i < dev->map_count; i++) { + map = dev->maplist[i]; + switch (map->type) { + case _DRM_REGISTERS: + case _DRM_FRAME_BUFFER: +#ifdef CONFIG_MTRR + if (map->mtrr >= 0) { + int retcode; + retcode = mtrr_del(map->mtrr, + map->offset, + map->size); + DRM_DEBUG("mtrr_del = %d\n", retcode); + } +#endif + drm_ioremapfree(map->handle, map->size, dev); + break; + case _DRM_SHM: + drm_free_pages((unsigned long)map->handle, + drm_order(map->size) + - PAGE_SHIFT, + DRM_MEM_SAREA); + break; + case _DRM_AGP: + /* Do nothing here, because this is all + handled in the AGP/GART driver. */ + break; + } + drm_free(map, sizeof(*map), DRM_MEM_MAPS); + } + drm_free(dev->maplist, + dev->map_count * sizeof(*dev->maplist), + DRM_MEM_MAPS); + dev->maplist = NULL; + dev->map_count = 0; + } + + drm_dma_takedown(dev); + + dev->queue_count = 0; + if (dev->lock.hw_lock) { + dev->lock.hw_lock = NULL; /* SHM removed */ + dev->lock.pid = 0; + wake_up_interruptible(&dev->lock.lock_queue); + } + up(&dev->struct_sem); + + return 0; +} + +/* r128_init is called via init_module at module load time, or via + * linux/init/main.c (this is not currently supported). */ + +static int __init r128_init(void) +{ + int retcode; + drm_device_t *dev = &r128_device; + + DRM_DEBUG("\n"); + + memset((void *)dev, 0, sizeof(*dev)); + dev->count_lock = SPIN_LOCK_UNLOCKED; + sema_init(&dev->struct_sem, 1); + +#ifdef MODULE + drm_parse_options(r128); +#endif + + if ((retcode = misc_register(&r128_misc))) { + DRM_ERROR("Cannot register \"%s\"\n", R128_NAME); + return retcode; + } + dev->device = MKDEV(MISC_MAJOR, r128_misc.minor); + dev->name = R128_NAME; + + drm_mem_init(); + drm_proc_init(dev); + +#if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE) + dev->agp = drm_agp_init(); + if (dev->agp == NULL) { + DRM_ERROR("Cannot initialize agpgart module.\n"); + drm_proc_cleanup(); + misc_deregister(&r128_misc); + r128_takedown(dev); + return -ENOMEM; + } + +#ifdef CONFIG_MTRR + dev->agp->agp_mtrr = mtrr_add(dev->agp->agp_info.aper_base, + dev->agp->agp_info.aper_size*1024*1024, + MTRR_TYPE_WRCOMB, + 1); +#endif +#endif + + if((retcode = drm_ctxbitmap_init(dev))) { + DRM_ERROR("Cannot allocate memory for context bitmap.\n"); + drm_proc_cleanup(); + misc_deregister(&r128_misc); + r128_takedown(dev); + return retcode; + } + + DRM_INFO("Initialized %s %d.%d.%d %s on minor %d\n", + R128_NAME, + R128_MAJOR, + R128_MINOR, + R128_PATCHLEVEL, + R128_DATE, + r128_misc.minor); + + return 0; +} + +/* r128_cleanup is called via cleanup_module at module unload time. */ + +static void __exit r128_cleanup(void) +{ + drm_device_t *dev = &r128_device; + + DRM_DEBUG("\n"); + + drm_proc_cleanup(); + if (misc_deregister(&r128_misc)) { + DRM_ERROR("Cannot unload module\n"); + } else { + DRM_INFO("Module unloaded\n"); + } + drm_ctxbitmap_cleanup(dev); + r128_takedown(dev); +#if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE) + if (dev->agp) { + drm_agp_uninit(); + drm_free(dev->agp, sizeof(*dev->agp), DRM_MEM_AGPLISTS); + dev->agp = NULL; + } +#endif +} + +module_init(r128_init); +module_exit(r128_cleanup); + + +int r128_version(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_version_t version; + int len; + + if (copy_from_user(&version, + (drm_version_t *)arg, + sizeof(version))) + return -EFAULT; + +#define DRM_COPY(name,value) \ + len = strlen(value); \ + if (len > name##_len) len = name##_len; \ + name##_len = strlen(value); \ + if (len && name) { \ + if (copy_to_user(name, value, len)) \ + return -EFAULT; \ + } + + version.version_major = R128_MAJOR; + version.version_minor = R128_MINOR; + version.version_patchlevel = R128_PATCHLEVEL; + + DRM_COPY(version.name, R128_NAME); + DRM_COPY(version.date, R128_DATE); + DRM_COPY(version.desc, R128_DESC); + + if (copy_to_user((drm_version_t *)arg, + &version, + sizeof(version))) + return -EFAULT; + return 0; +} + +int r128_open(struct inode *inode, struct file *filp) +{ + drm_device_t *dev = &r128_device; + int retcode = 0; + + DRM_DEBUG("open_count = %d\n", dev->open_count); + if (!(retcode = drm_open_helper(inode, filp, dev))) { +#if LINUX_VERSION_CODE < 0x020333 + MOD_INC_USE_COUNT; /* Needed before Linux 2.3.51 */ +#endif + atomic_inc(&dev->total_open); + spin_lock(&dev->count_lock); + if (!dev->open_count++) { + spin_unlock(&dev->count_lock); + return r128_setup(dev); + } + spin_unlock(&dev->count_lock); + } + + return retcode; +} + +int r128_release(struct inode *inode, struct file *filp) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev; + int retcode = 0; + + lock_kernel(); + dev = priv->dev; + DRM_DEBUG("open_count = %d\n", dev->open_count); + if (!(retcode = drm_release(inode, filp))) { +#if LINUX_VERSION_CODE < 0x020333 + MOD_DEC_USE_COUNT; /* Needed before Linux 2.3.51 */ +#endif + atomic_inc(&dev->total_close); + spin_lock(&dev->count_lock); + if (!--dev->open_count) { + if (atomic_read(&dev->ioctl_count) || dev->blocked) { + DRM_ERROR("Device busy: %d %d\n", + atomic_read(&dev->ioctl_count), + dev->blocked); + spin_unlock(&dev->count_lock); + unlock_kernel(); + return -EBUSY; + } + spin_unlock(&dev->count_lock); + unlock_kernel(); + return r128_takedown(dev); + } + spin_unlock(&dev->count_lock); + } + + unlock_kernel(); + return retcode; +} + +/* r128_ioctl is called whenever a process performs an ioctl on /dev/drm. */ +int r128_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + int nr = DRM_IOCTL_NR(cmd); + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + int retcode = 0; + drm_ioctl_desc_t *ioctl; + drm_ioctl_t *func; + + atomic_inc(&dev->ioctl_count); + atomic_inc(&dev->total_ioctl); + ++priv->ioctl_count; + + DRM_DEBUG("pid = %d, cmd = 0x%02x, nr = 0x%02x, dev 0x%x, auth = %d\n", + current->pid, cmd, nr, dev->device, priv->authenticated); + + if (nr >= R128_IOCTL_COUNT) { + retcode = -EINVAL; + } else { + ioctl = &r128_ioctls[nr]; + func = ioctl->func; + + if (!func) { + DRM_DEBUG("no function\n"); + retcode = -EINVAL; + } else if ((ioctl->root_only && !capable(CAP_SYS_ADMIN)) + || (ioctl->auth_needed && !priv->authenticated)) { + retcode = -EACCES; + } else { + retcode = (func)(inode, filp, cmd, arg); + } + } + +#if 0 + if ( retcode ) { + DRM_INFO( "%s 0x%x ret = %d\n", __FUNCTION__, nr, retcode ); + } +#endif + + atomic_dec(&dev->ioctl_count); + return retcode; +} + +int r128_lock(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + DECLARE_WAITQUEUE(entry, current); + int ret = 0; + drm_lock_t lock; +#if DRM_DMA_HISTOGRAM + cycles_t start; + + dev->lck_start = start = get_cycles(); +#endif + + if (copy_from_user(&lock, (drm_lock_t *)arg, sizeof(lock))) + return -EFAULT; + + if (lock.context == DRM_KERNEL_CONTEXT) { + DRM_ERROR("Process %d using kernel context %d\n", + current->pid, lock.context); + return -EINVAL; + } + + DRM_DEBUG("%d (pid %d) requests lock (0x%08x), flags = 0x%08x\n", + lock.context, current->pid, dev->lock.hw_lock->lock, + lock.flags); + + if (lock.context < 0) + return -EINVAL; + + if (!ret) { + add_wait_queue(&dev->lock.lock_queue, &entry); + for (;;) { + current->state = TASK_INTERRUPTIBLE; + if (!dev->lock.hw_lock) { + /* Device has been unregistered */ + ret = -EINTR; + break; + } + if (drm_lock_take(&dev->lock.hw_lock->lock, + lock.context)) { + dev->lock.pid = current->pid; + dev->lock.lock_time = jiffies; + atomic_inc(&dev->total_locks); + break; /* Got lock */ + } + + /* Contention */ + atomic_inc(&dev->total_sleeps); + schedule(); + if (signal_pending(current)) { + ret = -ERESTARTSYS; + break; + } + } + current->state = TASK_RUNNING; + remove_wait_queue(&dev->lock.lock_queue, &entry); + } + + if (!ret) { + sigemptyset(&dev->sigmask); + sigaddset(&dev->sigmask, SIGSTOP); + sigaddset(&dev->sigmask, SIGTSTP); + sigaddset(&dev->sigmask, SIGTTIN); + sigaddset(&dev->sigmask, SIGTTOU); + dev->sigdata.context = lock.context; + dev->sigdata.lock = dev->lock.hw_lock; + block_all_signals(drm_notifier, &dev->sigdata, &dev->sigmask); + if (lock.flags & _DRM_LOCK_READY) { + /* Wait for space in DMA/FIFO */ + } + if (lock.flags & _DRM_LOCK_QUIESCENT) { + /* Make hardware quiescent */ + DRM_DEBUG( "not quiescent!\n" ); +#if 0 + r128_quiescent(dev); +#endif + } + } + +#if LINUX_VERSION_CODE < 0x020400 + if (lock.context != r128_res_ctx.handle) { + current->counter = 5; + current->priority = DEF_PRIORITY/4; + } +#endif + DRM_DEBUG("%d %s\n", lock.context, ret ? "interrupted" : "has lock"); + +#if DRM_DMA_HISTOGRAM + atomic_inc(&dev->histo.lacq[drm_histogram_slot(get_cycles() - start)]); +#endif + + return ret; +} + + +int r128_unlock(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_lock_t lock; + + if (copy_from_user(&lock, (drm_lock_t *)arg, sizeof(lock))) + return -EFAULT; + + if (lock.context == DRM_KERNEL_CONTEXT) { + DRM_ERROR("Process %d using kernel context %d\n", + current->pid, lock.context); + return -EINVAL; + } + + DRM_DEBUG("%d frees lock (%d holds)\n", + lock.context, + _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock)); + atomic_inc(&dev->total_unlocks); + if (_DRM_LOCK_IS_CONT(dev->lock.hw_lock->lock)) + atomic_inc(&dev->total_contends); + drm_lock_transfer(dev, &dev->lock.hw_lock->lock, DRM_KERNEL_CONTEXT); + /* FIXME: Try to send data to card here */ + if (!dev->context_flag) { + if (drm_lock_free(dev, &dev->lock.hw_lock->lock, + DRM_KERNEL_CONTEXT)) { + DRM_ERROR("\n"); + } + } + +#if LINUX_VERSION_CODE < 0x020400 + if (lock.context != r128_res_ctx.handle) { + current->counter = 5; + current->priority = DEF_PRIORITY; + } +#endif + unblock_all_signals(); + return 0; +} diff -urN linux-2.4.10/drivers/char/drm-4.0/r128_drv.h linux-2.4.10-lia/drivers/char/drm-4.0/r128_drv.h --- linux-2.4.10/drivers/char/drm-4.0/r128_drv.h Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/r128_drv.h Wed Aug 15 20:52:12 2001 @@ -0,0 +1,469 @@ +/* r128_drv.h -- Private header for r128 driver -*- linux-c -*- + * Created: Mon Dec 13 09:51:11 1999 by faith@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rickard E. (Rik) Faith + * Kevin E. Martin + * Gareth Hughes + * + */ + +#ifndef __R128_DRV_H__ +#define __R128_DRV_H__ + +typedef struct drm_r128_freelist { + unsigned int age; + drm_buf_t *buf; + struct drm_r128_freelist *next; + struct drm_r128_freelist *prev; +} drm_r128_freelist_t; + +typedef struct drm_r128_ring_buffer { + u32 *start; + u32 *end; + int size; + int size_l2qw; + + volatile u32 *head; + u32 tail; + u32 tail_mask; + int space; +} drm_r128_ring_buffer_t; + +typedef struct drm_r128_private { + drm_r128_ring_buffer_t ring; + drm_r128_sarea_t *sarea_priv; + + int cce_mode; + int cce_fifo_size; + int cce_secure; + int cce_running; + + drm_r128_freelist_t *head; + drm_r128_freelist_t *tail; + + int usec_timeout; + int is_pci; + + atomic_t idle_count; + + unsigned int fb_bpp; + unsigned int front_offset; + unsigned int front_pitch; + unsigned int back_offset; + unsigned int back_pitch; + + unsigned int depth_bpp; + unsigned int depth_offset; + unsigned int depth_pitch; + unsigned int span_offset; + + u32 front_pitch_offset_c; + u32 back_pitch_offset_c; + u32 depth_pitch_offset_c; + u32 span_pitch_offset_c; + + drm_map_t *sarea; + drm_map_t *fb; + drm_map_t *mmio; + drm_map_t *cce_ring; + drm_map_t *ring_rptr; + drm_map_t *buffers; + drm_map_t *agp_textures; +} drm_r128_private_t; + +typedef struct drm_r128_buf_priv { + u32 age; + int prim; + int discard; + int dispatched; + drm_r128_freelist_t *list_entry; +} drm_r128_buf_priv_t; + + /* r128_drv.c */ +extern int r128_version( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); +extern int r128_open( struct inode *inode, struct file *filp ); +extern int r128_release( struct inode *inode, struct file *filp ); +extern int r128_ioctl( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); +extern int r128_lock( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); +extern int r128_unlock( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); + + /* r128_cce.c */ +extern int r128_cce_init( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); +extern int r128_cce_start( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); +extern int r128_cce_stop( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); +extern int r128_cce_reset( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); +extern int r128_cce_idle( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); +extern int r128_engine_reset( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); +extern int r128_cce_packet( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); +extern int r128_cce_buffers( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); + +extern void r128_freelist_reset( drm_device_t *dev ); +extern drm_buf_t *r128_freelist_get( drm_device_t *dev ); + +extern int r128_wait_ring( drm_r128_private_t *dev_priv, int n ); +extern void r128_update_ring_snapshot( drm_r128_private_t *dev_priv ); + + /* r128_state.c */ +extern int r128_cce_clear( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); +extern int r128_cce_swap( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); +extern int r128_cce_vertex( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); +extern int r128_cce_indices( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); +extern int r128_cce_blit( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); +extern int r128_cce_depth( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); +extern int r128_cce_stipple( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); + + /* r128_bufs.c */ +extern int r128_addbufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int r128_mapbufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); + + /* r128_context.c */ +extern int r128_resctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int r128_addctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int r128_modctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int r128_getctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int r128_switchctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int r128_newctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int r128_rmctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); + +extern int r128_context_switch(drm_device_t *dev, int old, int new); +extern int r128_context_switch_complete(drm_device_t *dev, int new); + + +/* Register definitions, register access macros and drmAddMap constants + * for Rage 128 kernel driver. + */ + +#define R128_AUX_SC_CNTL 0x1660 +# define R128_AUX1_SC_EN (1 << 0) +# define R128_AUX1_SC_MODE_OR (0 << 1) +# define R128_AUX1_SC_MODE_NAND (1 << 1) +# define R128_AUX2_SC_EN (1 << 2) +# define R128_AUX2_SC_MODE_OR (0 << 3) +# define R128_AUX2_SC_MODE_NAND (1 << 3) +# define R128_AUX3_SC_EN (1 << 4) +# define R128_AUX3_SC_MODE_OR (0 << 5) +# define R128_AUX3_SC_MODE_NAND (1 << 5) +#define R128_AUX1_SC_LEFT 0x1664 +#define R128_AUX1_SC_RIGHT 0x1668 +#define R128_AUX1_SC_TOP 0x166c +#define R128_AUX1_SC_BOTTOM 0x1670 +#define R128_AUX2_SC_LEFT 0x1674 +#define R128_AUX2_SC_RIGHT 0x1678 +#define R128_AUX2_SC_TOP 0x167c +#define R128_AUX2_SC_BOTTOM 0x1680 +#define R128_AUX3_SC_LEFT 0x1684 +#define R128_AUX3_SC_RIGHT 0x1688 +#define R128_AUX3_SC_TOP 0x168c +#define R128_AUX3_SC_BOTTOM 0x1690 + +#define R128_BRUSH_DATA0 0x1480 +#define R128_BUS_CNTL 0x0030 +# define R128_BUS_MASTER_DIS (1 << 6) + +#define R128_CLOCK_CNTL_INDEX 0x0008 +#define R128_CLOCK_CNTL_DATA 0x000c +# define R128_PLL_WR_EN (1 << 7) + +#define R128_CONSTANT_COLOR_C 0x1d34 + +#define R128_DP_GUI_MASTER_CNTL 0x146c +# define R128_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) +# define R128_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) +# define R128_GMC_BRUSH_SOLID_COLOR (13 << 4) +# define R128_GMC_BRUSH_NONE (15 << 4) +# define R128_GMC_DST_16BPP (4 << 8) +# define R128_GMC_DST_24BPP (5 << 8) +# define R128_GMC_DST_32BPP (6 << 8) +# define R128_GMC_DST_DATATYPE_SHIFT 8 +# define R128_GMC_SRC_DATATYPE_COLOR (3 << 12) +# define R128_DP_SRC_SOURCE_MEMORY (2 << 24) +# define R128_DP_SRC_SOURCE_HOST_DATA (3 << 24) +# define R128_GMC_CLR_CMP_CNTL_DIS (1 << 28) +# define R128_GMC_AUX_CLIP_DIS (1 << 29) +# define R128_GMC_WR_MSK_DIS (1 << 30) +# define R128_ROP3_S 0x00cc0000 +# define R128_ROP3_P 0x00f00000 +#define R128_DP_WRITE_MASK 0x16cc +#define R128_DST_PITCH_OFFSET_C 0x1c80 +# define R128_DST_TILE (1 << 31) + +#define R128_GEN_RESET_CNTL 0x00f0 +# define R128_SOFT_RESET_GUI (1 << 0) + +#define R128_GUI_SCRATCH_REG0 0x15e0 +#define R128_GUI_SCRATCH_REG1 0x15e4 +#define R128_GUI_SCRATCH_REG2 0x15e8 +#define R128_GUI_SCRATCH_REG3 0x15ec +#define R128_GUI_SCRATCH_REG4 0x15f0 +#define R128_GUI_SCRATCH_REG5 0x15f4 + +#define R128_GUI_STAT 0x1740 +# define R128_GUI_FIFOCNT_MASK 0x0fff +# define R128_GUI_ACTIVE (1 << 31) + +#define R128_MCLK_CNTL 0x000f +# define R128_FORCE_GCP (1 << 16) +# define R128_FORCE_PIPE3D_CP (1 << 17) +# define R128_FORCE_RCP (1 << 18) + +#define R128_PC_GUI_CTLSTAT 0x1748 +#define R128_PC_NGUI_CTLSTAT 0x0184 +# define R128_PC_FLUSH_GUI (3 << 0) +# define R128_PC_RI_GUI (1 << 2) +# define R128_PC_FLUSH_ALL 0x00ff +# define R128_PC_BUSY (1 << 31) + +#define R128_PRIM_TEX_CNTL_C 0x1cb0 + +#define R128_SCALE_3D_CNTL 0x1a00 +#define R128_SEC_TEX_CNTL_C 0x1d00 +#define R128_SEC_TEXTURE_BORDER_COLOR_C 0x1d3c +#define R128_SETUP_CNTL 0x1bc4 +#define R128_STEN_REF_MASK_C 0x1d40 + +#define R128_TEX_CNTL_C 0x1c9c +# define R128_TEX_CACHE_FLUSH (1 << 23) + +#define R128_WINDOW_XY_OFFSET 0x1bcc + + +/* CCE registers + */ +#define R128_PM4_BUFFER_OFFSET 0x0700 +#define R128_PM4_BUFFER_CNTL 0x0704 +# define R128_PM4_MASK (15 << 28) +# define R128_PM4_NONPM4 (0 << 28) +# define R128_PM4_192PIO (1 << 28) +# define R128_PM4_192BM (2 << 28) +# define R128_PM4_128PIO_64INDBM (3 << 28) +# define R128_PM4_128BM_64INDBM (4 << 28) +# define R128_PM4_64PIO_128INDBM (5 << 28) +# define R128_PM4_64BM_128INDBM (6 << 28) +# define R128_PM4_64PIO_64VCBM_64INDBM (7 << 28) +# define R128_PM4_64BM_64VCBM_64INDBM (8 << 28) +# define R128_PM4_64PIO_64VCPIO_64INDPIO (15 << 28) + +#define R128_PM4_BUFFER_WM_CNTL 0x0708 +# define R128_WMA_SHIFT 0 +# define R128_WMB_SHIFT 8 +# define R128_WMC_SHIFT 16 +# define R128_WB_WM_SHIFT 24 + +#define R128_PM4_BUFFER_DL_RPTR_ADDR 0x070c +#define R128_PM4_BUFFER_DL_RPTR 0x0710 +#define R128_PM4_BUFFER_DL_WPTR 0x0714 +# define R128_PM4_BUFFER_DL_DONE (1 << 31) + +#define R128_PM4_VC_FPU_SETUP 0x071c + +#define R128_PM4_IW_INDOFF 0x0738 +#define R128_PM4_IW_INDSIZE 0x073c + +#define R128_PM4_STAT 0x07b8 +# define R128_PM4_FIFOCNT_MASK 0x0fff +# define R128_PM4_BUSY (1 << 16) +# define R128_PM4_GUI_ACTIVE (1 << 31) + +#define R128_PM4_MICROCODE_ADDR 0x07d4 +#define R128_PM4_MICROCODE_RADDR 0x07d8 +#define R128_PM4_MICROCODE_DATAH 0x07dc +#define R128_PM4_MICROCODE_DATAL 0x07e0 + +#define R128_PM4_BUFFER_ADDR 0x07f0 +#define R128_PM4_MICRO_CNTL 0x07fc +# define R128_PM4_MICRO_FREERUN (1 << 30) + +#define R128_PM4_FIFO_DATA_EVEN 0x1000 +#define R128_PM4_FIFO_DATA_ODD 0x1004 + + +/* CCE command packets + */ +#define R128_CCE_PACKET0 0x00000000 +#define R128_CCE_PACKET1 0x40000000 +#define R128_CCE_PACKET2 0x80000000 +#define R128_CCE_PACKET3 0xC0000000 +# define R128_CNTL_HOSTDATA_BLT 0x00009400 +# define R128_CNTL_PAINT_MULTI 0x00009A00 +# define R128_CNTL_BITBLT_MULTI 0x00009B00 +# define R128_3D_RNDR_GEN_INDX_PRIM 0x00002300 + +#define R128_CCE_PACKET_MASK 0xC0000000 +#define R128_CCE_PACKET_COUNT_MASK 0x3fff0000 +#define R128_CCE_PACKET0_REG_MASK 0x000007ff +#define R128_CCE_PACKET1_REG0_MASK 0x000007ff +#define R128_CCE_PACKET1_REG1_MASK 0x003ff800 + +#define R128_CCE_VC_CNTL_PRIM_TYPE_NONE 0x00000000 +#define R128_CCE_VC_CNTL_PRIM_TYPE_POINT 0x00000001 +#define R128_CCE_VC_CNTL_PRIM_TYPE_LINE 0x00000002 +#define R128_CCE_VC_CNTL_PRIM_TYPE_POLY_LINE 0x00000003 +#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004 +#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005 +#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006 +#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 0x00000007 +#define R128_CCE_VC_CNTL_PRIM_WALK_IND 0x00000010 +#define R128_CCE_VC_CNTL_PRIM_WALK_LIST 0x00000020 +#define R128_CCE_VC_CNTL_PRIM_WALK_RING 0x00000030 +#define R128_CCE_VC_CNTL_NUM_SHIFT 16 + +#define R128_DATATYPE_CI8 2 +#define R128_DATATYPE_ARGB1555 3 +#define R128_DATATYPE_RGB565 4 +#define R128_DATATYPE_RGB888 5 +#define R128_DATATYPE_ARGB8888 6 +#define R128_DATATYPE_RGB332 7 +#define R128_DATATYPE_RGB8 9 +#define R128_DATATYPE_ARGB4444 15 + +/* Constants */ +#define R128_AGP_OFFSET 0x02000000 + +#define R128_WATERMARK_L 16 +#define R128_WATERMARK_M 8 +#define R128_WATERMARK_N 8 +#define R128_WATERMARK_K 128 + +#define R128_MAX_USEC_TIMEOUT 100000 /* 100 ms */ + +#define R128_LAST_FRAME_REG R128_GUI_SCRATCH_REG0 +#define R128_LAST_DISPATCH_REG R128_GUI_SCRATCH_REG1 +#define R128_MAX_VB_AGE 0xffffffff + +#define R128_MAX_VB_VERTS (0xffff) + + +#define R128_BASE(reg) ((unsigned long)(dev_priv->mmio->handle)) +#define R128_ADDR(reg) (R128_BASE(reg) + reg) + +#define R128_READ(reg) readl(R128_ADDR(reg)) +#define R128_WRITE(reg,val) writel(val,R128_ADDR(reg)) + +#define R128_READ8(reg) readb(R128_ADDR(reg)) +#define R128_WRITE8(reg,val) writeb(val,R128_ADDR(reg)) + +#define R128_WRITE_PLL(addr,val) \ +do { \ + R128_WRITE8(R128_CLOCK_CNTL_INDEX, ((addr) & 0x1f) | R128_PLL_WR_EN); \ + R128_WRITE(R128_CLOCK_CNTL_DATA, (val)); \ +} while (0) + +extern int R128_READ_PLL(drm_device_t *dev, int addr); + +#define R128CCE0(p,r,n) ((p) | ((n) << 16) | ((r) >> 2)) +#define R128CCE1(p,r1,r2) ((p) | (((r2) >> 2) << 11) | ((r1) >> 2)) +#define R128CCE2(p) ((p)) +#define R128CCE3(p,n) ((p) | ((n) << 16)) + + + + +#define CCE_PACKET0( reg, n ) (R128_CCE_PACKET0 | \ + ((n) << 16) | ((reg) >> 2)) +#define CCE_PACKET1( reg0, reg1 ) (R128_CCE_PACKET1 | \ + (((reg1) >> 2) << 11) | ((reg0) >> 2)) +#define CCE_PACKET2() (R128_CCE_PACKET2) +#define CCE_PACKET3( pkt, n ) (R128_CCE_PACKET3 | \ + (pkt) | ((n) << 16)) + + +#define r128_flush_write_combine() mb() + + +#define R128_VERBOSE 0 + +#define RING_LOCALS int write; unsigned int tail_mask; volatile u32 *ring; + +#define BEGIN_RING( n ) do { \ + if ( R128_VERBOSE ) { \ + DRM_INFO( "BEGIN_RING( %d ) in %s\n", \ + n, __FUNCTION__ ); \ + } \ + if ( dev_priv->ring.space < n * sizeof(u32) ) { \ + r128_wait_ring( dev_priv, n * sizeof(u32) ); \ + } \ + dev_priv->ring.space -= n * sizeof(u32); \ + ring = dev_priv->ring.start; \ + write = dev_priv->ring.tail; \ + tail_mask = dev_priv->ring.tail_mask; \ +} while (0) + +#define ADVANCE_RING() do { \ + if ( R128_VERBOSE ) { \ + DRM_INFO( "ADVANCE_RING() tail=0x%06x wr=0x%06x\n", \ + write, dev_priv->ring.tail ); \ + } \ + if ( write < 32 ) { \ + memcpy( dev_priv->ring.end, \ + dev_priv->ring.start, \ + write * sizeof(u32) ); \ + } \ + r128_flush_write_combine(); \ + dev_priv->ring.tail = write; \ + R128_WRITE( R128_PM4_BUFFER_DL_WPTR, write ); \ +} while (0) + +#define OUT_RING( x ) do { \ + if ( R128_VERBOSE ) { \ + DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \ + (unsigned int)(x), write ); \ + } \ + ring[write++] = x; \ + write &= tail_mask; \ +} while (0) + +#define R128_PERFORMANCE_BOXES 0 + +#endif /* __R128_DRV_H__ */ diff -urN linux-2.4.10/drivers/char/drm-4.0/r128_state.c linux-2.4.10-lia/drivers/char/drm-4.0/r128_state.c --- linux-2.4.10/drivers/char/drm-4.0/r128_state.c Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/r128_state.c Wed Aug 15 20:52:12 2001 @@ -0,0 +1,1605 @@ +/* r128_state.c -- State support for r128 -*- linux-c -*- + * Created: Thu Jan 27 02:53:43 2000 by gareth@valinux.com + * + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Gareth Hughes + * + */ + +#define __NO_VERSION__ +#include "drmP.h" +#include "r128_drv.h" +#include "drm.h" + + +/* ================================================================ + * CCE hardware state programming functions + */ + +static void r128_emit_clip_rects( drm_r128_private_t *dev_priv, + drm_clip_rect_t *boxes, int count ) +{ + u32 aux_sc_cntl = 0x00000000; + RING_LOCALS; + DRM_DEBUG( " %s\n", __FUNCTION__ ); + + BEGIN_RING( 17 ); + + if ( count >= 1 ) { + OUT_RING( CCE_PACKET0( R128_AUX1_SC_LEFT, 3 ) ); + OUT_RING( boxes[0].x1 ); + OUT_RING( boxes[0].x2 - 1 ); + OUT_RING( boxes[0].y1 ); + OUT_RING( boxes[0].y2 - 1 ); + + aux_sc_cntl |= (R128_AUX1_SC_EN | R128_AUX1_SC_MODE_OR); + } + if ( count >= 2 ) { + OUT_RING( CCE_PACKET0( R128_AUX2_SC_LEFT, 3 ) ); + OUT_RING( boxes[1].x1 ); + OUT_RING( boxes[1].x2 - 1 ); + OUT_RING( boxes[1].y1 ); + OUT_RING( boxes[1].y2 - 1 ); + + aux_sc_cntl |= (R128_AUX2_SC_EN | R128_AUX2_SC_MODE_OR); + } + if ( count >= 3 ) { + OUT_RING( CCE_PACKET0( R128_AUX3_SC_LEFT, 3 ) ); + OUT_RING( boxes[2].x1 ); + OUT_RING( boxes[2].x2 - 1 ); + OUT_RING( boxes[2].y1 ); + OUT_RING( boxes[2].y2 - 1 ); + + aux_sc_cntl |= (R128_AUX3_SC_EN | R128_AUX3_SC_MODE_OR); + } + + OUT_RING( CCE_PACKET0( R128_AUX_SC_CNTL, 0 ) ); + OUT_RING( aux_sc_cntl ); + + ADVANCE_RING(); +} + +static inline void r128_emit_core( drm_r128_private_t *dev_priv ) +{ + drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_r128_context_regs_t *ctx = &sarea_priv->context_state; + RING_LOCALS; + DRM_DEBUG( " %s\n", __FUNCTION__ ); + + BEGIN_RING( 2 ); + + OUT_RING( CCE_PACKET0( R128_SCALE_3D_CNTL, 0 ) ); + OUT_RING( ctx->scale_3d_cntl ); + + ADVANCE_RING(); +} + +static inline void r128_emit_context( drm_r128_private_t *dev_priv ) +{ + drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_r128_context_regs_t *ctx = &sarea_priv->context_state; + RING_LOCALS; + DRM_DEBUG( " %s\n", __FUNCTION__ ); + + BEGIN_RING( 13 ); + + OUT_RING( CCE_PACKET0( R128_DST_PITCH_OFFSET_C, 11 ) ); + OUT_RING( ctx->dst_pitch_offset_c ); + OUT_RING( ctx->dp_gui_master_cntl_c ); + OUT_RING( ctx->sc_top_left_c ); + OUT_RING( ctx->sc_bottom_right_c ); + OUT_RING( ctx->z_offset_c ); + OUT_RING( ctx->z_pitch_c ); + OUT_RING( ctx->z_sten_cntl_c ); + OUT_RING( ctx->tex_cntl_c ); + OUT_RING( ctx->misc_3d_state_cntl_reg ); + OUT_RING( ctx->texture_clr_cmp_clr_c ); + OUT_RING( ctx->texture_clr_cmp_msk_c ); + OUT_RING( ctx->fog_color_c ); + + ADVANCE_RING(); +} + +static inline void r128_emit_setup( drm_r128_private_t *dev_priv ) +{ + drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_r128_context_regs_t *ctx = &sarea_priv->context_state; + RING_LOCALS; + DRM_DEBUG( " %s\n", __FUNCTION__ ); + + BEGIN_RING( 3 ); + + OUT_RING( CCE_PACKET1( R128_SETUP_CNTL, R128_PM4_VC_FPU_SETUP ) ); + OUT_RING( ctx->setup_cntl ); + OUT_RING( ctx->pm4_vc_fpu_setup ); + + ADVANCE_RING(); +} + +static inline void r128_emit_masks( drm_r128_private_t *dev_priv ) +{ + drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_r128_context_regs_t *ctx = &sarea_priv->context_state; + RING_LOCALS; + DRM_DEBUG( " %s\n", __FUNCTION__ ); + + BEGIN_RING( 5 ); + + OUT_RING( CCE_PACKET0( R128_DP_WRITE_MASK, 0 ) ); + OUT_RING( ctx->dp_write_mask ); + + OUT_RING( CCE_PACKET0( R128_STEN_REF_MASK_C, 1 ) ); + OUT_RING( ctx->sten_ref_mask_c ); + OUT_RING( ctx->plane_3d_mask_c ); + + ADVANCE_RING(); +} + +static inline void r128_emit_window( drm_r128_private_t *dev_priv ) +{ + drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_r128_context_regs_t *ctx = &sarea_priv->context_state; + RING_LOCALS; + DRM_DEBUG( " %s\n", __FUNCTION__ ); + + BEGIN_RING( 2 ); + + OUT_RING( CCE_PACKET0( R128_WINDOW_XY_OFFSET, 0 ) ); + OUT_RING( ctx->window_xy_offset ); + + ADVANCE_RING(); +} + +static inline void r128_emit_tex0( drm_r128_private_t *dev_priv ) +{ + drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_r128_context_regs_t *ctx = &sarea_priv->context_state; + drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[0]; + int i; + RING_LOCALS; + DRM_DEBUG( " %s\n", __FUNCTION__ ); + + BEGIN_RING( 7 + R128_TEX_MAXLEVELS ); + + OUT_RING( CCE_PACKET0( R128_PRIM_TEX_CNTL_C, + 2 + R128_TEX_MAXLEVELS ) ); + OUT_RING( tex->tex_cntl ); + OUT_RING( tex->tex_combine_cntl ); + OUT_RING( ctx->tex_size_pitch_c ); + for ( i = 0 ; i < R128_TEX_MAXLEVELS ; i++ ) { + OUT_RING( tex->tex_offset[i] ); + } + + OUT_RING( CCE_PACKET0( R128_CONSTANT_COLOR_C, 1 ) ); + OUT_RING( ctx->constant_color_c ); + OUT_RING( tex->tex_border_color ); + + ADVANCE_RING(); +} + +static inline void r128_emit_tex1( drm_r128_private_t *dev_priv ) +{ + drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[1]; + int i; + RING_LOCALS; + DRM_DEBUG( " %s\n", __FUNCTION__ ); + + BEGIN_RING( 5 + R128_TEX_MAXLEVELS ); + + OUT_RING( CCE_PACKET0( R128_SEC_TEX_CNTL_C, + 1 + R128_TEX_MAXLEVELS ) ); + OUT_RING( tex->tex_cntl ); + OUT_RING( tex->tex_combine_cntl ); + for ( i = 0 ; i < R128_TEX_MAXLEVELS ; i++ ) { + OUT_RING( tex->tex_offset[i] ); + } + + OUT_RING( CCE_PACKET0( R128_SEC_TEXTURE_BORDER_COLOR_C, 0 ) ); + OUT_RING( tex->tex_border_color ); + + ADVANCE_RING(); +} + +static inline void r128_emit_state( drm_r128_private_t *dev_priv ) +{ + drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; + unsigned int dirty = sarea_priv->dirty; + + DRM_DEBUG( "%s: dirty=0x%08x\n", __FUNCTION__, dirty ); + + if ( dirty & R128_UPLOAD_CORE ) { + r128_emit_core( dev_priv ); + sarea_priv->dirty &= ~R128_UPLOAD_CORE; + } + + if ( dirty & R128_UPLOAD_CONTEXT ) { + r128_emit_context( dev_priv ); + sarea_priv->dirty &= ~R128_UPLOAD_CONTEXT; + } + + if ( dirty & R128_UPLOAD_SETUP ) { + r128_emit_setup( dev_priv ); + sarea_priv->dirty &= ~R128_UPLOAD_SETUP; + } + + if ( dirty & R128_UPLOAD_MASKS ) { + r128_emit_masks( dev_priv ); + sarea_priv->dirty &= ~R128_UPLOAD_MASKS; + } + + if ( dirty & R128_UPLOAD_WINDOW ) { + r128_emit_window( dev_priv ); + sarea_priv->dirty &= ~R128_UPLOAD_WINDOW; + } + + if ( dirty & R128_UPLOAD_TEX0 ) { + r128_emit_tex0( dev_priv ); + sarea_priv->dirty &= ~R128_UPLOAD_TEX0; + } + + if ( dirty & R128_UPLOAD_TEX1 ) { + r128_emit_tex1( dev_priv ); + sarea_priv->dirty &= ~R128_UPLOAD_TEX1; + } + + /* Turn off the texture cache flushing */ + sarea_priv->context_state.tex_cntl_c &= ~R128_TEX_CACHE_FLUSH; + + sarea_priv->dirty &= ~R128_REQUIRE_QUIESCENCE; +} + + +#if R128_PERFORMANCE_BOXES +/* ================================================================ + * Performance monitoring functions + */ + +static void r128_clear_box( drm_r128_private_t *dev_priv, + int x, int y, int w, int h, + int r, int g, int b ) +{ + u32 pitch, offset; + u32 fb_bpp, color; + RING_LOCALS; + + switch ( dev_priv->fb_bpp ) { + case 16: + fb_bpp = R128_GMC_DST_16BPP; + color = (((r & 0xf8) << 8) | + ((g & 0xfc) << 3) | + ((b & 0xf8) >> 3)); + break; + case 24: + fb_bpp = R128_GMC_DST_24BPP; + color = ((r << 16) | (g << 8) | b); + break; + case 32: + fb_bpp = R128_GMC_DST_32BPP; + color = (((0xff) << 24) | (r << 16) | (g << 8) | b); + break; + default: + return; + } + + offset = dev_priv->back_offset; + pitch = dev_priv->back_pitch >> 3; + + BEGIN_RING( 6 ); + + OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); + OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL + | R128_GMC_BRUSH_SOLID_COLOR + | fb_bpp + | R128_GMC_SRC_DATATYPE_COLOR + | R128_ROP3_P + | R128_GMC_CLR_CMP_CNTL_DIS + | R128_GMC_AUX_CLIP_DIS ); + + OUT_RING( (pitch << 21) | (offset >> 5) ); + OUT_RING( color ); + + OUT_RING( (x << 16) | y ); + OUT_RING( (w << 16) | h ); + + ADVANCE_RING(); +} + +static void r128_cce_performance_boxes( drm_r128_private_t *dev_priv ) +{ + if ( atomic_read( &dev_priv->idle_count ) == 0 ) { + r128_clear_box( dev_priv, 64, 4, 8, 8, 0, 255, 0 ); + } else { + atomic_set( &dev_priv->idle_count, 0 ); + } +} + +#endif + + +/* ================================================================ + * CCE command dispatch functions + */ + +static void r128_print_dirty( const char *msg, unsigned int flags ) +{ + DRM_INFO( "%s: (0x%x) %s%s%s%s%s%s%s%s%s\n", + msg, + flags, + (flags & R128_UPLOAD_CORE) ? "core, " : "", + (flags & R128_UPLOAD_CONTEXT) ? "context, " : "", + (flags & R128_UPLOAD_SETUP) ? "setup, " : "", + (flags & R128_UPLOAD_TEX0) ? "tex0, " : "", + (flags & R128_UPLOAD_TEX1) ? "tex1, " : "", + (flags & R128_UPLOAD_MASKS) ? "masks, " : "", + (flags & R128_UPLOAD_WINDOW) ? "window, " : "", + (flags & R128_UPLOAD_CLIPRECTS) ? "cliprects, " : "", + (flags & R128_REQUIRE_QUIESCENCE) ? "quiescence, " : "" ); +} + +static void r128_cce_dispatch_clear( drm_device_t *dev, + unsigned int flags, + int cx, int cy, int cw, int ch, + unsigned int clear_color, + unsigned int clear_depth ) +{ + drm_r128_private_t *dev_priv = dev->dev_private; + drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; + int nbox = sarea_priv->nbox; + drm_clip_rect_t *pbox = sarea_priv->boxes; + u32 fb_bpp, depth_bpp; + int i; + RING_LOCALS; + DRM_DEBUG( "%s\n", __FUNCTION__ ); + + r128_update_ring_snapshot( dev_priv ); + + switch ( dev_priv->fb_bpp ) { + case 16: + fb_bpp = R128_GMC_DST_16BPP; + break; + case 32: + fb_bpp = R128_GMC_DST_32BPP; + break; + default: + return; + } + switch ( dev_priv->depth_bpp ) { + case 16: + depth_bpp = R128_GMC_DST_16BPP; + break; + case 24: + case 32: + depth_bpp = R128_GMC_DST_32BPP; + break; + default: + return; + } + + for ( i = 0 ; i < nbox ; i++ ) { + int x = pbox[i].x1; + int y = pbox[i].y1; + int w = pbox[i].x2 - x; + int h = pbox[i].y2 - y; + + DRM_DEBUG( "dispatch clear %d,%d-%d,%d flags 0x%x\n", + pbox[i].x1, pbox[i].y1, pbox[i].x2, + pbox[i].y2, flags ); + + if ( flags & (R128_FRONT | R128_BACK) ) { + BEGIN_RING( 2 ); + + OUT_RING( CCE_PACKET0( R128_DP_WRITE_MASK, 0 ) ); + OUT_RING( sarea_priv->context_state.plane_3d_mask_c ); + + ADVANCE_RING(); + } + + if ( flags & R128_FRONT ) { + BEGIN_RING( 6 ); + + OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); + OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL + | R128_GMC_BRUSH_SOLID_COLOR + | fb_bpp + | R128_GMC_SRC_DATATYPE_COLOR + | R128_ROP3_P + | R128_GMC_CLR_CMP_CNTL_DIS + | R128_GMC_AUX_CLIP_DIS ); + + OUT_RING( dev_priv->front_pitch_offset_c ); + OUT_RING( clear_color ); + + OUT_RING( (x << 16) | y ); + OUT_RING( (w << 16) | h ); + + ADVANCE_RING(); + } + + if ( flags & R128_BACK ) { + BEGIN_RING( 6 ); + + OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); + OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL + | R128_GMC_BRUSH_SOLID_COLOR + | fb_bpp + | R128_GMC_SRC_DATATYPE_COLOR + | R128_ROP3_P + | R128_GMC_CLR_CMP_CNTL_DIS + | R128_GMC_AUX_CLIP_DIS ); + + OUT_RING( dev_priv->back_pitch_offset_c ); + OUT_RING( clear_color ); + + OUT_RING( (x << 16) | y ); + OUT_RING( (w << 16) | h ); + + ADVANCE_RING(); + } + + if ( flags & R128_DEPTH ) { + BEGIN_RING( 6 ); + + OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); + OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL + | R128_GMC_BRUSH_SOLID_COLOR + | depth_bpp + | R128_GMC_SRC_DATATYPE_COLOR + | R128_ROP3_P + | R128_GMC_CLR_CMP_CNTL_DIS + | R128_GMC_AUX_CLIP_DIS + | R128_GMC_WR_MSK_DIS ); + + OUT_RING( dev_priv->depth_pitch_offset_c ); + OUT_RING( clear_depth ); + + OUT_RING( (x << 16) | y ); + OUT_RING( (w << 16) | h ); + + ADVANCE_RING(); + } + } +} + +static void r128_cce_dispatch_swap( drm_device_t *dev ) +{ + drm_r128_private_t *dev_priv = dev->dev_private; + drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; + int nbox = sarea_priv->nbox; + drm_clip_rect_t *pbox = sarea_priv->boxes; + u32 fb_bpp; + int i; + RING_LOCALS; + DRM_DEBUG( "%s\n", __FUNCTION__ ); + + r128_update_ring_snapshot( dev_priv ); + +#if R128_PERFORMANCE_BOXES + /* Do some trivial performance monitoring... + */ + r128_cce_performance_boxes( dev_priv ); +#endif + + switch ( dev_priv->fb_bpp ) { + case 16: + fb_bpp = R128_GMC_DST_16BPP; + break; + case 32: + default: + fb_bpp = R128_GMC_DST_32BPP; + break; + } + + for ( i = 0 ; i < nbox ; i++ ) { + int x = pbox[i].x1; + int y = pbox[i].y1; + int w = pbox[i].x2 - x; + int h = pbox[i].y2 - y; + + BEGIN_RING( 7 ); + + OUT_RING( CCE_PACKET3( R128_CNTL_BITBLT_MULTI, 5 ) ); + OUT_RING( R128_GMC_SRC_PITCH_OFFSET_CNTL + | R128_GMC_DST_PITCH_OFFSET_CNTL + | R128_GMC_BRUSH_NONE + | fb_bpp + | R128_GMC_SRC_DATATYPE_COLOR + | R128_ROP3_S + | R128_DP_SRC_SOURCE_MEMORY + | R128_GMC_CLR_CMP_CNTL_DIS + | R128_GMC_AUX_CLIP_DIS + | R128_GMC_WR_MSK_DIS ); + + OUT_RING( dev_priv->back_pitch_offset_c ); + OUT_RING( dev_priv->front_pitch_offset_c ); + + OUT_RING( (x << 16) | y ); + OUT_RING( (x << 16) | y ); + OUT_RING( (w << 16) | h ); + + ADVANCE_RING(); + } + + /* Increment the frame counter. The client-side 3D driver must + * throttle the framerate by waiting for this value before + * performing the swapbuffer ioctl. + */ + dev_priv->sarea_priv->last_frame++; + + BEGIN_RING( 2 ); + + OUT_RING( CCE_PACKET0( R128_LAST_FRAME_REG, 0 ) ); + OUT_RING( dev_priv->sarea_priv->last_frame ); + + ADVANCE_RING(); +} + +static void r128_cce_dispatch_vertex( drm_device_t *dev, + drm_buf_t *buf ) +{ + drm_r128_private_t *dev_priv = dev->dev_private; + drm_r128_buf_priv_t *buf_priv = buf->dev_private; + drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; + int format = sarea_priv->vc_format; + int offset = dev_priv->buffers->offset + buf->offset - dev->agp->base; + int size = buf->used; + int prim = buf_priv->prim; + int i = 0; + RING_LOCALS; + DRM_DEBUG( "%s: buf=%d nbox=%d\n", + __FUNCTION__, buf->idx, sarea_priv->nbox ); + + r128_update_ring_snapshot( dev_priv ); + + if ( 0 ) + r128_print_dirty( "dispatch_vertex", sarea_priv->dirty ); + + if ( buf->used ) { + buf_priv->dispatched = 1; + + if ( sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS ) { + r128_emit_state( dev_priv ); + } + + do { + /* Emit the next set of up to three cliprects */ + if ( i < sarea_priv->nbox ) { + r128_emit_clip_rects( dev_priv, + &sarea_priv->boxes[i], + sarea_priv->nbox - i ); + } + + /* Emit the vertex buffer rendering commands */ + BEGIN_RING( 5 ); + + OUT_RING( CCE_PACKET3( R128_3D_RNDR_GEN_INDX_PRIM, 3 ) ); + OUT_RING( offset ); + OUT_RING( size ); + OUT_RING( format ); + OUT_RING( prim | R128_CCE_VC_CNTL_PRIM_WALK_LIST | + (size << R128_CCE_VC_CNTL_NUM_SHIFT) ); + + ADVANCE_RING(); + + i += 3; + } while ( i < sarea_priv->nbox ); + } + + if ( buf_priv->discard ) { + buf_priv->age = dev_priv->sarea_priv->last_dispatch; + + /* Emit the vertex buffer age */ + BEGIN_RING( 2 ); + + OUT_RING( CCE_PACKET0( R128_LAST_DISPATCH_REG, 0 ) ); + OUT_RING( buf_priv->age ); + + ADVANCE_RING(); + + buf->pending = 1; + buf->used = 0; + /* FIXME: Check dispatched field */ + buf_priv->dispatched = 0; + } + + dev_priv->sarea_priv->last_dispatch++; + +#if 0 + if ( dev_priv->submit_age == R128_MAX_VB_AGE ) { + ret = r128_do_cce_idle( dev_priv ); + if ( ret < 0 ) return ret; + dev_priv->submit_age = 0; + r128_freelist_reset( dev ); + } +#endif + + sarea_priv->dirty &= ~R128_UPLOAD_CLIPRECTS; + sarea_priv->nbox = 0; +} + + + + +static void r128_cce_dispatch_indirect( drm_device_t *dev, + drm_buf_t *buf, + int start, int end ) +{ + drm_r128_private_t *dev_priv = dev->dev_private; + drm_r128_buf_priv_t *buf_priv = buf->dev_private; + RING_LOCALS; + DRM_DEBUG( "indirect: buf=%d s=0x%x e=0x%x\n", + buf->idx, start, end ); + + r128_update_ring_snapshot( dev_priv ); + + if ( start != end ) { + int offset = (dev_priv->buffers->offset - dev->agp->base + + buf->offset + start); + int dwords = (end - start + 3) / sizeof(u32); + + /* Indirect buffer data must be an even number of + * dwords, so if we've been given an odd number we must + * pad the data with a Type-2 CCE packet. + */ + if ( dwords & 1 ) { + u32 *data = (u32 *) + ((char *)dev_priv->buffers->handle + + buf->offset + start); + data[dwords++] = R128_CCE_PACKET2; + } + + buf_priv->dispatched = 1; + + /* Fire off the indirect buffer */ + BEGIN_RING( 3 ); + + OUT_RING( CCE_PACKET0( R128_PM4_IW_INDOFF, 1 ) ); + OUT_RING( offset ); + OUT_RING( dwords ); + + ADVANCE_RING(); + } + + if ( buf_priv->discard ) { + buf_priv->age = dev_priv->sarea_priv->last_dispatch; + + /* Emit the indirect buffer age */ + BEGIN_RING( 2 ); + + OUT_RING( CCE_PACKET0( R128_LAST_DISPATCH_REG, 0 ) ); + OUT_RING( buf_priv->age ); + + ADVANCE_RING(); + + buf->pending = 1; + buf->used = 0; + /* FIXME: Check dispatched field */ + buf_priv->dispatched = 0; + } + + dev_priv->sarea_priv->last_dispatch++; + +#if 0 + if ( dev_priv->submit_age == R128_MAX_VB_AGE ) { + ret = r128_do_cce_idle( dev_priv ); + if ( ret < 0 ) return ret; + dev_priv->submit_age = 0; + r128_freelist_reset( dev ); + } +#endif +} + +static void r128_cce_dispatch_indices( drm_device_t *dev, + drm_buf_t *buf, + int start, int end, + int count ) +{ + drm_r128_private_t *dev_priv = dev->dev_private; + drm_r128_buf_priv_t *buf_priv = buf->dev_private; + drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; + int format = sarea_priv->vc_format; + int offset = dev_priv->buffers->offset - dev->agp->base; + int prim = buf_priv->prim; + u32 *data; + int dwords; + int i = 0; + RING_LOCALS; + DRM_DEBUG( "indices: s=%d e=%d c=%d\n", start, end, count ); + + r128_update_ring_snapshot( dev_priv ); + + if ( 0 ) + r128_print_dirty( "dispatch_indices", sarea_priv->dirty ); + + if ( start != end ) { + buf_priv->dispatched = 1; + + if ( sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS ) { + r128_emit_state( dev_priv ); + } + + dwords = (end - start + 3) / sizeof(u32); + + data = (u32 *)((char *)dev_priv->buffers->handle + + buf->offset + start); + + data[0] = CCE_PACKET3( R128_3D_RNDR_GEN_INDX_PRIM, dwords-2 ); + + data[1] = offset; + data[2] = R128_MAX_VB_VERTS; + data[3] = format; + data[4] = (prim | R128_CCE_VC_CNTL_PRIM_WALK_IND | + (count << 16)); + + if ( count & 0x1 ) { + data[dwords-1] &= 0x0000ffff; + } + + do { + /* Emit the next set of up to three cliprects */ + if ( i < sarea_priv->nbox ) { + r128_emit_clip_rects( dev_priv, + &sarea_priv->boxes[i], + sarea_priv->nbox - i ); + } + + r128_cce_dispatch_indirect( dev, buf, start, end ); + + i += 3; + } while ( i < sarea_priv->nbox ); + } + + if ( buf_priv->discard ) { + buf_priv->age = dev_priv->sarea_priv->last_dispatch; + + /* Emit the vertex buffer age */ + BEGIN_RING( 2 ); + + OUT_RING( CCE_PACKET0( R128_LAST_DISPATCH_REG, 0 ) ); + OUT_RING( buf_priv->age ); + + ADVANCE_RING(); + + buf->pending = 1; + /* FIXME: Check dispatched field */ + buf_priv->dispatched = 0; + } + + dev_priv->sarea_priv->last_dispatch++; + +#if 0 + if ( dev_priv->submit_age == R128_MAX_VB_AGE ) { + ret = r128_do_cce_idle( dev_priv ); + if ( ret < 0 ) return ret; + dev_priv->submit_age = 0; + r128_freelist_reset( dev ); + } +#endif + + sarea_priv->dirty &= ~R128_UPLOAD_CLIPRECTS; + sarea_priv->nbox = 0; +} + +static int r128_cce_dispatch_blit( drm_device_t *dev, + drm_r128_blit_t *blit ) +{ + drm_r128_private_t *dev_priv = dev->dev_private; + drm_device_dma_t *dma = dev->dma; + drm_buf_t *buf; + drm_r128_buf_priv_t *buf_priv; + u32 *data; + int dword_shift, dwords; + RING_LOCALS; + DRM_DEBUG( "%s\n", __FUNCTION__ ); + + r128_update_ring_snapshot( dev_priv ); + + /* The compiler won't optimize away a division by a variable, + * even if the only legal values are powers of two. Thus, we'll + * use a shift instead. + */ + switch ( blit->format ) { + case R128_DATATYPE_ARGB1555: + case R128_DATATYPE_RGB565: + case R128_DATATYPE_ARGB4444: + dword_shift = 1; + break; + case R128_DATATYPE_ARGB8888: + dword_shift = 0; + break; + default: + DRM_ERROR( "invalid blit format %d\n", blit->format ); + return -EINVAL; + } + + /* Flush the pixel cache, and mark the contents as Read Invalid. + * This ensures no pixel data gets mixed up with the texture + * data from the host data blit, otherwise part of the texture + * image may be corrupted. + */ + BEGIN_RING( 2 ); + + OUT_RING( CCE_PACKET0( R128_PC_GUI_CTLSTAT, 0 ) ); + OUT_RING( R128_PC_RI_GUI | R128_PC_FLUSH_GUI ); + + ADVANCE_RING(); + + /* Dispatch the indirect buffer. + */ + buf = dma->buflist[blit->idx]; + buf_priv = buf->dev_private; + + if ( buf->pid != current->pid ) { + DRM_ERROR( "process %d using buffer owned by %d\n", + current->pid, buf->pid ); + return -EINVAL; + } + if ( buf->pending ) { + DRM_ERROR( "sending pending buffer %d\n", blit->idx ); + return -EINVAL; + } + + buf_priv->discard = 1; + + dwords = (blit->width * blit->height) >> dword_shift; + + data = (u32 *)((char *)dev_priv->buffers->handle + buf->offset); + + data[0] = CCE_PACKET3( R128_CNTL_HOSTDATA_BLT, dwords + 6 ); + data[1] = ( R128_GMC_DST_PITCH_OFFSET_CNTL + | R128_GMC_BRUSH_NONE + | (blit->format << 8) + | R128_GMC_SRC_DATATYPE_COLOR + | R128_ROP3_S + | R128_DP_SRC_SOURCE_HOST_DATA + | R128_GMC_CLR_CMP_CNTL_DIS + | R128_GMC_AUX_CLIP_DIS + | R128_GMC_WR_MSK_DIS ); + + data[2] = (blit->pitch << 21) | (blit->offset >> 5); + data[3] = 0xffffffff; + data[4] = 0xffffffff; + data[5] = (blit->y << 16) | blit->x; + data[6] = (blit->height << 16) | blit->width; + data[7] = dwords; + + buf->used = (dwords + 8) * sizeof(u32); + + r128_cce_dispatch_indirect( dev, buf, 0, buf->used ); + + /* Flush the pixel cache after the blit completes. This ensures + * the texture data is written out to memory before rendering + * continues. + */ + BEGIN_RING( 2 ); + + OUT_RING( CCE_PACKET0( R128_PC_GUI_CTLSTAT, 0 ) ); + OUT_RING( R128_PC_FLUSH_GUI ); + + ADVANCE_RING(); + + return 0; +} + + +/* ================================================================ + * Tiled depth buffer management + * + * FIXME: These should all set the destination write mask for when we + * have hardware stencil support. + */ + +static int r128_cce_dispatch_write_span( drm_device_t *dev, + drm_r128_depth_t *depth ) +{ + drm_r128_private_t *dev_priv = dev->dev_private; + int count, x, y; + u32 *buffer; + u8 *mask; + u32 depth_bpp; + int i; + RING_LOCALS; + DRM_DEBUG( "%s\n", __FUNCTION__ ); + + r128_update_ring_snapshot( dev_priv ); + + switch ( dev_priv->depth_bpp ) { + case 16: + depth_bpp = R128_GMC_DST_16BPP; + break; + case 24: + case 32: + depth_bpp = R128_GMC_DST_32BPP; + break; + default: + return -EINVAL; + } + + count = depth->n; + if ( copy_from_user( &x, depth->x, sizeof(x) ) ) { + return -EFAULT; + } + if ( copy_from_user( &y, depth->y, sizeof(y) ) ) { + return -EFAULT; + } + + buffer = kmalloc( depth->n * sizeof(u32), 0 ); + if ( buffer == NULL ) + return -ENOMEM; + if ( copy_from_user( buffer, depth->buffer, + depth->n * sizeof(u32) ) ) { + kfree( buffer ); + return -EFAULT; + } + + if ( depth->mask ) { + mask = kmalloc( depth->n * sizeof(u8), 0 ); + if ( mask == NULL ) { + kfree( buffer ); + return -ENOMEM; + } + if ( copy_from_user( mask, depth->mask, + depth->n * sizeof(u8) ) ) { + kfree( buffer ); + kfree( mask ); + return -EFAULT; + } + + for ( i = 0 ; i < count ; i++, x++ ) { + if ( mask[i] ) { + BEGIN_RING( 6 ); + + OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, + 4 ) ); + OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL + | R128_GMC_BRUSH_SOLID_COLOR + | depth_bpp + | R128_GMC_SRC_DATATYPE_COLOR + | R128_ROP3_P + | R128_GMC_CLR_CMP_CNTL_DIS + | R128_GMC_WR_MSK_DIS ); + + OUT_RING( dev_priv->depth_pitch_offset_c ); + OUT_RING( buffer[i] ); + + OUT_RING( (x << 16) | y ); + OUT_RING( (1 << 16) | 1 ); + + ADVANCE_RING(); + } + } + + kfree( mask ); + } else { + for ( i = 0 ; i < count ; i++, x++ ) { + BEGIN_RING( 6 ); + + OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); + OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL + | R128_GMC_BRUSH_SOLID_COLOR + | depth_bpp + | R128_GMC_SRC_DATATYPE_COLOR + | R128_ROP3_P + | R128_GMC_CLR_CMP_CNTL_DIS + | R128_GMC_WR_MSK_DIS ); + + OUT_RING( dev_priv->depth_pitch_offset_c ); + OUT_RING( buffer[i] ); + + OUT_RING( (x << 16) | y ); + OUT_RING( (1 << 16) | 1 ); + + ADVANCE_RING(); + } + } + + kfree( buffer ); + + return 0; +} + +static int r128_cce_dispatch_write_pixels( drm_device_t *dev, + drm_r128_depth_t *depth ) +{ + drm_r128_private_t *dev_priv = dev->dev_private; + int count, *x, *y; + u32 *buffer; + u8 *mask; + u32 depth_bpp; + int i; + RING_LOCALS; + DRM_DEBUG( "%s\n", __FUNCTION__ ); + + r128_update_ring_snapshot( dev_priv ); + + switch ( dev_priv->depth_bpp ) { + case 16: + depth_bpp = R128_GMC_DST_16BPP; + break; + case 24: + case 32: + depth_bpp = R128_GMC_DST_32BPP; + break; + default: + return -EINVAL; + } + + count = depth->n; + + x = kmalloc( count * sizeof(*x), 0 ); + if ( x == NULL ) { + return -ENOMEM; + } + y = kmalloc( count * sizeof(*y), 0 ); + if ( y == NULL ) { + kfree( x ); + return -ENOMEM; + } + if ( copy_from_user( x, depth->x, count * sizeof(int) ) ) { + kfree( x ); + kfree( y ); + return -EFAULT; + } + if ( copy_from_user( y, depth->y, count * sizeof(int) ) ) { + kfree( x ); + kfree( y ); + return -EFAULT; + } + + buffer = kmalloc( depth->n * sizeof(u32), 0 ); + if ( buffer == NULL ) { + kfree( x ); + kfree( y ); + return -ENOMEM; + } + if ( copy_from_user( buffer, depth->buffer, + depth->n * sizeof(u32) ) ) { + kfree( x ); + kfree( y ); + kfree( buffer ); + return -EFAULT; + } + + if ( depth->mask ) { + mask = kmalloc( depth->n * sizeof(u8), 0 ); + if ( mask == NULL ) { + kfree( x ); + kfree( y ); + kfree( buffer ); + return -ENOMEM; + } + if ( copy_from_user( mask, depth->mask, + depth->n * sizeof(u8) ) ) { + kfree( x ); + kfree( y ); + kfree( buffer ); + kfree( mask ); + return -EFAULT; + } + + for ( i = 0 ; i < count ; i++ ) { + if ( mask[i] ) { + BEGIN_RING( 6 ); + + OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, + 4 ) ); + OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL + | R128_GMC_BRUSH_SOLID_COLOR + | depth_bpp + | R128_GMC_SRC_DATATYPE_COLOR + | R128_ROP3_P + | R128_GMC_CLR_CMP_CNTL_DIS + | R128_GMC_WR_MSK_DIS ); + + OUT_RING( dev_priv->depth_pitch_offset_c ); + OUT_RING( buffer[i] ); + + OUT_RING( (x[i] << 16) | y[i] ); + OUT_RING( (1 << 16) | 1 ); + + ADVANCE_RING(); + } + } + + kfree( mask ); + } else { + for ( i = 0 ; i < count ; i++ ) { + BEGIN_RING( 6 ); + + OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); + OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL + | R128_GMC_BRUSH_SOLID_COLOR + | depth_bpp + | R128_GMC_SRC_DATATYPE_COLOR + | R128_ROP3_P + | R128_GMC_CLR_CMP_CNTL_DIS + | R128_GMC_WR_MSK_DIS ); + + OUT_RING( dev_priv->depth_pitch_offset_c ); + OUT_RING( buffer[i] ); + + OUT_RING( (x[i] << 16) | y[i] ); + OUT_RING( (1 << 16) | 1 ); + + ADVANCE_RING(); + } + } + + kfree( x ); + kfree( y ); + kfree( buffer ); + + return 0; +} + +static int r128_cce_dispatch_read_span( drm_device_t *dev, + drm_r128_depth_t *depth ) +{ + drm_r128_private_t *dev_priv = dev->dev_private; + int count, x, y; + u32 depth_bpp; + RING_LOCALS; + DRM_DEBUG( "%s\n", __FUNCTION__ ); + + r128_update_ring_snapshot( dev_priv ); + + switch ( dev_priv->depth_bpp ) { + case 16: + depth_bpp = R128_GMC_DST_16BPP; + break; + case 24: + case 32: + depth_bpp = R128_GMC_DST_32BPP; + break; + default: + return -EINVAL; + } + + count = depth->n; + if ( copy_from_user( &x, depth->x, sizeof(x) ) ) { + return -EFAULT; + } + if ( copy_from_user( &y, depth->y, sizeof(y) ) ) { + return -EFAULT; + } + + BEGIN_RING( 7 ); + + OUT_RING( CCE_PACKET3( R128_CNTL_BITBLT_MULTI, 5 ) ); + OUT_RING( R128_GMC_SRC_PITCH_OFFSET_CNTL + | R128_GMC_DST_PITCH_OFFSET_CNTL + | R128_GMC_BRUSH_NONE + | depth_bpp + | R128_GMC_SRC_DATATYPE_COLOR + | R128_ROP3_S + | R128_DP_SRC_SOURCE_MEMORY + | R128_GMC_CLR_CMP_CNTL_DIS + | R128_GMC_WR_MSK_DIS ); + + OUT_RING( dev_priv->depth_pitch_offset_c ); + OUT_RING( dev_priv->span_pitch_offset_c ); + + OUT_RING( (x << 16) | y ); + OUT_RING( (0 << 16) | 0 ); + OUT_RING( (count << 16) | 1 ); + + ADVANCE_RING(); + + return 0; +} + +static int r128_cce_dispatch_read_pixels( drm_device_t *dev, + drm_r128_depth_t *depth ) +{ + drm_r128_private_t *dev_priv = dev->dev_private; + int count, *x, *y; + u32 depth_bpp; + int i; + RING_LOCALS; + DRM_DEBUG( "%s\n", __FUNCTION__ ); + + r128_update_ring_snapshot( dev_priv ); + + switch ( dev_priv->depth_bpp ) { + case 16: + depth_bpp = R128_GMC_DST_16BPP; + break; + case 24: + case 32: + depth_bpp = R128_GMC_DST_32BPP; + break; + default: + return -EINVAL; + } + + count = depth->n; + if ( count > dev_priv->depth_pitch ) { + count = dev_priv->depth_pitch; + } + + x = kmalloc( count * sizeof(*x), 0 ); + if ( x == NULL ) { + return -ENOMEM; + } + y = kmalloc( count * sizeof(*y), 0 ); + if ( y == NULL ) { + kfree( x ); + return -ENOMEM; + } + if ( copy_from_user( x, depth->x, count * sizeof(int) ) ) { + kfree( x ); + kfree( y ); + return -EFAULT; + } + if ( copy_from_user( y, depth->y, count * sizeof(int) ) ) { + kfree( x ); + kfree( y ); + return -EFAULT; + } + + for ( i = 0 ; i < count ; i++ ) { + BEGIN_RING( 7 ); + + OUT_RING( CCE_PACKET3( R128_CNTL_BITBLT_MULTI, 5 ) ); + OUT_RING( R128_GMC_SRC_PITCH_OFFSET_CNTL + | R128_GMC_DST_PITCH_OFFSET_CNTL + | R128_GMC_BRUSH_NONE + | depth_bpp + | R128_GMC_SRC_DATATYPE_COLOR + | R128_ROP3_S + | R128_DP_SRC_SOURCE_MEMORY + | R128_GMC_CLR_CMP_CNTL_DIS + | R128_GMC_WR_MSK_DIS ); + + OUT_RING( dev_priv->depth_pitch_offset_c ); + OUT_RING( dev_priv->span_pitch_offset_c ); + + OUT_RING( (x[i] << 16) | y[i] ); + OUT_RING( (i << 16) | 0 ); + OUT_RING( (1 << 16) | 1 ); + + ADVANCE_RING(); + } + + kfree( x ); + kfree( y ); + + return 0; +} + + +/* ================================================================ + * Polygon stipple + */ + +static void r128_cce_dispatch_stipple( drm_device_t *dev, u32 *stipple ) +{ + drm_r128_private_t *dev_priv = dev->dev_private; + int i; + RING_LOCALS; + DRM_DEBUG( "%s\n", __FUNCTION__ ); + + r128_update_ring_snapshot( dev_priv ); + + BEGIN_RING( 33 ); + + OUT_RING( CCE_PACKET0( R128_BRUSH_DATA0, 31 ) ); + for ( i = 0 ; i < 32 ; i++ ) { + OUT_RING( stipple[i] ); + } + + ADVANCE_RING(); +} + + +/* ================================================================ + * IOCTL functions + */ + +int r128_cce_clear( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_r128_private_t *dev_priv = dev->dev_private; + drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_r128_clear_t clear; + DRM_DEBUG( "%s\n", __FUNCTION__ ); + + if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || + dev->lock.pid != current->pid ) { + DRM_ERROR( "r128_cce_clear called without lock held\n" ); + return -EINVAL; + } + + if ( copy_from_user( &clear, (drm_r128_clear_t *) arg, + sizeof(clear) ) ) + return -EFAULT; + + if ( sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS ) + sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS; + + r128_cce_dispatch_clear( dev, clear.flags, + clear.x, clear.y, clear.w, clear.h, + clear.clear_color, clear.clear_depth ); + + /* Make sure we restore the 3D state next time. + */ + dev_priv->sarea_priv->dirty |= R128_UPLOAD_CONTEXT | R128_UPLOAD_MASKS; + + return 0; +} + +int r128_cce_swap( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_r128_private_t *dev_priv = dev->dev_private; + drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; + DRM_DEBUG( "%s\n", __FUNCTION__ ); + + if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || + dev->lock.pid != current->pid ) { + DRM_ERROR( "r128_cce_swap called without lock held\n" ); + return -EINVAL; + } + + if ( sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS ) + sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS; + + r128_cce_dispatch_swap( dev ); + + /* Make sure we restore the 3D state next time. + */ + dev_priv->sarea_priv->dirty |= R128_UPLOAD_CONTEXT | R128_UPLOAD_MASKS; + + return 0; +} + +int r128_cce_vertex( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_r128_private_t *dev_priv = dev->dev_private; + drm_device_dma_t *dma = dev->dma; + drm_buf_t *buf; + drm_r128_buf_priv_t *buf_priv; + drm_r128_vertex_t vertex; + + if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || + dev->lock.pid != current->pid ) { + DRM_ERROR( "%s called without lock held\n", __FUNCTION__ ); + return -EINVAL; + } + if ( !dev_priv || dev_priv->is_pci ) { + DRM_ERROR( "%s called with a PCI card\n", __FUNCTION__ ); + return -EINVAL; + } + + if ( copy_from_user( &vertex, (drm_r128_vertex_t *)arg, + sizeof(vertex) ) ) + return -EFAULT; + + DRM_DEBUG( "%s: pid=%d index=%d count=%d discard=%d\n", + __FUNCTION__, current->pid, + vertex.idx, vertex.count, vertex.discard ); + + if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) { + DRM_ERROR( "buffer index %d (of %d max)\n", + vertex.idx, dma->buf_count - 1 ); + return -EINVAL; + } + if ( vertex.prim < 0 || + vertex.prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 ) { + DRM_ERROR( "buffer prim %d\n", vertex.prim ); + return -EINVAL; + } + + buf = dma->buflist[vertex.idx]; + buf_priv = buf->dev_private; + + if ( buf->pid != current->pid ) { + DRM_ERROR( "process %d using buffer owned by %d\n", + current->pid, buf->pid ); + return -EINVAL; + } + if ( buf->pending ) { + DRM_ERROR( "sending pending buffer %d\n", vertex.idx ); + return -EINVAL; + } + + buf->used = vertex.count; + buf_priv->prim = vertex.prim; + buf_priv->discard = vertex.discard; + + r128_cce_dispatch_vertex( dev, buf ); + + return 0; +} + +int r128_cce_indices( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_r128_private_t *dev_priv = dev->dev_private; + drm_device_dma_t *dma = dev->dma; + drm_buf_t *buf; + drm_r128_buf_priv_t *buf_priv; + drm_r128_indices_t elts; + int count; + + if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || + dev->lock.pid != current->pid ) { + DRM_ERROR( "%s called without lock held\n", __FUNCTION__ ); + return -EINVAL; + } + if ( !dev_priv || dev_priv->is_pci ) { + DRM_ERROR( "%s called with a PCI card\n", __FUNCTION__ ); + return -EINVAL; + } + + if ( copy_from_user( &elts, (drm_r128_indices_t *)arg, + sizeof(elts) ) ) + return -EFAULT; + + DRM_DEBUG( "%s: pid=%d buf=%d s=%d e=%d d=%d\n", + __FUNCTION__, current->pid, + elts.idx, elts.start, elts.end, elts.discard ); + + if ( elts.idx < 0 || elts.idx >= dma->buf_count ) { + DRM_ERROR( "buffer index %d (of %d max)\n", + elts.idx, dma->buf_count - 1 ); + return -EINVAL; + } + if ( elts.prim < 0 || + elts.prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 ) { + DRM_ERROR( "buffer prim %d\n", elts.prim ); + return -EINVAL; + } + + buf = dma->buflist[elts.idx]; + buf_priv = buf->dev_private; + + if ( buf->pid != current->pid ) { + DRM_ERROR( "process %d using buffer owned by %d\n", + current->pid, buf->pid ); + return -EINVAL; + } + if ( buf->pending ) { + DRM_ERROR( "sending pending buffer %d\n", elts.idx ); + return -EINVAL; + } + + count = (elts.end - elts.start) / sizeof(u16); + elts.start -= R128_INDEX_PRIM_OFFSET; + + if ( elts.start & 0x7 ) { + DRM_ERROR( "misaligned buffer 0x%x\n", elts.start ); + return -EINVAL; + } + if ( elts.start < buf->used ) { + DRM_ERROR( "no header 0x%x - 0x%x\n", elts.start, buf->used ); + return -EINVAL; + } + + buf->used = elts.end; + buf_priv->prim = elts.prim; + buf_priv->discard = elts.discard; + + r128_cce_dispatch_indices( dev, buf, elts.start, elts.end, count ); + + return 0; +} + +int r128_cce_blit( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_device_dma_t *dma = dev->dma; + drm_r128_blit_t blit; + + if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || + dev->lock.pid != current->pid ) { + DRM_ERROR( "%s called without lock held\n", __FUNCTION__ ); + return -EINVAL; + } + + if ( copy_from_user( &blit, (drm_r128_blit_t *)arg, + sizeof(blit) ) ) + return -EFAULT; + + DRM_DEBUG( "%s: pid=%d index=%d\n", + __FUNCTION__, current->pid, blit.idx ); + + if ( blit.idx < 0 || blit.idx >= dma->buf_count ) { + DRM_ERROR( "buffer index %d (of %d max)\n", + blit.idx, dma->buf_count - 1 ); + return -EINVAL; + } + + return r128_cce_dispatch_blit( dev, &blit ); +} + +int r128_cce_depth( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_r128_depth_t depth; + + if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || + dev->lock.pid != current->pid ) { + DRM_ERROR( "%s called without lock held\n", __FUNCTION__ ); + return -EINVAL; + } + + if ( copy_from_user( &depth, (drm_r128_depth_t *)arg, + sizeof(depth) ) ) + return -EFAULT; + + switch ( depth.func ) { + case R128_WRITE_SPAN: + return r128_cce_dispatch_write_span( dev, &depth ); + case R128_WRITE_PIXELS: + return r128_cce_dispatch_write_pixels( dev, &depth ); + case R128_READ_SPAN: + return r128_cce_dispatch_read_span( dev, &depth ); + case R128_READ_PIXELS: + return r128_cce_dispatch_read_pixels( dev, &depth ); + } + + return -EINVAL; +} + +int r128_cce_stipple( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_r128_stipple_t stipple; + u32 mask[32]; + + if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || + dev->lock.pid != current->pid ) { + DRM_ERROR( "%s called without lock held\n", __FUNCTION__ ); + return -EINVAL; + } + + if ( copy_from_user( &stipple, (drm_r128_stipple_t *)arg, + sizeof(stipple) ) ) + return -EFAULT; + + if ( copy_from_user( &mask, stipple.mask, + 32 * sizeof(u32) ) ) + return -EFAULT; + + r128_cce_dispatch_stipple( dev, mask ); + + return 0; +} diff -urN linux-2.4.10/drivers/char/drm-4.0/radeon_bufs.c linux-2.4.10-lia/drivers/char/drm-4.0/radeon_bufs.c --- linux-2.4.10/drivers/char/drm-4.0/radeon_bufs.c Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/radeon_bufs.c Wed Aug 15 20:52:12 2001 @@ -0,0 +1,312 @@ +/* radeon_bufs.c -- IOCTLs to manage buffers -*- linux-c -*- + * + * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Fremont, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: Kevin E. Martin + * Rickard E. (Rik) Faith + * Jeff Hartmann + * + */ + +#define __NO_VERSION__ +#include +#include "drmP.h" +#include "radeon_drv.h" +#include "linux/un.h" + + +#if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE) +int radeon_addbufs_agp(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_device_dma_t *dma = dev->dma; + drm_buf_desc_t request; + drm_buf_entry_t *entry; + drm_buf_t *buf; + unsigned long offset; + unsigned long agp_offset; + int count; + int order; + int size; + int alignment; + int page_order; + int total; + int byte_count; + int i; + + if (!dma) return -EINVAL; + + if (copy_from_user(&request, (drm_buf_desc_t *)arg, sizeof(request))) + return -EFAULT; + + count = request.count; + order = drm_order(request.size); + size = 1 << order; + + alignment = (request.flags & _DRM_PAGE_ALIGN) ? PAGE_ALIGN(size):size; + page_order = order - PAGE_SHIFT > 0 ? order - PAGE_SHIFT : 0; + total = PAGE_SIZE << page_order; + + byte_count = 0; + agp_offset = dev->agp->base + request.agp_start; + + DRM_DEBUG("count: %d\n", count); + DRM_DEBUG("order: %d\n", order); + DRM_DEBUG("size: %d\n", size); + DRM_DEBUG("agp_offset: %ld\n", agp_offset); + DRM_DEBUG("alignment: %d\n", alignment); + DRM_DEBUG("page_order: %d\n", page_order); + DRM_DEBUG("total: %d\n", total); + + if (order < DRM_MIN_ORDER || order > DRM_MAX_ORDER) return -EINVAL; + if (dev->queue_count) return -EBUSY; /* Not while in use */ + + spin_lock(&dev->count_lock); + if (dev->buf_use) { + spin_unlock(&dev->count_lock); + return -EBUSY; + } + atomic_inc(&dev->buf_alloc); + spin_unlock(&dev->count_lock); + + down(&dev->struct_sem); + entry = &dma->bufs[order]; + if (entry->buf_count) { + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); + return -ENOMEM; /* May only call once for each order */ + } + + /* Might be too low a limit. XFree folks need to fix this properly */ + + if(count < 0 || count > 4096) + { + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); + return -EINVAL; + } + + entry->buflist = drm_alloc(count * sizeof(*entry->buflist), + DRM_MEM_BUFS); + if (!entry->buflist) { + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); + return -ENOMEM; + } + memset(entry->buflist, 0, count * sizeof(*entry->buflist)); + + entry->buf_size = size; + entry->page_order = page_order; + offset = 0; + + for (offset = 0; + entry->buf_count < count; + offset += alignment, ++entry->buf_count) { + buf = &entry->buflist[entry->buf_count]; + buf->idx = dma->buf_count + entry->buf_count; + buf->total = alignment; + buf->order = order; + buf->used = 0; + buf->offset = (dma->byte_count + offset); + buf->address = (void *)(agp_offset + offset); + buf->next = NULL; + buf->waiting = 0; + buf->pending = 0; + init_waitqueue_head(&buf->dma_wait); + buf->pid = 0; + + buf->dev_priv_size = sizeof(drm_radeon_buf_priv_t); + buf->dev_private = drm_alloc(sizeof(drm_radeon_buf_priv_t), + DRM_MEM_BUFS); + if (!buf->dev_private) { + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); + return -ENOMEM; + } + memset(buf->dev_private, 0, buf->dev_priv_size); + +#if DRM_DMA_HISTOGRAM + buf->time_queued = 0; + buf->time_dispatched = 0; + buf->time_completed = 0; + buf->time_freed = 0; +#endif + + byte_count += PAGE_SIZE << page_order; + + DRM_DEBUG("buffer %d @ %p\n", + entry->buf_count, buf->address); + } + + DRM_DEBUG("byte_count: %d\n", byte_count); + + dma->buflist = drm_realloc(dma->buflist, + dma->buf_count * sizeof(*dma->buflist), + (dma->buf_count + entry->buf_count) + * sizeof(*dma->buflist), + DRM_MEM_BUFS); + for (i = dma->buf_count; i < dma->buf_count + entry->buf_count; i++) + dma->buflist[i] = &entry->buflist[i - dma->buf_count]; + + dma->buf_count += entry->buf_count; + dma->byte_count += byte_count; + + drm_freelist_create(&entry->freelist, entry->buf_count); + for (i = 0; i < entry->buf_count; i++) { + drm_freelist_put(dev, &entry->freelist, &entry->buflist[i]); + } + + up(&dev->struct_sem); + + request.count = entry->buf_count; + request.size = size; + + if (copy_to_user((drm_buf_desc_t *)arg, &request, sizeof(request))) + return -EFAULT; + + dma->flags = _DRM_DMA_USE_AGP; + + atomic_dec(&dev->buf_alloc); + return 0; +} +#endif + +int radeon_addbufs(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_radeon_private_t *dev_priv = dev->dev_private; + drm_buf_desc_t request; + + if (!dev_priv || dev_priv->is_pci) return -EINVAL; + + if (copy_from_user(&request, (drm_buf_desc_t *)arg, sizeof(request))) + return -EFAULT; + +#if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE) + if (request.flags & _DRM_AGP_BUFFER) + return radeon_addbufs_agp(inode, filp, cmd, arg); + else +#endif + return -EINVAL; +} + +int radeon_mapbufs(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_radeon_private_t *dev_priv = dev->dev_private; + drm_device_dma_t *dma = dev->dma; + int retcode = 0; + const int zero = 0; + unsigned long virtual; + unsigned long address; + drm_buf_map_t request; + int i; + + if (!dma || !dev_priv || dev_priv->is_pci) return -EINVAL; + + DRM_DEBUG("\n"); + + spin_lock(&dev->count_lock); + if (atomic_read(&dev->buf_alloc)) { + spin_unlock(&dev->count_lock); + return -EBUSY; + } + ++dev->buf_use; /* Can't allocate more after this call */ + spin_unlock(&dev->count_lock); + + if (copy_from_user(&request, (drm_buf_map_t *)arg, sizeof(request))) + return -EFAULT; + + if (request.count >= dma->buf_count) { + if (dma->flags & _DRM_DMA_USE_AGP) { + drm_map_t *map; + + map = dev_priv->buffers; + if (!map) { + retcode = -EINVAL; + goto done; + } + + down_write(¤t->mm->mmap_sem); + virtual = do_mmap(filp, 0, map->size, + PROT_READ|PROT_WRITE, + MAP_SHARED, + (unsigned long)map->offset); + up_write(¤t->mm->mmap_sem); + } else { + down_write(¤t->mm->mmap_sem); + virtual = do_mmap(filp, 0, dma->byte_count, + PROT_READ|PROT_WRITE, MAP_SHARED, 0); + up_write(¤t->mm->mmap_sem); + } + if (virtual > -1024UL) { + /* Real error */ + retcode = (signed long)virtual; + goto done; + } + request.virtual = (void *)virtual; + + for (i = 0; i < dma->buf_count; i++) { + if (copy_to_user(&request.list[i].idx, + &dma->buflist[i]->idx, + sizeof(request.list[0].idx))) { + retcode = -EFAULT; + goto done; + } + if (copy_to_user(&request.list[i].total, + &dma->buflist[i]->total, + sizeof(request.list[0].total))) { + retcode = -EFAULT; + goto done; + } + if (copy_to_user(&request.list[i].used, + &zero, + sizeof(zero))) { + retcode = -EFAULT; + goto done; + } + address = virtual + dma->buflist[i]->offset; + if (copy_to_user(&request.list[i].address, + &address, + sizeof(address))) { + retcode = -EFAULT; + goto done; + } + } + } + done: + request.count = dma->buf_count; + DRM_DEBUG("%d buffers, retcode = %d\n", request.count, retcode); + + if (copy_to_user((drm_buf_map_t *)arg, &request, sizeof(request))) + return -EFAULT; + + return retcode; +} diff -urN linux-2.4.10/drivers/char/drm-4.0/radeon_context.c linux-2.4.10-lia/drivers/char/drm-4.0/radeon_context.c --- linux-2.4.10/drivers/char/drm-4.0/radeon_context.c Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/radeon_context.c Wed Aug 15 20:52:12 2001 @@ -0,0 +1,215 @@ +/* radeon_context.c -- IOCTLs for Radeon contexts -*- linux-c -*- + * + * Copyright 1999, 2000 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Fremont, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Author: Kevin E. Martin + * Rickard E. (Rik) Faith + * + */ + +#define __NO_VERSION__ +#include "drmP.h" +#include "radeon_drv.h" + +extern drm_ctx_t radeon_res_ctx; + +static int radeon_alloc_queue(drm_device_t *dev) +{ + return drm_ctxbitmap_next(dev); +} + +int radeon_context_switch(drm_device_t *dev, int old, int new) +{ + char buf[64]; + + atomic_inc(&dev->total_ctx); + + if (test_and_set_bit(0, &dev->context_flag)) { + DRM_ERROR("Reentering -- FIXME\n"); + return -EBUSY; + } + +#if DRM_DMA_HISTOGRAM + dev->ctx_start = get_cycles(); +#endif + + DRM_DEBUG("Context switch from %d to %d\n", old, new); + + if (new == dev->last_context) { + clear_bit(0, &dev->context_flag); + return 0; + } + + if (drm_flags & DRM_FLAG_NOCTX) { + radeon_context_switch_complete(dev, new); + } else { + sprintf(buf, "C %d %d\n", old, new); + drm_write_string(dev, buf); + } + + return 0; +} + +int radeon_context_switch_complete(drm_device_t *dev, int new) +{ + dev->last_context = new; /* PRE/POST: This is the _only_ writer. */ + dev->last_switch = jiffies; + + if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { + DRM_ERROR("Lock isn't held after context switch\n"); + } + + /* If a context switch is ever initiated + when the kernel holds the lock, release + that lock here. */ +#if DRM_DMA_HISTOGRAM + atomic_inc(&dev->histo.ctx[drm_histogram_slot(get_cycles() + - dev->ctx_start)]); + +#endif + clear_bit(0, &dev->context_flag); + wake_up(&dev->context_wait); + + return 0; +} + + +int radeon_resctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_ctx_res_t res; + drm_ctx_t ctx; + int i; + + DRM_DEBUG("%d\n", DRM_RESERVED_CONTEXTS); + if (copy_from_user(&res, (drm_ctx_res_t *)arg, sizeof(res))) + return -EFAULT; + if (res.count >= DRM_RESERVED_CONTEXTS) { + memset(&ctx, 0, sizeof(ctx)); + for (i = 0; i < DRM_RESERVED_CONTEXTS; i++) { + ctx.handle = i; + if (copy_to_user(&res.contexts[i], &i, sizeof(i))) + return -EFAULT; + } + } + res.count = DRM_RESERVED_CONTEXTS; + if (copy_to_user((drm_ctx_res_t *)arg, &res, sizeof(res))) + return -EFAULT; + return 0; +} + + +int radeon_addctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ctx_t ctx; + + if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx))) + return -EFAULT; + if ((ctx.handle = radeon_alloc_queue(dev)) == DRM_KERNEL_CONTEXT) { + /* Skip kernel's context and get a new one. */ + ctx.handle = radeon_alloc_queue(dev); + } + DRM_DEBUG("%d\n", ctx.handle); + if (ctx.handle == -1) { + DRM_DEBUG("Not enough free contexts.\n"); + /* Should this return -EBUSY instead? */ + return -ENOMEM; + } + + if (copy_to_user((drm_ctx_t *)arg, &ctx, sizeof(ctx))) + return -EFAULT; + return 0; +} + +int radeon_modctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_ctx_t ctx; + + if (copy_from_user(&ctx, (drm_ctx_t*)arg, sizeof(ctx))) + return -EFAULT; + if (ctx.flags==_DRM_CONTEXT_PRESERVED) + radeon_res_ctx.handle=ctx.handle; + return 0; +} + +int radeon_getctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_ctx_t ctx; + + if (copy_from_user(&ctx, (drm_ctx_t*)arg, sizeof(ctx))) + return -EFAULT; + /* This is 0, because we don't hanlde any context flags */ + ctx.flags = 0; + if (copy_to_user((drm_ctx_t*)arg, &ctx, sizeof(ctx))) + return -EFAULT; + return 0; +} + +int radeon_switchctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ctx_t ctx; + + if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx))) + return -EFAULT; + DRM_DEBUG("%d\n", ctx.handle); + return radeon_context_switch(dev, dev->last_context, ctx.handle); +} + +int radeon_newctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ctx_t ctx; + + if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx))) + return -EFAULT; + DRM_DEBUG("%d\n", ctx.handle); + radeon_context_switch_complete(dev, ctx.handle); + + return 0; +} + +int radeon_rmctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ctx_t ctx; + + if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx))) + return -EFAULT; + DRM_DEBUG("%d\n", ctx.handle); + drm_ctxbitmap_free(dev, ctx.handle); + + return 0; +} diff -urN linux-2.4.10/drivers/char/drm-4.0/radeon_cp.c linux-2.4.10-lia/drivers/char/drm-4.0/radeon_cp.c --- linux-2.4.10/drivers/char/drm-4.0/radeon_cp.c Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/radeon_cp.c Mon Aug 20 18:09:34 2001 @@ -0,0 +1,1353 @@ +/* radeon_cp.c -- CP support for Radeon -*- linux-c -*- + * + * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Fremont, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Kevin E. Martin + * Gareth Hughes + * + */ + +#define __NO_VERSION__ +#include "drmP.h" +#include "radeon_drv.h" + +#include /* For task queue support */ +#include + +#define RADEON_FIFO_DEBUG 0 + + +/* CP microcode (from ATI) */ +static u32 radeon_cp_microcode[][2] = { + { 0x21007000, 0000000000 }, + { 0x20007000, 0000000000 }, + { 0x000000b4, 0x00000004 }, + { 0x000000b8, 0x00000004 }, + { 0x6f5b4d4c, 0000000000 }, + { 0x4c4c427f, 0000000000 }, + { 0x5b568a92, 0000000000 }, + { 0x4ca09c6d, 0000000000 }, + { 0xad4c4c4c, 0000000000 }, + { 0x4ce1af3d, 0000000000 }, + { 0xd8afafaf, 0000000000 }, + { 0xd64c4cdc, 0000000000 }, + { 0x4cd10d10, 0000000000 }, + { 0x000f0000, 0x00000016 }, + { 0x362f242d, 0000000000 }, + { 0x00000012, 0x00000004 }, + { 0x000f0000, 0x00000016 }, + { 0x362f282d, 0000000000 }, + { 0x000380e7, 0x00000002 }, + { 0x04002c97, 0x00000002 }, + { 0x000f0001, 0x00000016 }, + { 0x333a3730, 0000000000 }, + { 0x000077ef, 0x00000002 }, + { 0x00061000, 0x00000002 }, + { 0x00000021, 0x0000001a }, + { 0x00004000, 0x0000001e }, + { 0x00061000, 0x00000002 }, + { 0x00000021, 0x0000001a }, + { 0x00004000, 0x0000001e }, + { 0x00061000, 0x00000002 }, + { 0x00000021, 0x0000001a }, + { 0x00004000, 0x0000001e }, + { 0x00000017, 0x00000004 }, + { 0x0003802b, 0x00000002 }, + { 0x040067e0, 0x00000002 }, + { 0x00000017, 0x00000004 }, + { 0x000077e0, 0x00000002 }, + { 0x00065000, 0x00000002 }, + { 0x000037e1, 0x00000002 }, + { 0x040067e1, 0x00000006 }, + { 0x000077e0, 0x00000002 }, + { 0x000077e1, 0x00000002 }, + { 0x000077e1, 0x00000006 }, + { 0xffffffff, 0000000000 }, + { 0x10000000, 0000000000 }, + { 0x0003802b, 0x00000002 }, + { 0x040067e0, 0x00000006 }, + { 0x00007675, 0x00000002 }, + { 0x00007676, 0x00000002 }, + { 0x00007677, 0x00000002 }, + { 0x00007678, 0x00000006 }, + { 0x0003802c, 0x00000002 }, + { 0x04002676, 0x00000002 }, + { 0x00007677, 0x00000002 }, + { 0x00007678, 0x00000006 }, + { 0x0000002f, 0x00000018 }, + { 0x0000002f, 0x00000018 }, + { 0000000000, 0x00000006 }, + { 0x00000030, 0x00000018 }, + { 0x00000030, 0x00000018 }, + { 0000000000, 0x00000006 }, + { 0x01605000, 0x00000002 }, + { 0x00065000, 0x00000002 }, + { 0x00098000, 0x00000002 }, + { 0x00061000, 0x00000002 }, + { 0x64c0603e, 0x00000004 }, + { 0x000380e6, 0x00000002 }, + { 0x040025c5, 0x00000002 }, + { 0x00080000, 0x00000016 }, + { 0000000000, 0000000000 }, + { 0x0400251d, 0x00000002 }, + { 0x00007580, 0x00000002 }, + { 0x00067581, 0x00000002 }, + { 0x04002580, 0x00000002 }, + { 0x00067581, 0x00000002 }, + { 0x00000049, 0x00000004 }, + { 0x00005000, 0000000000 }, + { 0x000380e6, 0x00000002 }, + { 0x040025c5, 0x00000002 }, + { 0x00061000, 0x00000002 }, + { 0x0000750e, 0x00000002 }, + { 0x00019000, 0x00000002 }, + { 0x00011055, 0x00000014 }, + { 0x00000055, 0x00000012 }, + { 0x0400250f, 0x00000002 }, + { 0x0000504f, 0x00000004 }, + { 0x000380e6, 0x00000002 }, + { 0x040025c5, 0x00000002 }, + { 0x00007565, 0x00000002 }, + { 0x00007566, 0x00000002 }, + { 0x00000058, 0x00000004 }, + { 0x000380e6, 0x00000002 }, + { 0x040025c5, 0x00000002 }, + { 0x01e655b4, 0x00000002 }, + { 0x4401b0e4, 0x00000002 }, + { 0x01c110e4, 0x00000002 }, + { 0x26667066, 0x00000018 }, + { 0x040c2565, 0x00000002 }, + { 0x00000066, 0x00000018 }, + { 0x04002564, 0x00000002 }, + { 0x00007566, 0x00000002 }, + { 0x0000005d, 0x00000004 }, + { 0x00401069, 0x00000008 }, + { 0x00101000, 0x00000002 }, + { 0x000d80ff, 0x00000002 }, + { 0x0080006c, 0x00000008 }, + { 0x000f9000, 0x00000002 }, + { 0x000e00ff, 0x00000002 }, + { 0000000000, 0x00000006 }, + { 0x0000008f, 0x00000018 }, + { 0x0000005b, 0x00000004 }, + { 0x000380e6, 0x00000002 }, + { 0x040025c5, 0x00000002 }, + { 0x00007576, 0x00000002 }, + { 0x00065000, 0x00000002 }, + { 0x00009000, 0x00000002 }, + { 0x00041000, 0x00000002 }, + { 0x0c00350e, 0x00000002 }, + { 0x00049000, 0x00000002 }, + { 0x00051000, 0x00000002 }, + { 0x01e785f8, 0x00000002 }, + { 0x00200000, 0x00000002 }, + { 0x0060007e, 0x0000000c }, + { 0x00007563, 0x00000002 }, + { 0x006075f0, 0x00000021 }, + { 0x20007073, 0x00000004 }, + { 0x00005073, 0x00000004 }, + { 0x000380e6, 0x00000002 }, + { 0x040025c5, 0x00000002 }, + { 0x00007576, 0x00000002 }, + { 0x00007577, 0x00000002 }, + { 0x0000750e, 0x00000002 }, + { 0x0000750f, 0x00000002 }, + { 0x00a05000, 0x00000002 }, + { 0x00600083, 0x0000000c }, + { 0x006075f0, 0x00000021 }, + { 0x000075f8, 0x00000002 }, + { 0x00000083, 0x00000004 }, + { 0x000a750e, 0x00000002 }, + { 0x000380e6, 0x00000002 }, + { 0x040025c5, 0x00000002 }, + { 0x0020750f, 0x00000002 }, + { 0x00600086, 0x00000004 }, + { 0x00007570, 0x00000002 }, + { 0x00007571, 0x00000002 }, + { 0x00007572, 0x00000006 }, + { 0x000380e6, 0x00000002 }, + { 0x040025c5, 0x00000002 }, + { 0x00005000, 0x00000002 }, + { 0x00a05000, 0x00000002 }, + { 0x00007568, 0x00000002 }, + { 0x00061000, 0x00000002 }, + { 0x00000095, 0x0000000c }, + { 0x00058000, 0x00000002 }, + { 0x0c607562, 0x00000002 }, + { 0x00000097, 0x00000004 }, + { 0x000380e6, 0x00000002 }, + { 0x040025c5, 0x00000002 }, + { 0x00600096, 0x00000004 }, + { 0x400070e5, 0000000000 }, + { 0x000380e6, 0x00000002 }, + { 0x040025c5, 0x00000002 }, + { 0x000380e5, 0x00000002 }, + { 0x000000a8, 0x0000001c }, + { 0x000650aa, 0x00000018 }, + { 0x040025bb, 0x00000002 }, + { 0x000610ab, 0x00000018 }, + { 0x040075bc, 0000000000 }, + { 0x000075bb, 0x00000002 }, + { 0x000075bc, 0000000000 }, + { 0x00090000, 0x00000006 }, + { 0x00090000, 0x00000002 }, + { 0x000d8002, 0x00000006 }, + { 0x00007832, 0x00000002 }, + { 0x00005000, 0x00000002 }, + { 0x000380e7, 0x00000002 }, + { 0x04002c97, 0x00000002 }, + { 0x00007820, 0x00000002 }, + { 0x00007821, 0x00000002 }, + { 0x00007800, 0000000000 }, + { 0x01200000, 0x00000002 }, + { 0x20077000, 0x00000002 }, + { 0x01200000, 0x00000002 }, + { 0x20007000, 0x00000002 }, + { 0x00061000, 0x00000002 }, + { 0x0120751b, 0x00000002 }, + { 0x8040750a, 0x00000002 }, + { 0x8040750b, 0x00000002 }, + { 0x00110000, 0x00000002 }, + { 0x000380e5, 0x00000002 }, + { 0x000000c6, 0x0000001c }, + { 0x000610ab, 0x00000018 }, + { 0x844075bd, 0x00000002 }, + { 0x000610aa, 0x00000018 }, + { 0x840075bb, 0x00000002 }, + { 0x000610ab, 0x00000018 }, + { 0x844075bc, 0x00000002 }, + { 0x000000c9, 0x00000004 }, + { 0x804075bd, 0x00000002 }, + { 0x800075bb, 0x00000002 }, + { 0x804075bc, 0x00000002 }, + { 0x00108000, 0x00000002 }, + { 0x01400000, 0x00000002 }, + { 0x006000cd, 0x0000000c }, + { 0x20c07000, 0x00000020 }, + { 0x000000cf, 0x00000012 }, + { 0x00800000, 0x00000006 }, + { 0x0080751d, 0x00000006 }, + { 0000000000, 0000000000 }, + { 0x0000775c, 0x00000002 }, + { 0x00a05000, 0x00000002 }, + { 0x00661000, 0x00000002 }, + { 0x0460275d, 0x00000020 }, + { 0x00004000, 0000000000 }, + { 0x01e00830, 0x00000002 }, + { 0x21007000, 0000000000 }, + { 0x6464614d, 0000000000 }, + { 0x69687420, 0000000000 }, + { 0x00000073, 0000000000 }, + { 0000000000, 0000000000 }, + { 0x00005000, 0x00000002 }, + { 0x000380d0, 0x00000002 }, + { 0x040025e0, 0x00000002 }, + { 0x000075e1, 0000000000 }, + { 0x00000001, 0000000000 }, + { 0x000380e0, 0x00000002 }, + { 0x04002394, 0x00000002 }, + { 0x00005000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0x00000008, 0000000000 }, + { 0x00000004, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, +}; + + +#define DO_IOREMAP(_m, _d) (_m)->handle = drm_ioremap((_m)->offset, \ + (_m)->size, (_d)) + +#define DO_IOREMAPFREE(_m, _d) \ + do { \ + if ((_m)->handle && (_m)->size) \ + drm_ioremapfree((_m)->handle, (_m)->size, (_d));\ + } while (0) + +#define DO_FIND_MAP(_m, _o) \ + do { \ + int _i; \ + for (_i = 0; _i < dev->map_count; _i++) { \ + if (dev->maplist[_i]->offset == _o) { \ + _m = dev->maplist[_i]; \ + break; \ + } \ + } \ + } while (0) + + +int RADEON_READ_PLL(drm_device_t *dev, int addr) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + + RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f); + return RADEON_READ(RADEON_CLOCK_CNTL_DATA); +} + +#if RADEON_FIFO_DEBUG +static void radeon_status( drm_radeon_private_t *dev_priv ) +{ + printk( "%s:\n", __FUNCTION__ ); + printk( "RBBM_STATUS = 0x%08x\n", + (unsigned int)RADEON_READ( RADEON_RBBM_STATUS ) ); + printk( "CP_RB_RTPR = 0x%08x\n", + (unsigned int)RADEON_READ( RADEON_CP_RB_RPTR ) ); + printk( "CP_RB_WTPR = 0x%08x\n", + (unsigned int)RADEON_READ( RADEON_CP_RB_WPTR ) ); +} +#endif + + +/* ================================================================ + * Engine, FIFO control + */ + +static int radeon_do_pixcache_flush( drm_radeon_private_t *dev_priv ) +{ + u32 tmp; + int i; + + tmp = RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT ); + tmp |= RADEON_RB2D_DC_FLUSH_ALL; + RADEON_WRITE( RADEON_RB2D_DSTCACHE_CTLSTAT, tmp ); + + for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { + if ( !(RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT ) + & RADEON_RB2D_DC_BUSY) ) { + return 0; + } + udelay( 1 ); + } + +#if RADEON_FIFO_DEBUG + DRM_ERROR( "failed!\n" ); + radeon_status( dev_priv ); +#endif + return -EBUSY; +} + +static int radeon_do_wait_for_fifo( drm_radeon_private_t *dev_priv, + int entries ) +{ + int i; + + for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { + int slots = ( RADEON_READ( RADEON_RBBM_STATUS ) + & RADEON_RBBM_FIFOCNT_MASK ); + if ( slots >= entries ) return 0; + udelay( 1 ); + } + +#if RADEON_FIFO_DEBUG + DRM_ERROR( "failed!\n" ); + radeon_status( dev_priv ); +#endif + return -EBUSY; +} + +static int radeon_do_wait_for_idle( drm_radeon_private_t *dev_priv ) +{ + int i, ret; + + ret = radeon_do_wait_for_fifo( dev_priv, 64 ); + if ( ret < 0 ) return ret; + + for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { + if ( !(RADEON_READ( RADEON_RBBM_STATUS ) + & RADEON_RBBM_ACTIVE) ) { + radeon_do_pixcache_flush( dev_priv ); + return 0; + } + udelay( 1 ); + } + +#if RADEON_FIFO_DEBUG + DRM_ERROR( "failed!\n" ); + radeon_status( dev_priv ); +#endif + return -EBUSY; +} + + +/* ================================================================ + * CP control, initialization + */ + +/* Load the microcode for the CP */ +static void radeon_cp_load_microcode( drm_radeon_private_t *dev_priv ) +{ + int i; + + radeon_do_wait_for_idle( dev_priv ); + + RADEON_WRITE( RADEON_CP_ME_RAM_ADDR, 0 ); + for ( i = 0 ; i < 256 ; i++ ) { + RADEON_WRITE( RADEON_CP_ME_RAM_DATAH, + radeon_cp_microcode[i][1] ); + RADEON_WRITE( RADEON_CP_ME_RAM_DATAL, + radeon_cp_microcode[i][0] ); + } +} + +/* Flush any pending commands to the CP. This should only be used just + * prior to a wait for idle, as it informs the engine that the command + * stream is ending. + */ +static void radeon_do_cp_flush( drm_radeon_private_t *dev_priv ) +{ +#if 0 + u32 tmp; + + tmp = RADEON_READ( RADEON_CP_RB_WPTR ) | (1 << 31); + RADEON_WRITE( RADEON_CP_RB_WPTR, tmp ); +#endif +} + +/* Wait for the CP to go idle. + */ +int radeon_do_cp_idle( drm_radeon_private_t *dev_priv ) +{ + RING_LOCALS; + + BEGIN_RING( 6 ); + + RADEON_PURGE_CACHE(); + RADEON_PURGE_ZCACHE(); + RADEON_WAIT_UNTIL_IDLE(); + + ADVANCE_RING(); + + return radeon_do_wait_for_idle( dev_priv ); +} + +/* Start the Command Processor. + */ +static void radeon_do_cp_start( drm_radeon_private_t *dev_priv ) +{ + RING_LOCALS; + + radeon_do_wait_for_idle( dev_priv ); + + RADEON_WRITE( RADEON_CP_CSQ_CNTL, dev_priv->cp_mode ); + + dev_priv->cp_running = 1; + + BEGIN_RING( 6 ); + + RADEON_PURGE_CACHE(); + RADEON_PURGE_ZCACHE(); + RADEON_WAIT_UNTIL_IDLE(); + + ADVANCE_RING(); +} + +/* Reset the Command Processor. This will not flush any pending + * commands, so you must wait for the CP command stream to complete + * before calling this routine. + */ +static void radeon_do_cp_reset( drm_radeon_private_t *dev_priv ) +{ + u32 cur_read_ptr; + + cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR ); + RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr ); + *dev_priv->ring.head = cur_read_ptr; + dev_priv->ring.tail = cur_read_ptr; +} + +/* Stop the Command Processor. This will not flush any pending + * commands, so you must flush the command stream and wait for the CP + * to go idle before calling this routine. + */ +static void radeon_do_cp_stop( drm_radeon_private_t *dev_priv ) +{ + RADEON_WRITE( RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS ); + + dev_priv->cp_running = 0; +} + +/* Reset the engine. This will stop the CP if it is running. + */ +static int radeon_do_engine_reset( drm_device_t *dev ) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset; + DRM_DEBUG( "%s\n", __FUNCTION__ ); + + radeon_do_pixcache_flush( dev_priv ); + + clock_cntl_index = RADEON_READ( RADEON_CLOCK_CNTL_INDEX ); + mclk_cntl = RADEON_READ_PLL( dev, RADEON_MCLK_CNTL ); + + /* FIXME: remove magic number here and in radeon ddx driver!!! */ + RADEON_WRITE_PLL( RADEON_MCLK_CNTL, mclk_cntl | 0x003f00000 ); + + rbbm_soft_reset = RADEON_READ( RADEON_RBBM_SOFT_RESET ); + + RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset | + RADEON_SOFT_RESET_CP | + RADEON_SOFT_RESET_HI | + RADEON_SOFT_RESET_SE | + RADEON_SOFT_RESET_RE | + RADEON_SOFT_RESET_PP | + RADEON_SOFT_RESET_E2 | + RADEON_SOFT_RESET_RB | + RADEON_SOFT_RESET_HDP ) ); + RADEON_READ( RADEON_RBBM_SOFT_RESET ); + RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset & + ~( RADEON_SOFT_RESET_CP | + RADEON_SOFT_RESET_HI | + RADEON_SOFT_RESET_SE | + RADEON_SOFT_RESET_RE | + RADEON_SOFT_RESET_PP | + RADEON_SOFT_RESET_E2 | + RADEON_SOFT_RESET_RB | + RADEON_SOFT_RESET_HDP ) ) ); + RADEON_READ( RADEON_RBBM_SOFT_RESET ); + + + RADEON_WRITE_PLL( RADEON_MCLK_CNTL, mclk_cntl ); + RADEON_WRITE( RADEON_CLOCK_CNTL_INDEX, clock_cntl_index ); + RADEON_WRITE( RADEON_RBBM_SOFT_RESET, rbbm_soft_reset ); + + /* Reset the CP ring */ + radeon_do_cp_reset( dev_priv ); + + /* The CP is no longer running after an engine reset */ + dev_priv->cp_running = 0; + + /* Reset any pending vertex, indirect buffers */ + radeon_freelist_reset( dev ); + + return 0; +} + +static void radeon_cp_init_ring_buffer( drm_device_t *dev ) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + u32 ring_start, cur_read_ptr; + u32 tmp; + + /* Initialize the memory controller */ + RADEON_WRITE( RADEON_MC_FB_LOCATION, + (dev_priv->agp_vm_start - 1) & 0xffff0000 ); + RADEON_WRITE( RADEON_MC_AGP_LOCATION, + (((dev_priv->agp_vm_start - 1 + + dev_priv->agp_size) & 0xffff0000) | + (dev_priv->agp_vm_start >> 16)) ); + + ring_start = (dev_priv->cp_ring->offset + - dev->agp->base + + dev_priv->agp_vm_start); + + RADEON_WRITE( RADEON_CP_RB_BASE, ring_start ); + + /* Set the write pointer delay */ + RADEON_WRITE( RADEON_CP_RB_WPTR_DELAY, 0 ); + + /* Initialize the ring buffer's read and write pointers */ + cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR ); + RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr ); + +#if defined(CONFIG_AGP_I460) && defined(__ia64__) + /* + * XXX - This is a 460GX specific hack + * + * We have to hack this right now. The GXB isn't claiming PCI writes + * from the card into the AGP aperture. Because of this, we have + * to get space outside of the aperture for RPTR_ADDR. + */ + if(dev->agp->agp_info.chipset == INTEL_460GX) { + dev_priv->ring.head = (void *) + __get_free_page(GFP_KERNEL | GFP_DMA); + atomic_inc(&virt_to_page(dev_priv->ring.head)->count); + set_bit(PG_locked, &virt_to_page(dev_priv->ring.head)->flags); + dev_priv->ring.head = __va(dev_priv->ring.head); + + *dev_priv->ring.head = cur_read_ptr; + dev_priv->ring.tail = cur_read_ptr; + + RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, __pa(dev_priv->ring.head)); + } else { +#else + *dev_priv->ring.head = cur_read_ptr; + dev_priv->ring.tail = cur_read_ptr; + + RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR, dev_priv->ring_rptr->offset ); +#endif +#if defined(CONFIG_AGP_I460) && defined(__ia64__) + } +#endif + /* Set ring buffer size */ + RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw ); + + radeon_do_wait_for_idle( dev_priv ); + + /* Turn off PCI GART */ + tmp = RADEON_READ( RADEON_AIC_CNTL ) & ~RADEON_PCIGART_TRANSLATE_EN; + RADEON_WRITE( RADEON_AIC_CNTL, tmp ); + + /* Turn on bus mastering */ + tmp = RADEON_READ( RADEON_BUS_CNTL ) & ~RADEON_BUS_MASTER_DIS; + RADEON_WRITE( RADEON_BUS_CNTL, tmp ); + + /* Sync everything up */ + RADEON_WRITE( RADEON_ISYNC_CNTL, + (RADEON_ISYNC_ANY2D_IDLE3D | + RADEON_ISYNC_ANY3D_IDLE2D | + RADEON_ISYNC_WAIT_IDLEGUI | + RADEON_ISYNC_CPSCRATCH_IDLEGUI) ); +} + +static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init ) +{ + drm_radeon_private_t *dev_priv; + int i; + + dev_priv = drm_alloc( sizeof(drm_radeon_private_t), DRM_MEM_DRIVER ); + if ( dev_priv == NULL ) + return -ENOMEM; + dev->dev_private = (void *)dev_priv; + + memset( dev_priv, 0, sizeof(drm_radeon_private_t) ); + + dev_priv->is_pci = init->is_pci; + + /* We don't support PCI cards until PCI GART is implemented. + * Fail here so we can remove all checks for PCI cards around + * the CP ring code. + */ + if ( dev_priv->is_pci ) { + drm_free( dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER ); + dev->dev_private = NULL; + return -EINVAL; + } + + dev_priv->usec_timeout = init->usec_timeout; + if ( dev_priv->usec_timeout < 1 || + dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT ) { + drm_free( dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER ); + dev->dev_private = NULL; + return -EINVAL; + } + + dev_priv->cp_mode = init->cp_mode; + + /* Simple idle check. + */ + atomic_set( &dev_priv->idle_count, 0 ); + + /* We don't support anything other than bus-mastering ring mode, + * but the ring can be in either AGP or PCI space for the ring + * read pointer. + */ + if ( ( init->cp_mode != RADEON_CSQ_PRIBM_INDDIS ) && + ( init->cp_mode != RADEON_CSQ_PRIBM_INDBM ) ) { + drm_free( dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER ); + dev->dev_private = NULL; + return -EINVAL; + } + + switch ( init->fb_bpp ) { + case 16: + dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565; + break; + case 32: + default: + dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888; + break; + } + dev_priv->front_offset = init->front_offset; + dev_priv->front_pitch = init->front_pitch; + dev_priv->back_offset = init->back_offset; + dev_priv->back_pitch = init->back_pitch; + + switch ( init->depth_bpp ) { + case 16: + dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z; + break; + case 32: + default: + dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z; + break; + } + dev_priv->depth_offset = init->depth_offset; + dev_priv->depth_pitch = init->depth_pitch; + + dev_priv->front_pitch_offset = (((dev_priv->front_pitch/64) << 22) | + (dev_priv->front_offset >> 10)); + dev_priv->back_pitch_offset = (((dev_priv->back_pitch/64) << 22) | + (dev_priv->back_offset >> 10)); + dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch/64) << 22) | + (dev_priv->depth_offset >> 10)); + + /* Hardware state for depth clears. Remove this if/when we no + * longer clear the depth buffer with a 3D rectangle. Hard-code + * all values to prevent unwanted 3D state from slipping through + * and screwing with the clear operation. + */ + dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE | + RADEON_Z_ENABLE | + (dev_priv->color_fmt << 10) | + RADEON_ZBLOCK16); + + dev_priv->depth_clear.rb3d_zstencilcntl = (dev_priv->depth_fmt | + RADEON_Z_TEST_ALWAYS | + RADEON_STENCIL_TEST_ALWAYS | + RADEON_STENCIL_S_FAIL_KEEP | + RADEON_STENCIL_ZPASS_KEEP | + RADEON_STENCIL_ZFAIL_KEEP | + RADEON_Z_WRITE_ENABLE); + + dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW | + RADEON_BFACE_SOLID | + RADEON_FFACE_SOLID | + RADEON_FLAT_SHADE_VTX_LAST | + + RADEON_DIFFUSE_SHADE_FLAT | + RADEON_ALPHA_SHADE_FLAT | + RADEON_SPECULAR_SHADE_FLAT | + RADEON_FOG_SHADE_FLAT | + + RADEON_VTX_PIX_CENTER_OGL | + RADEON_ROUND_MODE_TRUNC | + RADEON_ROUND_PREC_8TH_PIX); + + /* FIXME: We want multiple shared areas, including one shared + * only by the X Server and kernel module. + */ + for ( i = 0 ; i < dev->map_count ; i++ ) { + if ( dev->maplist[i]->type == _DRM_SHM ) { + dev_priv->sarea = dev->maplist[i]; + break; + } + } + + DO_FIND_MAP( dev_priv->fb, init->fb_offset ); + DO_FIND_MAP( dev_priv->mmio, init->mmio_offset ); + DO_FIND_MAP( dev_priv->cp_ring, init->ring_offset ); + DO_FIND_MAP( dev_priv->ring_rptr, init->ring_rptr_offset ); + DO_FIND_MAP( dev_priv->buffers, init->buffers_offset ); + + if ( !dev_priv->is_pci ) { + DO_FIND_MAP( dev_priv->agp_textures, + init->agp_textures_offset ); + } + + dev_priv->sarea_priv = + (drm_radeon_sarea_t *)((u8 *)dev_priv->sarea->handle + + init->sarea_priv_offset); + + DO_IOREMAP( dev_priv->cp_ring, dev ); + DO_IOREMAP( dev_priv->ring_rptr, dev ); + DO_IOREMAP( dev_priv->buffers, dev ); +#if 0 + if ( !dev_priv->is_pci ) { + DO_IOREMAP( dev_priv->agp_textures, dev ); + } +#endif + + dev_priv->agp_size = init->agp_size; + dev_priv->agp_vm_start = RADEON_READ( RADEON_CONFIG_APER_SIZE ); + dev_priv->agp_buffers_offset = (dev_priv->buffers->offset + - dev->agp->base + + dev_priv->agp_vm_start); + + dev_priv->ring.head = ((__volatile__ u32 *) + dev_priv->ring_rptr->handle); + + dev_priv->ring.start = (u32 *)dev_priv->cp_ring->handle; + dev_priv->ring.end = ((u32 *)dev_priv->cp_ring->handle + + init->ring_size / sizeof(u32)); + dev_priv->ring.size = init->ring_size; + dev_priv->ring.size_l2qw = drm_order( init->ring_size / 8 ); + + dev_priv->ring.tail_mask = + (dev_priv->ring.size / sizeof(u32)) - 1; + +#if 0 + /* Initialize the scratch register pointer. This will cause + * the scratch register values to be written out to memory + * whenever they are updated. + * FIXME: This doesn't quite work yet, so we're disabling it + * for the release. + */ + RADEON_WRITE( RADEON_SCRATCH_ADDR, (dev_priv->ring_rptr->offset + + RADEON_SCRATCH_REG_OFFSET) ); + RADEON_WRITE( RADEON_SCRATCH_UMSK, 0x7 ); +#endif + + dev_priv->scratch = ((__volatile__ u32 *) + dev_priv->ring_rptr->handle + + (RADEON_SCRATCH_REG_OFFSET / sizeof(u32))); + + dev_priv->sarea_priv->last_frame = 0; + RADEON_WRITE( RADEON_LAST_FRAME_REG, + dev_priv->sarea_priv->last_frame ); + + dev_priv->sarea_priv->last_dispatch = 0; + RADEON_WRITE( RADEON_LAST_DISPATCH_REG, + dev_priv->sarea_priv->last_dispatch ); + + dev_priv->sarea_priv->last_clear = 0; + RADEON_WRITE( RADEON_LAST_CLEAR_REG, + dev_priv->sarea_priv->last_clear ); + + radeon_cp_load_microcode( dev_priv ); + radeon_cp_init_ring_buffer( dev ); + radeon_do_engine_reset( dev ); + +#if ROTATE_BUFS + dev_priv->last_buf = 0; +#endif + + return 0; +} + +static int radeon_do_cleanup_cp( drm_device_t *dev ) +{ + if ( dev->dev_private ) { + drm_radeon_private_t *dev_priv = dev->dev_private; + + DO_IOREMAPFREE( dev_priv->cp_ring, dev ); + DO_IOREMAPFREE( dev_priv->ring_rptr, dev ); + DO_IOREMAPFREE( dev_priv->buffers, dev ); +#if 0 + if ( !dev_priv->is_pci ) { + DO_IOREMAPFREE( dev_priv->agp_textures, dev ); + } +#endif + +#if defined(CONFIG_AGP_I460) && defined(__ia64__) + /* + * Free the page we grabbed for RPTR_ADDR. + */ + if(dev->agp->agp_info.chipset == INTEL_460GX) { + atomic_dec(&virt_to_page(dev_priv->ring.head)->count); + clear_bit(PG_locked, + &virt_to_page(dev_priv->ring.head)->flags); + wake_up(&virt_to_page(dev_priv->ring.head)->wait); + free_page((unsigned long) dev_priv->ring.head); + } +#endif + + drm_free( dev->dev_private, sizeof(drm_radeon_private_t), + DRM_MEM_DRIVER ); + dev->dev_private = NULL; + } + + return 0; +} + +int radeon_cp_init( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_radeon_init_t init; + + if ( copy_from_user( &init, (drm_radeon_init_t *)arg, sizeof(init) ) ) + return -EFAULT; + + switch ( init.func ) { + case RADEON_INIT_CP: + return radeon_do_init_cp( dev, &init ); + case RADEON_CLEANUP_CP: + return radeon_do_cleanup_cp( dev ); + } + + return -EINVAL; +} + +int radeon_cp_start( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_radeon_private_t *dev_priv = dev->dev_private; + DRM_DEBUG( "%s\n", __FUNCTION__ ); + + if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || + dev->lock.pid != current->pid ) { + DRM_ERROR( "%s called without lock held\n", __FUNCTION__ ); + return -EINVAL; + } + if ( dev_priv->cp_running ) { + DRM_DEBUG( "%s while CP running\n", __FUNCTION__ ); + return 0; + } + if ( dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS ) { + DRM_DEBUG( "%s called with bogus CP mode (%d)\n", + __FUNCTION__, dev_priv->cp_mode ); + return 0; + } + + radeon_do_cp_start( dev_priv ); + + return 0; +} + +/* Stop the CP. The engine must have been idled before calling this + * routine. + */ +int radeon_cp_stop( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_radeon_private_t *dev_priv = dev->dev_private; + drm_radeon_cp_stop_t stop; + int ret; + DRM_DEBUG( "%s\n", __FUNCTION__ ); + + if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || + dev->lock.pid != current->pid ) { + DRM_ERROR( "%s called without lock held\n", __FUNCTION__ ); + return -EINVAL; + } + + if ( copy_from_user( &stop, (drm_radeon_init_t *)arg, sizeof(stop) ) ) + return -EFAULT; + + /* Flush any pending CP commands. This ensures any outstanding + * commands are exectuted by the engine before we turn it off. + */ + if ( stop.flush ) { + radeon_do_cp_flush( dev_priv ); + } + + /* If we fail to make the engine go idle, we return an error + * code so that the DRM ioctl wrapper can try again. + */ + if ( stop.idle ) { + ret = radeon_do_cp_idle( dev_priv ); + if ( ret < 0 ) return ret; + } + + /* Finally, we can turn off the CP. If the engine isn't idle, + * we will get some dropped triangles as they won't be fully + * rendered before the CP is shut down. + */ + radeon_do_cp_stop( dev_priv ); + + /* Reset the engine */ + radeon_do_engine_reset( dev ); + + return 0; +} + +/* Just reset the CP ring. Called as part of an X Server engine reset. + */ +int radeon_cp_reset( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_radeon_private_t *dev_priv = dev->dev_private; + DRM_DEBUG( "%s\n", __FUNCTION__ ); + + if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || + dev->lock.pid != current->pid ) { + DRM_ERROR( "%s called without lock held\n", __FUNCTION__ ); + return -EINVAL; + } + if ( !dev_priv ) { + DRM_DEBUG( "%s called before init done\n", __FUNCTION__ ); + return -EINVAL; + } + + radeon_do_cp_reset( dev_priv ); + + /* The CP is no longer running after an engine reset */ + dev_priv->cp_running = 0; + + return 0; +} + +int radeon_cp_idle( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_radeon_private_t *dev_priv = dev->dev_private; + DRM_DEBUG( "%s\n", __FUNCTION__ ); + + if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || + dev->lock.pid != current->pid ) { + DRM_ERROR( "%s called without lock held\n", __FUNCTION__ ); + return -EINVAL; + } + + return radeon_do_cp_idle( dev_priv ); +} + +int radeon_engine_reset( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + DRM_DEBUG( "%s\n", __FUNCTION__ ); + + if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || + dev->lock.pid != current->pid ) { + DRM_ERROR( "%s called without lock held\n", __FUNCTION__ ); + return -EINVAL; + } + + return radeon_do_engine_reset( dev ); +} + + +/* ================================================================ + * Fullscreen mode + */ + +static int radeon_do_init_pageflip( drm_device_t *dev ) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + DRM_DEBUG( "%s\n", __FUNCTION__ ); + + dev_priv->crtc_offset = RADEON_READ( RADEON_CRTC_OFFSET ); + dev_priv->crtc_offset_cntl = RADEON_READ( RADEON_CRTC_OFFSET_CNTL ); + + RADEON_WRITE( RADEON_CRTC_OFFSET, dev_priv->front_offset ); + RADEON_WRITE( RADEON_CRTC_OFFSET_CNTL, + dev_priv->crtc_offset_cntl | + RADEON_CRTC_OFFSET_FLIP_CNTL ); + + dev_priv->page_flipping = 1; + dev_priv->current_page = 0; + + return 0; +} + +int radeon_do_cleanup_pageflip( drm_device_t *dev ) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + DRM_DEBUG( "%s\n", __FUNCTION__ ); + + RADEON_WRITE( RADEON_CRTC_OFFSET, dev_priv->crtc_offset ); + RADEON_WRITE( RADEON_CRTC_OFFSET_CNTL, dev_priv->crtc_offset_cntl ); + + dev_priv->page_flipping = 0; + dev_priv->current_page = 0; + + return 0; +} + +int radeon_fullscreen( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_radeon_fullscreen_t fs; + + if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || + dev->lock.pid != current->pid ) { + DRM_ERROR( "%s called without lock held\n", __FUNCTION__ ); + return -EINVAL; + } + + if ( copy_from_user( &fs, (drm_radeon_fullscreen_t *)arg, + sizeof(fs) ) ) + return -EFAULT; + + switch ( fs.func ) { + case RADEON_INIT_FULLSCREEN: + return radeon_do_init_pageflip( dev ); + case RADEON_CLEANUP_FULLSCREEN: + return radeon_do_cleanup_pageflip( dev ); + } + + return -EINVAL; +} + + +/* ================================================================ + * Freelist management + */ +#define RADEON_BUFFER_USED 0xffffffff +#define RADEON_BUFFER_FREE 0 + +#if 0 +static int radeon_freelist_init( drm_device_t *dev ) +{ + drm_device_dma_t *dma = dev->dma; + drm_radeon_private_t *dev_priv = dev->dev_private; + drm_buf_t *buf; + drm_radeon_buf_priv_t *buf_priv; + drm_radeon_freelist_t *entry; + int i; + + dev_priv->head = drm_alloc( sizeof(drm_radeon_freelist_t), + DRM_MEM_DRIVER ); + if ( dev_priv->head == NULL ) + return -ENOMEM; + + memset( dev_priv->head, 0, sizeof(drm_radeon_freelist_t) ); + dev_priv->head->age = RADEON_BUFFER_USED; + + for ( i = 0 ; i < dma->buf_count ; i++ ) { + buf = dma->buflist[i]; + buf_priv = buf->dev_private; + + entry = drm_alloc( sizeof(drm_radeon_freelist_t), + DRM_MEM_DRIVER ); + if ( !entry ) return -ENOMEM; + + entry->age = RADEON_BUFFER_FREE; + entry->buf = buf; + entry->prev = dev_priv->head; + entry->next = dev_priv->head->next; + if ( !entry->next ) + dev_priv->tail = entry; + + buf_priv->discard = 0; + buf_priv->dispatched = 0; + buf_priv->list_entry = entry; + + dev_priv->head->next = entry; + + if ( dev_priv->head->next ) + dev_priv->head->next->prev = entry; + } + + return 0; + +} +#endif + +drm_buf_t *radeon_freelist_get( drm_device_t *dev ) +{ + drm_device_dma_t *dma = dev->dma; + drm_radeon_private_t *dev_priv = dev->dev_private; + drm_radeon_buf_priv_t *buf_priv; + drm_buf_t *buf; + int i, t; +#if ROTATE_BUFS + int start; +#endif + + /* FIXME: Optimize -- use freelist code */ + + for ( i = 0 ; i < dma->buf_count ; i++ ) { + buf = dma->buflist[i]; + buf_priv = buf->dev_private; + if ( buf->pid == 0 ) { + DRM_DEBUG( " ret buf=%d last=%d pid=0\n", + buf->idx, dev_priv->last_buf ); + return buf; + } + DRM_DEBUG( " skipping buf=%d pid=%d\n", + buf->idx, buf->pid ); + } + +#if ROTATE_BUFS + if ( ++dev_priv->last_buf >= dma->buf_count ) + dev_priv->last_buf = 0; + start = dev_priv->last_buf; +#endif + for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) { +#if 0 + /* FIXME: Disable this for now */ + u32 done_age = dev_priv->scratch[RADEON_LAST_DISPATCH]; +#else + u32 done_age = RADEON_READ( RADEON_LAST_DISPATCH_REG ); +#endif +#if ROTATE_BUFS + for ( i = start ; i < dma->buf_count ; i++ ) { +#else + for ( i = 0 ; i < dma->buf_count ; i++ ) { +#endif + buf = dma->buflist[i]; + buf_priv = buf->dev_private; + if ( buf->pending && buf_priv->age <= done_age ) { + /* The buffer has been processed, so it + * can now be used. + */ + buf->pending = 0; + DRM_DEBUG( " ret buf=%d last=%d age=%d done=%d\n", buf->idx, dev_priv->last_buf, buf_priv->age, done_age ); + return buf; + } + DRM_DEBUG( " skipping buf=%d age=%d done=%d\n", + buf->idx, buf_priv->age, + done_age ); +#if ROTATE_BUFS + start = 0; +#endif + } + udelay( 1 ); + } + + DRM_ERROR( "returning NULL!\n" ); + return NULL; +} + +void radeon_freelist_reset( drm_device_t *dev ) +{ + drm_device_dma_t *dma = dev->dma; +#if ROTATE_BUFS + drm_radeon_private_t *dev_priv = dev->dev_private; +#endif + int i; + +#if ROTATE_BUFS + dev_priv->last_buf = 0; +#endif + for ( i = 0 ; i < dma->buf_count ; i++ ) { + drm_buf_t *buf = dma->buflist[i]; + drm_radeon_buf_priv_t *buf_priv = buf->dev_private; + buf_priv->age = 0; + } +} + + +/* ================================================================ + * CP command submission + */ + +int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n ) +{ + drm_radeon_ring_buffer_t *ring = &dev_priv->ring; + int i; + + for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { + ring->space = *ring->head - ring->tail; + if ( ring->space <= 0 ) + ring->space += ring->size; + + if ( ring->space >= n ) + return 0; + + udelay( 1 ); + } + + /* FIXME: This return value is ignored in the BEGIN_RING macro! */ + DRM_ERROR( "failed!\n" ); + return -EBUSY; +} + +void radeon_update_ring_snapshot( drm_radeon_private_t *dev_priv ) +{ + drm_radeon_ring_buffer_t *ring = &dev_priv->ring; + + ring->space = *ring->head - ring->tail; + if ( ring->space == 0 ) + atomic_inc( &dev_priv->idle_count ); + if ( ring->space <= 0 ) + ring->space += ring->size; +} + +static int radeon_cp_get_buffers( drm_device_t *dev, drm_dma_t *d ) +{ + int i; + drm_buf_t *buf; + + for ( i = d->granted_count ; i < d->request_count ; i++ ) { + buf = radeon_freelist_get( dev ); + if ( !buf ) return -EAGAIN; + + buf->pid = current->pid; + + if ( copy_to_user( &d->request_indices[i], &buf->idx, + sizeof(buf->idx) ) ) + return -EFAULT; + if ( copy_to_user( &d->request_sizes[i], &buf->total, + sizeof(buf->total) ) ) + return -EFAULT; + + d->granted_count++; + } + return 0; +} + +int radeon_cp_buffers( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_device_dma_t *dma = dev->dma; + int ret = 0; + drm_dma_t d; + + if ( copy_from_user( &d, (drm_dma_t *) arg, sizeof(d) ) ) + return -EFAULT; + + if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || + dev->lock.pid != current->pid ) { + DRM_ERROR( "%s called without lock held\n", __FUNCTION__ ); + return -EINVAL; + } + + /* Please don't send us buffers. + */ + if ( d.send_count != 0 ) { + DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n", + current->pid, d.send_count ); + return -EINVAL; + } + + /* We'll send you buffers. + */ + if ( d.request_count < 0 || d.request_count > dma->buf_count ) { + DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n", + current->pid, d.request_count, dma->buf_count ); + return -EINVAL; + } + + d.granted_count = 0; + + if ( d.request_count ) { + ret = radeon_cp_get_buffers( dev, &d ); + } + + if ( copy_to_user( (drm_dma_t *) arg, &d, sizeof(d) ) ) + return -EFAULT; + + return ret; +} diff -urN linux-2.4.10/drivers/char/drm-4.0/radeon_drm.h linux-2.4.10-lia/drivers/char/drm-4.0/radeon_drm.h --- linux-2.4.10/drivers/char/drm-4.0/radeon_drm.h Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/radeon_drm.h Wed Aug 15 20:52:12 2001 @@ -0,0 +1,325 @@ +/* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*- + * + * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Fremont, California. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Kevin E. Martin + * Gareth Hughes + * + */ + +#ifndef __RADEON_DRM_H__ +#define __RADEON_DRM_H__ + +/* WARNING: If you change any of these defines, make sure to change the + * defines in the X server file (radeon_sarea.h) + */ +#ifndef __RADEON_SAREA_DEFINES__ +#define __RADEON_SAREA_DEFINES__ + +/* What needs to be changed for the current vertex buffer? + */ +#define RADEON_UPLOAD_CONTEXT 0x00000001 +#define RADEON_UPLOAD_VERTFMT 0x00000002 +#define RADEON_UPLOAD_LINE 0x00000004 +#define RADEON_UPLOAD_BUMPMAP 0x00000008 +#define RADEON_UPLOAD_MASKS 0x00000010 +#define RADEON_UPLOAD_VIEWPORT 0x00000020 +#define RADEON_UPLOAD_SETUP 0x00000040 +#define RADEON_UPLOAD_TCL 0x00000080 +#define RADEON_UPLOAD_MISC 0x00000100 +#define RADEON_UPLOAD_TEX0 0x00000200 +#define RADEON_UPLOAD_TEX1 0x00000400 +#define RADEON_UPLOAD_TEX2 0x00000800 +#define RADEON_UPLOAD_TEX0IMAGES 0x00001000 +#define RADEON_UPLOAD_TEX1IMAGES 0x00002000 +#define RADEON_UPLOAD_TEX2IMAGES 0x00004000 +#define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */ +#define RADEON_REQUIRE_QUIESCENCE 0x00010000 +#define RADEON_UPLOAD_ALL 0x0001ffff + +#define RADEON_FRONT 0x1 +#define RADEON_BACK 0x2 +#define RADEON_DEPTH 0x4 + +/* Primitive types + */ +#define RADEON_POINTS 0x1 +#define RADEON_LINES 0x2 +#define RADEON_LINE_STRIP 0x3 +#define RADEON_TRIANGLES 0x4 +#define RADEON_TRIANGLE_FAN 0x5 +#define RADEON_TRIANGLE_STRIP 0x6 + +/* Vertex/indirect buffer size + */ +#define RADEON_BUFFER_SIZE 16384 + +/* Byte offsets for indirect buffer data + */ +#define RADEON_INDEX_PRIM_OFFSET 20 +#define RADEON_HOSTDATA_BLIT_OFFSET 32 + +#define RADEON_SCRATCH_REG_OFFSET 32 + +/* Keep these small for testing + */ +#define RADEON_NR_SAREA_CLIPRECTS 12 + +/* There are 2 heaps (local/AGP). Each region within a heap is a + * minimum of 64k, and there are at most 64 of them per heap. + */ +#define RADEON_LOCAL_TEX_HEAP 0 +#define RADEON_AGP_TEX_HEAP 1 +#define RADEON_NR_TEX_HEAPS 2 +#define RADEON_NR_TEX_REGIONS 64 +#define RADEON_LOG_TEX_GRANULARITY 16 + +#define RADEON_MAX_TEXTURE_LEVELS 11 +#define RADEON_MAX_TEXTURE_UNITS 3 + +#endif /* __RADEON_SAREA_DEFINES__ */ + +typedef struct { + unsigned int red; + unsigned int green; + unsigned int blue; + unsigned int alpha; +} radeon_color_regs_t; + +typedef struct { + /* Context state */ + unsigned int pp_misc; /* 0x1c14 */ + unsigned int pp_fog_color; + unsigned int re_solid_color; + unsigned int rb3d_blendcntl; + unsigned int rb3d_depthoffset; + unsigned int rb3d_depthpitch; + unsigned int rb3d_zstencilcntl; + + unsigned int pp_cntl; /* 0x1c38 */ + unsigned int rb3d_cntl; + unsigned int rb3d_coloroffset; + unsigned int re_width_height; + unsigned int rb3d_colorpitch; + unsigned int se_cntl; + + /* Vertex format state */ + unsigned int se_coord_fmt; /* 0x1c50 */ + + /* Line state */ + unsigned int re_line_pattern; /* 0x1cd0 */ + unsigned int re_line_state; + + unsigned int se_line_width; /* 0x1db8 */ + + /* Bumpmap state */ + unsigned int pp_lum_matrix; /* 0x1d00 */ + + unsigned int pp_rot_matrix_0; /* 0x1d58 */ + unsigned int pp_rot_matrix_1; + + /* Mask state */ + unsigned int rb3d_stencilrefmask; /* 0x1d7c */ + unsigned int rb3d_ropcntl; + unsigned int rb3d_planemask; + + /* Viewport state */ + unsigned int se_vport_xscale; /* 0x1d98 */ + unsigned int se_vport_xoffset; + unsigned int se_vport_yscale; + unsigned int se_vport_yoffset; + unsigned int se_vport_zscale; + unsigned int se_vport_zoffset; + + /* Setup state */ + unsigned int se_cntl_status; /* 0x2140 */ + +#ifdef TCL_ENABLE + /* TCL state */ + radeon_color_regs_t se_tcl_material_emmissive; /* 0x2210 */ + radeon_color_regs_t se_tcl_material_ambient; + radeon_color_regs_t se_tcl_material_diffuse; + radeon_color_regs_t se_tcl_material_specular; + unsigned int se_tcl_shininess; + unsigned int se_tcl_output_vtx_fmt; + unsigned int se_tcl_output_vtx_sel; + unsigned int se_tcl_matrix_select_0; + unsigned int se_tcl_matrix_select_1; + unsigned int se_tcl_ucp_vert_blend_ctl; + unsigned int se_tcl_texture_proc_ctl; + unsigned int se_tcl_light_model_ctl; + unsigned int se_tcl_per_light_ctl[4]; +#endif + + /* Misc state */ + unsigned int re_top_left; /* 0x26c0 */ + unsigned int re_misc; +} drm_radeon_context_regs_t; + +/* Setup registers for each texture unit + */ +typedef struct { + unsigned int pp_txfilter; + unsigned int pp_txformat; + unsigned int pp_txoffset; + unsigned int pp_txcblend; + unsigned int pp_txablend; + unsigned int pp_tfactor; + + unsigned int pp_border_color; + +#ifdef CUBIC_ENABLE + unsigned int pp_cubic_faces; + unsigned int pp_cubic_offset[5]; +#endif +} drm_radeon_texture_regs_t; + +typedef struct { + unsigned char next, prev; + unsigned char in_use; + int age; +} drm_radeon_tex_region_t; + +typedef struct { + /* The channel for communication of state information to the kernel + * on firing a vertex buffer. + */ + drm_radeon_context_regs_t context_state; + drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS]; + unsigned int dirty; + unsigned int vertsize; + unsigned int vc_format; + + /* The current cliprects, or a subset thereof. + */ + drm_clip_rect_t boxes[RADEON_NR_SAREA_CLIPRECTS]; + unsigned int nbox; + + /* Counters for client-side throttling of rendering clients. + */ + unsigned int last_frame; + unsigned int last_dispatch; + unsigned int last_clear; + + drm_radeon_tex_region_t tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS+1]; + int tex_age[RADEON_NR_TEX_HEAPS]; + int ctx_owner; +} drm_radeon_sarea_t; + + +/* WARNING: If you change any of these defines, make sure to change the + * defines in the Xserver file (xf86drmRadeon.h) + */ +typedef struct drm_radeon_init { + enum { + RADEON_INIT_CP = 0x01, + RADEON_CLEANUP_CP = 0x02 + } func; + int sarea_priv_offset; + int is_pci; + int cp_mode; + int agp_size; + int ring_size; + int usec_timeout; + + unsigned int fb_bpp; + unsigned int front_offset, front_pitch; + unsigned int back_offset, back_pitch; + unsigned int depth_bpp; + unsigned int depth_offset, depth_pitch; + + unsigned int fb_offset; + unsigned int mmio_offset; + unsigned int ring_offset; + unsigned int ring_rptr_offset; + unsigned int buffers_offset; + unsigned int agp_textures_offset; +} drm_radeon_init_t; + +typedef struct drm_radeon_cp_stop { + int flush; + int idle; +} drm_radeon_cp_stop_t; + +typedef struct drm_radeon_fullscreen { + enum { + RADEON_INIT_FULLSCREEN = 0x01, + RADEON_CLEANUP_FULLSCREEN = 0x02 + } func; +} drm_radeon_fullscreen_t; + +#define CLEAR_X1 0 +#define CLEAR_Y1 1 +#define CLEAR_X2 2 +#define CLEAR_Y2 3 +#define CLEAR_DEPTH 4 + +typedef struct drm_radeon_clear { + unsigned int flags; + int x, y, w, h; + unsigned int clear_color; + unsigned int clear_depth; + union { + float f[5]; + unsigned int ui[5]; + } rect; +} drm_radeon_clear_t; + +typedef struct drm_radeon_vertex { + int prim; + int idx; /* Index of vertex buffer */ + int count; /* Number of vertices in buffer */ + int discard; /* Client finished with buffer? */ +} drm_radeon_vertex_t; + +typedef struct drm_radeon_indices { + int prim; + int idx; + int start; + int end; + int discard; /* Client finished with buffer? */ +} drm_radeon_indices_t; + +typedef struct drm_radeon_blit { + int idx; + int pitch; + int offset; + int format; + unsigned short x, y; + unsigned short width, height; +} drm_radeon_blit_t; + +typedef struct drm_radeon_stipple { + unsigned int *mask; +} drm_radeon_stipple_t; + +typedef struct drm_radeon_indirect { + int idx; + int start; + int end; + int discard; +} drm_radeon_indirect_t; + +#endif diff -urN linux-2.4.10/drivers/char/drm-4.0/radeon_drv.c linux-2.4.10-lia/drivers/char/drm-4.0/radeon_drv.c --- linux-2.4.10/drivers/char/drm-4.0/radeon_drv.c Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/radeon_drv.c Mon Aug 20 18:09:34 2001 @@ -0,0 +1,702 @@ +/* radeon_drv.c -- ATI Radeon driver -*- linux-c -*- + * + * Copyright 1999, 2000 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Fremont, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: Kevin E. Martin + * Rickard E. (Rik) Faith + * + */ + +#include +#include "drmP.h" +#include "radeon_drv.h" + +#define RADEON_NAME "radeon" +#define RADEON_DESC "ATI Radeon" +#define RADEON_DATE "20010105" +#define RADEON_MAJOR 1 +#define RADEON_MINOR 0 +#define RADEON_PATCHLEVEL 0 + +static drm_device_t radeon_device; +drm_ctx_t radeon_res_ctx; + +static struct file_operations radeon_fops = { +#if LINUX_VERSION_CODE >= 0x020400 + /* This started being used during 2.4.0-test */ + owner: THIS_MODULE, +#endif + open: radeon_open, + flush: drm_flush, + release: radeon_release, + ioctl: radeon_ioctl, + mmap: drm_mmap, + read: drm_read, + fasync: drm_fasync, + poll: drm_poll, +}; + +static struct miscdevice radeon_misc = { + minor: MISC_DYNAMIC_MINOR, + name: RADEON_NAME, + fops: &radeon_fops, +}; + +static drm_ioctl_desc_t radeon_ioctls[] = { + [DRM_IOCTL_NR(DRM_IOCTL_VERSION)] = { radeon_version, 0, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_GET_UNIQUE)] = { drm_getunique, 0, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_GET_MAGIC)] = { drm_getmagic, 0, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_IRQ_BUSID)] = { drm_irq_busid, 0, 1 }, + + [DRM_IOCTL_NR(DRM_IOCTL_SET_UNIQUE)] = { drm_setunique, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_BLOCK)] = { drm_block, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_UNBLOCK)] = { drm_unblock, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_AUTH_MAGIC)] = { drm_authmagic, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_ADD_MAP)] = { drm_addmap, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_ADD_BUFS)] = { radeon_addbufs, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_MARK_BUFS)] = { drm_markbufs, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_INFO_BUFS)] = { drm_infobufs, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_MAP_BUFS)] = { radeon_mapbufs, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_FREE_BUFS)] = { drm_freebufs, 1, 0 }, + + [DRM_IOCTL_NR(DRM_IOCTL_ADD_CTX)] = { radeon_addctx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_RM_CTX)] = { radeon_rmctx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_MOD_CTX)] = { radeon_modctx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_GET_CTX)] = { radeon_getctx, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_SWITCH_CTX)] = { radeon_switchctx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_NEW_CTX)] = { radeon_newctx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_RES_CTX)] = { radeon_resctx, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_ADD_DRAW)] = { drm_adddraw, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_RM_DRAW)] = { drm_rmdraw, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_DMA)] = { radeon_cp_buffers, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_LOCK)] = { radeon_lock, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_UNLOCK)] = { radeon_unlock, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_FINISH)] = { drm_finish, 1, 0 }, + +#if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE) + [DRM_IOCTL_NR(DRM_IOCTL_AGP_ACQUIRE)] = { drm_agp_acquire, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_RELEASE)] = { drm_agp_release, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_ENABLE)] = { drm_agp_enable, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_INFO)] = { drm_agp_info, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_ALLOC)] = { drm_agp_alloc, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_FREE)] = { drm_agp_free, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_BIND)] = { drm_agp_bind, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_UNBIND)] = { drm_agp_unbind, 1, 1 }, +#endif + + [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_INIT)] = { radeon_cp_init, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_START)] = { radeon_cp_start, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_STOP)] = { radeon_cp_stop, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_RESET)] = { radeon_cp_reset, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_IDLE)] = { radeon_cp_idle, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_RADEON_RESET)] = { radeon_engine_reset, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_RADEON_FULLSCREEN)] = { radeon_fullscreen, 1, 0 }, + + [DRM_IOCTL_NR(DRM_IOCTL_RADEON_SWAP)] = { radeon_cp_swap, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CLEAR)] = { radeon_cp_clear, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_RADEON_VERTEX)] = { radeon_cp_vertex, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_RADEON_INDICES)] = { radeon_cp_indices, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_RADEON_BLIT)] = { radeon_cp_blit, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_RADEON_STIPPLE)] = { radeon_cp_stipple, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_RADEON_INDIRECT)]= { radeon_cp_indirect,1, 1 }, +}; +#define RADEON_IOCTL_COUNT DRM_ARRAY_SIZE(radeon_ioctls) + +#ifdef MODULE +static char *radeon = NULL; +#endif + +MODULE_AUTHOR("VA Linux Systems, Inc."); +MODULE_DESCRIPTION("radeon"); +MODULE_PARM(radeon, "s"); + +#ifndef MODULE +/* radeon_options is called by the kernel to parse command-line options + * passed via the boot-loader (e.g., LILO). It calls the insmod option + * routine, drm_parse_drm. + */ + +static int __init radeon_options(char *str) +{ + drm_parse_options(str); + return 1; +} + +__setup("radeon=", radeon_options); +#endif + +static int radeon_setup(drm_device_t *dev) +{ + int i; + + atomic_set(&dev->ioctl_count, 0); + atomic_set(&dev->vma_count, 0); + dev->buf_use = 0; + atomic_set(&dev->buf_alloc, 0); + + drm_dma_setup(dev); + + atomic_set(&dev->total_open, 0); + atomic_set(&dev->total_close, 0); + atomic_set(&dev->total_ioctl, 0); + atomic_set(&dev->total_irq, 0); + atomic_set(&dev->total_ctx, 0); + atomic_set(&dev->total_locks, 0); + atomic_set(&dev->total_unlocks, 0); + atomic_set(&dev->total_contends, 0); + atomic_set(&dev->total_sleeps, 0); + + for (i = 0; i < DRM_HASH_SIZE; i++) { + dev->magiclist[i].head = NULL; + dev->magiclist[i].tail = NULL; + } + dev->maplist = NULL; + dev->map_count = 0; + dev->vmalist = NULL; + dev->lock.hw_lock = NULL; + init_waitqueue_head(&dev->lock.lock_queue); + dev->queue_count = 0; + dev->queue_reserved = 0; + dev->queue_slots = 0; + dev->queuelist = NULL; + dev->irq = 0; + dev->context_flag = 0; + dev->interrupt_flag = 0; + dev->dma_flag = 0; + dev->last_context = 0; + dev->last_switch = 0; + dev->last_checked = 0; + init_timer(&dev->timer); + init_waitqueue_head(&dev->context_wait); + + dev->ctx_start = 0; + dev->lck_start = 0; + + dev->buf_rp = dev->buf; + dev->buf_wp = dev->buf; + dev->buf_end = dev->buf + DRM_BSZ; + dev->buf_async = NULL; + init_waitqueue_head(&dev->buf_readers); + init_waitqueue_head(&dev->buf_writers); + + radeon_res_ctx.handle = -1; + + DRM_DEBUG("\n"); + + /* The kernel's context could be created here, but is now created + in drm_dma_enqueue. This is more resource-efficient for + hardware that does not do DMA, but may mean that + drm_select_queue fails between the time the interrupt is + initialized and the time the queues are initialized. */ + + return 0; +} + + +static int radeon_takedown(drm_device_t *dev) +{ + int i; + drm_magic_entry_t *pt, *next; + drm_map_t *map; + drm_vma_entry_t *vma, *vma_next; + + DRM_DEBUG("\n"); + + down(&dev->struct_sem); + del_timer(&dev->timer); + + if (dev->devname) { + drm_free(dev->devname, strlen(dev->devname)+1, DRM_MEM_DRIVER); + dev->devname = NULL; + } + + if (dev->unique) { + drm_free(dev->unique, strlen(dev->unique)+1, DRM_MEM_DRIVER); + dev->unique = NULL; + dev->unique_len = 0; + } + /* Clear pid list */ + for (i = 0; i < DRM_HASH_SIZE; i++) { + for (pt = dev->magiclist[i].head; pt; pt = next) { + next = pt->next; + drm_free(pt, sizeof(*pt), DRM_MEM_MAGIC); + } + dev->magiclist[i].head = dev->magiclist[i].tail = NULL; + } + +#if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE) + /* Clear AGP information */ + if (dev->agp) { + drm_agp_mem_t *entry; + drm_agp_mem_t *nexte; + + /* Remove AGP resources, but leave dev->agp + intact until radeon_cleanup is called. */ + for (entry = dev->agp->memory; entry; entry = nexte) { + nexte = entry->next; + if (entry->bound) drm_unbind_agp(entry->memory); + drm_free_agp(entry->memory, entry->pages); + drm_free(entry, sizeof(*entry), DRM_MEM_AGPLISTS); + } + dev->agp->memory = NULL; + + if (dev->agp->acquired) _drm_agp_release(); + + dev->agp->acquired = 0; + dev->agp->enabled = 0; + } +#endif + + /* Clear vma list (only built for debugging) */ + if (dev->vmalist) { + for (vma = dev->vmalist; vma; vma = vma_next) { + vma_next = vma->next; + drm_free(vma, sizeof(*vma), DRM_MEM_VMAS); + } + dev->vmalist = NULL; + } + + /* Clear map area and mtrr information */ + if (dev->maplist) { + for (i = 0; i < dev->map_count; i++) { + map = dev->maplist[i]; + switch (map->type) { + case _DRM_REGISTERS: + case _DRM_FRAME_BUFFER: +#ifdef CONFIG_MTRR + if (map->mtrr >= 0) { + int retcode; + retcode = mtrr_del(map->mtrr, + map->offset, + map->size); + DRM_DEBUG("mtrr_del = %d\n", retcode); + } +#endif + drm_ioremapfree(map->handle, map->size, dev); + break; + case _DRM_SHM: + drm_free_pages((unsigned long)map->handle, + drm_order(map->size) + - PAGE_SHIFT, + DRM_MEM_SAREA); + break; + case _DRM_AGP: + /* Do nothing here, because this is all + handled in the AGP/GART driver. */ + break; + } + drm_free(map, sizeof(*map), DRM_MEM_MAPS); + } + drm_free(dev->maplist, + dev->map_count * sizeof(*dev->maplist), + DRM_MEM_MAPS); + dev->maplist = NULL; + dev->map_count = 0; + } + + drm_dma_takedown(dev); + + dev->queue_count = 0; + if (dev->lock.hw_lock) { + dev->lock.hw_lock = NULL; /* SHM removed */ + dev->lock.pid = 0; + wake_up_interruptible(&dev->lock.lock_queue); + } + up(&dev->struct_sem); + + return 0; +} + +/* radeon_init is called via init_module at module load time, or via + * linux/init/main.c (this is not currently supported). */ + +static int __init radeon_init(void) +{ + int retcode; + drm_device_t *dev = &radeon_device; + + DRM_DEBUG("\n"); + + memset((void *)dev, 0, sizeof(*dev)); + dev->count_lock = SPIN_LOCK_UNLOCKED; + sema_init(&dev->struct_sem, 1); + +#ifdef MODULE + drm_parse_options(radeon); +#endif + + if ((retcode = misc_register(&radeon_misc))) { + DRM_ERROR("Cannot register \"%s\"\n", RADEON_NAME); + return retcode; + } + dev->device = MKDEV(MISC_MAJOR, radeon_misc.minor); + dev->name = RADEON_NAME; + + drm_mem_init(); + drm_proc_init(dev); + +#if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE) + dev->agp = drm_agp_init(); + if (dev->agp == NULL) { + DRM_ERROR("Cannot initialize agpgart module.\n"); + drm_proc_cleanup(); + misc_deregister(&radeon_misc); + radeon_takedown(dev); + return -ENOMEM; + } + +#ifdef CONFIG_MTRR + dev->agp->agp_mtrr = mtrr_add(dev->agp->agp_info.aper_base, + dev->agp->agp_info.aper_size*1024*1024, + MTRR_TYPE_WRCOMB, + 1); +#endif +#endif + + if((retcode = drm_ctxbitmap_init(dev))) { + DRM_ERROR("Cannot allocate memory for context bitmap.\n"); + drm_proc_cleanup(); + misc_deregister(&radeon_misc); + radeon_takedown(dev); + return retcode; + } + + DRM_INFO("Initialized %s %d.%d.%d %s on minor %d\n", + RADEON_NAME, + RADEON_MAJOR, + RADEON_MINOR, + RADEON_PATCHLEVEL, + RADEON_DATE, + radeon_misc.minor); + + return 0; +} + +/* radeon_cleanup is called via cleanup_module at module unload time. */ + +static void __exit radeon_cleanup(void) +{ + drm_device_t *dev = &radeon_device; + + DRM_DEBUG("\n"); + + drm_proc_cleanup(); + if (misc_deregister(&radeon_misc)) { + DRM_ERROR("Cannot unload module\n"); + } else { + DRM_INFO("Module unloaded\n"); + } + drm_ctxbitmap_cleanup(dev); + radeon_takedown(dev); +#if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE) + if (dev->agp) { + drm_agp_uninit(); + drm_free(dev->agp, sizeof(*dev->agp), DRM_MEM_AGPLISTS); + dev->agp = NULL; + } +#endif +} + +module_init(radeon_init); +module_exit(radeon_cleanup); + + +int radeon_version(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_version_t version; + int len; + + if (copy_from_user(&version, + (drm_version_t *)arg, + sizeof(version))) + return -EFAULT; + +#define DRM_COPY(name,value) \ + len = strlen(value); \ + if (len > name##_len) len = name##_len; \ + name##_len = strlen(value); \ + if (len && name) { \ + if (copy_to_user(name, value, len)) \ + return -EFAULT; \ + } + + version.version_major = RADEON_MAJOR; + version.version_minor = RADEON_MINOR; + version.version_patchlevel = RADEON_PATCHLEVEL; + + DRM_COPY(version.name, RADEON_NAME); + DRM_COPY(version.date, RADEON_DATE); + DRM_COPY(version.desc, RADEON_DESC); + + if (copy_to_user((drm_version_t *)arg, + &version, + sizeof(version))) + return -EFAULT; + return 0; +} + +int radeon_open(struct inode *inode, struct file *filp) +{ + drm_device_t *dev = &radeon_device; + int retcode = 0; + + DRM_DEBUG("open_count = %d\n", dev->open_count); + if (!(retcode = drm_open_helper(inode, filp, dev))) { +#if LINUX_VERSION_CODE < 0x020333 + MOD_INC_USE_COUNT; /* Needed before Linux 2.3.51 */ +#endif + atomic_inc(&dev->total_open); + spin_lock(&dev->count_lock); + if (!dev->open_count++) { + spin_unlock(&dev->count_lock); + return radeon_setup(dev); + } + spin_unlock(&dev->count_lock); + } + + return retcode; +} + +int radeon_release(struct inode *inode, struct file *filp) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev; + int retcode = 0; + + lock_kernel(); + dev = priv->dev; + + DRM_DEBUG("open_count = %d\n", dev->open_count); + + /* Force the cleanup of page flipping when required */ + if ( dev->dev_private ) { + drm_radeon_private_t *dev_priv = dev->dev_private; + if ( dev_priv->page_flipping ) { + radeon_do_cleanup_pageflip( dev ); + } + } + + if (!(retcode = drm_release(inode, filp))) { +#if LINUX_VERSION_CODE < 0x020333 + MOD_DEC_USE_COUNT; /* Needed before Linux 2.3.51 */ +#endif + atomic_inc(&dev->total_close); + spin_lock(&dev->count_lock); + if (!--dev->open_count) { + if (atomic_read(&dev->ioctl_count) || dev->blocked) { + DRM_ERROR("Device busy: %d %d\n", + atomic_read(&dev->ioctl_count), + dev->blocked); + spin_unlock(&dev->count_lock); + unlock_kernel(); + return -EBUSY; + } + spin_unlock(&dev->count_lock); + unlock_kernel(); + return radeon_takedown(dev); + } + spin_unlock(&dev->count_lock); + } + + unlock_kernel(); + return retcode; +} + +/* radeon_ioctl is called whenever a process performs an ioctl on /dev/drm. */ + +int radeon_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + int nr = DRM_IOCTL_NR(cmd); + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + int retcode = 0; + drm_ioctl_desc_t *ioctl; + drm_ioctl_t *func; + + atomic_inc(&dev->ioctl_count); + atomic_inc(&dev->total_ioctl); + ++priv->ioctl_count; + + DRM_DEBUG("pid = %d, cmd = 0x%02x, nr = 0x%02x, dev 0x%x, auth = %d\n", + current->pid, cmd, nr, dev->device, priv->authenticated); + + if (nr >= RADEON_IOCTL_COUNT) { + retcode = -EINVAL; + } else { + ioctl = &radeon_ioctls[nr]; + func = ioctl->func; + + if (!func) { + DRM_DEBUG("no function\n"); + retcode = -EINVAL; + } else if ((ioctl->root_only && !capable(CAP_SYS_ADMIN)) + || (ioctl->auth_needed && !priv->authenticated)) { + retcode = -EACCES; + } else { + retcode = (func)(inode, filp, cmd, arg); + } + } + + atomic_dec(&dev->ioctl_count); + return retcode; +} + +int radeon_lock(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + DECLARE_WAITQUEUE(entry, current); + int ret = 0; + drm_lock_t lock; +#if DRM_DMA_HISTOGRAM + cycles_t start; + + dev->lck_start = start = get_cycles(); +#endif + + if (copy_from_user(&lock, (drm_lock_t *)arg, sizeof(lock))) + return -EFAULT; + + if (lock.context == DRM_KERNEL_CONTEXT) { + DRM_ERROR("Process %d using kernel context %d\n", + current->pid, lock.context); + return -EINVAL; + } + + DRM_DEBUG("%d (pid %d) requests lock (0x%08x), flags = 0x%08x\n", + lock.context, current->pid, dev->lock.hw_lock->lock, + lock.flags); + + if (lock.context < 0 /* || lock.context >= dev->queue_count */) + return -EINVAL; + + if (!ret) { + add_wait_queue(&dev->lock.lock_queue, &entry); + for (;;) { + current->state = TASK_INTERRUPTIBLE; + if (!dev->lock.hw_lock) { + /* Device has been unregistered */ + ret = -EINTR; + break; + } + if (drm_lock_take(&dev->lock.hw_lock->lock, + lock.context)) { + dev->lock.pid = current->pid; + dev->lock.lock_time = jiffies; + atomic_inc(&dev->total_locks); + break; /* Got lock */ + } + + /* Contention */ + atomic_inc(&dev->total_sleeps); + schedule(); + if (signal_pending(current)) { + ret = -ERESTARTSYS; + break; + } + } + current->state = TASK_RUNNING; + remove_wait_queue(&dev->lock.lock_queue, &entry); + } + + if (!ret) { + sigemptyset(&dev->sigmask); + sigaddset(&dev->sigmask, SIGSTOP); + sigaddset(&dev->sigmask, SIGTSTP); + sigaddset(&dev->sigmask, SIGTTIN); + sigaddset(&dev->sigmask, SIGTTOU); + dev->sigdata.context = lock.context; + dev->sigdata.lock = dev->lock.hw_lock; + block_all_signals(drm_notifier, &dev->sigdata, &dev->sigmask); + if (lock.flags & _DRM_LOCK_READY) { + /* Wait for space in DMA/FIFO */ + } + if (lock.flags & _DRM_LOCK_QUIESCENT) { + /* Make hardware quiescent */ + DRM_DEBUG("not quiescent!\n"); +#if 0 + radeon_quiescent(dev); +#endif + } + } + +#if LINUX_VERSION_CODE < 0x020400 + if (lock.context != radeon_res_ctx.handle) { + current->counter = 5; + current->priority = DEF_PRIORITY/4; + } +#endif + DRM_DEBUG("%d %s\n", lock.context, ret ? "interrupted" : "has lock"); + +#if DRM_DMA_HISTOGRAM + atomic_inc(&dev->histo.lacq[drm_histogram_slot(get_cycles() - start)]); +#endif + + return ret; +} + + +int radeon_unlock(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_lock_t lock; + + if (copy_from_user(&lock, (drm_lock_t *)arg, sizeof(lock))) + return -EFAULT; + + if (lock.context == DRM_KERNEL_CONTEXT) { + DRM_ERROR("Process %d using kernel context %d\n", + current->pid, lock.context); + return -EINVAL; + } + + DRM_DEBUG("%d frees lock (%d holds)\n", + lock.context, + _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock)); + atomic_inc(&dev->total_unlocks); + if (_DRM_LOCK_IS_CONT(dev->lock.hw_lock->lock)) + atomic_inc(&dev->total_contends); + drm_lock_transfer(dev, &dev->lock.hw_lock->lock, DRM_KERNEL_CONTEXT); + /* FIXME: Try to send data to card here */ + if (!dev->context_flag) { + if (drm_lock_free(dev, &dev->lock.hw_lock->lock, + DRM_KERNEL_CONTEXT)) { + DRM_ERROR("\n"); + } + } + +#if LINUX_VERSION_CODE < 0x020400 + if (lock.context != radeon_res_ctx.handle) { + current->counter = 5; + current->priority = DEF_PRIORITY; + } +#endif + unblock_all_signals(); + return 0; +} diff -urN linux-2.4.10/drivers/char/drm-4.0/radeon_drv.h linux-2.4.10-lia/drivers/char/drm-4.0/radeon_drv.h --- linux-2.4.10/drivers/char/drm-4.0/radeon_drv.h Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/radeon_drv.h Wed Aug 15 20:52:12 2001 @@ -0,0 +1,709 @@ +/* radeon_drv.h -- Private header for radeon driver -*- linux-c -*- + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Fremont, California. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rickard E. (Rik) Faith + * Kevin E. Martin + * Gareth Hughes + * + */ + +#ifndef __RADEON_DRV_H__ +#define __RADEON_DRV_H__ + +typedef struct drm_radeon_freelist { + unsigned int age; + drm_buf_t *buf; + struct drm_radeon_freelist *next; + struct drm_radeon_freelist *prev; +} drm_radeon_freelist_t; + +typedef struct drm_radeon_ring_buffer { + u32 *start; + u32 *end; + int size; + int size_l2qw; + + volatile u32 *head; + u32 tail; + u32 tail_mask; + int space; +} drm_radeon_ring_buffer_t; + +typedef struct drm_radeon_depth_clear_t { + u32 rb3d_cntl; + u32 rb3d_zstencilcntl; + u32 se_cntl; +} drm_radeon_depth_clear_t; + +typedef struct drm_radeon_private { + drm_radeon_ring_buffer_t ring; + drm_radeon_sarea_t *sarea_priv; + + int agp_size; + u32 agp_vm_start; + u32 agp_buffers_offset; + + int cp_mode; + int cp_running; + + drm_radeon_freelist_t *head; + drm_radeon_freelist_t *tail; +/* FIXME: ROTATE_BUFS is a hask to cycle through bufs until freelist + code is used. Note this hides a problem with the scratch register + (used to keep track of last buffer completed) being written to before + the last buffer has actually completed rendering. */ +#define ROTATE_BUFS 1 +#if ROTATE_BUFS + int last_buf; +#endif + volatile u32 *scratch; + + int usec_timeout; + int is_pci; + + atomic_t idle_count; + + int page_flipping; + int current_page; + u32 crtc_offset; + u32 crtc_offset_cntl; + + unsigned int color_fmt; + unsigned int front_offset; + unsigned int front_pitch; + unsigned int back_offset; + unsigned int back_pitch; + + unsigned int depth_fmt; + unsigned int depth_offset; + unsigned int depth_pitch; + + u32 front_pitch_offset; + u32 back_pitch_offset; + u32 depth_pitch_offset; + + drm_radeon_depth_clear_t depth_clear; + + drm_map_t *sarea; + drm_map_t *fb; + drm_map_t *mmio; + drm_map_t *cp_ring; + drm_map_t *ring_rptr; + drm_map_t *buffers; + drm_map_t *agp_textures; +} drm_radeon_private_t; + +typedef struct drm_radeon_buf_priv { + u32 age; + int prim; + int discard; + int dispatched; + drm_radeon_freelist_t *list_entry; +} drm_radeon_buf_priv_t; + + /* radeon_drv.c */ +extern int radeon_version( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); +extern int radeon_open( struct inode *inode, struct file *filp ); +extern int radeon_release( struct inode *inode, struct file *filp ); +extern int radeon_ioctl( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); +extern int radeon_lock( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); +extern int radeon_unlock( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); + + /* radeon_cp.c */ +extern int radeon_cp_init( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); +extern int radeon_cp_start( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); +extern int radeon_cp_stop( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); +extern int radeon_cp_reset( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); +extern int radeon_cp_idle( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); +extern int radeon_engine_reset( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); +extern int radeon_fullscreen( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); +extern int radeon_cp_buffers( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); + +extern void radeon_freelist_reset( drm_device_t *dev ); +extern drm_buf_t *radeon_freelist_get( drm_device_t *dev ); + +extern int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n ); +extern void radeon_update_ring_snapshot( drm_radeon_private_t *dev_priv ); + +extern int radeon_do_cp_idle( drm_radeon_private_t *dev_priv ); +extern int radeon_do_cleanup_pageflip( drm_device_t *dev ); + + /* radeon_state.c */ +extern int radeon_cp_clear( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); +extern int radeon_cp_swap( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); +extern int radeon_cp_vertex( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); +extern int radeon_cp_indices( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); +extern int radeon_cp_blit( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); +extern int radeon_cp_stipple( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); +extern int radeon_cp_indirect( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); + + /* radeon_bufs.c */ +extern int radeon_addbufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int radeon_mapbufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); + + /* radeon_context.c */ +extern int radeon_resctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int radeon_addctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int radeon_modctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int radeon_getctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int radeon_switchctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int radeon_newctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int radeon_rmctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); + +extern int radeon_context_switch(drm_device_t *dev, int old, int new); +extern int radeon_context_switch_complete(drm_device_t *dev, int new); + + +/* Register definitions, register access macros and drmAddMap constants + * for Radeon kernel driver. + */ + +#define RADEON_AUX_SCISSOR_CNTL 0x26f0 +# define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24) +# define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25) +# define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26) +# define RADEON_SCISSOR_0_ENABLE (1 << 28) +# define RADEON_SCISSOR_1_ENABLE (1 << 29) +# define RADEON_SCISSOR_2_ENABLE (1 << 30) + +#define RADEON_BUS_CNTL 0x0030 +# define RADEON_BUS_MASTER_DIS (1 << 6) + +#define RADEON_CLOCK_CNTL_DATA 0x000c +# define RADEON_PLL_WR_EN (1 << 7) +#define RADEON_CLOCK_CNTL_INDEX 0x0008 +#define RADEON_CONFIG_APER_SIZE 0x0108 +#define RADEON_CRTC_OFFSET 0x0224 +#define RADEON_CRTC_OFFSET_CNTL 0x0228 +# define RADEON_CRTC_TILE_EN (1 << 15) +# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16) + +#define RADEON_RB3D_COLORPITCH 0x1c48 +#define RADEON_RB3D_DEPTHCLEARVALUE 0x1c30 +#define RADEON_RB3D_DEPTHXY_OFFSET 0x1c60 + +#define RADEON_DP_GUI_MASTER_CNTL 0x146c +# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) +# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) +# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4) +# define RADEON_GMC_BRUSH_NONE (15 << 4) +# define RADEON_GMC_DST_16BPP (4 << 8) +# define RADEON_GMC_DST_24BPP (5 << 8) +# define RADEON_GMC_DST_32BPP (6 << 8) +# define RADEON_GMC_DST_DATATYPE_SHIFT 8 +# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12) +# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) +# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) +# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) +# define RADEON_GMC_WR_MSK_DIS (1 << 30) +# define RADEON_ROP3_S 0x00cc0000 +# define RADEON_ROP3_P 0x00f00000 +#define RADEON_DP_WRITE_MASK 0x16cc +#define RADEON_DST_PITCH_OFFSET 0x142c +#define RADEON_DST_PITCH_OFFSET_C 0x1c80 +# define RADEON_DST_TILE_LINEAR (0 << 30) +# define RADEON_DST_TILE_MACRO (1 << 30) +# define RADEON_DST_TILE_MICRO (2 << 30) +# define RADEON_DST_TILE_BOTH (3 << 30) + +#define RADEON_SCRATCH_REG0 0x15e0 +#define RADEON_SCRATCH_REG1 0x15e4 +#define RADEON_SCRATCH_REG2 0x15e8 +#define RADEON_SCRATCH_REG3 0x15ec +#define RADEON_SCRATCH_REG4 0x15f0 +#define RADEON_SCRATCH_REG5 0x15f4 +#define RADEON_SCRATCH_UMSK 0x0770 +#define RADEON_SCRATCH_ADDR 0x0774 + +#define RADEON_HOST_PATH_CNTL 0x0130 +# define RADEON_HDP_SOFT_RESET (1 << 26) +# define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28) +# define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28) + +#define RADEON_ISYNC_CNTL 0x1724 +# define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0) +# define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1) +# define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2) +# define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3) +# define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4) +# define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5) + +#define RADEON_MC_AGP_LOCATION 0x014c +#define RADEON_MC_FB_LOCATION 0x0148 +#define RADEON_MCLK_CNTL 0x0012 + +#define RADEON_PP_BORDER_COLOR_0 0x1d40 +#define RADEON_PP_BORDER_COLOR_1 0x1d44 +#define RADEON_PP_BORDER_COLOR_2 0x1d48 +#define RADEON_PP_CNTL 0x1c38 +# define RADEON_SCISSOR_ENABLE (1 << 1) +#define RADEON_PP_LUM_MATRIX 0x1d00 +#define RADEON_PP_MISC 0x1c14 +#define RADEON_PP_ROT_MATRIX_0 0x1d58 +#define RADEON_PP_TXFILTER_0 0x1c54 +#define RADEON_PP_TXFILTER_1 0x1c6c +#define RADEON_PP_TXFILTER_2 0x1c84 + +#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c +# define RADEON_RB2D_DC_FLUSH (3 << 0) +# define RADEON_RB2D_DC_FREE (3 << 2) +# define RADEON_RB2D_DC_FLUSH_ALL 0xf +# define RADEON_RB2D_DC_BUSY (1 << 31) +#define RADEON_RB3D_CNTL 0x1c3c +# define RADEON_ALPHA_BLEND_ENABLE (1 << 0) +# define RADEON_PLANE_MASK_ENABLE (1 << 1) +# define RADEON_DITHER_ENABLE (1 << 2) +# define RADEON_ROUND_ENABLE (1 << 3) +# define RADEON_SCALE_DITHER_ENABLE (1 << 4) +# define RADEON_DITHER_INIT (1 << 5) +# define RADEON_ROP_ENABLE (1 << 6) +# define RADEON_STENCIL_ENABLE (1 << 7) +# define RADEON_Z_ENABLE (1 << 8) +# define RADEON_DEPTH_XZ_OFFEST_ENABLE (1 << 9) +# define RADEON_ZBLOCK8 (0 << 15) +# define RADEON_ZBLOCK16 (1 << 15) +#define RADEON_RB3D_DEPTHOFFSET 0x1c24 +#define RADEON_RB3D_PLANEMASK 0x1d84 +#define RADEON_RB3D_STENCILREFMASK 0x1d7c +#define RADEON_RB3D_ZCACHE_MODE 0x3250 +#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254 +# define RADEON_RB3D_ZC_FLUSH (1 << 0) +# define RADEON_RB3D_ZC_FREE (1 << 2) +# define RADEON_RB3D_ZC_FLUSH_ALL 0x5 +# define RADEON_RB3D_ZC_BUSY (1 << 31) +#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c +# define RADEON_Z_TEST_MASK (7 << 4) +# define RADEON_Z_TEST_ALWAYS (7 << 4) +# define RADEON_STENCIL_TEST_ALWAYS (7 << 12) +# define RADEON_STENCIL_S_FAIL_KEEP (0 << 16) +# define RADEON_STENCIL_ZPASS_KEEP (0 << 20) +# define RADEON_STENCIL_ZFAIL_KEEP (0 << 20) +# define RADEON_Z_WRITE_ENABLE (1 << 30) +#define RADEON_RBBM_SOFT_RESET 0x00f0 +# define RADEON_SOFT_RESET_CP (1 << 0) +# define RADEON_SOFT_RESET_HI (1 << 1) +# define RADEON_SOFT_RESET_SE (1 << 2) +# define RADEON_SOFT_RESET_RE (1 << 3) +# define RADEON_SOFT_RESET_PP (1 << 4) +# define RADEON_SOFT_RESET_E2 (1 << 5) +# define RADEON_SOFT_RESET_RB (1 << 6) +# define RADEON_SOFT_RESET_HDP (1 << 7) +#define RADEON_RBBM_STATUS 0x0e40 +# define RADEON_RBBM_FIFOCNT_MASK 0x007f +# define RADEON_RBBM_ACTIVE (1 << 31) +#define RADEON_RE_LINE_PATTERN 0x1cd0 +#define RADEON_RE_MISC 0x26c4 +#define RADEON_RE_TOP_LEFT 0x26c0 +#define RADEON_RE_WIDTH_HEIGHT 0x1c44 +#define RADEON_RE_STIPPLE_ADDR 0x1cc8 +#define RADEON_RE_STIPPLE_DATA 0x1ccc + +#define RADEON_SCISSOR_TL_0 0x1cd8 +#define RADEON_SCISSOR_BR_0 0x1cdc +#define RADEON_SCISSOR_TL_1 0x1ce0 +#define RADEON_SCISSOR_BR_1 0x1ce4 +#define RADEON_SCISSOR_TL_2 0x1ce8 +#define RADEON_SCISSOR_BR_2 0x1cec +#define RADEON_SE_COORD_FMT 0x1c50 +#define RADEON_SE_CNTL 0x1c4c +# define RADEON_FFACE_CULL_CW (0 << 0) +# define RADEON_BFACE_SOLID (3 << 1) +# define RADEON_FFACE_SOLID (3 << 3) +# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6) +# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8) +# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8) +# define RADEON_ALPHA_SHADE_FLAT (1 << 10) +# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10) +# define RADEON_SPECULAR_SHADE_FLAT (1 << 12) +# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12) +# define RADEON_FOG_SHADE_FLAT (1 << 14) +# define RADEON_FOG_SHADE_GOURAUD (2 << 14) +# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24) +# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25) +# define RADEON_VTX_PIX_CENTER_OGL (1 << 27) +# define RADEON_ROUND_MODE_TRUNC (0 << 28) +# define RADEON_ROUND_PREC_8TH_PIX (1 << 30) +#define RADEON_SE_CNTL_STATUS 0x2140 +#define RADEON_SE_LINE_WIDTH 0x1db8 +#define RADEON_SE_VPORT_XSCALE 0x1d98 +#define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8 +#define RADEON_SURFACE_ACCESS_CLR 0x0bfc +#define RADEON_SURFACE_CNTL 0x0b00 +# define RADEON_SURF_TRANSLATION_DIS (1 << 8) +# define RADEON_NONSURF_AP0_SWP_MASK (3 << 20) +# define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20) +# define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20) +# define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20) +# define RADEON_NONSURF_AP1_SWP_MASK (3 << 22) +# define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22) +# define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22) +# define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22) +#define RADEON_SURFACE0_INFO 0x0b0c +# define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0) +# define RADEON_SURF_TILE_MODE_MASK (3 << 16) +# define RADEON_SURF_TILE_MODE_MACRO (0 << 16) +# define RADEON_SURF_TILE_MODE_MICRO (1 << 16) +# define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16) +# define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16) +#define RADEON_SURFACE0_LOWER_BOUND 0x0b04 +#define RADEON_SURFACE0_UPPER_BOUND 0x0b08 +#define RADEON_SURFACE1_INFO 0x0b1c +#define RADEON_SURFACE1_LOWER_BOUND 0x0b14 +#define RADEON_SURFACE1_UPPER_BOUND 0x0b18 +#define RADEON_SURFACE2_INFO 0x0b2c +#define RADEON_SURFACE2_LOWER_BOUND 0x0b24 +#define RADEON_SURFACE2_UPPER_BOUND 0x0b28 +#define RADEON_SURFACE3_INFO 0x0b3c +#define RADEON_SURFACE3_LOWER_BOUND 0x0b34 +#define RADEON_SURFACE3_UPPER_BOUND 0x0b38 +#define RADEON_SURFACE4_INFO 0x0b4c +#define RADEON_SURFACE4_LOWER_BOUND 0x0b44 +#define RADEON_SURFACE4_UPPER_BOUND 0x0b48 +#define RADEON_SURFACE5_INFO 0x0b5c +#define RADEON_SURFACE5_LOWER_BOUND 0x0b54 +#define RADEON_SURFACE5_UPPER_BOUND 0x0b58 +#define RADEON_SURFACE6_INFO 0x0b6c +#define RADEON_SURFACE6_LOWER_BOUND 0x0b64 +#define RADEON_SURFACE6_UPPER_BOUND 0x0b68 +#define RADEON_SURFACE7_INFO 0x0b7c +#define RADEON_SURFACE7_LOWER_BOUND 0x0b74 +#define RADEON_SURFACE7_UPPER_BOUND 0x0b78 +#define RADEON_SW_SEMAPHORE 0x013c + +#define RADEON_WAIT_UNTIL 0x1720 +# define RADEON_WAIT_CRTC_PFLIP (1 << 0) +# define RADEON_WAIT_2D_IDLECLEAN (1 << 16) +# define RADEON_WAIT_3D_IDLECLEAN (1 << 17) +# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18) + +#define RADEON_RB3D_ZMASKOFFSET 0x1c34 +#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c +# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) +# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) + + +/* CP registers */ +#define RADEON_CP_ME_RAM_ADDR 0x07d4 +#define RADEON_CP_ME_RAM_RADDR 0x07d8 +#define RADEON_CP_ME_RAM_DATAH 0x07dc +#define RADEON_CP_ME_RAM_DATAL 0x07e0 + +#define RADEON_CP_RB_BASE 0x0700 +#define RADEON_CP_RB_CNTL 0x0704 +#define RADEON_CP_RB_RPTR_ADDR 0x070c +#define RADEON_CP_RB_RPTR 0x0710 +#define RADEON_CP_RB_WPTR 0x0714 + +#define RADEON_CP_RB_WPTR_DELAY 0x0718 +# define RADEON_PRE_WRITE_TIMER_SHIFT 0 +# define RADEON_PRE_WRITE_LIMIT_SHIFT 23 + +#define RADEON_CP_IB_BASE 0x0738 + +#define RADEON_CP_CSQ_CNTL 0x0740 +# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) +# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) +# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28) +# define RADEON_CSQ_PRIBM_INDDIS (2 << 28) +# define RADEON_CSQ_PRIPIO_INDBM (3 << 28) +# define RADEON_CSQ_PRIBM_INDBM (4 << 28) +# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) + +#define RADEON_AIC_CNTL 0x01d0 +# define RADEON_PCIGART_TRANSLATE_EN (1 << 0) + +/* CP command packets */ +#define RADEON_CP_PACKET0 0x00000000 +# define RADEON_ONE_REG_WR (1 << 15) +#define RADEON_CP_PACKET1 0x40000000 +#define RADEON_CP_PACKET2 0x80000000 +#define RADEON_CP_PACKET3 0xC0000000 +# define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300 +# define RADEON_WAIT_FOR_IDLE 0x00002600 +# define RADEON_3D_DRAW_IMMD 0x00002900 +# define RADEON_3D_CLEAR_ZMASK 0x00003200 +# define RADEON_CNTL_HOSTDATA_BLT 0x00009400 +# define RADEON_CNTL_PAINT_MULTI 0x00009A00 +# define RADEON_CNTL_BITBLT_MULTI 0x00009B00 + +#define RADEON_CP_PACKET_MASK 0xC0000000 +#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 +#define RADEON_CP_PACKET0_REG_MASK 0x000007ff +#define RADEON_CP_PACKET1_REG0_MASK 0x000007ff +#define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 + +#define RADEON_VTX_Z_PRESENT (1 << 31) + +#define RADEON_PRIM_TYPE_NONE (0 << 0) +#define RADEON_PRIM_TYPE_POINT (1 << 0) +#define RADEON_PRIM_TYPE_LINE (2 << 0) +#define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0) +#define RADEON_PRIM_TYPE_TRI_LIST (4 << 0) +#define RADEON_PRIM_TYPE_TRI_FAN (5 << 0) +#define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0) +#define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0) +#define RADEON_PRIM_TYPE_RECT_LIST (8 << 0) +#define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0) +#define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0) +#define RADEON_PRIM_WALK_IND (1 << 4) +#define RADEON_PRIM_WALK_LIST (2 << 4) +#define RADEON_PRIM_WALK_RING (3 << 4) +#define RADEON_COLOR_ORDER_BGRA (0 << 6) +#define RADEON_COLOR_ORDER_RGBA (1 << 6) +#define RADEON_MAOS_ENABLE (1 << 7) +#define RADEON_VTX_FMT_R128_MODE (0 << 8) +#define RADEON_VTX_FMT_RADEON_MODE (1 << 8) +#define RADEON_NUM_VERTICES_SHIFT 16 + +#define RADEON_COLOR_FORMAT_CI8 2 +#define RADEON_COLOR_FORMAT_ARGB1555 3 +#define RADEON_COLOR_FORMAT_RGB565 4 +#define RADEON_COLOR_FORMAT_ARGB8888 6 +#define RADEON_COLOR_FORMAT_RGB332 7 +#define RADEON_COLOR_FORMAT_RGB8 9 +#define RADEON_COLOR_FORMAT_ARGB4444 15 + +#define RADEON_TXF_8BPP_I 0 +#define RADEON_TXF_16BPP_AI88 1 +#define RADEON_TXF_8BPP_RGB332 2 +#define RADEON_TXF_16BPP_ARGB1555 3 +#define RADEON_TXF_16BPP_RGB565 4 +#define RADEON_TXF_16BPP_ARGB4444 5 +#define RADEON_TXF_32BPP_ARGB8888 6 +#define RADEON_TXF_32BPP_RGBA8888 7 + +/* Constants */ +#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ + +#define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0 +#define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1 +#define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2 +#define RADEON_LAST_DISPATCH 1 + +#define RADEON_MAX_VB_AGE 0x7fffffff +#define RADEON_MAX_VB_VERTS (0xffff) + + +#define RADEON_BASE(reg) ((unsigned long)(dev_priv->mmio->handle)) +#define RADEON_ADDR(reg) (RADEON_BASE(reg) + reg) + +#define RADEON_DEREF(reg) *(__volatile__ u32 *)RADEON_ADDR(reg) +#define RADEON_READ(reg) RADEON_DEREF(reg) +#define RADEON_WRITE(reg,val) do { RADEON_DEREF(reg) = val; } while (0) + +#define RADEON_DEREF8(reg) *(__volatile__ u8 *)RADEON_ADDR(reg) +#define RADEON_READ8(reg) RADEON_DEREF8(reg) +#define RADEON_WRITE8(reg,val) do { RADEON_DEREF8(reg) = val; } while (0) + +#define RADEON_WRITE_PLL(addr,val) \ +do { \ + RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, \ + ((addr) & 0x1f) | RADEON_PLL_WR_EN); \ + RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val)); \ +} while (0) + +extern int RADEON_READ_PLL(drm_device_t *dev, int addr); + + + +#define CP_PACKET0( reg, n ) \ + (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) +#define CP_PACKET0_TABLE( reg, n ) \ + (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2)) +#define CP_PACKET1( reg0, reg1 ) \ + (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2)) +#define CP_PACKET2() \ + (RADEON_CP_PACKET2) +#define CP_PACKET3( pkt, n ) \ + (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) + + +/* ================================================================ + * Engine control helper macros + */ + +#define RADEON_WAIT_UNTIL_2D_IDLE() \ +do { \ + OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ + OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ + RADEON_WAIT_HOST_IDLECLEAN) ); \ +} while (0) + +#define RADEON_WAIT_UNTIL_3D_IDLE() \ +do { \ + OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ + OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \ + RADEON_WAIT_HOST_IDLECLEAN) ); \ +} while (0) + +#define RADEON_WAIT_UNTIL_IDLE() \ +do { \ + OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ + OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ + RADEON_WAIT_3D_IDLECLEAN | \ + RADEON_WAIT_HOST_IDLECLEAN) ); \ +} while (0) + +#define RADEON_WAIT_UNTIL_PAGE_FLIPPED() \ +do { \ + OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ + OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \ +} while (0) + +#define RADEON_FLUSH_CACHE() \ +do { \ + OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \ + OUT_RING( RADEON_RB2D_DC_FLUSH ); \ +} while (0) + +#define RADEON_PURGE_CACHE() \ +do { \ + OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \ + OUT_RING( RADEON_RB2D_DC_FLUSH_ALL ); \ +} while (0) + +#define RADEON_FLUSH_ZCACHE() \ +do { \ + OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \ + OUT_RING( RADEON_RB3D_ZC_FLUSH ); \ +} while (0) + +#define RADEON_PURGE_ZCACHE() \ +do { \ + OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \ + OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \ +} while (0) + + +/* ================================================================ + * Misc helper macros + */ + +#define VB_AGE_CHECK_WITH_RET( dev_priv ) \ +do { \ + drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \ + if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \ + int __ret = radeon_do_cp_idle( dev_priv ); \ + if ( __ret < 0 ) return __ret; \ + sarea_priv->last_dispatch = 0; \ + radeon_freelist_reset( dev ); \ + } \ +} while (0) + +#define RADEON_DISPATCH_AGE( age ) \ +do { \ + OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \ + OUT_RING( age ); \ +} while (0) + +#define RADEON_FRAME_AGE( age ) \ +do { \ + OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \ + OUT_RING( age ); \ +} while (0) + +#define RADEON_CLEAR_AGE( age ) \ +do { \ + OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \ + OUT_RING( age ); \ +} while (0) + + +/* ================================================================ + * Ring control + */ + +#define radeon_flush_write_combine() mb() + + +#define RADEON_VERBOSE 0 + +#define RING_LOCALS int write; unsigned int mask; volatile u32 *ring; + +#define BEGIN_RING( n ) do { \ + if ( RADEON_VERBOSE ) { \ + DRM_INFO( "BEGIN_RING( %d ) in %s\n", \ + n, __FUNCTION__ ); \ + } \ + if ( dev_priv->ring.space < (n) * sizeof(u32) ) { \ + radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \ + } \ + dev_priv->ring.space -= (n) * sizeof(u32); \ + ring = dev_priv->ring.start; \ + write = dev_priv->ring.tail; \ + mask = dev_priv->ring.tail_mask; \ +} while (0) + +#define ADVANCE_RING() do { \ + if ( RADEON_VERBOSE ) { \ + DRM_INFO( "ADVANCE_RING() tail=0x%06x wr=0x%06x\n", \ + write, dev_priv->ring.tail ); \ + } \ + radeon_flush_write_combine(); \ + dev_priv->ring.tail = write; \ + RADEON_WRITE( RADEON_CP_RB_WPTR, write ); \ +} while (0) + +#define OUT_RING( x ) do { \ + if ( RADEON_VERBOSE ) { \ + DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \ + (unsigned int)(x), write ); \ + } \ + ring[write++] = (x); \ + write &= mask; \ +} while (0) + +#define RADEON_PERFORMANCE_BOXES 0 + +#endif /* __RADEON_DRV_H__ */ diff -urN linux-2.4.10/drivers/char/drm-4.0/radeon_state.c linux-2.4.10-lia/drivers/char/drm-4.0/radeon_state.c --- linux-2.4.10/drivers/char/drm-4.0/radeon_state.c Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/radeon_state.c Wed Aug 15 20:52:12 2001 @@ -0,0 +1,1447 @@ +/* radeon_state.c -- State support for Radeon -*- linux-c -*- + * + * Copyright 2000 VA Linux Systems, Inc., Fremont, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Kevin E. Martin + * Gareth Hughes + * + */ + +#define __NO_VERSION__ +#include "drmP.h" +#include "radeon_drv.h" +#include "drm.h" +#include + + +/* ================================================================ + * CP hardware state programming functions + */ + +static inline void radeon_emit_clip_rect( drm_radeon_private_t *dev_priv, + drm_clip_rect_t *box ) +{ + RING_LOCALS; + + DRM_DEBUG( " box: x1=%d y1=%d x2=%d y2=%d\n", + box->x1, box->y1, box->x2, box->y2 ); + + BEGIN_RING( 4 ); + + OUT_RING( CP_PACKET0( RADEON_RE_TOP_LEFT, 0 ) ); + OUT_RING( (box->y1 << 16) | box->x1 ); + + OUT_RING( CP_PACKET0( RADEON_RE_WIDTH_HEIGHT, 0 ) ); + OUT_RING( ((box->y2 - 1) << 16) | (box->x2 - 1) ); + + ADVANCE_RING(); +} + +static inline void radeon_emit_context( drm_radeon_private_t *dev_priv ) +{ + drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_radeon_context_regs_t *ctx = &sarea_priv->context_state; + RING_LOCALS; + DRM_DEBUG( " %s\n", __FUNCTION__ ); + + BEGIN_RING( 14 ); + + OUT_RING( CP_PACKET0( RADEON_PP_MISC, 6 ) ); + OUT_RING( ctx->pp_misc ); + OUT_RING( ctx->pp_fog_color ); + OUT_RING( ctx->re_solid_color ); + OUT_RING( ctx->rb3d_blendcntl ); + OUT_RING( ctx->rb3d_depthoffset ); + OUT_RING( ctx->rb3d_depthpitch ); + OUT_RING( ctx->rb3d_zstencilcntl ); + + OUT_RING( CP_PACKET0( RADEON_PP_CNTL, 2 ) ); + OUT_RING( ctx->pp_cntl ); + OUT_RING( ctx->rb3d_cntl ); + OUT_RING( ctx->rb3d_coloroffset ); + + OUT_RING( CP_PACKET0( RADEON_RB3D_COLORPITCH, 0 ) ); + OUT_RING( ctx->rb3d_colorpitch ); + + ADVANCE_RING(); +} + +static inline void radeon_emit_vertfmt( drm_radeon_private_t *dev_priv ) +{ + drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_radeon_context_regs_t *ctx = &sarea_priv->context_state; + RING_LOCALS; + DRM_DEBUG( " %s\n", __FUNCTION__ ); + + BEGIN_RING( 2 ); + + OUT_RING( CP_PACKET0( RADEON_SE_COORD_FMT, 0 ) ); + OUT_RING( ctx->se_coord_fmt ); + + ADVANCE_RING(); +} + +static inline void radeon_emit_line( drm_radeon_private_t *dev_priv ) +{ + drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_radeon_context_regs_t *ctx = &sarea_priv->context_state; + RING_LOCALS; + DRM_DEBUG( " %s\n", __FUNCTION__ ); + + BEGIN_RING( 5 ); + + OUT_RING( CP_PACKET0( RADEON_RE_LINE_PATTERN, 1 ) ); + OUT_RING( ctx->re_line_pattern ); + OUT_RING( ctx->re_line_state ); + + OUT_RING( CP_PACKET0( RADEON_SE_LINE_WIDTH, 0 ) ); + OUT_RING( ctx->se_line_width ); + + ADVANCE_RING(); +} + +static inline void radeon_emit_bumpmap( drm_radeon_private_t *dev_priv ) +{ + drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_radeon_context_regs_t *ctx = &sarea_priv->context_state; + RING_LOCALS; + DRM_DEBUG( " %s\n", __FUNCTION__ ); + + BEGIN_RING( 5 ); + + OUT_RING( CP_PACKET0( RADEON_PP_LUM_MATRIX, 0 ) ); + OUT_RING( ctx->pp_lum_matrix ); + + OUT_RING( CP_PACKET0( RADEON_PP_ROT_MATRIX_0, 1 ) ); + OUT_RING( ctx->pp_rot_matrix_0 ); + OUT_RING( ctx->pp_rot_matrix_1 ); + + ADVANCE_RING(); +} + +static inline void radeon_emit_masks( drm_radeon_private_t *dev_priv ) +{ + drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_radeon_context_regs_t *ctx = &sarea_priv->context_state; + RING_LOCALS; + DRM_DEBUG( " %s\n", __FUNCTION__ ); + + BEGIN_RING( 4 ); + + OUT_RING( CP_PACKET0( RADEON_RB3D_STENCILREFMASK, 2 ) ); + OUT_RING( ctx->rb3d_stencilrefmask ); + OUT_RING( ctx->rb3d_ropcntl ); + OUT_RING( ctx->rb3d_planemask ); + + ADVANCE_RING(); +} + +static inline void radeon_emit_viewport( drm_radeon_private_t *dev_priv ) +{ + drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_radeon_context_regs_t *ctx = &sarea_priv->context_state; + RING_LOCALS; + DRM_DEBUG( " %s\n", __FUNCTION__ ); + + BEGIN_RING( 7 ); + + OUT_RING( CP_PACKET0( RADEON_SE_VPORT_XSCALE, 5 ) ); + OUT_RING( ctx->se_vport_xscale ); + OUT_RING( ctx->se_vport_xoffset ); + OUT_RING( ctx->se_vport_yscale ); + OUT_RING( ctx->se_vport_yoffset ); + OUT_RING( ctx->se_vport_zscale ); + OUT_RING( ctx->se_vport_zoffset ); + + ADVANCE_RING(); +} + +static inline void radeon_emit_setup( drm_radeon_private_t *dev_priv ) +{ + drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_radeon_context_regs_t *ctx = &sarea_priv->context_state; + RING_LOCALS; + DRM_DEBUG( " %s\n", __FUNCTION__ ); + + BEGIN_RING( 4 ); + + OUT_RING( CP_PACKET0( RADEON_SE_CNTL, 0 ) ); + OUT_RING( ctx->se_cntl ); + OUT_RING( CP_PACKET0( RADEON_SE_CNTL_STATUS, 0 ) ); + OUT_RING( ctx->se_cntl_status ); + + ADVANCE_RING(); +} + +static inline void radeon_emit_tcl( drm_radeon_private_t *dev_priv ) +{ +#ifdef TCL_ENABLE + drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_radeon_context_regs_t *ctx = &sarea_priv->context_state; + RING_LOCALS; + DRM_DEBUG( " %s\n", __FUNCTION__ ); + + BEGIN_RING( 29 ); + + OUT_RING( CP_PACKET0( RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 27 ) ); + OUT_RING( ctx->se_tcl_material_emmissive.red ); + OUT_RING( ctx->se_tcl_material_emmissive.green ); + OUT_RING( ctx->se_tcl_material_emmissive.blue ); + OUT_RING( ctx->se_tcl_material_emmissive.alpha ); + OUT_RING( ctx->se_tcl_material_ambient.red ); + OUT_RING( ctx->se_tcl_material_ambient.green ); + OUT_RING( ctx->se_tcl_material_ambient.blue ); + OUT_RING( ctx->se_tcl_material_ambient.alpha ); + OUT_RING( ctx->se_tcl_material_diffuse.red ); + OUT_RING( ctx->se_tcl_material_diffuse.green ); + OUT_RING( ctx->se_tcl_material_diffuse.blue ); + OUT_RING( ctx->se_tcl_material_diffuse.alpha ); + OUT_RING( ctx->se_tcl_material_specular.red ); + OUT_RING( ctx->se_tcl_material_specular.green ); + OUT_RING( ctx->se_tcl_material_specular.blue ); + OUT_RING( ctx->se_tcl_material_specular.alpha ); + OUT_RING( ctx->se_tcl_shininess ); + OUT_RING( ctx->se_tcl_output_vtx_fmt ); + OUT_RING( ctx->se_tcl_output_vtx_sel ); + OUT_RING( ctx->se_tcl_matrix_select_0 ); + OUT_RING( ctx->se_tcl_matrix_select_1 ); + OUT_RING( ctx->se_tcl_ucp_vert_blend_ctl ); + OUT_RING( ctx->se_tcl_texture_proc_ctl ); + OUT_RING( ctx->se_tcl_light_model_ctl ); + for ( i = 0 ; i < 4 ; i++ ) { + OUT_RING( ctx->se_tcl_per_light_ctl[i] ); + } + + ADVANCE_RING(); +#else + DRM_ERROR( "TCL not enabled!\n" ); +#endif +} + +static inline void radeon_emit_misc( drm_radeon_private_t *dev_priv ) +{ + drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_radeon_context_regs_t *ctx = &sarea_priv->context_state; + RING_LOCALS; + DRM_DEBUG( " %s\n", __FUNCTION__ ); + + BEGIN_RING( 2 ); + + OUT_RING( CP_PACKET0( RADEON_RE_MISC, 0 ) ); + OUT_RING( ctx->re_misc ); + + ADVANCE_RING(); +} + +static inline void radeon_emit_tex0( drm_radeon_private_t *dev_priv ) +{ + drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_radeon_texture_regs_t *tex = &sarea_priv->tex_state[0]; + RING_LOCALS; + DRM_DEBUG( " %s: offset=0x%x\n", __FUNCTION__, tex->pp_txoffset ); + + BEGIN_RING( 9 ); + + OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_0, 5 ) ); + OUT_RING( tex->pp_txfilter ); + OUT_RING( tex->pp_txformat ); + OUT_RING( tex->pp_txoffset ); + OUT_RING( tex->pp_txcblend ); + OUT_RING( tex->pp_txablend ); + OUT_RING( tex->pp_tfactor ); + + OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_0, 0 ) ); + OUT_RING( tex->pp_border_color ); + + ADVANCE_RING(); +} + +static inline void radeon_emit_tex1( drm_radeon_private_t *dev_priv ) +{ + drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_radeon_texture_regs_t *tex = &sarea_priv->tex_state[1]; + RING_LOCALS; + DRM_DEBUG( " %s: offset=0x%x\n", __FUNCTION__, tex->pp_txoffset ); + + BEGIN_RING( 9 ); + + OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_1, 5 ) ); + OUT_RING( tex->pp_txfilter ); + OUT_RING( tex->pp_txformat ); + OUT_RING( tex->pp_txoffset ); + OUT_RING( tex->pp_txcblend ); + OUT_RING( tex->pp_txablend ); + OUT_RING( tex->pp_tfactor ); + + OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_1, 0 ) ); + OUT_RING( tex->pp_border_color ); + + ADVANCE_RING(); +} + +static inline void radeon_emit_tex2( drm_radeon_private_t *dev_priv ) +{ + drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_radeon_texture_regs_t *tex = &sarea_priv->tex_state[2]; + RING_LOCALS; + DRM_DEBUG( " %s\n", __FUNCTION__ ); + + BEGIN_RING( 9 ); + + OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_2, 5 ) ); + OUT_RING( tex->pp_txfilter ); + OUT_RING( tex->pp_txformat ); + OUT_RING( tex->pp_txoffset ); + OUT_RING( tex->pp_txcblend ); + OUT_RING( tex->pp_txablend ); + OUT_RING( tex->pp_tfactor ); + + OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_2, 0 ) ); + OUT_RING( tex->pp_border_color ); + + ADVANCE_RING(); +} + +static inline void radeon_emit_state( drm_radeon_private_t *dev_priv ) +{ + drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; + unsigned int dirty = sarea_priv->dirty; + + DRM_DEBUG( "%s: dirty=0x%08x\n", __FUNCTION__, dirty ); + + if ( dirty & RADEON_UPLOAD_CONTEXT ) { + radeon_emit_context( dev_priv ); + sarea_priv->dirty &= ~RADEON_UPLOAD_CONTEXT; + } + + if ( dirty & RADEON_UPLOAD_VERTFMT ) { + radeon_emit_vertfmt( dev_priv ); + sarea_priv->dirty &= ~RADEON_UPLOAD_VERTFMT; + } + + if ( dirty & RADEON_UPLOAD_LINE ) { + radeon_emit_line( dev_priv ); + sarea_priv->dirty &= ~RADEON_UPLOAD_LINE; + } + + if ( dirty & RADEON_UPLOAD_BUMPMAP ) { + radeon_emit_bumpmap( dev_priv ); + sarea_priv->dirty &= ~RADEON_UPLOAD_BUMPMAP; + } + + if ( dirty & RADEON_UPLOAD_MASKS ) { + radeon_emit_masks( dev_priv ); + sarea_priv->dirty &= ~RADEON_UPLOAD_MASKS; + } + + if ( dirty & RADEON_UPLOAD_VIEWPORT ) { + radeon_emit_viewport( dev_priv ); + sarea_priv->dirty &= ~RADEON_UPLOAD_VIEWPORT; + } + + if ( dirty & RADEON_UPLOAD_SETUP ) { + radeon_emit_setup( dev_priv ); + sarea_priv->dirty &= ~RADEON_UPLOAD_SETUP; + } + + if ( dirty & RADEON_UPLOAD_TCL ) { +#ifdef TCL_ENABLE + radeon_emit_tcl( dev_priv ); +#endif + sarea_priv->dirty &= ~RADEON_UPLOAD_TCL; + } + + if ( dirty & RADEON_UPLOAD_MISC ) { + radeon_emit_misc( dev_priv ); + sarea_priv->dirty &= ~RADEON_UPLOAD_MISC; + } + + if ( dirty & RADEON_UPLOAD_TEX0 ) { + radeon_emit_tex0( dev_priv ); + sarea_priv->dirty &= ~RADEON_UPLOAD_TEX0; + } + + if ( dirty & RADEON_UPLOAD_TEX1 ) { + radeon_emit_tex1( dev_priv ); + sarea_priv->dirty &= ~RADEON_UPLOAD_TEX1; + } + + if ( dirty & RADEON_UPLOAD_TEX2 ) { +#if 0 + radeon_emit_tex2( dev_priv ); +#endif + sarea_priv->dirty &= ~RADEON_UPLOAD_TEX2; + } + + sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES | + RADEON_UPLOAD_TEX1IMAGES | + RADEON_UPLOAD_TEX2IMAGES | + RADEON_REQUIRE_QUIESCENCE); +} + + +#if RADEON_PERFORMANCE_BOXES +/* ================================================================ + * Performance monitoring functions + */ + +static void radeon_clear_box( drm_radeon_private_t *dev_priv, + int x, int y, int w, int h, + int r, int g, int b ) +{ + u32 pitch, offset; + u32 color; + RING_LOCALS; + + switch ( dev_priv->color_fmt ) { + case RADEON_COLOR_FORMAT_RGB565: + color = (((r & 0xf8) << 8) | + ((g & 0xfc) << 3) | + ((b & 0xf8) >> 3)); + break; + case RADEON_COLOR_FORMAT_ARGB8888: + default: + color = (((0xff) << 24) | (r << 16) | (g << 8) | b); + break; + } + + offset = dev_priv->back_offset; + pitch = dev_priv->back_pitch >> 3; + + BEGIN_RING( 6 ); + + OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) ); + OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL | + RADEON_GMC_BRUSH_SOLID_COLOR | + (dev_priv->color_fmt << 8) | + RADEON_GMC_SRC_DATATYPE_COLOR | + RADEON_ROP3_P | + RADEON_GMC_CLR_CMP_CNTL_DIS ); + + OUT_RING( (pitch << 22) | (offset >> 5) ); + OUT_RING( color ); + + OUT_RING( (x << 16) | y ); + OUT_RING( (w << 16) | h ); + + ADVANCE_RING(); +} + +static void radeon_cp_performance_boxes( drm_radeon_private_t *dev_priv ) +{ + if ( atomic_read( &dev_priv->idle_count ) == 0 ) { + radeon_clear_box( dev_priv, 64, 4, 8, 8, 0, 255, 0 ); + } else { + atomic_set( &dev_priv->idle_count, 0 ); + } +} + +#endif + + +/* ================================================================ + * CP command dispatch functions + */ + +static void radeon_print_dirty( const char *msg, unsigned int flags ) +{ + DRM_DEBUG( "%s: (0x%x) %s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", + msg, + flags, + (flags & RADEON_UPLOAD_CONTEXT) ? "context, " : "", + (flags & RADEON_UPLOAD_VERTFMT) ? "vertfmt, " : "", + (flags & RADEON_UPLOAD_LINE) ? "line, " : "", + (flags & RADEON_UPLOAD_BUMPMAP) ? "bumpmap, " : "", + (flags & RADEON_UPLOAD_MASKS) ? "masks, " : "", + (flags & RADEON_UPLOAD_VIEWPORT) ? "viewport, " : "", + (flags & RADEON_UPLOAD_SETUP) ? "setup, " : "", + (flags & RADEON_UPLOAD_TCL) ? "tcl, " : "", + (flags & RADEON_UPLOAD_MISC) ? "misc, " : "", + (flags & RADEON_UPLOAD_TEX0) ? "tex0, " : "", + (flags & RADEON_UPLOAD_TEX1) ? "tex1, " : "", + (flags & RADEON_UPLOAD_TEX2) ? "tex2, " : "", + (flags & RADEON_UPLOAD_CLIPRECTS) ? "cliprects, " : "", + (flags & RADEON_REQUIRE_QUIESCENCE) ? "quiescence, " : "" ); +} + +static void radeon_cp_dispatch_clear( drm_device_t *dev, + drm_radeon_clear_t *clear ) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; + int nbox = sarea_priv->nbox; + drm_clip_rect_t *pbox = sarea_priv->boxes; + unsigned int flags = clear->flags; + int i; + RING_LOCALS; + DRM_DEBUG( "%s\n", __FUNCTION__ ); + + radeon_update_ring_snapshot( dev_priv ); + + if ( dev_priv->page_flipping && dev_priv->current_page == 1 ) { + unsigned int tmp = flags; + + flags &= ~(RADEON_FRONT | RADEON_BACK); + if ( tmp & RADEON_FRONT ) flags |= RADEON_BACK; + if ( tmp & RADEON_BACK ) flags |= RADEON_FRONT; + } + + for ( i = 0 ; i < nbox ; i++ ) { + int x = pbox[i].x1; + int y = pbox[i].y1; + int w = pbox[i].x2 - x; + int h = pbox[i].y2 - y; + + DRM_DEBUG( "dispatch clear %d,%d-%d,%d flags 0x%x\n", + x, y, w, h, flags ); + + if ( flags & (RADEON_FRONT | RADEON_BACK) ) { + BEGIN_RING( 4 ); + + /* Ensure the 3D stream is idle before doing a + * 2D fill to clear the front or back buffer. + */ + RADEON_WAIT_UNTIL_3D_IDLE(); + + OUT_RING( CP_PACKET0( RADEON_DP_WRITE_MASK, 0 ) ); + OUT_RING( sarea_priv->context_state.rb3d_planemask ); + + ADVANCE_RING(); + + /* Make sure we restore the 3D state next time. + */ + dev_priv->sarea_priv->dirty |= (RADEON_UPLOAD_CONTEXT | + RADEON_UPLOAD_MASKS); + } + + if ( flags & RADEON_FRONT ) { + BEGIN_RING( 6 ); + + OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) ); + OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL | + RADEON_GMC_BRUSH_SOLID_COLOR | + (dev_priv->color_fmt << 8) | + RADEON_GMC_SRC_DATATYPE_COLOR | + RADEON_ROP3_P | + RADEON_GMC_CLR_CMP_CNTL_DIS ); + + OUT_RING( dev_priv->front_pitch_offset ); + OUT_RING( clear->clear_color ); + + OUT_RING( (x << 16) | y ); + OUT_RING( (w << 16) | h ); + + ADVANCE_RING(); + } + + if ( flags & RADEON_BACK ) { + BEGIN_RING( 6 ); + + OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) ); + OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL | + RADEON_GMC_BRUSH_SOLID_COLOR | + (dev_priv->color_fmt << 8) | + RADEON_GMC_SRC_DATATYPE_COLOR | + RADEON_ROP3_P | + RADEON_GMC_CLR_CMP_CNTL_DIS ); + + OUT_RING( dev_priv->back_pitch_offset ); + OUT_RING( clear->clear_color ); + + OUT_RING( (x << 16) | y ); + OUT_RING( (w << 16) | h ); + + ADVANCE_RING(); + + } + + if ( flags & RADEON_DEPTH ) { + drm_radeon_depth_clear_t *depth_clear = + &dev_priv->depth_clear; + + if ( sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS ) { + radeon_emit_state( dev_priv ); + } + + /* FIXME: Render a rectangle to clear the depth + * buffer. So much for those "fast Z clears"... + */ + BEGIN_RING( 23 ); + + RADEON_WAIT_UNTIL_2D_IDLE(); + + OUT_RING( CP_PACKET0( RADEON_PP_CNTL, 1 ) ); + OUT_RING( 0x00000000 ); + OUT_RING( depth_clear->rb3d_cntl ); + OUT_RING( CP_PACKET0( RADEON_RB3D_ZSTENCILCNTL, 0 ) ); + OUT_RING( depth_clear->rb3d_zstencilcntl ); + OUT_RING( CP_PACKET0( RADEON_RB3D_PLANEMASK, 0 ) ); + OUT_RING( 0x00000000 ); + OUT_RING( CP_PACKET0( RADEON_SE_CNTL, 0 ) ); + OUT_RING( depth_clear->se_cntl ); + + OUT_RING( CP_PACKET3( RADEON_3D_DRAW_IMMD, 10 ) ); + OUT_RING( RADEON_VTX_Z_PRESENT ); + OUT_RING( (RADEON_PRIM_TYPE_RECT_LIST | + RADEON_PRIM_WALK_RING | + RADEON_MAOS_ENABLE | + RADEON_VTX_FMT_RADEON_MODE | + (3 << RADEON_NUM_VERTICES_SHIFT)) ); + + OUT_RING( clear->rect.ui[CLEAR_X1] ); + OUT_RING( clear->rect.ui[CLEAR_Y1] ); + OUT_RING( clear->rect.ui[CLEAR_DEPTH] ); + + OUT_RING( clear->rect.ui[CLEAR_X1] ); + OUT_RING( clear->rect.ui[CLEAR_Y2] ); + OUT_RING( clear->rect.ui[CLEAR_DEPTH] ); + + OUT_RING( clear->rect.ui[CLEAR_X2] ); + OUT_RING( clear->rect.ui[CLEAR_Y2] ); + OUT_RING( clear->rect.ui[CLEAR_DEPTH] ); + + ADVANCE_RING(); + + /* Make sure we restore the 3D state next time. + */ + dev_priv->sarea_priv->dirty |= (RADEON_UPLOAD_CONTEXT | + RADEON_UPLOAD_SETUP | + RADEON_UPLOAD_MASKS); + } + } + + /* Increment the clear counter. The client-side 3D driver must + * wait on this value before performing the clear ioctl. We + * need this because the card's so damned fast... + */ + dev_priv->sarea_priv->last_clear++; + + BEGIN_RING( 4 ); + + RADEON_CLEAR_AGE( dev_priv->sarea_priv->last_clear ); + RADEON_WAIT_UNTIL_IDLE(); + + ADVANCE_RING(); +} + +static void radeon_cp_dispatch_swap( drm_device_t *dev ) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; + int nbox = sarea_priv->nbox; + drm_clip_rect_t *pbox = sarea_priv->boxes; + int i; + RING_LOCALS; + DRM_DEBUG( "%s\n", __FUNCTION__ ); + + radeon_update_ring_snapshot( dev_priv ); + +#if RADEON_PERFORMANCE_BOXES + /* Do some trivial performance monitoring... + */ + radeon_cp_performance_boxes( dev_priv ); +#endif + + /* Wait for the 3D stream to idle before dispatching the bitblt. + * This will prevent data corruption between the two streams. + */ + BEGIN_RING( 2 ); + + RADEON_WAIT_UNTIL_3D_IDLE(); + + ADVANCE_RING(); + + for ( i = 0 ; i < nbox ; i++ ) { + int x = pbox[i].x1; + int y = pbox[i].y1; + int w = pbox[i].x2 - x; + int h = pbox[i].y2 - y; + + DRM_DEBUG( "dispatch swap %d,%d-%d,%d\n", + x, y, w, h ); + + BEGIN_RING( 7 ); + + OUT_RING( CP_PACKET3( RADEON_CNTL_BITBLT_MULTI, 5 ) ); + OUT_RING( RADEON_GMC_SRC_PITCH_OFFSET_CNTL | + RADEON_GMC_DST_PITCH_OFFSET_CNTL | + RADEON_GMC_BRUSH_NONE | + (dev_priv->color_fmt << 8) | + RADEON_GMC_SRC_DATATYPE_COLOR | + RADEON_ROP3_S | + RADEON_DP_SRC_SOURCE_MEMORY | + RADEON_GMC_CLR_CMP_CNTL_DIS | + RADEON_GMC_WR_MSK_DIS ); + + OUT_RING( dev_priv->back_pitch_offset ); + OUT_RING( dev_priv->front_pitch_offset ); + + OUT_RING( (x << 16) | y ); + OUT_RING( (x << 16) | y ); + OUT_RING( (w << 16) | h ); + + ADVANCE_RING(); + } + + /* Increment the frame counter. The client-side 3D driver must + * throttle the framerate by waiting for this value before + * performing the swapbuffer ioctl. + */ + dev_priv->sarea_priv->last_frame++; + + BEGIN_RING( 4 ); + + RADEON_FRAME_AGE( dev_priv->sarea_priv->last_frame ); + RADEON_WAIT_UNTIL_2D_IDLE(); + + ADVANCE_RING(); +} + +static void radeon_cp_dispatch_flip( drm_device_t *dev ) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + RING_LOCALS; + DRM_DEBUG( "%s: page=%d\n", __FUNCTION__, dev_priv->current_page ); + + radeon_update_ring_snapshot( dev_priv ); + +#if RADEON_PERFORMANCE_BOXES + /* Do some trivial performance monitoring... + */ + radeon_cp_performance_boxes( dev_priv ); +#endif + + BEGIN_RING( 6 ); + + RADEON_WAIT_UNTIL_3D_IDLE(); + RADEON_WAIT_UNTIL_PAGE_FLIPPED(); + + OUT_RING( CP_PACKET0( RADEON_CRTC_OFFSET, 0 ) ); + + if ( dev_priv->current_page == 0 ) { + OUT_RING( dev_priv->back_offset ); + dev_priv->current_page = 1; + } else { + OUT_RING( dev_priv->front_offset ); + dev_priv->current_page = 0; + } + + ADVANCE_RING(); + + /* Increment the frame counter. The client-side 3D driver must + * throttle the framerate by waiting for this value before + * performing the swapbuffer ioctl. + */ + dev_priv->sarea_priv->last_frame++; + + BEGIN_RING( 2 ); + + RADEON_FRAME_AGE( dev_priv->sarea_priv->last_frame ); + + ADVANCE_RING(); +} + +static void radeon_cp_dispatch_vertex( drm_device_t *dev, + drm_buf_t *buf ) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + drm_radeon_buf_priv_t *buf_priv = buf->dev_private; + drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; + int format = sarea_priv->vc_format; + int offset = dev_priv->agp_buffers_offset + buf->offset; + int size = buf->used; + int prim = buf_priv->prim; + int i = 0; + RING_LOCALS; + DRM_DEBUG( "%s: nbox=%d\n", __FUNCTION__, sarea_priv->nbox ); + + radeon_update_ring_snapshot( dev_priv ); + + if ( 0 ) + radeon_print_dirty( "dispatch_vertex", sarea_priv->dirty ); + + if ( buf->used ) { + buf_priv->dispatched = 1; + + if ( sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS ) { + radeon_emit_state( dev_priv ); + } + + do { + /* Emit the next set of up to three cliprects */ + if ( i < sarea_priv->nbox ) { + radeon_emit_clip_rect( dev_priv, + &sarea_priv->boxes[i] ); + } + + /* Emit the vertex buffer rendering commands */ + BEGIN_RING( 5 ); + + OUT_RING( CP_PACKET3( RADEON_3D_RNDR_GEN_INDX_PRIM, 3 ) ); + OUT_RING( offset ); + OUT_RING( size ); + OUT_RING( format ); + OUT_RING( prim | RADEON_PRIM_WALK_LIST | + RADEON_COLOR_ORDER_RGBA | + RADEON_VTX_FMT_RADEON_MODE | + (size << RADEON_NUM_VERTICES_SHIFT) ); + + ADVANCE_RING(); + + i++; + } while ( i < sarea_priv->nbox ); + } + + if ( buf_priv->discard ) { + buf_priv->age = dev_priv->sarea_priv->last_dispatch; + + /* Emit the vertex buffer age */ + BEGIN_RING( 2 ); + RADEON_DISPATCH_AGE( buf_priv->age ); + ADVANCE_RING(); + + buf->pending = 1; + buf->used = 0; + /* FIXME: Check dispatched field */ + buf_priv->dispatched = 0; + } + + dev_priv->sarea_priv->last_dispatch++; + + sarea_priv->dirty &= ~RADEON_UPLOAD_CLIPRECTS; + sarea_priv->nbox = 0; +} + + +static void radeon_cp_dispatch_indirect( drm_device_t *dev, + drm_buf_t *buf, + int start, int end ) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + drm_radeon_buf_priv_t *buf_priv = buf->dev_private; + RING_LOCALS; + DRM_DEBUG( "indirect: buf=%d s=0x%x e=0x%x\n", + buf->idx, start, end ); + + radeon_update_ring_snapshot( dev_priv ); + + if ( start != end ) { + int offset = (dev_priv->agp_buffers_offset + + buf->offset + start); + int dwords = (end - start + 3) / sizeof(u32); + + /* Indirect buffer data must be an even number of + * dwords, so if we've been given an odd number we must + * pad the data with a Type-2 CP packet. + */ + if ( dwords & 1 ) { + u32 *data = (u32 *) + ((char *)dev_priv->buffers->handle + + buf->offset + start); + data[dwords++] = RADEON_CP_PACKET2; + } + + buf_priv->dispatched = 1; + + /* Fire off the indirect buffer */ + BEGIN_RING( 3 ); + + OUT_RING( CP_PACKET0( RADEON_CP_IB_BASE, 1 ) ); + OUT_RING( offset ); + OUT_RING( dwords ); + + ADVANCE_RING(); + } + + if ( buf_priv->discard ) { + buf_priv->age = dev_priv->sarea_priv->last_dispatch; + + /* Emit the indirect buffer age */ + BEGIN_RING( 2 ); + RADEON_DISPATCH_AGE( buf_priv->age ); + ADVANCE_RING(); + + buf->pending = 1; + buf->used = 0; + /* FIXME: Check dispatched field */ + buf_priv->dispatched = 0; + } + + dev_priv->sarea_priv->last_dispatch++; +} + +static void radeon_cp_dispatch_indices( drm_device_t *dev, + drm_buf_t *buf, + int start, int end, + int count ) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + drm_radeon_buf_priv_t *buf_priv = buf->dev_private; + drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; + int format = sarea_priv->vc_format; + int offset = dev_priv->agp_buffers_offset; + int prim = buf_priv->prim; + u32 *data; + int dwords; + int i = 0; + RING_LOCALS; + DRM_DEBUG( "indices: s=%d e=%d c=%d\n", start, end, count ); + + radeon_update_ring_snapshot( dev_priv ); + + if ( 0 ) + radeon_print_dirty( "dispatch_indices", sarea_priv->dirty ); + + if ( start != end ) { + buf_priv->dispatched = 1; + + if ( sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS ) { + radeon_emit_state( dev_priv ); + } + + dwords = (end - start + 3) / sizeof(u32); + + data = (u32 *)((char *)dev_priv->buffers->handle + + buf->offset + start); + + data[0] = CP_PACKET3( RADEON_3D_RNDR_GEN_INDX_PRIM, dwords-2 ); + + data[1] = offset; + data[2] = RADEON_MAX_VB_VERTS; + data[3] = format; + data[4] = (prim | RADEON_PRIM_WALK_IND | + RADEON_COLOR_ORDER_RGBA | + RADEON_VTX_FMT_RADEON_MODE | + (count << RADEON_NUM_VERTICES_SHIFT) ); + + if ( count & 0x1 ) { + data[dwords-1] &= 0x0000ffff; + } + + do { + /* Emit the next set of up to three cliprects */ + if ( i < sarea_priv->nbox ) { + radeon_emit_clip_rect( dev_priv, + &sarea_priv->boxes[i] ); + } + + radeon_cp_dispatch_indirect( dev, buf, start, end ); + + i++; + } while ( i < sarea_priv->nbox ); + } + + if ( buf_priv->discard ) { + buf_priv->age = dev_priv->sarea_priv->last_dispatch; + + /* Emit the vertex buffer age */ + BEGIN_RING( 2 ); + RADEON_DISPATCH_AGE( buf_priv->age ); + ADVANCE_RING(); + + buf->pending = 1; + /* FIXME: Check dispatched field */ + buf_priv->dispatched = 0; + } + + dev_priv->sarea_priv->last_dispatch++; + + sarea_priv->dirty &= ~RADEON_UPLOAD_CLIPRECTS; + sarea_priv->nbox = 0; +} + +static int radeon_cp_dispatch_blit( drm_device_t *dev, + drm_radeon_blit_t *blit ) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + drm_device_dma_t *dma = dev->dma; + drm_buf_t *buf; + drm_radeon_buf_priv_t *buf_priv; + u32 format; + u32 *data; + int dword_shift, dwords; + RING_LOCALS; + DRM_DEBUG( "blit: ofs=0x%x p=%d f=%d x=%hd y=%hd w=%hd h=%hd\n", + blit->offset >> 10, blit->pitch, blit->format, + blit->x, blit->y, blit->width, blit->height ); + + radeon_update_ring_snapshot( dev_priv ); + + /* The compiler won't optimize away a division by a variable, + * even if the only legal values are powers of two. Thus, we'll + * use a shift instead. + */ + switch ( blit->format ) { + case RADEON_TXF_32BPP_ARGB8888: + case RADEON_TXF_32BPP_RGBA8888: + format = RADEON_COLOR_FORMAT_ARGB8888; + dword_shift = 0; + break; + case RADEON_TXF_16BPP_AI88: + case RADEON_TXF_16BPP_ARGB1555: + case RADEON_TXF_16BPP_RGB565: + case RADEON_TXF_16BPP_ARGB4444: + format = RADEON_COLOR_FORMAT_RGB565; + dword_shift = 1; + break; + case RADEON_TXF_8BPP_I: + case RADEON_TXF_8BPP_RGB332: + format = RADEON_COLOR_FORMAT_CI8; + dword_shift = 2; + break; + default: + DRM_ERROR( "invalid blit format %d\n", blit->format ); + return -EINVAL; + } + + /* Flush the pixel cache. This ensures no pixel data gets mixed + * up with the texture data from the host data blit, otherwise + * part of the texture image may be corrupted. + */ + BEGIN_RING( 4 ); + + RADEON_FLUSH_CACHE(); + RADEON_WAIT_UNTIL_IDLE(); + + ADVANCE_RING(); + + /* Dispatch the indirect buffer. + */ + buf = dma->buflist[blit->idx]; + buf_priv = buf->dev_private; + + if ( buf->pid != current->pid ) { + DRM_ERROR( "process %d using buffer owned by %d\n", + current->pid, buf->pid ); + return -EINVAL; + } + if ( buf->pending ) { + DRM_ERROR( "sending pending buffer %d\n", blit->idx ); + return -EINVAL; + } + + buf_priv->discard = 1; + + dwords = (blit->width * blit->height) >> dword_shift; + if ( !dwords ) dwords = 1; + + data = (u32 *)((char *)dev_priv->buffers->handle + buf->offset); + + data[0] = CP_PACKET3( RADEON_CNTL_HOSTDATA_BLT, dwords + 6 ); + data[1] = (RADEON_GMC_DST_PITCH_OFFSET_CNTL | + RADEON_GMC_BRUSH_NONE | + (format << 8) | + RADEON_GMC_SRC_DATATYPE_COLOR | + RADEON_ROP3_S | + RADEON_DP_SRC_SOURCE_HOST_DATA | + RADEON_GMC_CLR_CMP_CNTL_DIS | + RADEON_GMC_WR_MSK_DIS); + + data[2] = (blit->pitch << 22) | (blit->offset >> 10); + data[3] = 0xffffffff; + data[4] = 0xffffffff; + data[5] = (blit->y << 16) | blit->x; + data[6] = (blit->height << 16) | blit->width; + data[7] = dwords; + + buf->used = (dwords + 8) * sizeof(u32); + + radeon_cp_dispatch_indirect( dev, buf, 0, buf->used ); + + /* Flush the pixel cache after the blit completes. This ensures + * the texture data is written out to memory before rendering + * continues. + */ + BEGIN_RING( 4 ); + + RADEON_FLUSH_CACHE(); + RADEON_WAIT_UNTIL_2D_IDLE(); + + ADVANCE_RING(); + + return 0; +} + +static void radeon_cp_dispatch_stipple( drm_device_t *dev, u32 *stipple ) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + int i; + RING_LOCALS; + DRM_DEBUG( "%s\n", __FUNCTION__ ); + + radeon_update_ring_snapshot( dev_priv ); + + BEGIN_RING( 35 ); + + OUT_RING( CP_PACKET0( RADEON_RE_STIPPLE_ADDR, 0 ) ); + OUT_RING( 0x00000000 ); + + OUT_RING( CP_PACKET0_TABLE( RADEON_RE_STIPPLE_DATA, 31 ) ); + for ( i = 0 ; i < 32 ; i++ ) { + OUT_RING( stipple[i] ); + } + + ADVANCE_RING(); +} + + +/* ================================================================ + * IOCTL functions + */ + +int radeon_cp_clear( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_radeon_private_t *dev_priv = dev->dev_private; + drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_radeon_clear_t clear; + DRM_DEBUG( "%s\n", __FUNCTION__ ); + + if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || + dev->lock.pid != current->pid ) { + DRM_ERROR( "%s called without lock held\n", __FUNCTION__ ); + return -EINVAL; + } + + if ( copy_from_user( &clear, (drm_radeon_clear_t *) arg, + sizeof(clear) ) ) + return -EFAULT; + + if ( sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS ) + sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS; + + radeon_cp_dispatch_clear( dev, &clear ); + + return 0; +} + +int radeon_cp_swap( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_radeon_private_t *dev_priv = dev->dev_private; + drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; + DRM_DEBUG( "%s\n", __FUNCTION__ ); + + if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || + dev->lock.pid != current->pid ) { + DRM_ERROR( "%s called without lock held\n", __FUNCTION__ ); + return -EINVAL; + } + + if ( sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS ) + sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS; + + if ( !dev_priv->page_flipping ) { + radeon_cp_dispatch_swap( dev ); + dev_priv->sarea_priv->dirty |= (RADEON_UPLOAD_CONTEXT | + RADEON_UPLOAD_MASKS); + } else { + radeon_cp_dispatch_flip( dev ); + } + + return 0; +} + +int radeon_cp_vertex( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_radeon_private_t *dev_priv = dev->dev_private; + drm_device_dma_t *dma = dev->dma; + drm_buf_t *buf; + drm_radeon_buf_priv_t *buf_priv; + drm_radeon_vertex_t vertex; + + if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || + dev->lock.pid != current->pid ) { + DRM_ERROR( "%s called without lock held\n", __FUNCTION__ ); + return -EINVAL; + } + if ( !dev_priv || dev_priv->is_pci ) { + DRM_ERROR( "%s called with a PCI card\n", __FUNCTION__ ); + return -EINVAL; + } + + if ( copy_from_user( &vertex, (drm_radeon_vertex_t *)arg, + sizeof(vertex) ) ) + return -EFAULT; + + DRM_DEBUG( "%s: pid=%d index=%d count=%d discard=%d\n", + __FUNCTION__, current->pid, + vertex.idx, vertex.count, vertex.discard ); + + if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) { + DRM_ERROR( "buffer index %d (of %d max)\n", + vertex.idx, dma->buf_count - 1 ); + return -EINVAL; + } + if ( vertex.prim < 0 || + vertex.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST ) { + DRM_ERROR( "buffer prim %d\n", vertex.prim ); + return -EINVAL; + } + + VB_AGE_CHECK_WITH_RET( dev_priv ); + + buf = dma->buflist[vertex.idx]; + buf_priv = buf->dev_private; + + if ( buf->pid != current->pid ) { + DRM_ERROR( "process %d using buffer owned by %d\n", + current->pid, buf->pid ); + return -EINVAL; + } + if ( buf->pending ) { + DRM_ERROR( "sending pending buffer %d\n", vertex.idx ); + return -EINVAL; + } + + buf->used = vertex.count; + buf_priv->prim = vertex.prim; + buf_priv->discard = vertex.discard; + + radeon_cp_dispatch_vertex( dev, buf ); + + return 0; +} + +int radeon_cp_indices( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_radeon_private_t *dev_priv = dev->dev_private; + drm_device_dma_t *dma = dev->dma; + drm_buf_t *buf; + drm_radeon_buf_priv_t *buf_priv; + drm_radeon_indices_t elts; + int count; + + if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || + dev->lock.pid != current->pid ) { + DRM_ERROR( "%s called without lock held\n", __FUNCTION__ ); + return -EINVAL; + } + if ( !dev_priv || dev_priv->is_pci ) { + DRM_ERROR( "%s called with a PCI card\n", __FUNCTION__ ); + return -EINVAL; + } + + if ( copy_from_user( &elts, (drm_radeon_indices_t *)arg, + sizeof(elts) ) ) + return -EFAULT; + + DRM_DEBUG( "%s: pid=%d index=%d start=%d end=%d discard=%d\n", + __FUNCTION__, current->pid, + elts.idx, elts.start, elts.end, elts.discard ); + + if ( elts.idx < 0 || elts.idx >= dma->buf_count ) { + DRM_ERROR( "buffer index %d (of %d max)\n", + elts.idx, dma->buf_count - 1 ); + return -EINVAL; + } + if ( elts.prim < 0 || + elts.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST ) { + DRM_ERROR( "buffer prim %d\n", elts.prim ); + return -EINVAL; + } + + VB_AGE_CHECK_WITH_RET( dev_priv ); + + buf = dma->buflist[elts.idx]; + buf_priv = buf->dev_private; + + if ( buf->pid != current->pid ) { + DRM_ERROR( "process %d using buffer owned by %d\n", + current->pid, buf->pid ); + return -EINVAL; + } + if ( buf->pending ) { + DRM_ERROR( "sending pending buffer %d\n", elts.idx ); + return -EINVAL; + } + + count = (elts.end - elts.start) / sizeof(u16); + elts.start -= RADEON_INDEX_PRIM_OFFSET; + + if ( elts.start & 0x7 ) { + DRM_ERROR( "misaligned buffer 0x%x\n", elts.start ); + return -EINVAL; + } + if ( elts.start < buf->used ) { + DRM_ERROR( "no header 0x%x - 0x%x\n", elts.start, buf->used ); + return -EINVAL; + } + + buf->used = elts.end; + buf_priv->prim = elts.prim; + buf_priv->discard = elts.discard; + + radeon_cp_dispatch_indices( dev, buf, elts.start, elts.end, count ); + + return 0; +} + +int radeon_cp_blit( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_radeon_private_t *dev_priv = dev->dev_private; + drm_device_dma_t *dma = dev->dma; + drm_radeon_blit_t blit; + + if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || + dev->lock.pid != current->pid ) { + DRM_ERROR( "%s called without lock held\n", __FUNCTION__ ); + return -EINVAL; + } + + if ( copy_from_user( &blit, (drm_radeon_blit_t *)arg, + sizeof(blit) ) ) + return -EFAULT; + + DRM_DEBUG( "%s: pid=%d index=%d\n", + __FUNCTION__, current->pid, blit.idx ); + + if ( blit.idx < 0 || blit.idx > dma->buf_count ) { + DRM_ERROR( "sending %d buffers (of %d max)\n", + blit.idx, dma->buf_count ); + return -EINVAL; + } + + VB_AGE_CHECK_WITH_RET( dev_priv ); + + return radeon_cp_dispatch_blit( dev, &blit ); +} + +int radeon_cp_stipple( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_radeon_stipple_t stipple; + u32 mask[32]; + + if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || + dev->lock.pid != current->pid ) { + DRM_ERROR( "%s called without lock held\n", __FUNCTION__ ); + return -EINVAL; + } + + if ( copy_from_user( &stipple, (drm_radeon_stipple_t *)arg, + sizeof(stipple) ) ) + return -EFAULT; + + if ( copy_from_user( &mask, stipple.mask, + 32 * sizeof(u32) ) ) + return -EFAULT; + + radeon_cp_dispatch_stipple( dev, mask ); + + return 0; +} + +int radeon_cp_indirect( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_radeon_private_t *dev_priv = dev->dev_private; + drm_device_dma_t *dma = dev->dma; + drm_buf_t *buf; + drm_radeon_buf_priv_t *buf_priv; + drm_radeon_indirect_t indirect; + RING_LOCALS; + + if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || + dev->lock.pid != current->pid ) { + DRM_ERROR( "%s called without lock held\n", __FUNCTION__ ); + return -EINVAL; + } + if ( !dev_priv || dev_priv->is_pci ) { + DRM_ERROR( "%s called with a PCI card\n", __FUNCTION__ ); + return -EINVAL; + } + + if ( copy_from_user( &indirect, (drm_radeon_indirect_t *)arg, + sizeof(indirect) ) ) + return -EFAULT; + + DRM_DEBUG( "indirect: idx=%d s=%d e=%d d=%d\n", + indirect.idx, indirect.start, + indirect.end, indirect.discard ); + + if ( indirect.idx < 0 || indirect.idx >= dma->buf_count ) { + DRM_ERROR( "buffer index %d (of %d max)\n", + indirect.idx, dma->buf_count - 1 ); + return -EINVAL; + } + + buf = dma->buflist[indirect.idx]; + buf_priv = buf->dev_private; + + if ( buf->pid != current->pid ) { + DRM_ERROR( "process %d using buffer owned by %d\n", + current->pid, buf->pid ); + return -EINVAL; + } + if ( buf->pending ) { + DRM_ERROR( "sending pending buffer %d\n", indirect.idx ); + return -EINVAL; + } + + if ( indirect.start < buf->used ) { + DRM_ERROR( "reusing indirect: start=0x%x actual=0x%x\n", + indirect.start, buf->used ); + return -EINVAL; + } + + VB_AGE_CHECK_WITH_RET( dev_priv ); + + buf->used = indirect.end; + buf_priv->discard = indirect.discard; + + /* Wait for the 3D stream to idle before the indirect buffer + * containing 2D acceleration commands is processed. + */ + BEGIN_RING( 2 ); + + RADEON_WAIT_UNTIL_3D_IDLE(); + + ADVANCE_RING(); + + /* Dispatch the indirect buffer full of commands from the + * X server. This is insecure and is thus only available to + * privileged clients. + */ + radeon_cp_dispatch_indirect( dev, buf, indirect.start, indirect.end ); + + return 0; +} diff -urN linux-2.4.10/drivers/char/drm-4.0/tdfx_context.c linux-2.4.10-lia/drivers/char/drm-4.0/tdfx_context.c --- linux-2.4.10/drivers/char/drm-4.0/tdfx_context.c Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/tdfx_context.c Wed Aug 15 20:52:12 2001 @@ -0,0 +1,219 @@ +/* tdfx_context.c -- IOCTLs for tdfx contexts -*- linux-c -*- + * Created: Thu Oct 7 10:50:22 1999 by faith@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rickard E. (Rik) Faith + * Daryll Strauss + * + */ + +#define __NO_VERSION__ +#include "drmP.h" +#include "tdfx_drv.h" + +extern drm_ctx_t tdfx_res_ctx; + +static int tdfx_alloc_queue(drm_device_t *dev) +{ + return drm_ctxbitmap_next(dev); +} + +int tdfx_context_switch(drm_device_t *dev, int old, int new) +{ + char buf[64]; + + atomic_inc(&dev->total_ctx); + + if (test_and_set_bit(0, &dev->context_flag)) { + DRM_ERROR("Reentering -- FIXME\n"); + return -EBUSY; + } + +#if DRM_DMA_HISTOGRAM + dev->ctx_start = get_cycles(); +#endif + + DRM_DEBUG("Context switch from %d to %d\n", old, new); + + if (new == dev->last_context) { + clear_bit(0, &dev->context_flag); + return 0; + } + + if (drm_flags & DRM_FLAG_NOCTX) { + tdfx_context_switch_complete(dev, new); + } else { + sprintf(buf, "C %d %d\n", old, new); + drm_write_string(dev, buf); + } + + return 0; +} + +int tdfx_context_switch_complete(drm_device_t *dev, int new) +{ + dev->last_context = new; /* PRE/POST: This is the _only_ writer. */ + dev->last_switch = jiffies; + + if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { + DRM_ERROR("Lock isn't held after context switch\n"); + } + + /* If a context switch is ever initiated + when the kernel holds the lock, release + that lock here. */ +#if DRM_DMA_HISTOGRAM + atomic_inc(&dev->histo.ctx[drm_histogram_slot(get_cycles() + - dev->ctx_start)]); + +#endif + clear_bit(0, &dev->context_flag); + wake_up(&dev->context_wait); + + return 0; +} + + +int tdfx_resctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_ctx_res_t res; + drm_ctx_t ctx; + int i; + + DRM_DEBUG("%d\n", DRM_RESERVED_CONTEXTS); + if (copy_from_user(&res, (drm_ctx_res_t *)arg, sizeof(res))) + return -EFAULT; + if (res.count >= DRM_RESERVED_CONTEXTS) { + memset(&ctx, 0, sizeof(ctx)); + for (i = 0; i < DRM_RESERVED_CONTEXTS; i++) { + ctx.handle = i; + if (copy_to_user(&res.contexts[i], + &i, + sizeof(i))) + return -EFAULT; + } + } + res.count = DRM_RESERVED_CONTEXTS; + if (copy_to_user((drm_ctx_res_t *)arg, &res, sizeof(res))) + return -EFAULT; + return 0; +} + + +int tdfx_addctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ctx_t ctx; + + if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx))) + return -EFAULT; + if ((ctx.handle = tdfx_alloc_queue(dev)) == DRM_KERNEL_CONTEXT) { + /* Skip kernel's context and get a new one. */ + ctx.handle = tdfx_alloc_queue(dev); + } + DRM_DEBUG("%d\n", ctx.handle); + if (ctx.handle == -1) { + DRM_DEBUG("Not enough free contexts.\n"); + /* Should this return -EBUSY instead? */ + return -ENOMEM; + } + + if (copy_to_user((drm_ctx_t *)arg, &ctx, sizeof(ctx))) + return -EFAULT; + return 0; +} + +int tdfx_modctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_ctx_t ctx; + + if (copy_from_user(&ctx, (drm_ctx_t*)arg, sizeof(ctx))) + return -EFAULT; + if (ctx.flags==_DRM_CONTEXT_PRESERVED) + tdfx_res_ctx.handle=ctx.handle; + return 0; +} + +int tdfx_getctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_ctx_t ctx; + + if (copy_from_user(&ctx, (drm_ctx_t*)arg, sizeof(ctx))) + return -EFAULT; + /* This is 0, because we don't handle any context flags */ + ctx.flags = 0; + if (copy_to_user((drm_ctx_t*)arg, &ctx, sizeof(ctx))) + return -EFAULT; + return 0; +} + +int tdfx_switchctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ctx_t ctx; + + if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx))) + return -EFAULT; + DRM_DEBUG("%d\n", ctx.handle); + return tdfx_context_switch(dev, dev->last_context, ctx.handle); +} + +int tdfx_newctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ctx_t ctx; + + if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx))) + return -EFAULT; + DRM_DEBUG("%d\n", ctx.handle); + tdfx_context_switch_complete(dev, ctx.handle); + + return 0; +} + +int tdfx_rmctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ctx_t ctx; + + if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx))) + return -EFAULT; + DRM_DEBUG("%d\n", ctx.handle); + drm_ctxbitmap_free(dev, ctx.handle); + + return 0; +} diff -urN linux-2.4.10/drivers/char/drm-4.0/tdfx_drv.c linux-2.4.10-lia/drivers/char/drm-4.0/tdfx_drv.c --- linux-2.4.10/drivers/char/drm-4.0/tdfx_drv.c Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/tdfx_drv.c Mon Aug 20 18:09:34 2001 @@ -0,0 +1,696 @@ +/* tdfx_drv.c -- tdfx driver -*- linux-c -*- + * Created: Thu Oct 7 10:38:32 1999 by faith@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rickard E. (Rik) Faith + * Daryll Strauss + * + */ + +#include +#include "drmP.h" +#include "tdfx_drv.h" + +#define TDFX_NAME "tdfx" +#define TDFX_DESC "3dfx Banshee/Voodoo3+" +#define TDFX_DATE "20000928" +#define TDFX_MAJOR 1 +#define TDFX_MINOR 0 +#define TDFX_PATCHLEVEL 0 + +static drm_device_t tdfx_device; +drm_ctx_t tdfx_res_ctx; + +static struct file_operations tdfx_fops = { +#if LINUX_VERSION_CODE >= 0x020400 + /* This started being used during 2.4.0-test */ + owner: THIS_MODULE, +#endif + open: tdfx_open, + flush: drm_flush, + release: tdfx_release, + ioctl: tdfx_ioctl, + mmap: drm_mmap, + read: drm_read, + fasync: drm_fasync, + poll: drm_poll, +}; + +static struct miscdevice tdfx_misc = { + minor: MISC_DYNAMIC_MINOR, + name: TDFX_NAME, + fops: &tdfx_fops, +}; + +static drm_ioctl_desc_t tdfx_ioctls[] = { + [DRM_IOCTL_NR(DRM_IOCTL_VERSION)] = { tdfx_version, 0, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_GET_UNIQUE)] = { drm_getunique, 0, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_GET_MAGIC)] = { drm_getmagic, 0, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_IRQ_BUSID)] = { drm_irq_busid, 0, 1 }, + + [DRM_IOCTL_NR(DRM_IOCTL_SET_UNIQUE)] = { drm_setunique, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_BLOCK)] = { drm_block, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_UNBLOCK)] = { drm_unblock, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_AUTH_MAGIC)] = { drm_authmagic, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_ADD_MAP)] = { drm_addmap, 1, 1 }, + + [DRM_IOCTL_NR(DRM_IOCTL_ADD_CTX)] = { tdfx_addctx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_RM_CTX)] = { tdfx_rmctx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_MOD_CTX)] = { tdfx_modctx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_GET_CTX)] = { tdfx_getctx, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_SWITCH_CTX)] = { tdfx_switchctx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_NEW_CTX)] = { tdfx_newctx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_RES_CTX)] = { tdfx_resctx, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_ADD_DRAW)] = { drm_adddraw, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_RM_DRAW)] = { drm_rmdraw, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_LOCK)] = { tdfx_lock, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_UNLOCK)] = { tdfx_unlock, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_FINISH)] = { drm_finish, 1, 0 }, +#if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE) + [DRM_IOCTL_NR(DRM_IOCTL_AGP_ACQUIRE)] = {drm_agp_acquire, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_RELEASE)] = {drm_agp_release, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_ENABLE)] = {drm_agp_enable, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_INFO)] = {drm_agp_info, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_ALLOC)] = {drm_agp_alloc, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_FREE)] = {drm_agp_free, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_BIND)] = {drm_agp_unbind, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_UNBIND)] = {drm_agp_bind, 1, 1}, +#endif +}; +#define TDFX_IOCTL_COUNT DRM_ARRAY_SIZE(tdfx_ioctls) + +#ifdef MODULE +static char *tdfx = NULL; +#endif + +MODULE_AUTHOR("VA Linux Systems, Inc."); +MODULE_DESCRIPTION("tdfx"); +MODULE_PARM(tdfx, "s"); + +#ifndef MODULE +/* tdfx_options is called by the kernel to parse command-line options + * passed via the boot-loader (e.g., LILO). It calls the insmod option + * routine, drm_parse_drm. + */ + +static int __init tdfx_options(char *str) +{ + drm_parse_options(str); + return 1; +} + +__setup("tdfx=", tdfx_options); +#endif + +static int tdfx_setup(drm_device_t *dev) +{ + int i; + + atomic_set(&dev->ioctl_count, 0); + atomic_set(&dev->vma_count, 0); + dev->buf_use = 0; + atomic_set(&dev->buf_alloc, 0); + + atomic_set(&dev->total_open, 0); + atomic_set(&dev->total_close, 0); + atomic_set(&dev->total_ioctl, 0); + atomic_set(&dev->total_irq, 0); + atomic_set(&dev->total_ctx, 0); + atomic_set(&dev->total_locks, 0); + atomic_set(&dev->total_unlocks, 0); + atomic_set(&dev->total_contends, 0); + atomic_set(&dev->total_sleeps, 0); + + for (i = 0; i < DRM_HASH_SIZE; i++) { + dev->magiclist[i].head = NULL; + dev->magiclist[i].tail = NULL; + } + dev->maplist = NULL; + dev->map_count = 0; + dev->vmalist = NULL; + dev->lock.hw_lock = NULL; + init_waitqueue_head(&dev->lock.lock_queue); + dev->queue_count = 0; + dev->queue_reserved = 0; + dev->queue_slots = 0; + dev->queuelist = NULL; + dev->irq = 0; + dev->context_flag = 0; + dev->interrupt_flag = 0; + dev->dma = 0; + dev->dma_flag = 0; + dev->last_context = 0; + dev->last_switch = 0; + dev->last_checked = 0; + init_timer(&dev->timer); + init_waitqueue_head(&dev->context_wait); + + dev->ctx_start = 0; + dev->lck_start = 0; + + dev->buf_rp = dev->buf; + dev->buf_wp = dev->buf; + dev->buf_end = dev->buf + DRM_BSZ; + dev->buf_async = NULL; + init_waitqueue_head(&dev->buf_readers); + init_waitqueue_head(&dev->buf_writers); + + tdfx_res_ctx.handle=-1; + + DRM_DEBUG("\n"); + + /* The kernel's context could be created here, but is now created + in drm_dma_enqueue. This is more resource-efficient for + hardware that does not do DMA, but may mean that + drm_select_queue fails between the time the interrupt is + initialized and the time the queues are initialized. */ + + return 0; +} + + +static int tdfx_takedown(drm_device_t *dev) +{ + int i; + drm_magic_entry_t *pt, *next; + drm_map_t *map; + drm_vma_entry_t *vma, *vma_next; + + DRM_DEBUG("\n"); + + down(&dev->struct_sem); + del_timer(&dev->timer); + + if (dev->devname) { + drm_free(dev->devname, strlen(dev->devname)+1, DRM_MEM_DRIVER); + dev->devname = NULL; + } + + if (dev->unique) { + drm_free(dev->unique, strlen(dev->unique)+1, DRM_MEM_DRIVER); + dev->unique = NULL; + dev->unique_len = 0; + } + /* Clear pid list */ + for (i = 0; i < DRM_HASH_SIZE; i++) { + for (pt = dev->magiclist[i].head; pt; pt = next) { + next = pt->next; + drm_free(pt, sizeof(*pt), DRM_MEM_MAGIC); + } + dev->magiclist[i].head = dev->magiclist[i].tail = NULL; + } +#if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE) + /* Clear AGP information */ + if (dev->agp) { + drm_agp_mem_t *temp; + drm_agp_mem_t *temp_next; + + temp = dev->agp->memory; + while(temp != NULL) { + temp_next = temp->next; + drm_free_agp(temp->memory, temp->pages); + drm_free(temp, sizeof(*temp), DRM_MEM_AGPLISTS); + temp = temp_next; + } + if (dev->agp->acquired) _drm_agp_release(); + } +#endif + /* Clear vma list (only built for debugging) */ + if (dev->vmalist) { + for (vma = dev->vmalist; vma; vma = vma_next) { + vma_next = vma->next; + drm_free(vma, sizeof(*vma), DRM_MEM_VMAS); + } + dev->vmalist = NULL; + } + + /* Clear map area and mtrr information */ + if (dev->maplist) { + for (i = 0; i < dev->map_count; i++) { + map = dev->maplist[i]; + switch (map->type) { + case _DRM_REGISTERS: + case _DRM_FRAME_BUFFER: +#ifdef CONFIG_MTRR + if (map->mtrr >= 0) { + int retcode; + retcode = mtrr_del(map->mtrr, + map->offset, + map->size); + DRM_DEBUG("mtrr_del = %d\n", retcode); + } +#endif + drm_ioremapfree(map->handle, map->size, dev); + break; + case _DRM_SHM: + drm_free_pages((unsigned long)map->handle, + drm_order(map->size) + - PAGE_SHIFT, + DRM_MEM_SAREA); + break; + case _DRM_AGP: + /* Do nothing here, because this is all + handled in the AGP/GART driver. */ + break; + } + drm_free(map, sizeof(*map), DRM_MEM_MAPS); + } + drm_free(dev->maplist, + dev->map_count * sizeof(*dev->maplist), + DRM_MEM_MAPS); + dev->maplist = NULL; + dev->map_count = 0; + } + + if (dev->lock.hw_lock) { + dev->lock.hw_lock = NULL; /* SHM removed */ + dev->lock.pid = 0; + wake_up_interruptible(&dev->lock.lock_queue); + } + up(&dev->struct_sem); + + return 0; +} + +/* tdfx_init is called via init_module at module load time, or via + * linux/init/main.c (this is not currently supported). */ + +static int __init tdfx_init(void) +{ + int retcode; + drm_device_t *dev = &tdfx_device; + + DRM_DEBUG("\n"); + + memset((void *)dev, 0, sizeof(*dev)); + dev->count_lock = SPIN_LOCK_UNLOCKED; + sema_init(&dev->struct_sem, 1); + +#ifdef MODULE + drm_parse_options(tdfx); +#endif + + if ((retcode = misc_register(&tdfx_misc))) { + DRM_ERROR("Cannot register \"%s\"\n", TDFX_NAME); + return retcode; + } + dev->device = MKDEV(MISC_MAJOR, tdfx_misc.minor); + dev->name = TDFX_NAME; + + drm_mem_init(); + drm_proc_init(dev); +#if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE) + dev->agp = drm_agp_init(); +#endif + if((retcode = drm_ctxbitmap_init(dev))) { + DRM_ERROR("Cannot allocate memory for context bitmap.\n"); + drm_proc_cleanup(); + misc_deregister(&tdfx_misc); + tdfx_takedown(dev); + return retcode; + } + + DRM_INFO("Initialized %s %d.%d.%d %s on minor %d\n", + TDFX_NAME, + TDFX_MAJOR, + TDFX_MINOR, + TDFX_PATCHLEVEL, + TDFX_DATE, + tdfx_misc.minor); + + return 0; +} + +/* tdfx_cleanup is called via cleanup_module at module unload time. */ + +static void __exit tdfx_cleanup(void) +{ + drm_device_t *dev = &tdfx_device; + + DRM_DEBUG("\n"); + + drm_proc_cleanup(); + if (misc_deregister(&tdfx_misc)) { + DRM_ERROR("Cannot unload module\n"); + } else { + DRM_INFO("Module unloaded\n"); + } + drm_ctxbitmap_cleanup(dev); + tdfx_takedown(dev); +#if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE) + if (dev->agp) { + drm_agp_uninit(); + drm_free(dev->agp, sizeof(*dev->agp), DRM_MEM_AGPLISTS); + dev->agp = NULL; + } +#endif +} + +module_init(tdfx_init); +module_exit(tdfx_cleanup); + + +int tdfx_version(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_version_t version; + int len; + + if (copy_from_user(&version, + (drm_version_t *)arg, + sizeof(version))) + return -EFAULT; + +#define DRM_COPY(name,value) \ + len = strlen(value); \ + if (len > name##_len) len = name##_len; \ + name##_len = strlen(value); \ + if (len && name) { \ + if (copy_to_user(name, value, len)) \ + return -EFAULT; \ + } + + version.version_major = TDFX_MAJOR; + version.version_minor = TDFX_MINOR; + version.version_patchlevel = TDFX_PATCHLEVEL; + + DRM_COPY(version.name, TDFX_NAME); + DRM_COPY(version.date, TDFX_DATE); + DRM_COPY(version.desc, TDFX_DESC); + + if (copy_to_user((drm_version_t *)arg, + &version, + sizeof(version))) + return -EFAULT; + return 0; +} + +int tdfx_open(struct inode *inode, struct file *filp) +{ + drm_device_t *dev = &tdfx_device; + int retcode = 0; + + DRM_DEBUG("open_count = %d\n", dev->open_count); + if (!(retcode = drm_open_helper(inode, filp, dev))) { +#if LINUX_VERSION_CODE < 0x020333 + MOD_INC_USE_COUNT; /* Needed before Linux 2.3.51 */ +#endif + atomic_inc(&dev->total_open); + spin_lock(&dev->count_lock); + if (!dev->open_count++) { + spin_unlock(&dev->count_lock); + return tdfx_setup(dev); + } + spin_unlock(&dev->count_lock); + } + return retcode; +} + +int tdfx_release(struct inode *inode, struct file *filp) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev; + int retcode = 0; + + lock_kernel(); + dev = priv->dev; + + DRM_DEBUG("open_count = %d\n", dev->open_count); + if (!(retcode = drm_release(inode, filp))) { +#if LINUX_VERSION_CODE < 0x020333 + MOD_DEC_USE_COUNT; /* Needed before Linux 2.3.51 */ +#endif + atomic_inc(&dev->total_close); + spin_lock(&dev->count_lock); + if (!--dev->open_count) { + if (atomic_read(&dev->ioctl_count) || dev->blocked) { + DRM_ERROR("Device busy: %d %d\n", + atomic_read(&dev->ioctl_count), + dev->blocked); + spin_unlock(&dev->count_lock); + unlock_kernel(); + return -EBUSY; + } + spin_unlock(&dev->count_lock); + unlock_kernel(); + return tdfx_takedown(dev); + } + spin_unlock(&dev->count_lock); + } + + unlock_kernel(); + return retcode; +} + +/* tdfx_ioctl is called whenever a process performs an ioctl on /dev/drm. */ + +int tdfx_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + int nr = DRM_IOCTL_NR(cmd); + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + int retcode = 0; + drm_ioctl_desc_t *ioctl; + drm_ioctl_t *func; + + atomic_inc(&dev->ioctl_count); + atomic_inc(&dev->total_ioctl); + ++priv->ioctl_count; + + DRM_DEBUG("pid = %d, cmd = 0x%02x, nr = 0x%02x, dev 0x%x, auth = %d\n", + current->pid, cmd, nr, dev->device, priv->authenticated); + + if (nr >= TDFX_IOCTL_COUNT) { + retcode = -EINVAL; + } else { + ioctl = &tdfx_ioctls[nr]; + func = ioctl->func; + + if (!func) { + DRM_DEBUG("no function\n"); + retcode = -EINVAL; + } else if ((ioctl->root_only && !capable(CAP_SYS_ADMIN)) + || (ioctl->auth_needed && !priv->authenticated)) { + retcode = -EACCES; + } else { + retcode = (func)(inode, filp, cmd, arg); + } + } + + atomic_dec(&dev->ioctl_count); + return retcode; +} + +int tdfx_lock(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + DECLARE_WAITQUEUE(entry, current); + int ret = 0; + drm_lock_t lock; +#if DRM_DMA_HISTOGRAM + cycles_t start; + + dev->lck_start = start = get_cycles(); +#endif + + if (copy_from_user(&lock, (drm_lock_t *)arg, sizeof(lock))) + return -EFAULT; + + if (lock.context == DRM_KERNEL_CONTEXT) { + DRM_ERROR("Process %d using kernel context %d\n", + current->pid, lock.context); + return -EINVAL; + } + + DRM_DEBUG("%d (pid %d) requests lock (0x%08x), flags = 0x%08x\n", + lock.context, current->pid, dev->lock.hw_lock->lock, + lock.flags); + +#if 0 + /* dev->queue_count == 0 right now for + tdfx. FIXME? */ + if (lock.context < 0 || lock.context >= dev->queue_count) + return -EINVAL; +#endif + + if (!ret) { +#if 0 + if (_DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock) + != lock.context) { + long j = jiffies - dev->lock.lock_time; + + if (lock.context == tdfx_res_ctx.handle && + j >= 0 && j < DRM_LOCK_SLICE) { + /* Can't take lock if we just had it and + there is contention. */ + DRM_DEBUG("%d (pid %d) delayed j=%d dev=%d jiffies=%d\n", + lock.context, current->pid, j, + dev->lock.lock_time, jiffies); + current->state = TASK_INTERRUPTIBLE; + current->policy |= SCHED_YIELD; + schedule_timeout(DRM_LOCK_SLICE-j); + DRM_DEBUG("jiffies=%d\n", jiffies); + } + } +#endif + add_wait_queue(&dev->lock.lock_queue, &entry); + for (;;) { + current->state = TASK_INTERRUPTIBLE; + if (!dev->lock.hw_lock) { + /* Device has been unregistered */ + ret = -EINTR; + break; + } + if (drm_lock_take(&dev->lock.hw_lock->lock, + lock.context)) { + dev->lock.pid = current->pid; + dev->lock.lock_time = jiffies; + atomic_inc(&dev->total_locks); + break; /* Got lock */ + } + + /* Contention */ + atomic_inc(&dev->total_sleeps); +#if 1 + current->policy |= SCHED_YIELD; +#endif + schedule(); + if (signal_pending(current)) { + ret = -ERESTARTSYS; + break; + } + } + current->state = TASK_RUNNING; + remove_wait_queue(&dev->lock.lock_queue, &entry); + } + +#if 0 + if (!ret && dev->last_context != lock.context && + lock.context != tdfx_res_ctx.handle && + dev->last_context != tdfx_res_ctx.handle) { + add_wait_queue(&dev->context_wait, &entry); + current->state = TASK_INTERRUPTIBLE; + /* PRE: dev->last_context != lock.context */ + tdfx_context_switch(dev, dev->last_context, lock.context); + /* POST: we will wait for the context + switch and will dispatch on a later call + when dev->last_context == lock.context + NOTE WE HOLD THE LOCK THROUGHOUT THIS + TIME! */ + current->policy |= SCHED_YIELD; + schedule(); + current->state = TASK_RUNNING; + remove_wait_queue(&dev->context_wait, &entry); + if (signal_pending(current)) { + ret = -EINTR; + } else if (dev->last_context != lock.context) { + DRM_ERROR("Context mismatch: %d %d\n", + dev->last_context, lock.context); + } + } +#endif + + if (!ret) { + sigemptyset(&dev->sigmask); + sigaddset(&dev->sigmask, SIGSTOP); + sigaddset(&dev->sigmask, SIGTSTP); + sigaddset(&dev->sigmask, SIGTTIN); + sigaddset(&dev->sigmask, SIGTTOU); + dev->sigdata.context = lock.context; + dev->sigdata.lock = dev->lock.hw_lock; + block_all_signals(drm_notifier, &dev->sigdata, &dev->sigmask); + + if (lock.flags & _DRM_LOCK_READY) { + /* Wait for space in DMA/FIFO */ + } + if (lock.flags & _DRM_LOCK_QUIESCENT) { + /* Make hardware quiescent */ +#if 0 + tdfx_quiescent(dev); +#endif + } + } + +#if LINUX_VERSION_CODE < 0x020400 + if (lock.context != tdfx_res_ctx.handle) { + current->counter = 5; + current->priority = DEF_PRIORITY/4; + } +#endif + DRM_DEBUG("%d %s\n", lock.context, ret ? "interrupted" : "has lock"); + +#if DRM_DMA_HISTOGRAM + atomic_inc(&dev->histo.lacq[drm_histogram_slot(get_cycles() - start)]); +#endif + + return ret; +} + + +int tdfx_unlock(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_lock_t lock; + + if (copy_from_user(&lock, (drm_lock_t *)arg, sizeof(lock))) + return -EFAULT; + + if (lock.context == DRM_KERNEL_CONTEXT) { + DRM_ERROR("Process %d using kernel context %d\n", + current->pid, lock.context); + return -EINVAL; + } + + DRM_DEBUG("%d frees lock (%d holds)\n", + lock.context, + _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock)); + atomic_inc(&dev->total_unlocks); + if (_DRM_LOCK_IS_CONT(dev->lock.hw_lock->lock)) + atomic_inc(&dev->total_contends); + drm_lock_transfer(dev, &dev->lock.hw_lock->lock, DRM_KERNEL_CONTEXT); + /* FIXME: Try to send data to card here */ + if (!dev->context_flag) { + if (drm_lock_free(dev, &dev->lock.hw_lock->lock, + DRM_KERNEL_CONTEXT)) { + DRM_ERROR("\n"); + } + } + +#if LINUX_VERSION_CODE < 0x020400 + if (lock.context != tdfx_res_ctx.handle) { + current->counter = 5; + current->priority = DEF_PRIORITY; + } +#endif + + unblock_all_signals(); + return 0; +} diff -urN linux-2.4.10/drivers/char/drm-4.0/tdfx_drv.h linux-2.4.10-lia/drivers/char/drm-4.0/tdfx_drv.h --- linux-2.4.10/drivers/char/drm-4.0/tdfx_drv.h Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/tdfx_drv.h Wed Aug 15 20:52:12 2001 @@ -0,0 +1,67 @@ +/* tdfx_drv.h -- Private header for tdfx driver -*- linux-c -*- + * Created: Thu Oct 7 10:40:04 1999 by faith@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rickard E. (Rik) Faith + * Daryll Strauss + * + */ + +#ifndef _TDFX_DRV_H_ +#define _TDFX_DRV_H_ + + /* tdfx_drv.c */ +extern int tdfx_version(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int tdfx_open(struct inode *inode, struct file *filp); +extern int tdfx_release(struct inode *inode, struct file *filp); +extern int tdfx_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int tdfx_lock(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int tdfx_unlock(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); + + /* tdfx_context.c */ + +extern int tdfx_resctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int tdfx_addctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int tdfx_modctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int tdfx_getctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int tdfx_switchctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int tdfx_newctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int tdfx_rmctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); + +extern int tdfx_context_switch(drm_device_t *dev, int old, int new); +extern int tdfx_context_switch_complete(drm_device_t *dev, int new); +#endif diff -urN linux-2.4.10/drivers/char/drm-4.0/vm.c linux-2.4.10-lia/drivers/char/drm-4.0/vm.c --- linux-2.4.10/drivers/char/drm-4.0/vm.c Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/drm-4.0/vm.c Mon Aug 20 18:09:34 2001 @@ -0,0 +1,451 @@ +/* vm.c -- Memory mapping for DRM -*- linux-c -*- + * Created: Mon Jan 4 08:58:31 1999 by faith@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rickard E. (Rik) Faith + * + */ + +#define __NO_VERSION__ +#include +#include "drmP.h" + +struct vm_operations_struct drm_vm_ops = { + nopage: drm_vm_nopage, + open: drm_vm_open, + close: drm_vm_close, +}; + +struct vm_operations_struct drm_vm_shm_ops = { + nopage: drm_vm_shm_nopage, + open: drm_vm_open, + close: drm_vm_close, +}; + +struct vm_operations_struct drm_vm_shm_lock_ops = { + nopage: drm_vm_shm_nopage_lock, + open: drm_vm_open, + close: drm_vm_close, +}; + +struct vm_operations_struct drm_vm_dma_ops = { + nopage: drm_vm_dma_nopage, + open: drm_vm_open, + close: drm_vm_close, +}; + +#if LINUX_VERSION_CODE < 0x020317 +unsigned long drm_vm_nopage(struct vm_area_struct *vma, + unsigned long address, + int write_access) +#else + /* Return type changed in 2.3.23 */ +struct page *drm_vm_nopage(struct vm_area_struct *vma, + unsigned long address, + int write_access) +#endif +{ +#if defined(__ia64__) + drm_file_t *priv = vma->vm_file->private_data; + drm_device_t *dev = priv->dev; + drm_map_t *map = NULL; + int i; + + /* + * Find the right map + */ + + if(!dev->agp->cant_use_aperture) goto vm_nopage_error; + + for (i = 0; i < dev->map_count; i++) { + map = dev->maplist[i]; + if (!map) continue; + if (map->offset == VM_OFFSET(vma)) break; + } + + if (map && map->type == _DRM_AGP) { + unsigned long offset = address - vma->vm_start; + unsigned long baddr = VM_OFFSET(vma) + offset, paddr; + struct drm_agp_mem *agpmem; + struct page *page; + + /* + * It's AGP memory - find the real physical page to map + */ + for(agpmem = dev->agp->memory; agpmem; agpmem = agpmem->next) { + if (agpmem->bound <= baddr && + agpmem->bound + agpmem->pages * PAGE_SIZE > baddr) + break; + } + + if (!agpmem) goto vm_nopage_error; + + /* + * Get the page, inc the use count, and return it + */ + offset = (baddr - agpmem->bound) >> PAGE_SHIFT; + + /* + * This is bad. What we really want to do here is unmask + * the GART table entry held in the agp_memory structure. + * There isn't a convenient way to call agp_bridge.unmask_ + * memory from here, so hard code it for now. + */ + paddr = (agpmem->memory->memory[offset] & 0xffffff) << 12; + + page = virt_to_page(__va(paddr)); + get_page(page); + +#if LINUX_VERSION_CODE < 0x020317 + return page_address(page); +#else + return page; +#endif + } +vm_nopage_error: +#endif + return NOPAGE_SIGBUS; /* Disallow mremap */ +} + +#if LINUX_VERSION_CODE < 0x020317 +unsigned long drm_vm_shm_nopage(struct vm_area_struct *vma, + unsigned long address, + int write_access) +#else + /* Return type changed in 2.3.23 */ +struct page *drm_vm_shm_nopage(struct vm_area_struct *vma, + unsigned long address, + int write_access) +#endif +{ +#if LINUX_VERSION_CODE >= 0x020300 + drm_map_t *map = (drm_map_t *)vma->vm_private_data; +#else + drm_map_t *map = (drm_map_t *)vma->vm_pte; +#endif + unsigned long physical; + unsigned long offset; + + if (address > vma->vm_end) return NOPAGE_SIGBUS; /* Disallow mremap */ + if (!map) return NOPAGE_OOM; /* Nothing allocated */ + + offset = address - vma->vm_start; + physical = (unsigned long)map->handle + offset; + atomic_inc(&virt_to_page(physical)->count); /* Dec. by kernel */ + + DRM_DEBUG("0x%08lx => 0x%08lx\n", address, physical); +#if LINUX_VERSION_CODE < 0x020317 + return physical; +#else + return virt_to_page(physical); +#endif +} + +#if LINUX_VERSION_CODE < 0x020317 +unsigned long drm_vm_shm_nopage_lock(struct vm_area_struct *vma, + unsigned long address, + int write_access) +#else + /* Return type changed in 2.3.23 */ +struct page *drm_vm_shm_nopage_lock(struct vm_area_struct *vma, + unsigned long address, + int write_access) +#endif +{ + drm_file_t *priv = vma->vm_file->private_data; + drm_device_t *dev = priv->dev; + unsigned long physical; + unsigned long offset; + unsigned long page; + + if (address > vma->vm_end) return NOPAGE_SIGBUS; /* Disallow mremap */ + if (!dev->lock.hw_lock) return NOPAGE_OOM; /* Nothing allocated */ + + offset = address - vma->vm_start; + page = offset >> PAGE_SHIFT; + physical = (unsigned long)dev->lock.hw_lock + offset; + atomic_inc(&virt_to_page(physical)->count); /* Dec. by kernel */ + + DRM_DEBUG("0x%08lx (page %lu) => 0x%08lx\n", address, page, physical); +#if LINUX_VERSION_CODE < 0x020317 + return physical; +#else + return virt_to_page(physical); +#endif +} + +#if LINUX_VERSION_CODE < 0x020317 +unsigned long drm_vm_dma_nopage(struct vm_area_struct *vma, + unsigned long address, + int write_access) +#else + /* Return type changed in 2.3.23 */ +struct page *drm_vm_dma_nopage(struct vm_area_struct *vma, + unsigned long address, + int write_access) +#endif +{ + drm_file_t *priv = vma->vm_file->private_data; + drm_device_t *dev = priv->dev; + drm_device_dma_t *dma = dev->dma; + unsigned long physical; + unsigned long offset; + unsigned long page; + + if (!dma) return NOPAGE_SIGBUS; /* Error */ + if (address > vma->vm_end) return NOPAGE_SIGBUS; /* Disallow mremap */ + if (!dma->pagelist) return NOPAGE_OOM ; /* Nothing allocated */ + + offset = address - vma->vm_start; /* vm_[pg]off[set] should be 0 */ + page = offset >> PAGE_SHIFT; + physical = dma->pagelist[page] + (offset & (~PAGE_MASK)); + atomic_inc(&virt_to_page(physical)->count); /* Dec. by kernel */ + + DRM_DEBUG("0x%08lx (page %lu) => 0x%08lx\n", address, page, physical); +#if LINUX_VERSION_CODE < 0x020317 + return physical; +#else + return virt_to_page(physical); +#endif +} + +void drm_vm_open(struct vm_area_struct *vma) +{ + drm_file_t *priv = vma->vm_file->private_data; + drm_device_t *dev = priv->dev; +#if DRM_DEBUG_CODE + drm_vma_entry_t *vma_entry; +#endif + + DRM_DEBUG("0x%08lx,0x%08lx\n", + vma->vm_start, vma->vm_end - vma->vm_start); + atomic_inc(&dev->vma_count); +#if LINUX_VERSION_CODE < 0x020333 + /* The map can exist after the fd is closed. */ + MOD_INC_USE_COUNT; /* Needed before Linux 2.3.51 */ +#endif + + +#if DRM_DEBUG_CODE + vma_entry = drm_alloc(sizeof(*vma_entry), DRM_MEM_VMAS); + if (vma_entry) { + down(&dev->struct_sem); + vma_entry->vma = vma; + vma_entry->next = dev->vmalist; + vma_entry->pid = current->pid; + dev->vmalist = vma_entry; + up(&dev->struct_sem); + } +#endif +} + +void drm_vm_close(struct vm_area_struct *vma) +{ + drm_file_t *priv = vma->vm_file->private_data; + drm_device_t *dev = priv->dev; +#if DRM_DEBUG_CODE + drm_vma_entry_t *pt, *prev; +#endif + + DRM_DEBUG("0x%08lx,0x%08lx\n", + vma->vm_start, vma->vm_end - vma->vm_start); +#if LINUX_VERSION_CODE < 0x020333 + MOD_DEC_USE_COUNT; /* Needed before Linux 2.3.51 */ +#endif + atomic_dec(&dev->vma_count); + +#if DRM_DEBUG_CODE + down(&dev->struct_sem); + for (pt = dev->vmalist, prev = NULL; pt; prev = pt, pt = pt->next) { + if (pt->vma == vma) { + if (prev) { + prev->next = pt->next; + } else { + dev->vmalist = pt->next; + } + drm_free(pt, sizeof(*pt), DRM_MEM_VMAS); + break; + } + } + up(&dev->struct_sem); +#endif +} + +int drm_mmap_dma(struct file *filp, struct vm_area_struct *vma) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev; + drm_device_dma_t *dma; + unsigned long length = vma->vm_end - vma->vm_start; + + lock_kernel(); + dev = priv->dev; + dma = dev->dma; + DRM_DEBUG("start = 0x%lx, end = 0x%lx, offset = 0x%lx\n", + vma->vm_start, vma->vm_end, VM_OFFSET(vma)); + + /* Length must match exact page count */ + if (!dma || (length >> PAGE_SHIFT) != dma->page_count) { + unlock_kernel(); + return -EINVAL; + } + unlock_kernel(); + + vma->vm_ops = &drm_vm_dma_ops; + vma->vm_flags |= VM_LOCKED | VM_SHM; /* Don't swap */ + +#if LINUX_VERSION_CODE < 0x020203 /* KERNEL_VERSION(2,2,3) */ + /* In Linux 2.2.3 and above, this is + handled in do_mmap() in mm/mmap.c. */ + ++filp->f_count; +#endif + vma->vm_file = filp; /* Needed for drm_vm_open() */ + drm_vm_open(vma); + return 0; +} + +int drm_mmap(struct file *filp, struct vm_area_struct *vma) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_map_t *map = NULL; + unsigned long off; + int i; + + DRM_DEBUG("start = 0x%lx, end = 0x%lx, offset = 0x%lx\n", + vma->vm_start, vma->vm_end, VM_OFFSET(vma)); + + if (!VM_OFFSET(vma)) return drm_mmap_dma(filp, vma); + + /* A sequential search of a linked list is + fine here because: 1) there will only be + about 5-10 entries in the list and, 2) a + DRI client only has to do this mapping + once, so it doesn't have to be optimized + for performance, even if the list was a + bit longer. */ + for (i = 0; i < dev->map_count; i++) { + map = dev->maplist[i]; + off = map->offset ^ VM_OFFSET(vma); +#ifdef __ia64__ + /* + * Ignore region bits, makes IA32 processes happier + * XXX This is a hack... + */ + off &= ~0xe000000000000000; +#endif // __ia64__ + if (off == 0) + break; + } + + if (i >= dev->map_count) return -EINVAL; + if (!map || ((map->flags&_DRM_RESTRICTED) && !capable(CAP_SYS_ADMIN))) + return -EPERM; + + /* Check for valid size. */ + if (map->size != vma->vm_end - vma->vm_start) return -EINVAL; + + if (!capable(CAP_SYS_ADMIN) && (map->flags & _DRM_READ_ONLY)) { + vma->vm_flags &= VM_MAYWRITE; +#if defined(__i386__) + pgprot_val(vma->vm_page_prot) &= ~_PAGE_RW; +#else + /* Ye gads this is ugly. With more thought + we could move this up higher and use + `protection_map' instead. */ + vma->vm_page_prot = __pgprot(pte_val(pte_wrprotect( + __pte(pgprot_val(vma->vm_page_prot))))); +#endif + } + + switch (map->type) { + case _DRM_AGP: +#if defined(__ia64__) + /* + * On ia64 we can't talk to bus dma address from + * the CPU, so for memory of type DRM_AGP, we'll deal with + * sorting out the real physical pages and mappings in + * in nopage() + */ + vma->vm_ops = &drm_vm_ops; + vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); + break; +#endif + case _DRM_FRAME_BUFFER: + case _DRM_REGISTERS: + if (VM_OFFSET(vma) >= __pa(high_memory)) { +#if defined(__i386__) + if (boot_cpu_data.x86 > 3 && map->type != _DRM_AGP) { + pgprot_val(vma->vm_page_prot) |= _PAGE_PCD; + pgprot_val(vma->vm_page_prot) &= ~_PAGE_PWT; + } +#elif defined(__ia64__) + if (map->type != _DRM_AGP) + vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); +#endif + vma->vm_flags |= VM_IO; /* not in core dump */ + } + if (remap_page_range(vma->vm_start, + VM_OFFSET(vma), + vma->vm_end - vma->vm_start, + vma->vm_page_prot)) + return -EAGAIN; + DRM_DEBUG(" Type = %d; start = 0x%lx, end = 0x%lx," + " offset = 0x%lx\n", + map->type, + vma->vm_start, vma->vm_end, VM_OFFSET(vma)); + vma->vm_ops = &drm_vm_ops; + break; + case _DRM_SHM: + if (map->flags & _DRM_CONTAINS_LOCK) + vma->vm_ops = &drm_vm_shm_lock_ops; + else { + vma->vm_ops = &drm_vm_shm_ops; +#if LINUX_VERSION_CODE >= 0x020300 + vma->vm_private_data = (void *)map; +#else + vma->vm_pte = (unsigned long)map; +#endif + } + + /* Don't let this area swap. Change when + DRM_KERNEL advisory is supported. */ + vma->vm_flags |= VM_LOCKED; + break; + default: + return -EINVAL; /* This should never happen. */ + } + vma->vm_flags |= VM_LOCKED | VM_SHM; /* Don't swap */ + +#if LINUX_VERSION_CODE < 0x020203 /* KERNEL_VERSION(2,2,3) */ + /* In Linux 2.2.3 and above, this is + handled in do_mmap() in mm/mmap.c. */ + ++filp->f_count; +#endif + vma->vm_file = filp; /* Needed for drm_vm_open() */ + drm_vm_open(vma); + return 0; +} diff -urN linux-2.4.10/drivers/char/efirtc.c linux-2.4.10-lia/drivers/char/efirtc.c --- linux-2.4.10/drivers/char/efirtc.c Mon Sep 24 15:06:59 2001 +++ linux-2.4.10-lia/drivers/char/efirtc.c Mon Sep 24 15:22:31 2001 @@ -40,7 +40,7 @@ #include #include -#define EFI_RTC_VERSION "0.2" +#define EFI_RTC_VERSION "0.3" #define EFI_ISDST (EFI_TIME_ADJUST_DAYLIGHT|EFI_TIME_IN_DAYLIGHT) /* @@ -315,56 +315,45 @@ spin_unlock_irqrestore(&efi_rtc_lock,flags); p += sprintf(p, - "Time :\n" - "Year : %u\n" - "Month : %u\n" - "Day : %u\n" - "Hour : %u\n" - "Minute : %u\n" - "Second : %u\n" - "Nanosecond: %u\n" - "Daylight : %u\n", - eft.year, eft.month, eft.day, eft.hour, eft.minute, - eft.second, eft.nanosecond, eft.daylight); + "Time : %u:%u:%u.%09u\n" + "Date : %u-%u-%u\n" + "Daylight : %u\n", + eft.hour, eft.minute, eft.second, eft.nanosecond, + eft.year, eft.month, eft.day, + eft.daylight); if ( eft.timezone == EFI_UNSPECIFIED_TIMEZONE) - p += sprintf(p, "Timezone : unspecified\n"); + p += sprintf(p, "Timezone : unspecified\n"); else /* XXX fixme: convert to string? */ - p += sprintf(p, "Timezone : %u\n", eft.timezone); + p += sprintf(p, "Timezone : %u\n", eft.timezone); p += sprintf(p, - "\nWakeup Alm:\n" - "Enabled : %s\n" - "Pending : %s\n" - "Year : %u\n" - "Month : %u\n" - "Day : %u\n" - "Hour : %u\n" - "Minute : %u\n" - "Second : %u\n" - "Nanosecond: %u\n" - "Daylight : %u\n", - enabled == 1 ? "Yes" : "No", - pending == 1 ? "Yes" : "No", - alm.year, alm.month, alm.day, alm.hour, alm.minute, - alm.second, alm.nanosecond, alm.daylight); + "Alarm Time : %u:%u:%u.%09u\n" + "Alarm Date : %u-%u-%u\n" + "Alarm Daylight : %u\n" + "Enabled : %s\n" + "Pending : %s\n", + alm.hour, alm.minute, alm.second, alm.nanosecond, + alm.year, alm.month, alm.day, + alm.daylight, + enabled == 1 ? "yes" : "no", + pending == 1 ? "yes" : "no"); if ( eft.timezone == EFI_UNSPECIFIED_TIMEZONE) - p += sprintf(p, "Timezone : unspecified\n"); + p += sprintf(p, "Timezone : unspecified\n"); else /* XXX fixme: convert to string? */ - p += sprintf(p, "Timezone : %u\n", eft.timezone); + p += sprintf(p, "Timezone : %u\n", alm.timezone); /* * now prints the capabilities */ p += sprintf(p, - "\nClock Cap :\n" - "Resolution: %u\n" - "Accuracy : %u\n" - "SetstoZero: %u\n", + "Resolution : %u\n" + "Accuracy : %u\n" + "SetstoZero : %u\n", cap.resolution, cap.accuracy, cap.sets_to_zero); return p - buf; @@ -390,7 +379,7 @@ misc_register(&efi_rtc_dev); - create_proc_read_entry ("efirtc", 0, NULL, efi_rtc_read_proc, NULL); + create_proc_read_entry ("driver/efirtc", 0, NULL, efi_rtc_read_proc, NULL); return 0; } diff -urN linux-2.4.10/drivers/char/mem.c linux-2.4.10-lia/drivers/char/mem.c --- linux-2.4.10/drivers/char/mem.c Mon Sep 24 15:07:02 2001 +++ linux-2.4.10-lia/drivers/char/mem.c Mon Sep 24 15:22:34 2001 @@ -191,9 +191,13 @@ * through a file pointer that was marked O_SYNC will be * done non-cached. */ - if (noncached_address(offset) || (file->f_flags & O_SYNC)) + if (noncached_address(offset) || (file->f_flags & O_SYNC) + || (vma->vm_flags & VM_NONCACHED)) vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); + if (vma->vm_flags & VM_WRITECOMBINED) + vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); + /* Don't try to swap out physical pages.. */ vma->vm_flags |= VM_RESERVED; @@ -470,13 +474,15 @@ switch (orig) { case 0: file->f_pos = offset; - return file->f_pos; + break; case 1: file->f_pos += offset; - return file->f_pos; + break; default: return -EINVAL; } + force_successful_syscall_return(); + return file->f_pos; } static int open_port(struct inode * inode, struct file * filp) diff -urN linux-2.4.10/drivers/char/simserial.c linux-2.4.10-lia/drivers/char/simserial.c --- linux-2.4.10/drivers/char/simserial.c Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/char/simserial.c Wed Mar 28 23:30:40 2001 @@ -0,0 +1,1104 @@ +/* + * Simulated Serial Driver (fake serial) + * + * This driver is mostly used for bringup purposes and will go away. + * It has a strong dependency on the system console. All outputs + * are rerouted to the same facility as the one used by printk which, in our + * case means sys_sim.c console (goes via the simulator). The code hereafter + * is completely leveraged from the serial.c driver. + * + * Copyright (C) 1999-2000 Hewlett-Packard Co + * Copyright (C) 1999 Stephane Eranian + * Copyright (C) 2000 David Mosberger-Tang + * + * 02/04/00 D. Mosberger Merged in serial.c bug fixes in rs_close(). + * 02/25/00 D. Mosberger Synced up with 2.3.99pre-5 version of serial.c. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#ifdef CONFIG_KDB +# include +#endif + +#undef SIMSERIAL_DEBUG /* define this to get some debug information */ + +#define KEYBOARD_INTR 3 /* must match with simulator! */ + +#define NR_PORTS 1 /* only one port for now */ +#define SERIAL_INLINE 1 + +#ifdef SERIAL_INLINE +#define _INLINE_ inline +#endif + +#ifndef MIN +#define MIN(a,b) ((a) < (b) ? (a) : (b)) +#endif + +#define IRQ_T(info) ((info->flags & ASYNC_SHARE_IRQ) ? SA_SHIRQ : SA_INTERRUPT) + +#define SSC_GETCHAR 21 + +extern long ia64_ssc (long, long, long, long, int); +extern void ia64_ssc_connect_irq (long intr, long irq); + +static char *serial_name = "SimSerial driver"; +static char *serial_version = "0.6"; + +/* + * This has been extracted from asm/serial.h. We need one eventually but + * I don't know exactly what we're going to put in it so just fake one + * for now. + */ +#define BASE_BAUD ( 1843200 / 16 ) + +#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST) + +/* + * Most of the values here are meaningless to this particular driver. + * However some values must be preserved for the code (leveraged from serial.c + * to work correctly). + * port must not be 0 + * type must not be UNKNOWN + * So I picked arbitrary (guess from where?) values instead + */ +static struct serial_state rs_table[NR_PORTS]={ + /* UART CLK PORT IRQ FLAGS */ + { 0, BASE_BAUD, 0x3F8, 0, STD_COM_FLAGS,0,PORT_16550 } /* ttyS0 */ +}; + +/* + * Just for the fun of it ! + */ +static struct serial_uart_config uart_config[] = { + { "unknown", 1, 0 }, + { "8250", 1, 0 }, + { "16450", 1, 0 }, + { "16550", 1, 0 }, + { "16550A", 16, UART_CLEAR_FIFO | UART_USE_FIFO }, + { "cirrus", 1, 0 }, + { "ST16650", 1, UART_CLEAR_FIFO | UART_STARTECH }, + { "ST16650V2", 32, UART_CLEAR_FIFO | UART_USE_FIFO | + UART_STARTECH }, + { "TI16750", 64, UART_CLEAR_FIFO | UART_USE_FIFO}, + { 0, 0} +}; + +static struct tty_driver serial_driver, callout_driver; +static int serial_refcount; + +static struct async_struct *IRQ_ports[NR_IRQS]; +static struct tty_struct *serial_table[NR_PORTS]; +static struct termios *serial_termios[NR_PORTS]; +static struct termios *serial_termios_locked[NR_PORTS]; + +static struct console *console; + +static unsigned char *tmp_buf; +static DECLARE_MUTEX(tmp_buf_sem); + +extern struct console *console_drivers; /* from kernel/printk.c */ + +/* + * ------------------------------------------------------------ + * rs_stop() and rs_start() + * + * This routines are called before setting or resetting tty->stopped. + * They enable or disable transmitter interrupts, as necessary. + * ------------------------------------------------------------ + */ +static void rs_stop(struct tty_struct *tty) +{ +#ifdef SIMSERIAL_DEBUG + printk("rs_stop: tty->stopped=%d tty->hw_stopped=%d tty->flow_stopped=%d\n", + tty->stopped, tty->hw_stopped, tty->flow_stopped); +#endif + +} + +static void rs_start(struct tty_struct *tty) +{ +#if SIMSERIAL_DEBUG + printk("rs_start: tty->stopped=%d tty->hw_stopped=%d tty->flow_stopped=%d\n", + tty->stopped, tty->hw_stopped, tty->flow_stopped); +#endif +} + +static void receive_chars(struct tty_struct *tty, struct pt_regs *regs) +{ + unsigned char ch; + static unsigned char seen_esc = 0; + + while ( (ch = ia64_ssc(0, 0, 0, 0, SSC_GETCHAR)) ) { + if ( ch == 27 && seen_esc == 0 ) { + seen_esc = 1; + continue; + } else { + if ( seen_esc==1 && ch == 'O' ) { + seen_esc = 2; + continue; + } else if ( seen_esc == 2 ) { + if ( ch == 'P' ) show_state(); /* F1 key */ + if ( ch == 'Q' ) show_buffers(); /* F2 key */ +#ifdef CONFIG_KDB + if ( ch == 'S' ) + kdb(KDB_REASON_KEYBOARD, 0, (kdb_eframe_t) regs); +#endif + + seen_esc = 0; + continue; + } + } + seen_esc = 0; + if (tty->flip.count >= TTY_FLIPBUF_SIZE) break; + + *tty->flip.char_buf_ptr = ch; + + *tty->flip.flag_buf_ptr = 0; + + tty->flip.flag_buf_ptr++; + tty->flip.char_buf_ptr++; + tty->flip.count++; + } + tty_flip_buffer_push(tty); +} + +/* + * This is the serial driver's interrupt routine for a single port + */ +static void rs_interrupt_single(int irq, void *dev_id, struct pt_regs * regs) +{ + struct async_struct * info; + + /* + * I don't know exactly why they don't use the dev_id opaque data + * pointer instead of this extra lookup table + */ + info = IRQ_ports[irq]; + if (!info || !info->tty) { + printk("simrs_interrupt_single: info|tty=0 info=%p problem\n", info); + return; + } + /* + * pretty simple in our case, because we only get interrupts + * on inbound traffic + */ + receive_chars(info->tty, regs); +} + +/* + * ------------------------------------------------------------------- + * Here ends the serial interrupt routines. + * ------------------------------------------------------------------- + */ + +#if 0 +/* + * not really used in our situation so keep them commented out for now + */ +static DECLARE_TASK_QUEUE(tq_serial); /* used to be at the top of the file */ +static void do_serial_bh(void) +{ + run_task_queue(&tq_serial); + printk("do_serial_bh: called\n"); +} +#endif + +static void do_softint(void *private_) +{ + printk("simserial: do_softint called\n"); +} + +static void rs_put_char(struct tty_struct *tty, unsigned char ch) +{ + struct async_struct *info = (struct async_struct *)tty->driver_data; + unsigned long flags; + + if (!tty || !info->xmit.buf) return; + + save_flags(flags); cli(); + if (CIRC_SPACE(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE) == 0) { + restore_flags(flags); + return; + } + info->xmit.buf[info->xmit.head] = ch; + info->xmit.head = (info->xmit.head + 1) & (SERIAL_XMIT_SIZE-1); + restore_flags(flags); +} + +static _INLINE_ void transmit_chars(struct async_struct *info, int *intr_done) +{ + int count; + unsigned long flags; + + save_flags(flags); cli(); + + if (info->x_char) { + char c = info->x_char; + + console->write(console, &c, 1); + + info->state->icount.tx++; + info->x_char = 0; + + goto out; + } + + if (info->xmit.head == info->xmit.tail || info->tty->stopped || info->tty->hw_stopped) { +#ifdef SIMSERIAL_DEBUG + printk("transmit_chars: head=%d, tail=%d, stopped=%d\n", + info->xmit.head, info->xmit.tail, info->tty->stopped); +#endif + goto out; + } + /* + * We removed the loop and try to do it in to chunks. We need + * 2 operations maximum because it's a ring buffer. + * + * First from current to tail if possible. + * Then from the beginning of the buffer until necessary + */ + + count = MIN(CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE), + SERIAL_XMIT_SIZE - info->xmit.tail); + console->write(console, info->xmit.buf+info->xmit.tail, count); + + info->xmit.tail = (info->xmit.tail+count) & (SERIAL_XMIT_SIZE-1); + + /* + * We have more at the beginning of the buffer + */ + count = CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE); + if (count) { + console->write(console, info->xmit.buf, count); + info->xmit.tail += count; + } +out: + restore_flags(flags); +} + +static void rs_flush_chars(struct tty_struct *tty) +{ + struct async_struct *info = (struct async_struct *)tty->driver_data; + + if (info->xmit.head == info->xmit.tail || tty->stopped || tty->hw_stopped || + !info->xmit.buf) + return; + + transmit_chars(info, NULL); +} + + +static int rs_write(struct tty_struct * tty, int from_user, + const unsigned char *buf, int count) +{ + int c, ret = 0; + struct async_struct *info = (struct async_struct *)tty->driver_data; + unsigned long flags; + + if (!tty || !info->xmit.buf || !tmp_buf) return 0; + + save_flags(flags); + if (from_user) { + down(&tmp_buf_sem); + while (1) { + int c1; + c = CIRC_SPACE_TO_END(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE); + if (count < c) + c = count; + if (c <= 0) + break; + + c -= copy_from_user(tmp_buf, buf, c); + if (!c) { + if (!ret) + ret = -EFAULT; + break; + } + cli(); + c1 = CIRC_SPACE_TO_END(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE); + if (c1 < c) + c = c1; + memcpy(info->xmit.buf + info->xmit.head, tmp_buf, c); + info->xmit.head = ((info->xmit.head + c) & + (SERIAL_XMIT_SIZE-1)); + restore_flags(flags); + buf += c; + count -= c; + ret += c; + } + up(&tmp_buf_sem); + } else { + cli(); + while (1) { + c = CIRC_SPACE_TO_END(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE); + if (count < c) + c = count; + if (c <= 0) { + break; + } + memcpy(info->xmit.buf + info->xmit.head, buf, c); + info->xmit.head = ((info->xmit.head + c) & + (SERIAL_XMIT_SIZE-1)); + buf += c; + count -= c; + ret += c; + } + restore_flags(flags); + } + /* + * Hey, we transmit directly from here in our case + */ + if (CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE) + && !tty->stopped && !tty->hw_stopped) { + transmit_chars(info, NULL); + } + return ret; +} + +static int rs_write_room(struct tty_struct *tty) +{ + struct async_struct *info = (struct async_struct *)tty->driver_data; + + return CIRC_SPACE(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE); +} + +static int rs_chars_in_buffer(struct tty_struct *tty) +{ + struct async_struct *info = (struct async_struct *)tty->driver_data; + + return CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE); +} + +static void rs_flush_buffer(struct tty_struct *tty) +{ + struct async_struct *info = (struct async_struct *)tty->driver_data; + unsigned long flags; + + save_flags(flags); cli(); + info->xmit.head = info->xmit.tail = 0; + restore_flags(flags); + + wake_up_interruptible(&tty->write_wait); + + if ((tty->flags & (1 << TTY_DO_WRITE_WAKEUP)) && + tty->ldisc.write_wakeup) + (tty->ldisc.write_wakeup)(tty); +} + +/* + * This function is used to send a high-priority XON/XOFF character to + * the device + */ +static void rs_send_xchar(struct tty_struct *tty, char ch) +{ + struct async_struct *info = (struct async_struct *)tty->driver_data; + + info->x_char = ch; + if (ch) { + /* + * I guess we could call console->write() directly but + * let's do that for now. + */ + transmit_chars(info, NULL); + } +} + +/* + * ------------------------------------------------------------ + * rs_throttle() + * + * This routine is called by the upper-layer tty layer to signal that + * incoming characters should be throttled. + * ------------------------------------------------------------ + */ +static void rs_throttle(struct tty_struct * tty) +{ + if (I_IXOFF(tty)) rs_send_xchar(tty, STOP_CHAR(tty)); + + printk("simrs_throttle called\n"); +} + +static void rs_unthrottle(struct tty_struct * tty) +{ + struct async_struct *info = (struct async_struct *)tty->driver_data; + + if (I_IXOFF(tty)) { + if (info->x_char) + info->x_char = 0; + else + rs_send_xchar(tty, START_CHAR(tty)); + } + printk("simrs_unthrottle called\n"); +} + +/* + * rs_break() --- routine which turns the break handling on or off + */ +static void rs_break(struct tty_struct *tty, int break_state) +{ +} + +static int rs_ioctl(struct tty_struct *tty, struct file * file, + unsigned int cmd, unsigned long arg) +{ + if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) && + (cmd != TIOCSERCONFIG) && (cmd != TIOCSERGSTRUCT) && + (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) { + if (tty->flags & (1 << TTY_IO_ERROR)) + return -EIO; + } + + switch (cmd) { + case TIOCMGET: + printk("rs_ioctl: TIOCMGET called\n"); + return -EINVAL; + case TIOCMBIS: + case TIOCMBIC: + case TIOCMSET: + printk("rs_ioctl: TIOCMBIS/BIC/SET called\n"); + return -EINVAL; + case TIOCGSERIAL: + printk("simrs_ioctl TIOCGSERIAL called\n"); + return 0; + case TIOCSSERIAL: + printk("simrs_ioctl TIOCSSERIAL called\n"); + return 0; + case TIOCSERCONFIG: + printk("rs_ioctl: TIOCSERCONFIG called\n"); + return -EINVAL; + + case TIOCSERGETLSR: /* Get line status register */ + printk("rs_ioctl: TIOCSERGETLSR called\n"); + return -EINVAL; + + case TIOCSERGSTRUCT: + printk("rs_ioctl: TIOCSERGSTRUCT called\n"); +#if 0 + if (copy_to_user((struct async_struct *) arg, + info, sizeof(struct async_struct))) + return -EFAULT; +#endif + return 0; + + /* + * Wait for any of the 4 modem inputs (DCD,RI,DSR,CTS) to change + * - mask passed in arg for lines of interest + * (use |'ed TIOCM_RNG/DSR/CD/CTS for masking) + * Caller should use TIOCGICOUNT to see which one it was + */ + case TIOCMIWAIT: + printk("rs_ioctl: TIOCMIWAIT: called\n"); + return 0; + /* + * Get counter of input serial line interrupts (DCD,RI,DSR,CTS) + * Return: write counters to the user passed counter struct + * NB: both 1->0 and 0->1 transitions are counted except for + * RI where only 0->1 is counted. + */ + case TIOCGICOUNT: + printk("rs_ioctl: TIOCGICOUNT called\n"); + return 0; + + case TIOCSERGWILD: + case TIOCSERSWILD: + /* "setserial -W" is called in Debian boot */ + printk ("TIOCSER?WILD ioctl obsolete, ignored.\n"); + return 0; + + default: + return -ENOIOCTLCMD; + } + return 0; +} + +#define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK)) + +static void rs_set_termios(struct tty_struct *tty, struct termios *old_termios) +{ + unsigned int cflag = tty->termios->c_cflag; + + if ( (cflag == old_termios->c_cflag) + && ( RELEVANT_IFLAG(tty->termios->c_iflag) + == RELEVANT_IFLAG(old_termios->c_iflag))) + return; + + + /* Handle turning off CRTSCTS */ + if ((old_termios->c_cflag & CRTSCTS) && + !(tty->termios->c_cflag & CRTSCTS)) { + tty->hw_stopped = 0; + rs_start(tty); + } +} +/* + * This routine will shutdown a serial port; interrupts are disabled, and + * DTR is dropped if the hangup on close termio flag is on. + */ +static void shutdown(struct async_struct * info) +{ + unsigned long flags; + struct serial_state *state; + int retval; + + if (!(info->flags & ASYNC_INITIALIZED)) return; + + state = info->state; + +#ifdef SIMSERIAL_DEBUG + printk("Shutting down serial port %d (irq %d)....", info->line, + state->irq); +#endif + + save_flags(flags); cli(); /* Disable interrupts */ + + /* + * First unlink the serial port from the IRQ chain... + */ + if (info->next_port) + info->next_port->prev_port = info->prev_port; + if (info->prev_port) + info->prev_port->next_port = info->next_port; + else + IRQ_ports[state->irq] = info->next_port; + + /* + * Free the IRQ, if necessary + */ + if (state->irq && (!IRQ_ports[state->irq] || + !IRQ_ports[state->irq]->next_port)) { + if (IRQ_ports[state->irq]) { + free_irq(state->irq, NULL); + retval = request_irq(state->irq, rs_interrupt_single, + IRQ_T(info), "serial", NULL); + + if (retval) + printk("serial shutdown: request_irq: error %d" + " Couldn't reacquire IRQ.\n", retval); + } else + free_irq(state->irq, NULL); + } + + if (info->xmit.buf) { + free_page((unsigned long) info->xmit.buf); + info->xmit.buf = 0; + } + + if (info->tty) set_bit(TTY_IO_ERROR, &info->tty->flags); + + info->flags &= ~ASYNC_INITIALIZED; + restore_flags(flags); +} + +/* + * ------------------------------------------------------------ + * rs_close() + * + * This routine is called when the serial port gets closed. First, we + * wait for the last remaining data to be sent. Then, we unlink its + * async structure from the interrupt chain if necessary, and we free + * that IRQ if nothing is left in the chain. + * ------------------------------------------------------------ + */ +static void rs_close(struct tty_struct *tty, struct file * filp) +{ + struct async_struct * info = (struct async_struct *)tty->driver_data; + struct serial_state *state; + unsigned long flags; + + if (!info ) return; + + state = info->state; + + save_flags(flags); cli(); + + if (tty_hung_up_p(filp)) { +#ifdef SIMSERIAL_DEBUG + printk("rs_close: hung_up\n"); +#endif + MOD_DEC_USE_COUNT; + restore_flags(flags); + return; + } +#ifdef SIMSERIAL_DEBUG + printk("rs_close ttys%d, count = %d\n", info->line, state->count); +#endif + if ((tty->count == 1) && (state->count != 1)) { + /* + * Uh, oh. tty->count is 1, which means that the tty + * structure will be freed. state->count should always + * be one in these conditions. If it's greater than + * one, we've got real problems, since it means the + * serial port won't be shutdown. + */ + printk("rs_close: bad serial port count; tty->count is 1, " + "state->count is %d\n", state->count); + state->count = 1; + } + if (--state->count < 0) { + printk("rs_close: bad serial port count for ttys%d: %d\n", + info->line, state->count); + state->count = 0; + } + if (state->count) { + MOD_DEC_USE_COUNT; + restore_flags(flags); + return; + } + info->flags |= ASYNC_CLOSING; + restore_flags(flags); + + /* + * Now we wait for the transmit buffer to clear; and we notify + * the line discipline to only process XON/XOFF characters. + */ + shutdown(info); + if (tty->driver.flush_buffer) tty->driver.flush_buffer(tty); + if (tty->ldisc.flush_buffer) tty->ldisc.flush_buffer(tty); + info->event = 0; + info->tty = 0; + if (info->blocked_open) { + if (info->close_delay) { + current->state = TASK_INTERRUPTIBLE; + schedule_timeout(info->close_delay); + } + wake_up_interruptible(&info->open_wait); + } + info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CALLOUT_ACTIVE|ASYNC_CLOSING); + wake_up_interruptible(&info->close_wait); + MOD_DEC_USE_COUNT; +} + +/* + * rs_wait_until_sent() --- wait until the transmitter is empty + */ +static void rs_wait_until_sent(struct tty_struct *tty, int timeout) +{ +} + + +/* + * rs_hangup() --- called by tty_hangup() when a hangup is signaled. + */ +static void rs_hangup(struct tty_struct *tty) +{ + struct async_struct * info = (struct async_struct *)tty->driver_data; + struct serial_state *state = info->state; + +#ifdef SIMSERIAL_DEBUG + printk("rs_hangup: called\n"); +#endif + + state = info->state; + + rs_flush_buffer(tty); + if (info->flags & ASYNC_CLOSING) + return; + shutdown(info); + + info->event = 0; + state->count = 0; + info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CALLOUT_ACTIVE); + info->tty = 0; + wake_up_interruptible(&info->open_wait); +} + + +static int get_async_struct(int line, struct async_struct **ret_info) +{ + struct async_struct *info; + struct serial_state *sstate; + + sstate = rs_table + line; + sstate->count++; + if (sstate->info) { + *ret_info = sstate->info; + return 0; + } + info = kmalloc(sizeof(struct async_struct), GFP_KERNEL); + if (!info) { + sstate->count--; + return -ENOMEM; + } + memset(info, 0, sizeof(struct async_struct)); + init_waitqueue_head(&info->open_wait); + init_waitqueue_head(&info->close_wait); + init_waitqueue_head(&info->delta_msr_wait); + info->magic = SERIAL_MAGIC; + info->port = sstate->port; + info->flags = sstate->flags; + info->xmit_fifo_size = sstate->xmit_fifo_size; + info->line = line; + info->tqueue.routine = do_softint; + info->tqueue.data = info; + info->state = sstate; + if (sstate->info) { + kfree(info); + *ret_info = sstate->info; + return 0; + } + *ret_info = sstate->info = info; + return 0; +} + +static int +startup(struct async_struct *info) +{ + unsigned long flags; + int retval=0; + void (*handler)(int, void *, struct pt_regs *); + struct serial_state *state= info->state; + unsigned long page; + + page = get_free_page(GFP_KERNEL); + if (!page) + return -ENOMEM; + + save_flags(flags); cli(); + + if (info->flags & ASYNC_INITIALIZED) { + free_page(page); + goto errout; + } + + if (!state->port || !state->type) { + if (info->tty) set_bit(TTY_IO_ERROR, &info->tty->flags); + free_page(page); + goto errout; + } + if (info->xmit.buf) + free_page(page); + else + info->xmit.buf = (unsigned char *) page; + +#ifdef SIMSERIAL_DEBUG + printk("startup: ttys%d (irq %d)...", info->line, state->irq); +#endif + + /* + * Allocate the IRQ if necessary + */ + if (state->irq && (!IRQ_ports[state->irq] || + !IRQ_ports[state->irq]->next_port)) { + if (IRQ_ports[state->irq]) { + retval = -EBUSY; + goto errout; + } else + handler = rs_interrupt_single; + + retval = request_irq(state->irq, handler, IRQ_T(info), + "simserial", NULL); + if (retval) { + if (capable(CAP_SYS_ADMIN)) { + if (info->tty) + set_bit(TTY_IO_ERROR, + &info->tty->flags); + retval = 0; + } + goto errout; + } + } + + /* + * Insert serial port into IRQ chain. + */ + info->prev_port = 0; + info->next_port = IRQ_ports[state->irq]; + if (info->next_port) + info->next_port->prev_port = info; + IRQ_ports[state->irq] = info; + + if (info->tty) clear_bit(TTY_IO_ERROR, &info->tty->flags); + + info->xmit.head = info->xmit.tail = 0; + +#if 0 + /* + * Set up serial timers... + */ + timer_table[RS_TIMER].expires = jiffies + 2*HZ/100; + timer_active |= 1 << RS_TIMER; +#endif + + /* + * Set up the tty->alt_speed kludge + */ + if (info->tty) { + if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_HI) + info->tty->alt_speed = 57600; + if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_VHI) + info->tty->alt_speed = 115200; + if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_SHI) + info->tty->alt_speed = 230400; + if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_WARP) + info->tty->alt_speed = 460800; + } + + info->flags |= ASYNC_INITIALIZED; + restore_flags(flags); + return 0; + +errout: + restore_flags(flags); + return retval; +} + + +/* + * This routine is called whenever a serial port is opened. It + * enables interrupts for a serial port, linking in its async structure into + * the IRQ chain. It also performs the serial-specific + * initialization for the tty structure. + */ +static int rs_open(struct tty_struct *tty, struct file * filp) +{ + struct async_struct *info; + int retval, line; + unsigned long page; + + MOD_INC_USE_COUNT; + line = MINOR(tty->device) - tty->driver.minor_start; + if ((line < 0) || (line >= NR_PORTS)) { + MOD_DEC_USE_COUNT; + return -ENODEV; + } + retval = get_async_struct(line, &info); + if (retval) { + MOD_DEC_USE_COUNT; + return retval; + } + tty->driver_data = info; + info->tty = tty; + +#ifdef SIMSERIAL_DEBUG + printk("rs_open %s%d, count = %d\n", tty->driver.name, info->line, + info->state->count); +#endif + info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0; + + if (!tmp_buf) { + page = get_free_page(GFP_KERNEL); + if (!page) { + /* MOD_DEC_USE_COUNT; "info->tty" will cause this? */ + return -ENOMEM; + } + if (tmp_buf) + free_page(page); + else + tmp_buf = (unsigned char *) page; + } + + /* + * If the port is the middle of closing, bail out now + */ + if (tty_hung_up_p(filp) || + (info->flags & ASYNC_CLOSING)) { + if (info->flags & ASYNC_CLOSING) + interruptible_sleep_on(&info->close_wait); + /* MOD_DEC_USE_COUNT; "info->tty" will cause this? */ +#ifdef SERIAL_DO_RESTART + return ((info->flags & ASYNC_HUP_NOTIFY) ? + -EAGAIN : -ERESTARTSYS); +#else + return -EAGAIN; +#endif + } + + /* + * Start up serial port + */ + retval = startup(info); + if (retval) { + /* MOD_DEC_USE_COUNT; "info->tty" will cause this? */ + return retval; + } + + if ((info->state->count == 1) && + (info->flags & ASYNC_SPLIT_TERMIOS)) { + if (tty->driver.subtype == SERIAL_TYPE_NORMAL) + *tty->termios = info->state->normal_termios; + else + *tty->termios = info->state->callout_termios; + } + + /* + * figure out which console to use (should be one already) + */ + console = console_drivers; + while (console) { + if ((console->flags & CON_ENABLED) && console->write) break; + console = console->next; + } + + info->session = current->session; + info->pgrp = current->pgrp; + +#ifdef SIMSERIAL_DEBUG + printk("rs_open ttys%d successful\n", info->line); +#endif + return 0; +} + +/* + * /proc fs routines.... + */ + +static inline int line_info(char *buf, struct serial_state *state) +{ + return sprintf(buf, "%d: uart:%s port:%lX irq:%d\n", + state->line, uart_config[state->type].name, + state->port, state->irq); +} + +int rs_read_proc(char *page, char **start, off_t off, int count, + int *eof, void *data) +{ + int i, len = 0, l; + off_t begin = 0; + + len += sprintf(page, "simserinfo:1.0 driver:%s\n", serial_version); + for (i = 0; i < NR_PORTS && len < 4000; i++) { + l = line_info(page + len, &rs_table[i]); + len += l; + if (len+begin > off+count) + goto done; + if (len+begin < off) { + begin += len; + len = 0; + } + } + *eof = 1; +done: + if (off >= len+begin) + return 0; + *start = page + (begin-off); + return ((count < begin+len-off) ? count : begin+len-off); +} + +/* + * --------------------------------------------------------------------- + * rs_init() and friends + * + * rs_init() is called at boot-time to initialize the serial driver. + * --------------------------------------------------------------------- + */ + +/* + * This routine prints out the appropriate serial driver version + * number, and identifies which options were configured into this + * driver. + */ +static inline void show_serial_version(void) +{ + printk(KERN_INFO "%s version %s with", serial_name, serial_version); + printk(" no serial options enabled\n"); +} + +/* + * The serial driver boot-time initialization code! + */ +static int __init +simrs_init (void) +{ + int i; + struct serial_state *state; + + show_serial_version(); + + /* Initialize the tty_driver structure */ + + memset(&serial_driver, 0, sizeof(struct tty_driver)); + serial_driver.magic = TTY_DRIVER_MAGIC; + serial_driver.driver_name = "simserial"; + serial_driver.name = "ttyS"; + serial_driver.major = TTY_MAJOR; + serial_driver.minor_start = 64; + serial_driver.num = 1; + serial_driver.type = TTY_DRIVER_TYPE_SERIAL; + serial_driver.subtype = SERIAL_TYPE_NORMAL; + serial_driver.init_termios = tty_std_termios; + serial_driver.init_termios.c_cflag = + B9600 | CS8 | CREAD | HUPCL | CLOCAL; + serial_driver.flags = TTY_DRIVER_REAL_RAW; + serial_driver.refcount = &serial_refcount; + serial_driver.table = serial_table; + serial_driver.termios = serial_termios; + serial_driver.termios_locked = serial_termios_locked; + + serial_driver.open = rs_open; + serial_driver.close = rs_close; + serial_driver.write = rs_write; + serial_driver.put_char = rs_put_char; + serial_driver.flush_chars = rs_flush_chars; + serial_driver.write_room = rs_write_room; + serial_driver.chars_in_buffer = rs_chars_in_buffer; + serial_driver.flush_buffer = rs_flush_buffer; + serial_driver.ioctl = rs_ioctl; + serial_driver.throttle = rs_throttle; + serial_driver.unthrottle = rs_unthrottle; + serial_driver.send_xchar = rs_send_xchar; + serial_driver.set_termios = rs_set_termios; + serial_driver.stop = rs_stop; + serial_driver.start = rs_start; + serial_driver.hangup = rs_hangup; + serial_driver.break_ctl = rs_break; + serial_driver.wait_until_sent = rs_wait_until_sent; + serial_driver.read_proc = rs_read_proc; + + /* + * Let's have a little bit of fun ! + */ + for (i = 0, state = rs_table; i < NR_PORTS; i++,state++) { + + if (state->type == PORT_UNKNOWN) continue; + + if (!state->irq) { + state->irq = ia64_alloc_irq(); + ia64_ssc_connect_irq(KEYBOARD_INTR, state->irq); + } + + printk(KERN_INFO "ttyS%02d at 0x%04lx (irq = %d) is a %s\n", + state->line, + state->port, state->irq, + uart_config[state->type].name); + } + /* + * The callout device is just like normal device except for + * major number and the subtype code. + */ + callout_driver = serial_driver; + callout_driver.name = "cua"; + callout_driver.major = TTYAUX_MAJOR; + callout_driver.subtype = SERIAL_TYPE_CALLOUT; + callout_driver.read_proc = 0; + callout_driver.proc_entry = 0; + + if (tty_register_driver(&serial_driver)) + panic("Couldn't register simserial driver\n"); + + if (tty_register_driver(&callout_driver)) + panic("Couldn't register callout driver\n"); + + return 0; +} + +#ifndef MODULE +__initcall(simrs_init); +#endif diff -urN linux-2.4.10/drivers/ide/ide-geometry.c linux-2.4.10-lia/drivers/ide/ide-geometry.c --- linux-2.4.10/drivers/ide/ide-geometry.c Thu Jan 4 12:50:17 2001 +++ linux-2.4.10-lia/drivers/ide/ide-geometry.c Thu Jan 4 23:10:38 2001 @@ -3,8 +3,11 @@ */ #include #include -#include #include + +#ifdef __i386__ +# include +#endif /* * We query CMOS about hard disks : it could be that we have a SCSI/ESDI/etc diff -urN linux-2.4.10/drivers/input/joydev.c linux-2.4.10-lia/drivers/input/joydev.c --- linux-2.4.10/drivers/input/joydev.c Wed Apr 11 19:02:30 2001 +++ linux-2.4.10-lia/drivers/input/joydev.c Mon Jul 23 14:11:15 2001 @@ -86,6 +86,12 @@ MODULE_DESCRIPTION("Joystick device driver"); MODULE_SUPPORTED_DEVICE("input/js"); +static inline unsigned long +jiffies_to_msec (unsigned long t) +{ + return 1000*(t / HZ) + 1000*(t % HZ)/HZ; +} + static int joydev_correct(int value, struct js_corr *corr) { switch (corr->type) { @@ -133,7 +139,7 @@ return; } - event.time = jiffies * (1000 / HZ); + event.time = jiffies_to_msec(jiffies); while (list) { @@ -278,7 +284,7 @@ struct js_event event; - event.time = jiffies * (1000/HZ); + event.time = jiffies_to_msec(jiffies); if (list->startup < joydev->nkey) { event.type = JS_EVENT_BUTTON | JS_EVENT_INIT; diff -urN linux-2.4.10/drivers/media/radio/Makefile linux-2.4.10-lia/drivers/media/radio/Makefile --- linux-2.4.10/drivers/media/radio/Makefile Sun Aug 5 13:15:05 2001 +++ linux-2.4.10-lia/drivers/media/radio/Makefile Mon Aug 13 23:45:57 2001 @@ -11,7 +11,7 @@ # Object file lists. -obj-y := +obj-y := dummy.o obj-m := obj-n := obj- := diff -urN linux-2.4.10/drivers/media/radio/dummy.c linux-2.4.10-lia/drivers/media/radio/dummy.c --- linux-2.4.10/drivers/media/radio/dummy.c Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/media/radio/dummy.c Tue Jan 23 01:18:20 2001 @@ -0,0 +1 @@ +/* just so the linker knows what kind of object files it's deadling with... */ diff -urN linux-2.4.10/drivers/media/video/Makefile linux-2.4.10-lia/drivers/media/video/Makefile --- linux-2.4.10/drivers/media/video/Makefile Wed Jul 4 14:41:33 2001 +++ linux-2.4.10-lia/drivers/media/video/Makefile Mon Jul 23 13:51:08 2001 @@ -11,7 +11,7 @@ # Object file lists. -obj-y := +obj-y := dummy.o obj-m := obj-n := obj- := diff -urN linux-2.4.10/drivers/media/video/dummy.c linux-2.4.10-lia/drivers/media/video/dummy.c --- linux-2.4.10/drivers/media/video/dummy.c Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/media/video/dummy.c Mon Oct 30 22:17:11 2000 @@ -0,0 +1 @@ +/* just so the linker knows what kind of object files it's deadling with... */ diff -urN linux-2.4.10/drivers/net/Makefile linux-2.4.10-lia/drivers/net/Makefile --- linux-2.4.10/drivers/net/Makefile Mon Sep 24 15:07:23 2001 +++ linux-2.4.10-lia/drivers/net/Makefile Mon Sep 24 15:22:54 2001 @@ -129,6 +129,7 @@ obj-$(CONFIG_ES3210) += es3210.o 8390.o obj-$(CONFIG_LNE390) += lne390.o 8390.o obj-$(CONFIG_NE3210) += ne3210.o 8390.o +obj-$(CONFIG_SIMETH) += simeth.o obj-$(CONFIG_PPP) += ppp_generic.o slhc.o obj-$(CONFIG_PPP_ASYNC) += ppp_async.o diff -urN linux-2.4.10/drivers/net/eepro100.c linux-2.4.10-lia/drivers/net/eepro100.c --- linux-2.4.10/drivers/net/eepro100.c Mon Sep 24 15:07:25 2001 +++ linux-2.4.10-lia/drivers/net/eepro100.c Mon Sep 24 15:22:56 2001 @@ -25,6 +25,8 @@ Disabled FC and ER, to avoid lockups when when we get FCP interrupts. 2000 Jul 17 Goutham Rao PCI DMA API fixes, adding pci_dma_sync_single calls where neccesary + 2000 Aug 31 David Mosberger + RX_ALIGN support: enables rx DMA without causing unaligned accesses. */ static const char *version = @@ -41,13 +43,17 @@ static int txdmacount = 128; static int rxdmacount /* = 0 */; +#if defined(__ia64__) || defined(__alpha__) || defined(__sparc__) || defined(__arm__) + /* align rx buffers to 2 bytes so that IP header is aligned */ +# define RX_ALIGN +# define RxFD_ALIGNMENT __attribute__ ((aligned (2), packed)) +#else +# define RxFD_ALIGNMENT +#endif + /* Set the copy breakpoint for the copy-only-tiny-buffer Rx method. Lower values use more memory, but are faster. */ -#if defined(__alpha__) || defined(__sparc__) || defined(__arm__) -static int rx_copybreak = 1518; -#else static int rx_copybreak = 200; -#endif /* Maximum events (Rx packets, etc.) to handle at each interrupt. */ static int max_interrupt_work = 20; @@ -380,18 +386,18 @@ /* The Speedo3 Rx and Tx frame/buffer descriptors. */ struct descriptor { /* A generic descriptor. */ - s32 cmd_status; /* All command and status fields. */ + volatile s32 cmd_status; /* All command and status fields. */ u32 link; /* struct descriptor * */ unsigned char params[0]; }; /* The Speedo3 Rx and Tx buffer descriptors. */ struct RxFD { /* Receive frame descriptor. */ - s32 status; + volatile s32 status; u32 link; /* struct RxFD * */ u32 rx_buf_addr; /* void * */ u32 count; -}; +} RxFD_ALIGNMENT; /* Selected elements of the Tx/RxFD.status word. */ enum RxFD_bits { @@ -1177,6 +1183,9 @@ for (i = 0; i < RX_RING_SIZE; i++) { struct sk_buff *skb; skb = dev_alloc_skb(PKT_BUF_SZ + sizeof(struct RxFD)); +#ifdef RX_ALIGN + skb_reserve(skb, 2); /* Align IP on 16 byte boundary */ +#endif sp->rx_skbuff[i] = skb; if (skb == NULL) break; /* OK. Just initially short of Rx bufs. */ @@ -1602,6 +1611,9 @@ struct sk_buff *skb; /* Get a fresh skbuff to replace the consumed one. */ skb = dev_alloc_skb(PKT_BUF_SZ + sizeof(struct RxFD)); +#ifdef RX_ALIGN + skb_reserve(skb, 2); /* Align IP on 16 byte boundary */ +#endif sp->rx_skbuff[entry] = skb; if (skb == NULL) { sp->rx_ringp[entry] = NULL; diff -urN linux-2.4.10/drivers/net/simeth.c linux-2.4.10-lia/drivers/net/simeth.c --- linux-2.4.10/drivers/net/simeth.c Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/net/simeth.c Wed Nov 1 23:19:29 2000 @@ -0,0 +1,596 @@ +/* + * Simulated Ethernet Driver + * + * Copyright (C) 1999-2000 Hewlett-Packard Co + * Copyright (C) 1999-2000 Stephane Eranain + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +#define SIMETH_RECV_MAX 10 + +/* + * Maximum possible received frame for Ethernet. + * We preallocate an sk_buff of that size to avoid costly + * memcpy for temporary buffer into sk_buff. We do basically + * what's done in other drivers, like eepro with a ring. + * The difference is, of course, that we don't have real DMA !!! + */ +#define SIMETH_FRAME_SIZE ETH_FRAME_LEN + + +#define SSC_NETDEV_PROBE 100 +#define SSC_NETDEV_SEND 101 +#define SSC_NETDEV_RECV 102 +#define SSC_NETDEV_ATTACH 103 +#define SSC_NETDEV_DETACH 104 + +#define NETWORK_INTR 8 + +/* + * This structure is need for the module version + * It hasn't been tested yet + */ +struct simeth_local { + struct net_device *next_module; + struct net_device_stats stats; + int simfd; /* descriptor in the simulator */ +}; + +static int simeth_probe1(void); +static int simeth_open(struct net_device *dev); +static int simeth_close(struct net_device *dev); +static int simeth_tx(struct sk_buff *skb, struct net_device *dev); +static int simeth_rx(struct net_device *dev); +static struct net_device_stats *simeth_get_stats(struct net_device *dev); +static void simeth_interrupt(int irq, void *dev_id, struct pt_regs * regs); +static void set_multicast_list(struct net_device *dev); +static int simeth_device_event(struct notifier_block *this,unsigned long event, void *ptr); + +static char *simeth_version="v0.2"; + +/* + * This variable is used to establish a mapping between the Linux/ia64 kernel + * and the host linux kernel. + * + * As of today, we support only one card, even though most of the code + * is ready for many more. The mapping is then: + * linux/ia64 -> linux/x86 + * eth0 -> eth1 + * + * In the future, we some string operations, we could easily support up + * to 10 cards (0-9). + * + * The default mapping can be changed on the kernel command line by + * specifying simeth=ethX (or whatever string you want). + */ +static char *simeth_device="eth0"; /* default host interface to use */ + + + +static volatile unsigned int card_count; /* how many cards "found" so far */ +static int simeth_debug=0; /* set to 1 to get debug information */ + +/* + * Used to catch IFF_UP & IFF_DOWN events + */ +static struct notifier_block simeth_dev_notifier = { + simeth_device_event, + 0 +}; + + +/* + * Function used when using a kernel command line option. + * + * Format: simeth=interface_name (like eth0) + */ +static int __init +simeth_setup(char *str) +{ + simeth_device = str; + return 1; +} + +__setup("simeth=", simeth_setup); + +/* + * Function used to probe for simeth devices when not installed + * as a loadable module + */ + +int __init +simeth_probe (void) +{ + return simeth_probe1(); +} + +extern long ia64_ssc (long, long, long, long, int); +extern void ia64_ssc_connect_irq (long intr, long irq); + +static inline int +netdev_probe(char *name, unsigned char *ether) +{ + return ia64_ssc(__pa(name), __pa(ether), 0,0, SSC_NETDEV_PROBE); +} + + +static inline int +netdev_connect(int irq) +{ + /* XXX Fix me + * this does not support multiple cards + * also no return value + */ + ia64_ssc_connect_irq(NETWORK_INTR, irq); + return 0; +} + +static inline int +netdev_attach(int fd, int irq, unsigned int ipaddr) +{ + /* this puts the host interface in the right mode (start interupting) */ + return ia64_ssc(fd, ipaddr, 0,0, SSC_NETDEV_ATTACH); +} + + +static inline int +netdev_detach(int fd) +{ + /* + * inactivate the host interface (don't interrupt anymore) */ + return ia64_ssc(fd, 0,0,0, SSC_NETDEV_DETACH); +} + +static inline int +netdev_send(int fd, unsigned char *buf, unsigned int len) +{ + return ia64_ssc(fd, __pa(buf), len, 0, SSC_NETDEV_SEND); +} + +static inline int +netdev_read(int fd, unsigned char *buf, unsigned int len) +{ + return ia64_ssc(fd, __pa(buf), len, 0, SSC_NETDEV_RECV); +} + +/* + * Function shared with module code, so cannot be in init section + * + * So far this function "detects" only one card (test_&_set) but could + * be extended easily. + * + * Return: + * - -ENODEV is no device found + * - -ENOMEM is no more memory + * - 0 otherwise + */ +static int +simeth_probe1(void) +{ + unsigned char mac_addr[ETH_ALEN]; + struct simeth_local *local; + struct net_device *dev; + int fd, i; + + /* + * XXX Fix me + * let's support just one card for now + */ + if (test_and_set_bit(0, &card_count)) + return -ENODEV; + + /* + * check with the simulator for the device + */ + fd = netdev_probe(simeth_device, mac_addr); + if (fd == -1) + return -ENODEV; + + dev = init_etherdev(NULL, sizeof(struct simeth_local)); + if (!dev) + return -ENOMEM; + + memcpy(dev->dev_addr, mac_addr, sizeof(mac_addr)); + + dev->irq = ia64_alloc_irq(); + + /* + * attach the interrupt in the simulator, this does enable interrupts + * until a netdev_attach() is called + */ + netdev_connect(dev->irq); + + memset(dev->priv, 0, sizeof(struct simeth_local)); + + local = dev->priv; + local->simfd = fd; /* keep track of underlying file descriptor */ + local->next_module = NULL; + + dev->open = simeth_open; + dev->stop = simeth_close; + dev->hard_start_xmit = simeth_tx; + dev->get_stats = simeth_get_stats; + dev->set_multicast_list = set_multicast_list; /* no yet used */ + + /* Fill in the fields of the device structure with ethernet-generic values. */ + ether_setup(dev); + + printk("simeth: %s alpha\n", simeth_version); + printk("%s: hosteth=%s simfd=%d, HwAddr", dev->name, simeth_device, local->simfd); + for(i = 0; i < ETH_ALEN; i++) { + printk(" %2.2x", dev->dev_addr[i]); + } + printk(", IRQ %d\n", dev->irq); + +#ifdef MODULE + local->next_module = simeth_dev; + simeth_dev = dev; +#endif + /* + * XXX Fix me + * would not work with more than one device ! + */ + register_netdevice_notifier(&simeth_dev_notifier); + + return 0; +} + +/* + * actually binds the device to an interrupt vector + */ +static int +simeth_open(struct net_device *dev) +{ + if (request_irq(dev->irq, simeth_interrupt, 0, "simeth", dev)) { + printk ("simeth: unable to get IRQ %d.\n", dev->irq); + return -EAGAIN; + } + + netif_start_queue(dev); + MOD_INC_USE_COUNT; + + return 0; +} + +/* copied from lapbether.c */ +static __inline__ int dev_is_ethdev(struct net_device *dev) +{ + return ( dev->type == ARPHRD_ETHER && strncmp(dev->name, "dummy", 5)); +} + + +/* + * Handler for IFF_UP or IFF_DOWN + * + * The reason for that is that we don't want to be interrupted when the + * interface is down. There is no way to unconnect in the simualtor. Instead + * we use this function to shutdown packet processing in the frame filter + * in the simulator. Thus no interrupts are generated + * + * + * That's also the place where we pass the IP address of this device to the + * simulator so that that we can start filtering packets for it + * + * There may be a better way of doing this, but I don't know which yet. + */ +static int +simeth_device_event(struct notifier_block *this,unsigned long event, void *ptr) +{ + struct net_device *dev = (struct net_device *)ptr; + struct simeth_local *local; + struct in_device *in_dev; + struct in_ifaddr **ifap = NULL; + struct in_ifaddr *ifa = NULL; + int r; + + + if ( ! dev ) { + printk(KERN_WARNING "simeth_device_event dev=0\n"); + return NOTIFY_DONE; + } + + if ( event != NETDEV_UP && event != NETDEV_DOWN ) return NOTIFY_DONE; + + /* + * Check whether or not it's for an ethernet device + * + * XXX Fixme: This works only as long as we support one + * type of ethernet device. + */ + if ( !dev_is_ethdev(dev) ) return NOTIFY_DONE; + + if ((in_dev=dev->ip_ptr) != NULL) { + for (ifap=&in_dev->ifa_list; (ifa=*ifap) != NULL; ifap=&ifa->ifa_next) + if (strcmp(dev->name, ifa->ifa_label) == 0) break; + } + if ( ifa == NULL ) { + printk("simeth_open: can't find device %s's ifa\n", dev->name); + return NOTIFY_DONE; + } + + printk("simeth_device_event: %s ipaddr=0x%x\n", dev->name, htonl(ifa->ifa_local)); + + /* + * XXX Fix me + * if the device was up, and we're simply reconfiguring it, not sure + * we get DOWN then UP. + */ + + local = dev->priv; + /* now do it for real */ + r = event == NETDEV_UP ? + netdev_attach(local->simfd, dev->irq, htonl(ifa->ifa_local)): + netdev_detach(local->simfd); + + printk("simeth: netdev_attach/detach: event=%s ->%d\n", event == NETDEV_UP ? "attach":"detach", r); + + return NOTIFY_DONE; +} + +static int +simeth_close(struct net_device *dev) +{ + netif_stop_queue(dev); + + free_irq(dev->irq, dev); + + MOD_DEC_USE_COUNT; + + return 0; +} + +/* + * Only used for debug + */ +static void +frame_print(unsigned char *from, unsigned char *frame, int len) +{ + int i; + + printk("%s: (%d) %02x", from, len, frame[0] & 0xff); + for(i=1; i < 6; i++ ) { + printk(":%02x", frame[i] &0xff); + } + printk(" %2x", frame[6] &0xff); + for(i=7; i < 12; i++ ) { + printk(":%02x", frame[i] &0xff); + } + printk(" [%02x%02x]\n", frame[12], frame[13]); + + for(i=14; i < len; i++ ) { + printk("%02x ", frame[i] &0xff); + if ( (i%10)==0) printk("\n"); + } + printk("\n"); +} + + +/* + * Function used to transmit of frame, very last one on the path before + * going to the simulator. + */ +static int +simeth_tx(struct sk_buff *skb, struct net_device *dev) +{ + struct simeth_local *local = (struct simeth_local *)dev->priv; + +#if 0 + /* ensure we have at least ETH_ZLEN bytes (min frame size) */ + unsigned int length = ETH_ZLEN < skb->len ? skb->len : ETH_ZLEN; + /* Where do the extra padding bytes comes from inthe skbuff ? */ +#else + /* the real driver in the host system is going to take care of that + * or maybe it's the NIC itself. + */ + unsigned int length = skb->len; +#endif + + local->stats.tx_bytes += skb->len; + local->stats.tx_packets++; + + + if (simeth_debug > 5) frame_print("simeth_tx", skb->data, length); + + netdev_send(local->simfd, skb->data, length); + + /* + * we are synchronous on write, so we don't simulate a + * trasnmit complete interrupt, thus we don't need to arm a tx + */ + + dev_kfree_skb(skb); + return 0; +} + +static inline struct sk_buff * +make_new_skb(struct net_device *dev) +{ + struct sk_buff *nskb; + + /* + * The +2 is used to make sure that the IP header is nicely + * aligned (on 4byte boundary I assume 14+2=16) + */ + nskb = dev_alloc_skb(SIMETH_FRAME_SIZE + 2); + if ( nskb == NULL ) { + printk(KERN_NOTICE "%s: memory squeeze. dropping packet.\n", dev->name); + return NULL; + } + nskb->dev = dev; + + skb_reserve(nskb, 2); /* Align IP on 16 byte boundaries */ + + skb_put(nskb,SIMETH_FRAME_SIZE); + + return nskb; +} + +/* + * called from interrupt handler to process a received frame + */ +static int +simeth_rx(struct net_device *dev) +{ + struct simeth_local *local; + struct sk_buff *skb; + int len; + int rcv_count = SIMETH_RECV_MAX; + + local = (struct simeth_local *)dev->priv; + /* + * the loop concept has been borrowed from other drivers + * looks to me like it's a throttling thing to avoid pushing to many + * packets at one time into the stack. Making sure we can process them + * upstream and make forward progress overall + */ + do { + if ( (skb=make_new_skb(dev)) == NULL ) { + printk(KERN_NOTICE "%s: memory squeeze. dropping packet.\n", dev->name); + local->stats.rx_dropped++; + return 0; + } + /* + * Read only one frame at a time + */ + len = netdev_read(local->simfd, skb->data, SIMETH_FRAME_SIZE); + if ( len == 0 ) { + if ( simeth_debug > 0 ) printk(KERN_WARNING "%s: count=%d netdev_read=0\n", dev->name, SIMETH_RECV_MAX-rcv_count); + break; + } +#if 0 + /* + * XXX Fix me + * Should really do a csum+copy here + */ + memcpy(skb->data, frame, len); +#endif + skb->protocol = eth_type_trans(skb, dev); + + if ( simeth_debug > 6 ) frame_print("simeth_rx", skb->data, len); + + /* + * push the packet up & trigger software interrupt + */ + netif_rx(skb); + + local->stats.rx_packets++; + local->stats.rx_bytes += len; + + } while ( --rcv_count ); + + return len; /* 0 = nothing left to read, otherwise, we can try again */ +} + +/* + * Interrupt handler (Yes, we can do it too !!!) + */ +static void +simeth_interrupt(int irq, void *dev_id, struct pt_regs * regs) +{ + struct net_device *dev = dev_id; + + if ( dev == NULL ) { + printk(KERN_WARNING "simeth: irq %d for unknown device\n", irq); + return; + } + + /* + * very simple loop because we get interrupts only when receving + */ + while (simeth_rx(dev)); +} + +static struct net_device_stats * +simeth_get_stats(struct net_device *dev) +{ + struct simeth_local *local = (struct simeth_local *) dev->priv; + + return &local->stats; +} + +/* fake multicast ability */ +static void +set_multicast_list(struct net_device *dev) +{ + printk(KERN_WARNING "%s: set_multicast_list called\n", dev->name); +} + +#ifdef CONFIG_NET_FASTROUTE +static int +simeth_accept_fastpath(struct net_device *dev, struct dst_entry *dst) +{ + printk(KERN_WARNING "%s: simeth_accept_fastpath called\n", dev->name); + return -1; +} +#endif + + +#ifdef MODULE +static int +simeth_init(void) +{ + unsigned int cards_found = 0; + + /* iterate over probe */ + + while ( simeth_probe1() == 0 ) cards_found++; + + return cards_found ? 0 : -ENODEV; +} + + +int +init_module(void) +{ + simeth_dev = NULL; + + /* the register_netdev is done "indirectly by ether_initdev() */ + + return simeth_init(); +} + +void +cleanup_module(void) +{ + struct net_device *next; + + while ( simeth_dev ) { + + next = ((struct simeth_private *)simeth_dev->priv)->next_module; + + unregister_netdev(simeth_dev); + + kfree(simeth_dev); + + simeth_dev = next; + } + /* + * XXX fix me + * not clean wihen multiple devices + */ + unregister_netdevice_notifier(&simeth_dev_notifier); +} +#else /* !MODULE */ +__initcall(simeth_probe); +#endif /* !MODULE */ diff -urN linux-2.4.10/drivers/pci/pci.c linux-2.4.10-lia/drivers/pci/pci.c --- linux-2.4.10/drivers/pci/pci.c Mon Sep 24 15:07:40 2001 +++ linux-2.4.10-lia/drivers/pci/pci.c Mon Sep 24 15:23:11 2001 @@ -1542,10 +1542,10 @@ switch (rqst) { case PM_SAVE_STATE: - error = pci_pm_save_state((u32)data); + error = pci_pm_save_state((unsigned long)data); break; case PM_SUSPEND: - error = pci_pm_suspend((u32)data); + error = pci_pm_suspend((unsigned long)data); break; case PM_RESUME: error = pci_pm_resume(); @@ -1862,9 +1862,9 @@ int map, block; if ((page = pool_find_page (pool, dma)) == 0) { - printk (KERN_ERR "pci_pool_free %s/%s, %p/%x (bad dma)\n", + printk (KERN_ERR "pci_pool_free %s/%s, %p/%lx (bad dma)\n", pool->dev ? pool->dev->slot_name : NULL, - pool->name, vaddr, dma); + pool->name, vaddr, (unsigned long) dma); return; } #ifdef CONFIG_PCIPOOL_DEBUG diff -urN linux-2.4.10/drivers/scsi/Config.in linux-2.4.10-lia/drivers/scsi/Config.in --- linux-2.4.10/drivers/scsi/Config.in Mon Sep 24 15:07:42 2001 +++ linux-2.4.10-lia/drivers/scsi/Config.in Mon Sep 24 15:23:14 2001 @@ -160,6 +160,7 @@ bool ' Include loadable firmware in driver' CONFIG_SCSI_QLOGIC_FC_FIRMWARE fi dep_tristate 'Qlogic QLA 1280 SCSI support' CONFIG_SCSI_QLOGIC_1280 $CONFIG_SCSI + dep_tristate 'Qlogic QLA 2100 driver support' CONFIG_SCSI_QLOGIC_QLA2100 $CONFIG_SCSI fi if [ "$CONFIG_X86" = "y" ]; then dep_tristate 'Seagate ST-02 and Future Domain TMC-8xx SCSI support' CONFIG_SCSI_SEAGATE $CONFIG_SCSI diff -urN linux-2.4.10/drivers/scsi/Makefile linux-2.4.10-lia/drivers/scsi/Makefile --- linux-2.4.10/drivers/scsi/Makefile Mon Sep 24 15:07:42 2001 +++ linux-2.4.10-lia/drivers/scsi/Makefile Mon Sep 24 15:23:14 2001 @@ -60,6 +60,7 @@ obj-$(CONFIG_SUN3_SCSI) += sun3_scsi.o obj-$(CONFIG_MVME16x_SCSI) += mvme16x.o 53c7xx.o obj-$(CONFIG_BVME6000_SCSI) += bvme6000.o 53c7xx.o +obj-$(CONFIG_SCSI_SIM) += simscsi.o obj-$(CONFIG_SCSI_SIM710) += sim710.o obj-$(CONFIG_SCSI_ADVANSYS) += advansys.o obj-$(CONFIG_SCSI_PCI2000) += pci2000.o @@ -88,6 +89,7 @@ obj-$(CONFIG_SCSI_QLOGIC_ISP) += qlogicisp.o obj-$(CONFIG_SCSI_QLOGIC_FC) += qlogicfc.o obj-$(CONFIG_SCSI_QLOGIC_1280) += qla1280.o +obj-$(CONFIG_SCSI_QLOGIC_QLA2100) += qla2x00.o obj-$(CONFIG_SCSI_PAS16) += pas16.o obj-$(CONFIG_SCSI_SEAGATE) += seagate.o obj-$(CONFIG_SCSI_FD_8xx) += seagate.o diff -urN linux-2.4.10/drivers/scsi/ql12160_fw.h linux-2.4.10-lia/drivers/scsi/ql12160_fw.h --- linux-2.4.10/drivers/scsi/ql12160_fw.h Mon Feb 7 19:45:28 2000 +++ linux-2.4.10-lia/drivers/scsi/ql12160_fw.h Mon Oct 30 22:17:11 2000 @@ -1,56 +1,93 @@ /* + ************************************************************************ + * * + * --- ISP12160 Initiator Firmware --- * + * 32 LUN Support * + * * + ************************************************************************ + * * + * Copyright (C) 1999,2000 Qlogic, Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted provided + * that the following conditions are met: + * 1. Redistribution of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. - * 2. The name of the author may not be used to endorse or promote products + + * 2. Redistribution in binary form must reproduce the above copyright + + * notice, this list of conditions and the following disclaimer in the + + * documentation and/or other materials provided with the distribution. + + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * * + ************************************************************************ + */ + /* - * Firmware Version 10.01.19 (12:38 Oct 12, 1999) + * Firmware Version 10.04.08 (11:30 May 31, 2000) */ #ifdef UNIQUE_FW_NAME -unsigned short fw12160i_version = 10*1024+1; +unsigned short fw12160i_version = 10*1024+4; #else -unsigned short risc_code_version = 10*1024+1; +unsigned short risc_code_version = 10*1024+4; #endif #ifdef UNIQUE_FW_NAME -unsigned char fw12160i_version_str[] = {10,1,19}; +unsigned char fw12160i_version_str[] = {10,4,8}; #else -unsigned char firmware_version[] = {10,1,19}; +unsigned char firmware_version[] = {10,4,8}; #endif #ifdef UNIQUE_FW_NAME -#define fw12160i_VERSION_STRING "10.1.19" +#define fw12160i_VERSION_STRING "10.04.08" #else -#define FW_VERSION_STRING "10.1.19" +#define FW_VERSION_STRING "10.04.08" #endif #ifdef UNIQUE_FW_NAME @@ -64,1326 +101,1383 @@ #else unsigned short risc_code01[] = { #endif - 0x0804, 0x1041, 0x0000, 0x32f8, 0x0000, 0x2043, 0x4f50, 0x5952, + 0x0804, 0x1041, 0x0000, 0x34e5, 0x0000, 0x2043, 0x4f50, 0x5952, 0x4947, 0x4854, 0x2031, 0x3939, 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0x8424, - 0xa192, 0x8d00, 0x2009, 0x0000, 0x2001, 0x0032, 0x080c, 0x1d83, - 0x2218, 0x2079, 0x4300, 0x2fa0, 0x2408, 0x2011, 0x0000, 0x20a9, + 0xa1a2, 0x4500, 0x8424, 0x8424, 0x8424, 0x8424, 0x8424, 0x8424, + 0xa192, 0x8f00, 0x2009, 0x0000, 0x2001, 0x0032, 0x080c, 0x1dcf, + 0x2218, 0x2079, 0x4500, 0x2fa0, 0x2408, 0x2011, 0x0000, 0x20a9, 0x0040, 0x42a4, 0x8109, 0x1dd8, 0x2009, 0xff00, 0x3400, 0xa102, 0x0218, 0x0110, 0x20a8, 0x42a4, 0x781b, 0x0064, 0x7814, 0xc0cd, - 0xc0d5, 0x7816, 0x2071, 0x0200, 0x00d6, 0x2069, 0x4340, 0x080c, - 0x42d8, 0x2001, 0x01ff, 0x2004, 0xd0fc, 0x1130, 0x2069, 0x4380, - 0x2071, 0x0100, 0x080c, 0x42d8, 0x7814, 0xc0d4, 0x7816, 0x00de, + 0xc0d5, 0x7816, 0x2071, 0x0200, 0x00d6, 0x2069, 0x4540, 0x080c, + 0x44bd, 0x2001, 0x01ff, 0x2004, 0xd0fc, 0x1130, 0x2069, 0x4580, + 0x2071, 0x0100, 0x080c, 0x44bd, 0x7814, 0xc0d4, 0x7816, 0x00de, 0x7eca, 0x7cc2, 0x7bc6, 0x7867, 0x0000, 0x7800, 0xc08d, 0x7802, 0x2031, 0x0030, 0x78af, 0x0101, 0x7823, 0x0002, 0x7827, 0x0002, - 0x2009, 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0xa005, 0x1110, 0x2001, 0x0101, 0x8001, 0x6812, + 0xd7fc, 0x0118, 0xa080, 0x8bd0, 0x0010, 0xa080, 0x8ac0, 0x2040, + 0x2004, 0xa065, 0x01e0, 0x6024, 0xa005, 0x01b0, 0x8001, 0x6026, + 0x1198, 0x6800, 0xa005, 0x0130, 0x6848, 0xac06, 0x1118, 0x080c, + 0x444a, 0x0068, 0x6860, 0xa005, 0x0118, 0x6027, 0x0001, 0x0020, + 0x080c, 0x4402, 0x2804, 0x0c28, 0x6000, 0x2c40, 0x0c10, 0xd7fc, + 0x1138, 0x2069, 0x4580, 0xc7fd, 0x2079, 0x0100, 0x0804, 0x437d, + 0x0005, 0x2009, 0x0000, 0x20a9, 0x0200, 0x6008, 0xd09c, 0x0558, + 0x6024, 0xa005, 0x0118, 0x8001, 0x6026, 0x0418, 0x6008, 0xc09c, + 0xd084, 0x1110, 0xd0ac, 0x01c0, 0x600a, 0x6004, 0xa005, 0x01d8, + 0x00d6, 0x00c6, 0x0016, 0x2068, 0x6010, 0x8001, 0x6012, 0x080c, + 0x376c, 0x2d00, 0x2c68, 0x2060, 0x080c, 0x1bc7, 0x080c, 0x1d7c, + 0x001e, 0x00ce, 0x00de, 0x0038, 0xc0bd, 0x600a, 0xa18d, 0x0001, + 0x0010, 0xa18d, 0x0100, 0xace0, 0x0010, 0x1f04, 0x43c5, 0xa184, + 0x0001, 0x0130, 0xa18c, 0xfffe, 0x690e, 0x080c, 0x2296, 0x0008, + 0x690e, 0x0005, 0x2c00, 0x687a, 0x6714, 0x6f72, 0x6017, 0x0000, + 0x602b, 0x0000, 0x601b, 0x0006, 0x60b4, 0xa084, 0x5f00, 0x601e, + 0x6020, 0xa084, 0x00ff, 0xa085, 0x0060, 0x6022, 0x6000, 0x2042, + 0x080c, 0x1b5f, 0x6818, 0xa005, 0x0110, 0x8001, 0x681a, 0x6808, + 0xc0a4, 0x680a, 0x6810, 0x7908, 0x8109, 0x790a, 0x8001, 0x1310, + 0x080c, 0x252b, 0x6812, 0x1118, 0x7910, 0xc1a5, 0x7912, 0x602f, + 0x0000, 0x6033, 0x0000, 0x2c68, 0x080c, 0x1d89, 0xd7fc, 0x1118, + 0x2069, 0x4540, 0x0010, 0x2069, 0x4580, 0x6910, 0xa184, 0x0100, + 0x2001, 0x0006, 0x1118, 0x6976, 0x2001, 0x0004, 0x2708, 0x080c, + 0x228b, 0x0005, 0x00d6, 0x6948, 0x2160, 0xd7fc, 0x1118, 0x2069, + 0x0200, 0x0010, 0x2069, 0x0100, 0x080c, 0x2446, 0x601b, 0x0006, + 0x6858, 0xa084, 0x5f00, 0x601e, 0x6020, 0xa084, 0x00ff, 0xa085, + 0x0048, 0x6022, 0x602f, 0x0000, 0x6033, 0x0000, 0x6808, 0xa084, + 0xfffd, 0x680a, 0x6830, 0xd0b4, 0x01b0, 0x684b, 0x0004, 0x20a9, + 0x0014, 0x6848, 0xd094, 0x0110, 0x1f04, 0x4471, 0x684b, 0x0009, + 0x20a9, 0x0014, 0x6848, 0xd084, 0x0110, 0x1f04, 0x447a, 0x20a9, + 0x00fa, 0x1f04, 0x4481, 0x681b, 0x0054, 0x00de, 0x6863, 0x0007, + 0x0005, 0x2079, 0x4500, 0x00e1, 0x0089, 0x00a9, 0x2009, 0x0002, + 0x2069, 0x4580, 0x680f, 0x0000, 0x6813, 0x0000, 0x6817, 0x0000, + 0x8109, 0x0118, 0x2069, 0x4540, 0x0ca8, 0x0005, 0x2019, 0x00a3, + 0x7b3a, 0x7b3e, 0x0005, 0x2019, 0x0033, 0x7b42, 0x7b46, 0x0005, + 0x2019, 0x32dd, 0x7b32, 0x7b36, 0x0005, 0x694c, 0xa185, 0x0000, + 0x0158, 0x00c6, 0x6abc, 0x2264, 0x6008, 0xc0b5, 0x600a, 0x8210, + 0x8109, 0x1dc8, 0x694e, 0x00ce, 0x0005, 0x70ec, 0xd0dc, 0x1118, + 0xd0d4, 0x0190, 0x0098, 0xae8e, 0x0100, 0x0138, 0x7814, 0xc0f5, + 0xc0c5, 0x7816, 0xd0d4, 0x11a8, 0x0088, 0x7814, 0xc0fd, 0xc0c5, + 0x7816, 0xd0d4, 0x1170, 0x0050, 0xd0e4, 0x0168, 0x70e4, 0xa084, + 0x01ff, 0xa086, 0x01ff, 0x0d38, 0x70a0, 0x70a2, 0x7804, 0xd08c, + 0x0110, 0x681f, 0x000c, 0x0005, 0x69ca }; #ifdef UNIQUE_FW_NAME -unsigned short fw12160i_length01 = 0x32f8; +unsigned short fw12160i_length01 = 0x34e5; #else -unsigned short risc_code_length01 = 0x32f8; +unsigned short risc_code_length01 = 0x34e5; #endif diff -urN linux-2.4.10/drivers/scsi/ql1280_fw.h linux-2.4.10-lia/drivers/scsi/ql1280_fw.h --- linux-2.4.10/drivers/scsi/ql1280_fw.h Mon Feb 7 19:45:28 2000 +++ linux-2.4.10-lia/drivers/scsi/ql1280_fw.h Mon Oct 30 22:17:11 2000 @@ -1,59 +1,117 @@ /************************************************************************ + * * + * --- ISP1240/1080/1280 Initiator Firmware --- * + * 32 LUN Support * + * * + ************************************************************************ - * Copyright (C) 1999,2000 Qlogic, Corporation. + + * * + + * Copyright (C) 1999,2000 Qlogic, Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted provided + * that the following conditions are met: + * 1. Redistribution of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. - * 2. The name of the author may not be used to endorse or promote products + + * 2. Redistribution in binary form must reproduce the above copyright + + * notice, this list of conditions and the following disclaimer in the + + * documentation and/or other materials provided with the distribution. + + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * * + ************************************************************************ + */ /* - * Firmware Version 8.09.00 (18:29 Apr 16, 1999) + * Firmware Version 8.13.08 (10:53 Jan 14, 2000) */ -unsigned short fw1280ei_version = 8*1024+9; +#ifdef UNIQUE_FW_NAME +unsigned short fw1280ei_version = 8*1024+13; +#else +unsigned short risc_code_version = 8*1024+13; +#endif + +#ifdef UNIQUE_FW_NAME +unsigned char fw1280ei_version_str[] = {8,13,8}; +#else +unsigned char firmware_version[] = {8,13,8}; +#endif -unsigned char fw1280ei_version_str[] = {8,9,0}; +#ifdef UNIQUE_FW_NAME +#define fw1280ei_VERSION_STRING "8.13.8" +#else +#define FW_VERSION_STRING "8.13.8" +#endif +#ifdef UNIQUE_FW_NAME unsigned short fw1280ei_addr01 = 0x1000 ; +#else +unsigned short risc_code_addr01 = 0x1000 ; +#endif +#ifdef UNIQUE_FW_NAME unsigned short fw1280ei_code01[] = { - 0x0078, 0x1041, 0x0000, 0x39e3, 0x0000, 0x2043, 0x4f50, 0x5952, +#else +unsigned short risc_code01[] = { +#endif + 0x0078, 0x1041, 0x0000, 0x3c71, 0x0000, 0x2043, 0x4f50, 0x5952, 0x4947, 0x4854, 0x2031, 0x3939, 0x312c, 0x3139, 0x3932, 0x2c31, 0x3939, 0x332c, 0x3139, 0x3934, 0x2051, 0x4c4f, 0x4749, 0x4320, 0x434f, 0x5250, 0x4f52, 0x4154, 0x494f, 0x4e00, 0x2049, 0x5350, 0x3132, 0x3430, 0x2046, 0x6972, 0x6d77, 0x6172, 0x6520, 0x2056, - 0x6572, 0x7369, 0x6f6e, 0x2030, 0x382e, 0x3039, 0x2020, 0x2043, + 0x6572, 0x7369, 0x6f6e, 0x2030, 0x382e, 0x3133, 0x2020, 0x2043, 0x7573, 0x746f, 0x6d65, 0x7220, 0x4e6f, 0x2e20, 0x3030, 0x2050, 0x726f, 0x6475, 0x6374, 0x204e, 0x6f2e, 0x2020, 0x3030, 0x2020, - 0x2400, 0x20c9, 0x93ff, 0x2001, 0x04fc, 0x2004, 0xa086, 0x1080, + 0x2400, 0x20c9, 0x96ff, 0x2001, 0x04fc, 0x2004, 0xa086, 0x1080, 0x00c0, 0x1054, 0x2071, 0x0100, 0x70a0, 0x70a2, 0x20c1, 0x0010, - 0x2089, 0x136a, 0x0078, 0x106d, 0x2001, 0x04fc, 0x2004, 0xa086, + 0x2089, 0x1374, 0x0078, 0x106d, 0x2001, 0x04fc, 0x2004, 0xa086, 0x1280, 0x00c0, 0x1069, 0x2071, 0x0200, 0x70a0, 0x70a2, 0x2071, - 0x0100, 0x70a0, 0x70a2, 0x20c1, 0x0010, 0x2089, 0x13ea, 0x0078, - 0x106d, 0x20c1, 0x0020, 0x2089, 0x1312, 0x2071, 0x0010, 0x70c3, + 0x0100, 0x70a0, 0x70a2, 0x20c1, 0x0010, 0x2089, 0x13f8, 0x0078, + 0x106d, 0x20c1, 0x0020, 0x2089, 0x131c, 0x2071, 0x0010, 0x70c3, 0x0004, 0x70c7, 0x4953, 0x70cb, 0x5020, 0x70cf, 0x2020, 0x70d3, 0x0008, 0x2001, 0x04fe, 0x70d6, 0x20c1, 0x0021, 0x2019, 0x0000, 0x2009, 0xfeff, 0x2100, 0x200b, 0xa5a5, 0xa1ec, 0x7fff, 0x2d64, @@ -61,1838 +119,1924 @@ 0xa286, 0xa5a5, 0x0040, 0x10a4, 0xa386, 0x000f, 0x0040, 0x10a0, 0x2c6a, 0x2a5a, 0x20c1, 0x0020, 0x2019, 0x000f, 0x0078, 0x1080, 0x2c6a, 0x2a5a, 0x0078, 0x10a2, 0x2c6a, 0x2a5a, 0x2130, 0x2128, - 0xa1a2, 0x4a00, 0x8424, 0x8424, 0x8424, 0x8424, 0x8424, 0x8424, - 0xa192, 0x9400, 0x2009, 0x0000, 0x2001, 0x0032, 0x1078, 0x2078, - 0x2218, 0x2079, 0x4a00, 0x2fa0, 0x2408, 0x2011, 0x0000, 0x20a9, - 0x0040, 0x42a4, 0x8109, 0x00c0, 0x10bf, 0x2001, 0x04fc, 0x2004, - 0xa086, 0x1080, 0x00c0, 0x10db, 0x2071, 0x0100, 0x0d7e, 0x2069, - 0x4a40, 0x1078, 0x49ae, 0x0d7f, 0x7810, 0xc0ed, 0x7812, 0x781b, - 0x0064, 0x0078, 0x1100, 0x2001, 0x04fc, 0x2004, 0xa086, 0x1280, - 0x00c0, 0x10fb, 0x7814, 0xc0ed, 0xc0d5, 0x7816, 0x781b, 0x0064, - 0x2071, 0x0200, 0x0d7e, 0x2069, 0x4a40, 0x1078, 0x49ae, 0x2069, - 0x4a80, 0x2071, 0x0100, 0x1078, 0x49ae, 0x7814, 0xc0d4, 0x7816, - 0x0d7f, 0x0078, 0x1100, 0x7814, 0xc0e5, 0x7816, 0x781b, 0x003c, - 0x7eca, 0x7cc2, 0x7bc6, 0x7867, 0x0000, 0x7800, 0xc08d, 0x7802, - 0x2031, 0x0030, 0x78af, 0x0101, 0x7823, 0x0002, 0x7827, 0x0002, - 0x2009, 0x0002, 0x2069, 0x4a40, 0x681b, 0x0003, 0x6823, 0x0007, - 0x6827, 0x00fa, 0x682b, 0x0008, 0x682f, 0x0028, 0x6837, 0x0000, - 0x683b, 0x0006, 0x6833, 0x0008, 0x683f, 0x0000, 0x8109, 0x0040, - 0x1154, 0x68d3, 0x000a, 0x68c3, 0x4ac0, 0x2079, 0x4a00, 0x7814, - 0xd0e4, 0x00c0, 0x113a, 0xd0ec, 0x00c0, 0x113e, 0x68d7, 0x7329, - 0x0078, 0x1140, 0x68d7, 0x730d, 0x0078, 0x1140, 0x68d7, 0x7329, - 0x68c7, 0x4fc0, 0x68cb, 0x4ec0, 0x68cf, 0x8fc0, 0x68ab, 0x9244, - 0x68af, 0x9249, 0x68b3, 0x9244, 0x68b7, 0x9244, 0x68a7, 0x0001, - 0x2069, 0x4a80, 0x0078, 0x1114, 0x68d3, 0x000a, 0x68c3, 0x4cc0, - 0x7814, 0xd0e4, 0x00c0, 0x1160, 0x68d7, 0x7439, 0x0078, 0x1162, - 0x68d7, 0x7419, 0x68c7, 0x6fc0, 0x68cb, 0x4f40, 0x68cf, 0x90d0, - 0x68ab, 0x9249, 0x68af, 0x924e, 0x68b3, 0x9249, 0x68b7, 0x9249, - 0x68a7, 0x0001, 0x7810, 0xd0ec, 0x00c0, 0x11b8, 0x7814, 0xd0e4, - 0x00c0, 0x11aa, 0x0e7e, 0x2069, 0x4ec0, 0x2071, 0x0200, 0x70ec, - 0xd0e4, 0x00c0, 0x118b, 0x2019, 0x0c0c, 0x2021, 0x000c, 0x1078, - 0x2007, 0x0078, 0x1191, 0x2019, 0x0c0a, 0x2021, 0x000a, 0x1078, - 0x2007, 0x2069, 0x4f40, 0x2071, 0x0100, 0x70ec, 0xd0e4, 0x00c0, - 0x11a1, 0x2019, 0x0c0c, 0x2021, 0x000c, 0x1078, 0x2007, 0x0078, - 0x11a7, 0x2019, 0x0c0a, 0x2021, 0x000a, 0x1078, 0x2007, 0x0e7f, - 0x0078, 0x11d1, 0x2019, 0x0c0c, 0x2021, 0x000c, 0x2069, 0x4ec0, - 0x1078, 0x2007, 0x2069, 0x4f40, 0x1078, 0x2007, 0x0078, 0x11d1, - 0x2069, 0x4ec0, 0x0e7e, 0x2071, 0x0100, 0x70ec, 0xd0e4, 0x00c0, - 0x11ca, 0x2019, 0x0c0c, 0x2021, 0x000c, 0x1078, 0x2007, 0x0e7f, - 0x0078, 0x11d1, 0x2019, 0x0c0a, 0x2021, 0x000a, 0x1078, 0x2007, - 0x0e7f, 0x2011, 0x0002, 0x2069, 0x4fc0, 0x2009, 0x0002, 0x20a9, - 0x0100, 0x683f, 0x0000, 0x680b, 0x0040, 0x7bc8, 0xa386, 0xfeff, - 0x00c0, 0x11e8, 0x6817, 0x0100, 0x681f, 0x0064, 0x0078, 0x11ec, - 0x6817, 0x0064, 0x681f, 0x0002, 0xade8, 0x0010, 0x00f0, 0x11d9, - 0x8109, 0x00c0, 0x11d7, 0x8211, 0x0040, 0x11fa, 0x2069, 0x6fc0, - 0x0078, 0x11d5, 0x1078, 0x2611, 0x1078, 0x441d, 0x1078, 0x1df2, - 0x1078, 0x4957, 0x2091, 0x2100, 0x2079, 0x4a00, 0x7810, 0xd0ec, - 0x0040, 0x120e, 0x2071, 0x0020, 0x0078, 0x1210, 0x2071, 0x0050, - 0x2091, 0x2200, 0x2079, 0x4a00, 0x2071, 0x0020, 0x2091, 0x2300, - 0x2079, 0x4a00, 0x7810, 0xd0ec, 0x0040, 0x1222, 0x2079, 0x0100, - 0x0078, 0x1224, 0x2079, 0x0200, 0x2071, 0x4a40, 0x2091, 0x2400, - 0x2079, 0x0100, 0x2071, 0x4a80, 0x2091, 0x2000, 0x2079, 0x4a00, - 0x2071, 0x0010, 0x3200, 0xa085, 0x303d, 0x2090, 0x2071, 0x0010, - 0x70c3, 0x0000, 0x0090, 0x1243, 0x70c0, 0xa086, 0x0002, 0x00c0, - 0x1243, 0x1078, 0x159d, 0x2039, 0x0000, 0x7810, 0xd0ec, 0x00c0, - 0x12c5, 0x1078, 0x1472, 0x78ac, 0xa005, 0x00c0, 0x1261, 0x0068, - 0x1257, 0x786c, 0xa065, 0x0040, 0x1257, 0x1078, 0x2368, 0x1078, - 0x209f, 0x0068, 0x126e, 0x786c, 0xa065, 0x0040, 0x1261, 0x1078, - 0x2368, 0x0068, 0x126e, 0x2009, 0x4a47, 0x2011, 0x4a87, 0x2104, - 0x220c, 0xa105, 0x0040, 0x126e, 0x1078, 0x1f1e, 0x2071, 0x4a40, - 0x70a4, 0xa005, 0x0040, 0x1293, 0x7450, 0xa485, 0x0000, 0x0040, - 0x1293, 0x2079, 0x0200, 0x2091, 0x8000, 0x72d4, 0xa28c, 0x303d, - 0x2190, 0x1078, 0x2a9c, 0x2091, 0x8000, 0x2091, 0x303d, 0x0068, - 0x1293, 0x2079, 0x4a00, 0x786c, 0xa065, 0x0040, 0x1293, 0x2071, - 0x0010, 0x1078, 0x2368, 0x00e0, 0x129b, 0x2079, 0x4a00, 0x2071, - 0x0010, 0x1078, 0x4765, 0x2071, 0x4a80, 0x70a4, 0xa005, 0x0040, - 0x12b3, 0x7050, 0xa025, 0x0040, 0x12b3, 0x2079, 0x0100, 0x2091, - 0x8000, 0x72d4, 0xa28c, 0x303d, 0x2190, 0x1078, 0x2a9c, 0x2091, - 0x8000, 0x2091, 0x303d, 0x2079, 0x4a00, 0x2071, 0x0010, 0x0068, - 0x12bf, 0x786c, 0xa065, 0x0040, 0x12bf, 0x1078, 0x2368, 0x00e0, - 0x1249, 0x1078, 0x4765, 0x0078, 0x1249, 0x1078, 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0x127e, 0x007e, 0x0d7e, 0x70d4, 0xa084, 0x4600, + 0x8004, 0x2090, 0x0d7f, 0x087f, 0x7108, 0xa184, 0x0003, 0x00c0, + 0x494f, 0x6828, 0xa005, 0x0040, 0x495f, 0x0078, 0x4517, 0x7108, + 0xd1fc, 0x0040, 0x4957, 0x1078, 0x46e0, 0x0078, 0x4944, 0x7007, + 0x0010, 0x7108, 0xd1fc, 0x0040, 0x4959, 0x1078, 0x46e0, 0x7008, + 0xa086, 0x0008, 0x00c0, 0x4944, 0x7000, 0xa005, 0x00c0, 0x4944, + 0x7003, 0x0000, 0x2049, 0x0000, 0x127f, 0x2000, 0x007c, 0x127e, + 0x147e, 0x137e, 0x157e, 0x0c7e, 0x0d7e, 0x70d4, 0xa084, 0x4600, + 0x8004, 0x2090, 0x0d7f, 0x2049, 0x496f, 0xad80, 0x0011, 0x20a0, + 0xb284, 0x0100, 0x0040, 0x4992, 0x2001, 0x4d04, 0x2004, 0xd0ec, + 0x0040, 0x498e, 0x2099, 0x0031, 0x0078, 0x4994, 0x2099, 0x0032, + 0x0078, 0x4994, 0x2099, 0x0031, 0x700c, 0xa084, 0x03ff, 0x682a, + 0x7007, 0x0008, 0x7007, 0x0002, 0x7003, 0x0001, 0x0040, 0x49a3, + 0x8000, 0x80ac, 0x53a5, 0x700c, 0xa084, 0x03ff, 0x0040, 0x49af, + 0x7007, 0x0004, 0x7004, 0xa084, 0x0004, 0x00c0, 0x49aa, 0x0c7f, + 0x2049, 0x0000, 0x7003, 0x0000, 0x157f, 0x137f, 0x147f, 0x127f, + 0x2000, 0x007c, 0x2091, 0x8000, 0x2091, 0x6000, 0x78ac, 0xa005, + 0x00c0, 0x49d1, 0x7974, 0x70d0, 0xa106, 0x00c0, 0x49d1, 0x781c, + 0xa005, 0x0040, 0x49d1, 0x781f, 0x0000, 0x0068, 0x49d1, 0x2091, + 0x4080, 0x7830, 0x8001, 0x7832, 0x00c0, 0x4a59, 0x7834, 0x7832, + 0x7810, 0xd0ec, 0x00c0, 0x4a52, 0x2061, 0x72c0, 0x2069, 0x4d80, + 0xc7fd, 0x68d0, 0xa005, 0x0040, 0x49eb, 0x8001, 0x68d2, 0x00c0, + 0x49eb, 0x1078, 0x4c22, 0x6800, 0xa084, 0x000f, 0x0040, 0x4a00, + 0xa086, 0x0001, 0x0040, 0x4a00, 0x6844, 0xa00d, 0x0040, 0x4a00, + 0x2104, 0xa005, 0x0040, 0x4a00, 0x8001, 0x200a, 0x0040, 0x4b95, + 0x6814, 0xa005, 0x0040, 0x4a25, 0x8001, 0x6816, 0x00c0, 0x4a25, + 0x68a7, 0x0001, 0x0f7e, 0xd7fc, 0x00c0, 0x4a1a, 0x7810, 0xd0ec, + 0x0040, 0x4a16, 0x2079, 0x0100, 0x0078, 0x4a1c, 0x2079, 0x0200, + 0x0078, 0x4a1c, 0x2079, 0x0100, 0x1078, 0x42fe, 0x0f7f, 0x6864, + 0xa005, 0x0040, 0x4a25, 0x1078, 0x25ea, 0x6880, 0xa005, 0x0040, + 0x4a32, 0x8001, 0x6882, 0x00c0, 0x4a32, 0x6867, 0x0000, 0x68d4, + 0xc0dd, 0x68d6, 0x68d4, 0xd0fc, 0x0040, 0x4a4f, 0xc0fc, 0x68d6, + 0x20a9, 0x0200, 0x6034, 0xa005, 0x0040, 0x4a4b, 0x8001, 0x6036, + 0x68d4, 0xc0fd, 0x68d6, 0x00c0, 0x4a4b, 0x6010, 0xa005, 0x0040, + 0x4a4b, 0x1078, 0x25ea, 0xace0, 0x0010, 0x00f0, 0x4a3a, 0xd7fc, + 0x0040, 0x4a59, 0x2061, 0x52c0, 0x2069, 0x4d40, 0xc7fc, 0x0078, + 0x49e1, 0x1078, 0x4a95, 0x7838, 0x8001, 0x783a, 0x00c0, 0x4a7b, + 0x783c, 0x783a, 0x2061, 0x52c0, 0x2069, 0x4d40, 0xc7fc, 0x680c, + 0xa005, 0x0040, 0x4a6d, 0x1078, 0x4aec, 0xd7fc, 0x00c0, 0x4a7b, + 0x7810, 0xd0ec, 0x00c0, 0x4a7b, 0x2061, 0x72c0, 0x2069, 0x4d80, + 0xc7fd, 0x0078, 0x4a67, 0x7814, 0xd0e4, 0x00c0, 0x4a7f, 0x7810, + 0xd0cc, 0x0040, 0x4a92, 0xd0ac, 0x00c0, 0x4a8b, 0xd0a4, 0x0040, + 0x4a92, 0xc0ad, 0x7812, 0x2091, 0x8001, 0x0068, 0x4a91, 0x1078, + 0x2356, 0x007c, 0x2091, 0x8001, 0x007c, 0x7840, 0x8001, 0x7842, + 0x00c0, 0x4aeb, 0x7844, 0x7842, 0x2091, 0x8000, 0x2061, 0x52c0, + 0x2069, 0x4d40, 0xc7fc, 0x7810, 0x2079, 0x0200, 0xd0ec, 0x0040, + 0x4aab, 0x2079, 0x0100, 0x68d8, 0xa005, 0x0040, 0x4ab7, 0x7de0, + 0xa504, 0x00c0, 0x4ab7, 0x68da, 0x68d4, 0xc0bc, 0x68d6, 0x2079, + 0x4d00, 0x6810, 0xa005, 0x00c0, 0x4abf, 0x2001, 0x0101, 0x8001, + 0x6812, 0xd7fc, 0x0040, 0x4ac8, 0xa080, 0x93d0, 0x0078, 0x4aca, + 0xa080, 0x92c0, 0x2040, 0x2004, 0xa065, 0x0040, 0x4adb, 0x6024, + 0xa005, 0x0040, 0x4ad7, 0x8001, 0x6026, 0x0040, 0x4b37, 0x6000, + 0x2c40, 0x0078, 0x4acc, 0xd7fc, 0x00c0, 0x4aeb, 0x7810, 0xd0ec, + 0x00c0, 0x4aeb, 0x2061, 0x72c0, 0x2069, 0x4d80, 0xc7fd, 0x2079, + 0x0200, 0x0078, 0x4aab, 0x007c, 0x2009, 0x0000, 0x20a9, 0x0200, + 0x6008, 0xd09c, 0x0040, 0x4b23, 0x6024, 0xa005, 0x0040, 0x4afc, + 0x8001, 0x6026, 0x0078, 0x4b21, 0x6008, 0xc09c, 0xd084, 0x00c0, + 0x4b04, 0xd0ac, 0x0040, 0x4b1b, 0x600a, 0x6004, 0xa06d, 0x0040, + 0x4b23, 0x0c7e, 0x017e, 0x6010, 0x8001, 0x6012, 0x1078, 0x3d56, + 0x2d00, 0x2c68, 0x2060, 0x1078, 0x1e42, 0x1078, 0x2004, 0x017f, + 0x0c7f, 0x0078, 0x4b23, 0xc0bd, 0x600a, 0xa18d, 0x0001, 0x0078, + 0x4b23, 0xa18d, 0x0100, 0xace0, 0x0010, 0x00f0, 0x4af0, 0xa184, + 0x0001, 0x0040, 0x4b32, 0xa18c, 0xfffe, 0x690e, 0x1078, 0x25ea, + 0x0078, 0x4b33, 0x690e, 0x007c, 0x00c0, 0x4b33, 0x786c, 0x6800, + 0xa005, 0x0040, 0x4b3f, 0x684c, 0xac06, 0x0040, 0x4b95, 0x6864, + 0xa005, 0x0040, 0x4b47, 0x6027, 0x0001, 0x0078, 0x4b94, 0x2c00, + 0x687e, 0x6714, 0x6f76, 0x6017, 0x0000, 0x602b, 0x0000, 0x601b, 0x0006, 0x60b4, 0xa084, 0x3f00, 0x601e, 0x6020, 0xa084, 0x00ff, - 0xa085, 0x0060, 0x6022, 0x6000, 0x2042, 0x6714, 0x6f76, 0x1078, - 0x1e02, 0x6818, 0xa005, 0x0040, 0x48d7, 0x8001, 0x681a, 0x6808, - 0xc0a4, 0x680a, 0x6810, 0x7908, 0x8109, 0x790a, 0x8001, 0x00d0, - 0x48e3, 0x1078, 0x28ec, 0x6812, 0x00c0, 0x48e9, 0x7910, 0xc1a5, - 0x7912, 0x602f, 0x0000, 0x6033, 0x0000, 0x2c68, 0x1078, 0x202a, - 0xd7fc, 0x00c0, 0x48f7, 0x2069, 0x4a40, 0x0078, 0x48f9, 0x2069, - 0x4a80, 0x6910, 0xa184, 0x0100, 0x2001, 0x0006, 0x00c0, 0x4903, - 0x697a, 0x2001, 0x0004, 0x2708, 0x1078, 0x25d1, 0x2091, 0x8001, - 0x007c, 0x0d7e, 0x694c, 0x2160, 0xd7fc, 0x00c0, 0x491b, 0x7810, - 0xd0ec, 0x0040, 0x4917, 0x2069, 0x0100, 0x0078, 0x491d, 0x2069, - 0x0200, 0x0078, 0x491d, 0x2069, 0x0100, 0x1078, 0x2881, 0x601b, - 0x0006, 0x6858, 0xa084, 0x3f00, 0x601e, 0x6020, 0xa084, 0x00ff, - 0xa085, 0x0048, 0x6022, 0x602f, 0x0000, 0x6033, 0x0000, 0x6830, - 0xd0b4, 0x0040, 0x494b, 0x684b, 0x0004, 0x20a9, 0x0014, 0x6848, - 0xd094, 0x0040, 0x493d, 0x00f0, 0x4937, 0x684b, 0x0009, 0x20a9, - 0x0014, 0x6848, 0xd084, 0x0040, 0x4947, 0x00f0, 0x4941, 0x20a9, - 0x00fa, 0x00f0, 0x4949, 0x6808, 0xa084, 0xfffd, 0x680a, 0x681b, - 0x0047, 0x0d7f, 0x6867, 0x0007, 0x2091, 0x8001, 0x007c, 0x2079, - 0x4a00, 0x1078, 0x498b, 0x1078, 0x4971, 0x1078, 0x497e, 0x2009, - 0x0002, 0x2069, 0x4a80, 0x680f, 0x0000, 0x6813, 0x0000, 0x6817, - 0x0000, 0x8109, 0x0040, 0x4970, 0x2069, 0x4a40, 0x0078, 0x4963, - 0x007c, 0x7810, 0xd0ec, 0x0040, 0x4979, 0x2019, 0x00cc, 0x0078, - 0x497b, 0x2019, 0x007b, 0x7b3a, 0x7b3e, 0x007c, 0x7814, 0xd0e4, - 0x00c0, 0x4986, 0x2019, 0x0040, 0x0078, 0x4988, 0x2019, 0x0026, - 0x7b42, 0x7b46, 0x007c, 0x7814, 0xd0e4, 0x00c0, 0x4993, 0x2019, - 0x3f94, 0x0078, 0x4995, 0x2019, 0x2624, 0x7b32, 0x7b36, 0x007c, - 0x6950, 0xa185, 0x0000, 0x0040, 0x49ad, 0x0c7e, 0x6ac0, 0x2264, - 0x602b, 0x0000, 0x602f, 0x0000, 0x6008, 0xc0b5, 0x600a, 0x8210, - 0x8109, 0x00c0, 0x499f, 0x6952, 0x0c7f, 0x007c, 0x70ec, 0xd0dc, - 0x00c0, 0x49b7, 0xd0d4, 0x0040, 0x49d6, 0x0078, 0x49d9, 0x7810, - 0xd0ec, 0x0040, 0x49c2, 0xc0f5, 0x7812, 0xd0ec, 0x0040, 0x49dd, - 0x0078, 0x49d9, 0xae8e, 0x0100, 0x0040, 0x49ce, 0x7814, 0xc0f5, - 0x7816, 0xd0d4, 0x00c0, 0x49dd, 0x0078, 0x49d9, 0x7814, 0xc0fd, - 0x7816, 0xd0d4, 0x00c0, 0x49dd, 0x0078, 0x49d9, 0xd0e4, 0x0040, - 0x49df, 0x7804, 0xd08c, 0x0040, 0x49df, 0x681f, 0x000c, 0x70a0, - 0x70a2, 0x007c, 0x699a + 0xa085, 0x0060, 0x6022, 0x6000, 0x2042, 0x1078, 0x1dcb, 0x6818, + 0xa005, 0x0040, 0x4b65, 0x8001, 0x681a, 0x6808, 0xc0a4, 0x680a, + 0x6810, 0x7908, 0x8109, 0x790a, 0x8001, 0x00d0, 0x4b71, 0x1078, + 0x290c, 0x6812, 0x00c0, 0x4b77, 0x7910, 0xc1a5, 0x7912, 0x602f, + 0x0000, 0x6033, 0x0000, 0x2c68, 0x1078, 0x2013, 0xd7fc, 0x00c0, + 0x4b85, 0x2069, 0x4d40, 0x0078, 0x4b87, 0x2069, 0x4d80, 0x6910, + 0xa184, 0x0100, 0x2001, 0x0006, 0x00c0, 0x4b91, 0x697a, 0x2001, + 0x0004, 0x2708, 0x1078, 0x25dd, 0x007c, 0x0d7e, 0x694c, 0x2160, + 0xd7fc, 0x00c0, 0x4ba7, 0x7810, 0xd0ec, 0x0040, 0x4ba3, 0x2069, + 0x0100, 0x0078, 0x4ba9, 0x2069, 0x0200, 0x0078, 0x4ba9, 0x2069, + 0x0100, 0x1078, 0x288d, 0x601b, 0x0006, 0x6858, 0xa084, 0x3f00, + 0x601e, 0x6020, 0xa084, 0x00ff, 0xa085, 0x0048, 0x6022, 0x602f, + 0x0000, 0x6033, 0x0000, 0x6808, 0xa084, 0xfffd, 0x680a, 0x6830, + 0xd0b4, 0x0040, 0x4bdb, 0x684b, 0x0004, 0x20a9, 0x0014, 0x6848, + 0xd094, 0x0040, 0x4bcd, 0x00f0, 0x4bc7, 0x684b, 0x0009, 0x20a9, + 0x0014, 0x6848, 0xd084, 0x0040, 0x4bd7, 0x00f0, 0x4bd1, 0x20a9, + 0x00fa, 0x00f0, 0x4bd9, 0x681b, 0x0047, 0x0d7f, 0x6867, 0x0007, + 0x007c, 0x2079, 0x4d00, 0x1078, 0x4c15, 0x1078, 0x4bfb, 0x1078, + 0x4c08, 0x2009, 0x0002, 0x2069, 0x4d80, 0x680f, 0x0000, 0x6813, + 0x0000, 0x6817, 0x0000, 0x8109, 0x0040, 0x4bfa, 0x2069, 0x4d40, + 0x0078, 0x4bed, 0x007c, 0x7810, 0xd0ec, 0x0040, 0x4c03, 0x2019, + 0x00cc, 0x0078, 0x4c05, 0x2019, 0x007b, 0x7b3a, 0x7b3e, 0x007c, + 0x7814, 0xd0e4, 0x00c0, 0x4c10, 0x2019, 0x0040, 0x0078, 0x4c12, + 0x2019, 0x0026, 0x7b42, 0x7b46, 0x007c, 0x7814, 0xd0e4, 0x00c0, + 0x4c1d, 0x2019, 0x3f94, 0x0078, 0x4c1f, 0x2019, 0x2624, 0x7b32, + 0x7b36, 0x007c, 0x6950, 0xa185, 0x0000, 0x0040, 0x4c37, 0x0c7e, + 0x6ac0, 0x2264, 0x602b, 0x0000, 0x602f, 0x0000, 0x6008, 0xc0b5, + 0x600a, 0x8210, 0x8109, 0x00c0, 0x4c29, 0x6952, 0x0c7f, 0x007c, + 0x70ec, 0xd0dc, 0x00c0, 0x4c41, 0xd0d4, 0x0040, 0x4c64, 0x0078, + 0x4c67, 0x2008, 0x7810, 0xd0ec, 0x0040, 0x4c50, 0xd1c4, 0x00c0, + 0x4c6f, 0xc0f5, 0x7812, 0xd0ec, 0x0040, 0x4c6b, 0x0078, 0x4c67, + 0xae8e, 0x0100, 0x0040, 0x4c5c, 0x7814, 0xc0f5, 0x7816, 0xd0d4, + 0x00c0, 0x4c6b, 0x0078, 0x4c67, 0x7814, 0xc0fd, 0x7816, 0xd0d4, + 0x00c0, 0x4c6b, 0x0078, 0x4c67, 0xd0e4, 0x0040, 0x4c6d, 0x7804, + 0xd08c, 0x0040, 0x4c6d, 0x681f, 0x000c, 0x70a0, 0x70a2, 0x007c, + 0x3782 }; -unsigned short fw1280ei_length01 = 0x39e3; +#ifdef UNIQUE_FW_NAME +unsigned short fw1280ei_length01 = 0x3c71; +#else +unsigned short risc_code_length01 = 0x3c71; +#endif diff -urN linux-2.4.10/drivers/scsi/ql2100_fw.h linux-2.4.10-lia/drivers/scsi/ql2100_fw.h --- linux-2.4.10/drivers/scsi/ql2100_fw.h Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/scsi/ql2100_fw.h Mon Jul 23 14:11:58 2001 @@ -0,0 +1,4740 @@ +/************************************************************************ + * * + * --- ISP2100 Fabric Initiator/Target Firmware --- * + * with expanded LUN addressing * + * and FcTape (FCP-2) support * + * * + * * + ************************************************************************ + Copyright (C) 2000 and 2001 Qlogic Corporation + (www.qlogic.com) + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. +************************************************************************/ +/* + * Firmware Version 1.19.16 (10:36 Nov 02, 2000) + */ + +#ifdef UNIQUE_FW_NAME +unsigned short fw2100tp_version = 1*1024+19; +#else +unsigned short risc_code_version = 1*1024+19; +#endif + +#ifdef UNIQUE_FW_NAME +unsigned char fw2100tp_version_str[] = {1,19,16}; +#else +unsigned char firmware_version[] = {1,19,16}; +#endif + +#ifdef UNIQUE_FW_NAME +#define fw2100tp_VERSION_STRING "1.19.16" +#else +#define FW_VERSION_STRING "1.19.16" +#endif + +#ifdef UNIQUE_FW_NAME +unsigned short fw2100tp_addr01 = 0x1000 ; +#else +unsigned short risc_code_addr01 = 0x1000 ; +#endif + +#ifdef UNIQUE_FW_NAME +unsigned short fw2100tp_code01[] = { +#else +unsigned short risc_code01[] = { +#endif + 0x0078, 0x102d, 0x0000, 0x9260, 0x0000, 0x0001, 0x0013, 0x0010, + 0x0017, 0x2043, 0x4f50, 0x5952, 0x4947, 0x4854, 0x2031, 0x3939, + 0x3920, 0x514c, 0x4f47, 0x4943, 0x2043, 0x4f52, 0x504f, 0x5241, + 0x5449, 0x4f4e, 0x2049, 0x5350, 0x3231, 0x3030, 0x2046, 0x6972, + 0x6d77, 0x6172, 0x6520, 0x2056, 0x6572, 0x7369, 0x6f6e, 0x2030, + 0x312e, 0x3139, 0x2020, 0x2020, 0x2400, 0x2091, 0x2000, 0x20c1, + 0x0021, 0x2039, 0xffff, 0x2019, 0xaaaa, 0x2760, 0x2069, 0x7fff, + 0x20c1, 0x0020, 0x2c2c, 0x2d34, 0x2762, 0x236a, 0x2c24, 0x2d04, + 0x266a, 0x2562, 0xa406, 0x00c0, 0x1052, 0x20c1, 0x0021, 0x2c2c, + 0x2362, 0x2c04, 0x2562, 0xa306, 0x0040, 0x1052, 0x20c1, 0x0020, + 0x2039, 0x8fff, 0x20a1, 0xaa00, 0x2708, 0x810d, 0x810d, 0x810d, + 0x810d, 0xa18c, 0x000f, 0x2001, 0x000a, 0xa112, 0xa00e, 0x21a8, + 0x41a4, 0x3400, 0x8211, 0x00c0, 0x105f, 0x2708, 0x3400, 0xa102, + 0x0040, 0x106f, 0x0048, 0x106f, 0x20a8, 0xa00e, 0x41a4, 0x20a1, + 0xa260, 0x2009, 0x0000, 0x20a9, 0x07a0, 0x41a4, 0x3400, 0x20c9, + 0xa7ff, 0x2059, 0x0000, 0x2b78, 0x7823, 0x0004, 0x2089, 0x255d, + 0x2051, 0xa300, 0x2a70, 0x775e, 0xa786, 0x8fff, 0x0040, 0x1092, + 0x705b, 0xca00, 0x7057, 0xc9f1, 0x7063, 0x0200, 0x7067, 0x0200, + 0x0078, 0x109a, 0x7057, 0xba01, 0x7063, 0x0100, 0x7067, 0x0100, + 0x705b, 0xba00, 0x1078, 0x12df, 0x1078, 0x13c0, 0x1078, 0x1569, + 0x1078, 0x1ca4, 0x1078, 0x4229, 0x1078, 0x74cf, 0x1078, 0x134b, + 0x1078, 0x2a3f, 0x1078, 0x4da2, 0x1078, 0x48b2, 0x1078, 0x57df, + 0x1078, 0x21f7, 0x1078, 0x5abf, 0x1078, 0x5369, 0x1078, 0x210d, + 0x1078, 0x21d4, 0x2091, 0x3009, 0x7823, 0x0000, 0x0090, 0x10cf, + 0x7820, 0xa086, 0x0002, 0x00c0, 0x10cf, 0x7823, 0x4000, 0x0068, + 0x10c7, 0x781b, 0x0001, 0x2091, 0x5000, 0x2091, 0x4080, 0x2a70, + 0x7003, 0x0000, 0x2001, 0x017f, 0x2003, 0x0000, 0x2a70, 0x7000, + 0xa08e, 0x0003, 0x00c0, 0x10ef, 0x1078, 0x35bc, 0x1078, 0x2a67, + 0x1078, 0x4df2, 0x1078, 0x4a75, 0x2009, 0x0100, 0x2104, 0xa082, + 0x0002, 0x0048, 0x10f3, 0x1078, 0x57fb, 0x0078, 0x10d6, 0x1079, + 0x10f7, 0x0078, 0x10dc, 0x1078, 0x6fa9, 0x0078, 0x10eb, 0x1101, + 0x1102, 0x11be, 0x10ff, 0x1246, 0x12dc, 0x12dd, 0x12de, 0x1078, + 0x1328, 0x007c, 0x127e, 0x0f7e, 0x2091, 0x8000, 0x7000, 0xa086, + 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0x9f56, 0x9f56, 0x9f56, + 0x9f56, 0x9f56, 0x9f56, 0x9f61, 0x9f56, 0x9f56, 0x6007, 0x003b, + 0x602b, 0x0009, 0x6013, 0x2a00, 0x6003, 0x0001, 0x1078, 0x5bf8, + 0x007c, 0x0c7e, 0x2260, 0x1078, 0xa134, 0x603f, 0x0000, 0x6024, + 0xc0f4, 0xc0cc, 0x6026, 0x0c7f, 0x0d7e, 0x2268, 0xa186, 0x0007, + 0x00c0, 0x9fc2, 0x6810, 0xa005, 0x0040, 0x9f7f, 0xa080, 0x0013, + 0x2004, 0xd0fc, 0x00c0, 0x9f7f, 0x0d7f, 0x0078, 0x9f56, 0x6007, + 0x003a, 0x6003, 0x0001, 0x1078, 0x5bf8, 0x1078, 0x6109, 0x0c7e, + 0x2d60, 0x6100, 0xa186, 0x0002, 0x00c0, 0xa050, 0x6010, 0xa005, + 0x00c0, 0x9f99, 0x6000, 0xa086, 0x0007, 0x10c0, 0x1328, 0x0078, + 0xa050, 0xa08c, 0xf000, 0x00c0, 0x9fa5, 0x0078, 0x9fa5, 0x2068, + 0x6800, 0xa005, 0x00c0, 0x9f9f, 0x2d00, 0xa080, 0x0013, 0x2004, + 0xa084, 0x0003, 0xa086, 0x0002, 0x00c0, 0x9fbe, 0x6010, 0x2068, + 0x684c, 0xc0dc, 0xc0f4, 0x684e, 0x6850, 0xc0f4, 0xc0fc, 0x6852, + 0x2009, 0x0043, 0x1078, 0x98c1, 0x0078, 0xa050, 0x2009, 0x0041, + 0x0078, 0xa04a, 0xa186, 0x0005, 0x00c0, 0xa009, 0x6810, 0xa080, + 0x0013, 0x2004, 0xd0bc, 0x00c0, 0x9fd0, 0x0d7f, 0x0078, 0x9f56, + 0xd0b4, 0x0040, 0x9fd8, 0xd0fc, 0x1040, 0x1328, 0x0078, 0x9f72, + 0x6007, 0x003a, 0x6003, 0x0001, 0x1078, 0x5bf8, 0x1078, 0x6109, + 0x0c7e, 0x2d60, 0x6100, 0xa186, 0x0002, 0x0040, 0x9feb, 0xa186, + 0x0004, 0x00c0, 0xa050, 0x2071, 0xa5e1, 0x7000, 0xa086, 0x0003, + 0x00c0, 0x9ff8, 0x7004, 0xac06, 0x00c0, 0x9ff8, 0x7003, 0x0000, + 0x6810, 0xa080, 0x0013, 0x200c, 0xc1f4, 0xc1dc, 0x2102, 0x8000, + 0x200c, 0xc1f4, 0xc1fc, 0xc1bc, 0x2102, 0x2009, 0x0042, 0x0078, + 0xa04a, 0x037e, 0x0d7e, 0x0d7e, 0x1078, 0x1381, 0x037f, 0x1040, + 0x1328, 0x6837, 0x010d, 0x6803, 0x0000, 0x683b, 0x0000, 0x685b, + 0x0000, 0x6b5e, 0x6857, 0x0045, 0x2c00, 0x6862, 0x6034, 0x6872, + 0x2360, 0x6024, 0xc0dd, 0x6026, 0x6018, 0xa080, 0x0028, 0x2004, + 0xa084, 0x00ff, 0x8007, 0x6320, 0x6b4a, 0x6846, 0x684f, 0x0000, + 0x6d6a, 0x6e66, 0x686f, 0x0001, 0x1078, 0x4982, 0x2019, 0x0045, + 0x6008, 0x2068, 0x1078, 0x9a6a, 0x2d00, 0x600a, 0x601f, 0x0006, + 0x6003, 0x0007, 0x6017, 0x0000, 0x603f, 0x0000, 0x0d7f, 0x037f, + 0x0078, 0xa051, 0x603f, 0x0000, 0x6003, 0x0007, 0x1078, 0x98c1, + 0x0c7f, 0x0d7f, 0x007c, 0xa186, 0x0013, 0x00c0, 0xa05d, 0x6004, + 0xa082, 0x0085, 0x2008, 0x0079, 0xa077, 0xa186, 0x0027, 0x00c0, + 0xa070, 0x1078, 0x6010, 0x037e, 0x0d7e, 0x6010, 0x2068, 0x2019, + 0x0004, 0x1078, 0x9e70, 0x0d7f, 0x037f, 0x1078, 0x6109, 0x007c, + 0xa186, 0x0014, 0x0040, 0xa061, 0x1078, 0x7583, 0x007c, 0xa080, + 0xa07e, 0xa07e, 0xa07e, 0xa07e, 0xa07e, 0xa080, 0x1078, 0x1328, + 0x1078, 0x6010, 0x6003, 0x000c, 0x1078, 0x6109, 0x007c, 0xa182, + 0x008c, 0x00c8, 0xa091, 0xa182, 0x0085, 0x0048, 0xa091, 0x0079, + 0xa094, 0x1078, 0x7583, 0x007c, 0xa09b, 0xa09b, 0xa09b, 0xa09b, + 0xa09d, 0xa0bc, 0xa09b, 0x1078, 0x1328, 0x0d7e, 0x2c68, 0x1078, + 0x74d7, 0x0040, 0xa0b7, 0x6003, 0x0001, 0x6007, 0x001e, 0x2009, + 0xa88e, 0x210c, 0x6136, 0x2009, 0xa88f, 0x210c, 0x613a, 0x600b, + 0xffff, 0x6918, 0x611a, 0x601f, 0x0004, 0x1078, 0x5bf8, 0x2d60, + 0x1078, 0x753d, 0x0d7f, 0x007c, 0x1078, 0x753d, 0x007c, 0x0e7e, + 0x6018, 0x2070, 0x7000, 0xd0ec, 0x0e7f, 0x007c, 0x6010, 0xa080, + 0x0013, 0x200c, 0xd1ec, 0x0040, 0xa110, 0x2001, 0xa371, 0x2004, + 0xd0ec, 0x0040, 0xa110, 0x6003, 0x0002, 0x6024, 0xc0e5, 0x6026, + 0xd1ac, 0x0040, 0xa0ee, 0x0f7e, 0x2c78, 0x1078, 0x488f, 0x0f7f, + 0x0040, 0xa0ee, 0x2001, 0xa5a2, 0x2004, 0x603e, 0x2009, 0xa371, + 0x210c, 0xd1f4, 0x00c0, 0xa10e, 0x0078, 0xa100, 0x2009, 0xa371, + 0x210c, 0xd1f4, 0x0040, 0xa0fa, 0x6024, 0xc0e4, 0x6026, 0xa006, + 0x0078, 0xa110, 0x2001, 0xa5a2, 0x200c, 0x8103, 0xa100, 0x603e, + 0x6018, 0xa088, 0x002b, 0x2104, 0xa005, 0x0040, 0xa10b, 0xa088, + 0x0003, 0x0078, 0xa103, 0x2c0a, 0x600f, 0x0000, 0xa085, 0x0001, + 0x007c, 0x017e, 0x0c7e, 0x0e7e, 0x6120, 0xa2f0, 0x002b, 0x2e04, + 0x2060, 0x8cff, 0x0040, 0xa130, 0x84ff, 0x00c0, 0xa123, 0x6020, + 0xa106, 0x00c0, 0xa12b, 0x600c, 0x2072, 0x1078, 0x5a41, 0x1078, + 0x753d, 0x0078, 0xa12d, 0xacf0, 0x0003, 0x2e64, 0x0078, 0xa119, + 0x0e7f, 0x0c7f, 0x017f, 0x007c, 0x0d7e, 0x6018, 0xa0e8, 0x002b, + 0x2d04, 0xa005, 0x0040, 0xa146, 0xac06, 0x0040, 0xa144, 0x2d04, + 0xa0e8, 0x0003, 0x0078, 0xa138, 0x600c, 0x206a, 0x0d7f, 0x007c, + 0x027e, 0x037e, 0x157e, 0x2011, 0xa325, 0x2204, 0xa084, 0x00ff, + 0x2019, 0xa88e, 0x2334, 0xa636, 0x00c0, 0xa174, 0x8318, 0x2334, + 0x2204, 0xa084, 0xff00, 0xa636, 0x00c0, 0xa174, 0x2011, 0xa890, + 0x6018, 0xa098, 0x000a, 0x20a9, 0x0004, 0x1078, 0x7e55, 0x00c0, + 0xa174, 0x2011, 0xa894, 0x6018, 0xa098, 0x0006, 0x20a9, 0x0004, + 0x1078, 0x7e55, 0x00c0, 0xa174, 0x157f, 0x037f, 0x027f, 0x007c, + 0x0e7e, 0x2071, 0xa300, 0x1078, 0x41f5, 0x1078, 0x260d, 0x0e7f, + 0x007c, 0x0e7e, 0x6018, 0x2070, 0x7000, 0xd0fc, 0x0040, 0xa18a, + 0x1078, 0xa18c, 0x0e7f, 0x007c, 0x6850, 0xc0e5, 0x6852, 0x007c, + 0x0e7e, 0x0c7e, 0x077e, 0x067e, 0x057e, 0x047e, 0x027e, 0x017e, + 0x127e, 0x2091, 0x8000, 0x2029, 0xa5b4, 0x252c, 0x2021, 0xa5ba, + 0x2424, 0x2061, 0xaa00, 0x2071, 0xa300, 0x7644, 0x7060, 0xa606, + 0x0040, 0xa1e4, 0x671c, 0xa786, 0x0001, 0x0040, 0xa1b3, 0xa786, + 0x0008, 0x00c0, 0xa1da, 0x2500, 0xac06, 0x0040, 0xa1da, 0x2400, + 0xac06, 0x0040, 0xa1da, 0x1078, 0x9ee5, 0x0040, 0xa1da, 0x1078, + 0x9ef9, 0x00c0, 0xa1da, 0x6000, 0xa086, 0x0004, 0x00c0, 0xa1cc, + 0x017e, 0x1078, 0x1749, 0x017f, 0x1078, 0x8c27, 0x00c0, 0xa1d2, + 0x1078, 0x2839, 0x1078, 0x8c3b, 0x00c0, 0xa1d8, 0x1078, 0x7a05, + 0x1078, 0x8c01, 0xace0, 0x0010, 0x2001, 0xa315, 0x2004, 0xac02, + 0x00c8, 0xa1e4, 0x0078, 0xa1a3, 0x127f, 0x017f, 0x027f, 0x047f, + 0x057f, 0x067f, 0x077f, 0x0c7f, 0x0e7f, 0x007c, 0x127e, 0x007e, + 0x0e7e, 0x2091, 0x8000, 0x2071, 0xa340, 0xd5a4, 0x0040, 0xa1fb, + 0x7034, 0x8000, 0x7036, 0xd5b4, 0x0040, 0xa201, 0x7030, 0x8000, + 0x7032, 0xd5ac, 0x0040, 0xa208, 0x2071, 0xa34a, 0x1078, 0xa237, + 0x0e7f, 0x007f, 0x127f, 0x007c, 0x127e, 0x007e, 0x0e7e, 0x2091, + 0x8000, 0x2071, 0xa340, 0xd5a4, 0x0040, 0xa219, 0x7034, 0x8000, + 0x7036, 0xd5b4, 0x0040, 0xa21f, 0x7030, 0x8000, 0x7032, 0xd5ac, + 0x0040, 0xa226, 0x2071, 0xa34a, 0x1078, 0xa237, 0x0e7f, 0x007f, + 0x127f, 0x007c, 0x127e, 0x007e, 0x0e7e, 0x2091, 0x8000, 0x2071, + 0xa342, 0x1078, 0xa237, 0x0e7f, 0x007f, 0x127f, 0x007c, 0x2e04, + 0x8000, 0x2072, 0x00c8, 0xa240, 0x8e70, 0x2e04, 0x8000, 0x2072, + 0x007c, 0x0e7e, 0x2071, 0xa340, 0x1078, 0xa237, 0x0e7f, 0x007c, + 0x0e7e, 0x2071, 0xa344, 0x1078, 0xa237, 0x0e7f, 0x007c, 0x0001, + 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080, 0x0100, + 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000, 0x6286 +}; +#ifdef UNIQUE_FW_NAME +unsigned short fw2100tp_length01 = 0x9260; +#else +unsigned short risc_code_length01 = 0x9260; +#endif + diff -urN linux-2.4.10/drivers/scsi/ql2200_fw.h linux-2.4.10-lia/drivers/scsi/ql2200_fw.h --- linux-2.4.10/drivers/scsi/ql2200_fw.h Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/scsi/ql2200_fw.h Mon Jul 23 14:12:06 2001 @@ -0,0 +1,5179 @@ +/************************************************************************ + * * + * --- ISP2200 Initiator/Target Firmware --- * + * with Fabric (Public Loop), Point-point, and * + * expanded LUN addressing for FCTAPE * + * * + ************************************************************************ + Copyright (C) 2000,2001 Qlogic Corporation + (www.qlogic.com) + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + ************************************************************************/ +/* + * Firmware Version 2.01.34 (18:00 Jun 05, 2001) + */ + +#ifdef UNIQUE_FW_NAME +unsigned short fw2200tp_version = 2*1024+1; +#else +unsigned short risc_code_version = 2*1024+1; +#endif + +#ifdef UNIQUE_FW_NAME +unsigned char fw2200tp_version_str[] = {2,1,34}; +#else +unsigned char firmware_version[] = {2,1,34}; +#endif + +#ifdef UNIQUE_FW_NAME +#define fw2200tp_VERSION_STRING "2.01.34" +#else +#define FW_VERSION_STRING "2.01.34" +#endif + +#ifdef UNIQUE_FW_NAME +unsigned short fw2200tp_addr01 = 0x1000 ; +#else +unsigned short risc_code_addr01 = 0x1000 ; +#endif + +#ifdef UNIQUE_FW_NAME +unsigned short fw2200tp_code01[] = { +#else +unsigned short risc_code01[] = { +#endif + 0x0470, 0x0000, 0x0000, 0xa019, 0x0000, 0x0002, 0x0001, 0x0022, + 0x0017, 0x2043, 0x4f50, 0x5952, 0x4947, 0x4854, 0x2032, 0x3030, + 0x3120, 0x514c, 0x4f47, 0x4943, 0x2043, 0x4f52, 0x504f, 0x5241, + 0x5449, 0x4f4e, 0x2049, 0x5350, 0x3232, 0x3030, 0x2046, 0x6972, + 0x6d77, 0x6172, 0x6520, 0x2056, 0x6572, 0x7369, 0x6f6e, 0x2030, + 0x322e, 0x3031, 0x2e33, 0x3420, 0x2020, 0x2020, 0x2400, 0x20c1, + 0x0005, 0x2001, 0x017f, 0x2003, 0x0000, 0x20c9, 0xb5ff, 0x2091, + 0x2000, 0x2059, 0x0000, 0x2b78, 0x7823, 0x0004, 0x2089, 0x2843, + 0x2051, 0xb100, 0x2a70, 0x2029, 0xe800, 0x2031, 0xffff, 0x2039, + 0xe7e9, 0x2021, 0x0200, 0x0804, 0x144d, 0x20a1, 0xb019, 0xa00e, + 0x20a9, 0x07e7, 0x41a4, 0x3400, 0x755e, 0x7662, 0x775a, 0x7466, + 0x746a, 0x20a1, 0xb800, 0x7160, 0x810d, 0x810d, 0x810d, 0x810d, + 0xa18c, 0x000f, 0x2001, 0x000b, 0xa112, 0xa00e, 0x21a8, 0x41a4, + 0x3400, 0x8211, 0x1dd8, 0x7160, 0x3400, 0xa102, 0x0120, 0x0218, + 0x20a8, 0xa00e, 0x41a4, 0x3800, 0xd08c, 0x01d8, 0x2009, 0xb100, + 0x810d, 0x810d, 0x810d, 0x810d, 0xa18c, 0x000f, 0x2001, 0x0001, + 0xa112, 0x20a1, 0x1000, 0xa00e, 0x21a8, 0x41a4, 0x8211, 0x1de0, + 0x2009, 0xb100, 0x3400, 0xa102, 0x0120, 0x0218, 0x20a8, 0xa00e, + 0x41a4, 0x080c, 0x1400, 0x080c, 0x1617, 0x080c, 0x17b0, 0x080c, + 0x1ebd, 0x080c, 0x4a74, 0x080c, 0x828d, 0x080c, 0x15a0, 0x080c, + 0x2d8c, 0x080c, 0x5b8b, 0x080c, 0x51aa, 0x080c, 0x668a, 0x080c, + 0x23ea, 0x080c, 0x68d4, 0x080c, 0x6194, 0x080c, 0x22de, 0x080c, + 0x23b8, 0x2091, 0x3009, 0x7823, 0x0000, 0x1004, 0x10c5, 0x7820, + 0xa086, 0x0002, 0x1150, 0x7823, 0x4000, 0x0e04, 0x10bd, 0x781b, + 0x0001, 0x2091, 0x5000, 0x2091, 0x4080, 0x2a70, 0x7003, 0x0000, + 0x2a70, 0x7000, 0xa08e, 0x0003, 0x1158, 0x080c, 0x3d97, 0x080c, + 0x2db3, 0x080c, 0x5bd9, 0x080c, 0x5359, 0x080c, 0x66b4, 0x0c80, + 0x000b, 0x0c98, 0x10e4, 0x10e5, 0x1207, 0x10e2, 0x12d0, 0x13fd, + 0x13fe, 0x13ff, 0x080c, 0x14fa, 0x0005, 0x0126, 0x00f6, 0x2091, + 0x8000, 0x7000, 0xa086, 0x0001, 0x1904, 0x11d5, 0x080c, 0x156d, + 0x080c, 0x58d5, 0x0150, 0x080c, 0x58fb, 0x15a0, 0x2079, 0x0100, + 0x7828, 0xa085, 0x1800, 0x782a, 0x0468, 0x080c, 0x5816, 0x7000, + 0xa086, 0x0001, 0x1904, 0x11d5, 0x7088, 0xa086, 0x0028, 0x1904, + 0x11d5, 0x2001, 0x0161, 0x2003, 0x0001, 0x2079, 0x0100, 0x7827, + 0xffff, 0x7a28, 0xa295, 0x1e2f, 0x7a2a, 0x2011, 0x57ea, 0x080c, + 0x6742, 0x2011, 0x57f7, 0x080c, 0x6742, 0x2011, 0x494f, 0x080c, + 0x6742, 0x2011, 0x8030, 0x2019, 0x0000, 0x7087, 0x0000, 0x080c, + 0x1d33, 0x00e8, 0x080c, 0x4305, 0x2079, 0x0100, 0x7844, 0xa005, + 0x1904, 0x11d5, 0x2011, 0x494f, 0x080c, 0x6742, 0x2011, 0x57f7, + 0x080c, 0x6742, 0x080c, 0x1d33, 0x2001, 0xb38d, 0x2004, 0x780e, + 0x7840, 0xa084, 0xfffb, 0x7842, 0x2011, 0x8010, 0x73c8, 0x080c, + 0x3d5b, 0x7238, 0xc284, 0x723a, 0x2001, 0xb10c, 0x200c, 0xc1ac, + 0x2102, 0x080c, 0x7c1d, 0x2011, 0x0004, 0x080c, 0x9870, 0x080c, + 0x50bf, 0x080c, 0x58d5, 0x0158, 0x080c, 0x4a5d, 0x0140, 0x7087, + 0x0001, 0x70c3, 0x0000, 0x080c, 0x44a2, 0x0804, 0x11d5, 0x080c, + 0x517b, 0x0120, 0x7a0c, 0xc2b4, 0x7a0e, 0x0050, 0x080c, 0x9c16, + 0x70d0, 0xd09c, 0x1128, 0x709c, 0xa005, 0x0110, 0x080c, 0x4a3b, + 0x70db, 0x0000, 0x70d7, 0x0000, 0x72d0, 0x080c, 0x58d5, 0x1178, + 0x2011, 0x0000, 0x0016, 0x080c, 0x27c4, 0x2019, 0xb38f, 0x211a, + 0x001e, 0x704f, 0xffff, 0x7053, 0x00ef, 0x7073, 0x0000, 0x2079, + 0xb152, 0x7804, 0xd0ac, 0x0108, 0xc295, 0x72d2, 0x080c, 0x58d5, + 0x0118, 0xa296, 0x0004, 0x0508, 0x2011, 0x0001, 0x080c, 0x9870, + 0x7097, 0x0000, 0x709b, 0xffff, 0x7003, 0x0002, 0x00fe, 0x080c, + 0x2991, 0x2011, 0x0005, 0x080c, 0x7d52, 0x080c, 0x6e9e, 0x080c, + 0x58d5, 0x0148, 0x00c6, 0x2061, 0x0100, 0x0016, 0x080c, 0x27c4, + 0x61e2, 0x001e, 0x00ce, 0x012e, 0x00d0, 0x7097, 0x0000, 0x709b, + 0xffff, 0x7003, 0x0002, 0x2011, 0x0005, 0x080c, 0x7d52, 0x080c, + 0x6e9e, 0x080c, 0x58d5, 0x0148, 0x00c6, 0x2061, 0x0100, 0x0016, + 0x080c, 0x27c4, 0x61e2, 0x001e, 0x00ce, 0x00fe, 0x012e, 0x0005, + 0x00c6, 0x080c, 0x58d5, 0x1118, 0x20a9, 0x0100, 0x0010, 0x20a9, + 0x0082, 0x080c, 0x58d5, 0x1118, 0x2009, 0x0000, 0x0010, 0x2009, + 0x007e, 0x0016, 0x0026, 0x0036, 0x2110, 0x0026, 0x2019, 0x0029, + 0x080c, 0x7f67, 0x002e, 0x080c, 0xaf53, 0x003e, 0x002e, 0x001e, + 0x080c, 0x2c6e, 0x8108, 0x1f04, 0x11e9, 0x00ce, 0x706f, 0x0000, + 0x7070, 0xa084, 0x00ff, 0x7072, 0x709f, 0x0000, 0x0005, 0x0126, + 0x2091, 0x8000, 0x7000, 0xa086, 0x0002, 0x1904, 0x12ce, 0x7098, + 0xa086, 0xffff, 0x0130, 0x080c, 0x2991, 0x080c, 0x6e9e, 0x0804, + 0x12ce, 0x70d0, 0xd0ac, 0x1110, 0xd09c, 0x0540, 0xd084, 0x0530, + 0x0006, 0x0016, 0x2001, 0x0103, 0x2009, 0xb38d, 0x210c, 0x2102, + 0x001e, 0x000e, 0xd08c, 0x01d0, 0x70d4, 0xa086, 0xffff, 0x0190, + 0x080c, 0x2af0, 0x080c, 0x6e9e, 0x70d0, 0xd094, 0x1904, 0x12ce, + 0x2011, 0x0001, 0x2019, 0x0000, 0x080c, 0x2b26, 0x080c, 0x6e9e, + 0x0804, 0x12ce, 0x70d8, 0xa005, 0x1904, 0x12ce, 0x7094, 0xa005, + 0x1904, 0x12ce, 0x70d0, 0xd0a4, 0x0118, 0xd0b4, 0x0904, 0x12ce, + 0x080c, 0x517b, 0x1904, 0x12ce, 0x2001, 0xb153, 0x2004, 0xd0ac, + 0x01c8, 0x0156, 0x00c6, 0x20a9, 0x007f, 0x2009, 0x0000, 0x0016, + 0x080c, 0x4e21, 0x1118, 0x6000, 0xd0ec, 0x1138, 0x001e, 0x8108, + 0x1f04, 0x125f, 0x00ce, 0x015e, 0x0028, 0x001e, 0x00ce, 0x015e, + 0x0804, 0x12ce, 0x0006, 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0x000e, 0x0005, 0xa182, 0x0085, 0x0002, + 0x9311, 0x930f, 0x930f, 0x931d, 0x930f, 0x930f, 0x930f, 0x080c, + 0x14fa, 0x6003, 0x0001, 0x6106, 0x080c, 0x69f6, 0x0126, 0x2091, + 0x8000, 0x080c, 0x6e9e, 0x012e, 0x0005, 0x0026, 0x0056, 0x00d6, + 0x00e6, 0x2071, 0xb680, 0x7224, 0x6212, 0x7220, 0x080c, 0x985a, + 0x01a0, 0x2268, 0x6800, 0xa086, 0x0000, 0x0178, 0x6018, 0x6d18, + 0xa52e, 0x1158, 0x00c6, 0x2d60, 0x080c, 0x954f, 0x00ce, 0x0128, + 0x6803, 0x0002, 0x6007, 0x0086, 0x0010, 0x6007, 0x0087, 0x6003, + 0x0001, 0x080c, 0x69f6, 0x080c, 0x6e9e, 0x00f6, 0x2278, 0x080c, + 0x5177, 0x00fe, 0x0150, 0x6820, 0xd0ec, 0x0138, 0x00c6, 0x2260, + 0x603f, 0x0000, 0x080c, 0x9b43, 0x00ce, 0x00ee, 0x00de, 0x005e, + 0x002e, 0x0005, 0xa186, 0x0013, 0x1160, 0x6004, 0xa08a, 0x0085, + 0x0a0c, 0x14fa, 0xa08a, 0x008c, 0x1a0c, 0x14fa, 0xa082, 0x0085, + 0x0072, 0xa186, 0x0027, 0x0120, 0xa186, 0x0014, 0x190c, 0x14fa, + 0x080c, 0x6dc1, 0x080c, 0x9a2b, 0x080c, 0x6e9e, 0x0005, 0x937e, + 0x9380, 0x9380, 0x937e, 0x937e, 0x937e, 0x937e, 0x080c, 0x14fa, + 0x080c, 0x6dc1, 0x080c, 0x9a2b, 0x080c, 0x6e9e, 0x0005, 0xa186, + 0x0013, 0x1128, 0x6004, 0xa082, 0x0085, 0x2008, 0x04a8, 0xa186, + 0x0027, 0x11e8, 0x080c, 0x6dc1, 0x080c, 0x2b73, 0x00d6, 0x6010, + 0x2068, 0x080c, 0x986a, 0x0150, 0x6837, 0x0103, 0x6847, 0x0000, + 0x684b, 0x0029, 0x080c, 0x5271, 0x080c, 0x9a1f, 0x00de, 0x080c, + 0x82eb, 0x080c, 0x6e9e, 0x0005, 0x080c, 0x8331, 0x0ce0, 0xa186, + 0x0014, 0x1dd0, 0x080c, 0x6dc1, 0x00d6, 0x6010, 0x2068, 0x080c, + 0x986a, 0x0d60, 0x6837, 0x0103, 0x6847, 0x0000, 0x684b, 0x0006, + 0x6850, 0xc0ec, 0x6852, 0x08f0, 0x0002, 0x93ce, 0x93cc, 0x93cc, + 0x93cc, 0x93cc, 0x93cc, 0x93e6, 0x080c, 0x14fa, 0x080c, 0x6dc1, + 0x6030, 0xa08c, 0xff00, 0x810f, 0xa186, 0x0039, 0x0118, 0xa186, + 0x0035, 0x1118, 0x2001, 0xb3b5, 0x0010, 0x2001, 0xb3b6, 0x2004, + 0x6016, 0x6003, 0x000c, 0x080c, 0x6e9e, 0x0005, 0x080c, 0x6dc1, + 0x6030, 0xa08c, 0xff00, 0x810f, 0xa186, 0x0039, 0x0118, 0xa186, + 0x0035, 0x1118, 0x2001, 0xb3b5, 0x0010, 0x2001, 0xb3b6, 0x2004, + 0x6016, 0x6003, 0x000e, 0x080c, 0x6e9e, 0x0005, 0xa182, 0x008c, + 0x1220, 0xa182, 0x0085, 0x0208, 0x001a, 0x080c, 0x8331, 0x0005, + 0x940f, 0x940f, 0x940f, 0x940f, 0x9411, 0x9464, 0x940f, 0x080c, + 0x14fa, 0x00d6, 0x00f6, 0x2c78, 0x080c, 0x5177, 0x00fe, 0x0168, + 0x6030, 0xa08c, 0xff00, 0x810f, 0xa186, 0x0039, 0x0118, 0xa186, + 0x0035, 0x1118, 0x00de, 0x0804, 0x9477, 0x080c, 0x9a1f, 0x080c, + 0x986a, 0x01c8, 0x6010, 0x2068, 0x6837, 0x0103, 0x6850, 0xd0b4, + 0x0128, 0x684b, 0x0006, 0xc0ec, 0x6852, 0x0048, 0xd0bc, 0x0118, + 0x684b, 0x0002, 0x0020, 0x684b, 0x0005, 0x080c, 0x9ae0, 0x6847, + 0x0000, 0x080c, 0x5271, 0x2c68, 0x080c, 0x8295, 0x01c0, 0x6003, + 0x0001, 0x6007, 0x001e, 0x600b, 0xffff, 0x2009, 0xb68e, 0x210c, + 0x6136, 0x2009, 0xb68f, 0x210c, 0x613a, 0x6918, 0x611a, 0x080c, + 0x9c35, 0x6950, 0x6152, 0x601f, 0x0001, 0x080c, 0x69f6, 0x2d60, + 0x080c, 0x82eb, 0x00de, 0x0005, 0x00f6, 0x2c78, 0x080c, 0x5177, + 0x00fe, 0x0598, 0x6030, 0xa08c, 0xff00, 0x810f, 0xa186, 0x0035, + 0x0130, 0xa186, 0x001e, 0x0118, 0xa186, 0x0039, 0x1530, 0x00d6, + 0x2c68, 0x080c, 0x9d16, 0x1904, 0x94bc, 0x080c, 0x8295, 0x01d8, + 0x6106, 0x6003, 0x0001, 0x601f, 0x0001, 0x6918, 0x611a, 0x6928, + 0x612a, 0x692c, 0x612e, 0x6930, 0xa18c, 0x00ff, 0x6132, 0x6934, + 0x6136, 0x6938, 0x613a, 0x6950, 0x6152, 0x080c, 0x9c35, 0x080c, + 0x69f6, 0x080c, 0x6e9e, 0x2d60, 0x00f8, 0x00d6, 0x6010, 0x2068, + 0x080c, 0x986a, 0x01c8, 0x6837, 0x0103, 0x6850, 0xd0b4, 0x0128, + 0xc0ec, 0x6852, 0x684b, 0x0006, 0x0048, 0xd0bc, 0x0118, 0x684b, + 0x0002, 0x0020, 0x684b, 0x0005, 0x080c, 0x9ae0, 0x6847, 0x0000, + 0x080c, 0x5271, 0x080c, 0x9a1f, 0x00de, 0x080c, 0x82eb, 0x0005, + 0x0016, 0x00d6, 0x6010, 0x2068, 0x080c, 0x986a, 0x0140, 0x6837, + 0x0103, 0x684b, 0x0028, 0x6847, 0x0000, 0x080c, 0x5271, 0x00de, + 0x001e, 0xa186, 0x0013, 0x0148, 0xa186, 0x0014, 0x0130, 0xa186, + 0x0027, 0x0118, 0x080c, 0x8331, 0x0030, 0x080c, 0x6dc1, 0x080c, + 0x9a2b, 0x080c, 0x6e9e, 0x0005, 0x0056, 0x0066, 0x00d6, 0x00f6, + 0x2029, 0x0001, 0xa182, 0x0101, 0x1208, 0x0010, 0x2009, 0x0100, + 0x2130, 0x2069, 0xb698, 0x831c, 0x2300, 0xad18, 0x2009, 0x0020, + 0xaf90, 0x001d, 0x080c, 0x953f, 0xa6b2, 0x0020, 0x7804, 0xa06d, + 0x0110, 0x080c, 0x1604, 0x080c, 0x15dd, 0x0500, 0x8528, 0x6837, + 0x0110, 0x683b, 0x0000, 0x2d20, 0x7c06, 0xa68a, 0x003d, 0x1228, + 0x2608, 0xad90, 0x000f, 0x0459, 0x0088, 0xa6b2, 0x003c, 0x2009, + 0x003c, 0x2d78, 0xad90, 0x000f, 0x0411, 0x0c28, 0x00fe, 0x852f, + 0xa5ad, 0x0003, 0x7d36, 0xa5ac, 0x0000, 0x0028, 0x00fe, 0x852f, + 0xa5ad, 0x0003, 0x7d36, 0x00de, 0x006e, 0x005e, 0x0005, 0x00f6, + 0x8dff, 0x0158, 0x6804, 0xa07d, 0x0130, 0x6807, 0x0000, 0x080c, + 0x5271, 0x2f68, 0x0cb8, 0x080c, 0x5271, 0x00fe, 0x0005, 0x0156, + 0xa184, 0x0001, 0x0108, 0x8108, 0x810c, 0x21a8, 0x2304, 0x8007, + 0x2012, 0x8318, 0x8210, 0x1f04, 0x9546, 0x015e, 0x0005, 0x0066, + 0x0126, 0x2091, 0x8000, 0x2031, 0x0001, 0x601c, 0xa084, 0x000f, + 0x0083, 0x012e, 0x006e, 0x0005, 0x0126, 0x2091, 0x8000, 0x0066, + 0x2031, 0x0000, 0x601c, 0xa084, 0x000f, 0x001b, 0x006e, 0x012e, + 0x0005, 0x9586, 0x9586, 0x9581, 0x95a8, 0x9574, 0x9581, 0x95a8, + 0x9581, 0x9581, 0x9574, 0x9581, 0x080c, 0x14fa, 0x0036, 0x2019, + 0x0010, 0x080c, 0xa8af, 0x601f, 0x0006, 0x6003, 0x0007, 0x003e, + 0x0005, 0xa006, 0x0005, 0xa085, 0x0001, 0x0005, 0x00d6, 0x86ff, + 0x11d8, 0x6010, 0x2068, 0x080c, 0x986a, 0x01c0, 0x6834, 0xa086, + 0x0139, 0x1128, 0x684b, 0x0005, 0x6853, 0x0000, 0x0028, 0xa00e, + 0x2001, 0x0005, 0x080c, 0x5344, 0x080c, 0x9ae0, 0x080c, 0x5271, + 0x080c, 0x82eb, 0xa085, 0x0001, 0x00de, 0x0005, 0xa006, 0x0ce0, + 0x6000, 0xa08a, 0x0010, 0x1a0c, 0x14fa, 0x000b, 0x0005, 0x95bf, + 0x95e0, 0x95c1, 0x95ff, 0x95dd, 0x95bf, 0x9581, 0x9586, 0x9586, + 0x9581, 0x9581, 0x9581, 0x9581, 0x9581, 0x9581, 0x9581, 0x080c, + 0x14fa, 0x86ff, 0x11b8, 0x601c, 0xa086, 0x0006, 0x0198, 0x00d6, + 0x6010, 0x2068, 0x080c, 0x986a, 0x0110, 0x080c, 0x9ae0, 0x00de, + 0x6007, 0x0085, 0x6003, 0x000b, 0x601f, 0x0002, 0x080c, 0x69f6, + 0x080c, 0x6e9e, 0xa085, 0x0001, 0x0005, 0x080c, 0x190f, 0x0c08, + 0x00e6, 0x2071, 0xb3d9, 0x7024, 0xac06, 0x1110, 0x080c, 0x7c41, + 0x601c, 0xa084, 0x000f, 0xa086, 0x0006, 0x1150, 0x0086, 0x0096, + 0x2049, 0x0001, 0x2c40, 0x080c, 0x7e0d, 0x009e, 0x008e, 0x0010, + 0x080c, 0x7b3e, 0x00ee, 0x1928, 0x080c, 0x9581, 0x0005, 0x0036, + 0x00e6, 0x2071, 0xb3d9, 0x703c, 0xac06, 0x1140, 0x2019, 0x0000, + 0x080c, 0x7cc4, 0x00ee, 0x003e, 0x0804, 0x95c1, 0x080c, 0x7f2b, + 0x00ee, 0x003e, 0x1904, 0x95c1, 0x080c, 0x9581, 0x0005, 0x00c6, + 0x601c, 0xa084, 0x000f, 0x0013, 0x00ce, 0x0005, 0x9630, 0x969a, + 0x97c8, 0x963b, 0x9a2b, 0x9630, 0xa8a1, 0x82eb, 0x969a, 0x9629, + 0x9833, 0x080c, 0x14fa, 0x080c, 0x9a66, 0x1110, 0x080c, 0x8890, + 0x0005, 0x080c, 0x6dc1, 0x080c, 0x6e9e, 0x080c, 0x82eb, 0x0005, + 0x6017, 0x0001, 0x0005, 0x6010, 0xa080, 0x0019, 0x2c02, 0x6000, + 0xa08a, 0x0010, 0x1a0c, 0x14fa, 0x000b, 0x0005, 0x9656, 0x9658, + 0x9678, 0x968a, 0x9697, 0x9656, 0x9630, 0x9630, 0x9630, 0x968a, + 0x968a, 0x9656, 0x9656, 0x9656, 0x9656, 0x9694, 0x080c, 0x14fa, + 0x00e6, 0x6010, 0x2070, 0x7050, 0xc0b5, 0x7052, 0x2071, 0xb3d9, + 0x7024, 0xac06, 0x0190, 0x080c, 0x7b3e, 0x6007, 0x0085, 0x6003, + 0x000b, 0x601f, 0x0002, 0x2001, 0xb3b6, 0x2004, 0x6016, 0x080c, + 0x69f6, 0x080c, 0x6e9e, 0x00ee, 0x0005, 0x6017, 0x0001, 0x0cd8, + 0x00d6, 0x6010, 0x2068, 0x6850, 0xc0b5, 0x6852, 0x00de, 0x6007, + 0x0085, 0x6003, 0x000b, 0x601f, 0x0002, 0x080c, 0x69f6, 0x080c, + 0x6e9e, 0x0005, 0x00d6, 0x6017, 0x0001, 0x6010, 0x2068, 0x6850, + 0xc0b5, 0x6852, 0x00de, 0x0005, 0x080c, 0x82eb, 0x0005, 0x080c, + 0x190f, 0x08f0, 0x6000, 0xa08a, 0x0010, 0x1a0c, 0x14fa, 0x000b, + 0x0005, 0x96b1, 0x9638, 0x96b3, 0x96b1, 0x96b3, 0x96b3, 0x9631, + 0x96b1, 0x962b, 0x962b, 0x96b1, 0x96b1, 0x96b1, 0x96b1, 0x96b1, + 0x96b1, 0x080c, 0x14fa, 0x00d6, 0x6018, 0x2068, 0x6804, 0xa084, + 0x00ff, 0x00de, 0xa08a, 0x000c, 0x1a0c, 0x14fa, 0x000b, 0x0005, + 0x96cc, 0x976e, 0x96ce, 0x9708, 0x96ce, 0x9708, 0x96ce, 0x96d8, + 0x96cc, 0x9708, 0x96cc, 0x96f4, 0x080c, 0x14fa, 0x6004, 0xa08e, + 0x0016, 0x0588, 0xa08e, 0x0004, 0x0570, 0xa08e, 0x0002, 0x0558, + 0x6004, 0x080c, 0x9a66, 0x0904, 0x9787, 0xa08e, 0x0021, 0x0904, + 0x978b, 0xa08e, 0x0022, 0x0904, 0x9787, 0xa08e, 0x003d, 0x0904, + 0x978b, 0xa08e, 0x0039, 0x0904, 0x978f, 0xa08e, 0x0035, 0x0904, + 0x978f, 0xa08e, 0x001e, 0x0188, 0xa08e, 0x0001, 0x1150, 0x00d6, + 0x6018, 0x2068, 0x6804, 0xa084, 0x00ff, 0x00de, 0xa086, 0x0006, + 0x0110, 0x080c, 0x2b73, 0x080c, 0x8890, 0x080c, 0x9a2b, 0x0005, + 0x00c6, 0x00d6, 0x6104, 0xa186, 0x0016, 0x0904, 0x975f, 0xa186, + 0x0002, 0x1518, 0x6018, 0x2068, 0x2001, 0xb134, 0x2004, 0xd0ac, + 0x1904, 0x97b1, 0x68a0, 0xd0bc, 0x1904, 0x97b1, 0x6840, 0xa084, + 0x00ff, 0xa005, 0x0190, 0x8001, 0x6842, 0x6013, 0x0000, 0x601f, + 0x0007, 0x6017, 0x0398, 0x603f, 0x0000, 0x080c, 0x8295, 0x0128, + 0x2d00, 0x601a, 0x601f, 0x0001, 0x0450, 0x00de, 0x00ce, 0x6004, + 0xa08e, 0x0002, 0x11a8, 0x6018, 0xa080, 0x0028, 0x2004, 0xa086, + 0x007e, 0x1170, 0x2009, 0xb134, 0x2104, 0xc085, 0x200a, 0x00e6, + 0x2071, 0xb100, 0x080c, 0x4a3b, 0x00ee, 0x080c, 0x8890, 0x0020, + 0x080c, 0x8890, 0x080c, 0x2b73, 0x00e6, 0x0126, 0x2091, 0x8000, + 0x080c, 0x2b99, 0x012e, 0x00ee, 0x080c, 0x9a2b, 0x0005, 0x2001, + 0x0002, 0x080c, 0x4d75, 0x6003, 0x0001, 0x6007, 0x0002, 0x080c, + 0x6a3c, 0x080c, 0x6e9e, 0x00de, 0x00ce, 0x0c80, 0x00c6, 0x00d6, + 0x6104, 0xa186, 0x0016, 0x0d58, 0x6018, 0x2068, 0x6840, 0xa084, + 0x00ff, 0xa005, 0x0904, 0x9735, 0x8001, 0x6842, 0x6003, 0x0001, + 0x080c, 0x6a3c, 0x080c, 0x6e9e, 0x00de, 0x00ce, 0x08b8, 0x080c, + 0x8890, 0x0804, 0x9705, 0x080c, 0x88be, 0x0804, 0x9705, 0x00d6, + 0x2c68, 0x6104, 0x080c, 0x9d16, 0x00de, 0x0118, 0x080c, 0x82eb, + 0x00b8, 0x6004, 0x8007, 0x6130, 0xa18c, 0x00ff, 0xa105, 0x6032, + 0x6007, 0x0085, 0x6003, 0x000b, 0x601f, 0x0002, 0x6038, 0x600a, + 0x2001, 0xb3b6, 0x2004, 0x6016, 0x080c, 0x69f6, 0x080c, 0x6e9e, + 0x0005, 0x00de, 0x00ce, 0x080c, 0x8890, 0x080c, 0x2b73, 0x00e6, + 0x0126, 0x2091, 0x8000, 0x080c, 0x2b99, 0x6013, 0x0000, 0x601f, + 0x0007, 0x6017, 0x0398, 0x603f, 0x0000, 0x012e, 0x00ee, 0x0005, + 0x6000, 0xa08a, 0x0010, 0x1a0c, 0x14fa, 0x000b, 0x0005, 0x97df, + 0x97df, 0x97df, 0x97df, 0x97df, 0x97df, 0x97df, 0x97df, 0x97df, + 0x9630, 0x97df, 0x9638, 0x97e1, 0x9638, 0x97ee, 0x97df, 0x080c, + 0x14fa, 0x6004, 0xa086, 0x008b, 0x0148, 0x6007, 0x008b, 0x6003, + 0x000d, 0x080c, 0x69f6, 0x080c, 0x6e9e, 0x0005, 0x080c, 0x9a1f, + 0x080c, 0x986a, 0x0580, 0x080c, 0x2b73, 0x00d6, 0x080c, 0x986a, + 0x0168, 0x6010, 0x2068, 0x6837, 0x0103, 0x684b, 0x0006, 0x6847, + 0x0000, 0x6850, 0xc0ed, 0x6852, 0x080c, 0x5271, 0x2c68, 0x080c, + 0x8295, 0x0150, 0x6818, 0x601a, 0x080c, 0x9c35, 0x00c6, 0x2d60, + 0x080c, 0x9a2b, 0x00ce, 0x0008, 0x2d60, 0x00de, 0x6013, 0x0000, + 0x601f, 0x0001, 0x6007, 0x0001, 0x6003, 0x0001, 0x080c, 0x6a3c, + 0x080c, 0x6e9e, 0x0078, 0x6030, 0xa08c, 0xff00, 0x810f, 0xa186, + 0x0039, 0x0118, 0xa186, 0x0035, 0x1118, 0x080c, 0x2b73, 0x08b0, + 0x080c, 0x9a2b, 0x0005, 0x6000, 0xa08a, 0x0010, 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0x0076, 0x0056, 0x6218, 0x0086, 0x2041, 0x0000, 0x2029, 0x0001, + 0x2019, 0x0048, 0x0096, 0x2049, 0x0000, 0x080c, 0x7e0d, 0x009e, + 0x008e, 0x2039, 0x0000, 0x080c, 0x7ea7, 0x2c20, 0x080c, 0xab57, + 0x005e, 0x007e, 0x0005, 0x0026, 0x0046, 0x0056, 0x0076, 0x00c6, + 0x0156, 0x2c20, 0x20a9, 0x007f, 0x2009, 0x0000, 0x0016, 0x0036, + 0x080c, 0x4e21, 0x11c0, 0x2c10, 0x0086, 0x2041, 0x0000, 0x2828, + 0x0046, 0x2021, 0x0001, 0x080c, 0xaee2, 0x004e, 0x0096, 0x2049, + 0x0000, 0x080c, 0x7e0d, 0x009e, 0x008e, 0x2039, 0x0000, 0x080c, + 0x7ea7, 0x080c, 0xab57, 0x003e, 0x001e, 0x8108, 0x1f04, 0xac36, + 0x015e, 0x00ce, 0x007e, 0x005e, 0x004e, 0x002e, 0x0005, 0x0016, + 0x00f6, 0x3800, 0xd08c, 0x0130, 0xad82, 0x1000, 0x02b0, 0xad82, + 0xb100, 0x0230, 0xad82, 0xe800, 0x0280, 0xad82, 0xffff, 0x1268, + 0x6800, 0xa07d, 0x0138, 0x6803, 0x0000, 0x6b52, 0x080c, 0x5271, + 0x2f68, 0x0cb0, 0x6b52, 0x080c, 0x5271, 0x00fe, 0x001e, 0x0005, + 0x00e6, 0x0046, 0x0036, 0x2061, 0xb800, 0xa005, 0x1138, 0x2071, + 0xb100, 0x7444, 0x7064, 0x8001, 0xa402, 0x12d8, 0x2100, 0xac06, + 0x0168, 0x6000, 0xa086, 0x0000, 0x0148, 0x6008, 0xa206, 0x1130, + 0x6018, 0xa1a0, 0x0006, 0x2424, 0xa406, 0x0140, 0xace0, 0x0018, + 0x2001, 0xb116, 0x2004, 0xac02, 0x1220, 0x0c40, 0xa085, 0x0001, + 0x0008, 0xa006, 0x003e, 0x004e, 0x00ee, 0x0005, 0x00d6, 0x0006, + 0x080c, 0x15dd, 0x000e, 0x090c, 0x14fa, 0x6837, 0x010d, 0x685e, + 0x0026, 0x2010, 0x080c, 0x985a, 0x2001, 0x0000, 0x0120, 0x2200, + 0xa080, 0x0014, 0x2004, 0x002e, 0x684a, 0x6956, 0x6c46, 0x684f, + 0x0000, 0x2001, 0xb3bd, 0x2004, 0x6852, 0xa006, 0x68b2, 0x6802, + 0x683a, 0x685a, 0x080c, 0x5271, 0x00de, 0x0005, 0x6700, 0xa786, + 0x0000, 0x0158, 0xa786, 0x0001, 0x0140, 0xa786, 0x000a, 0x0128, + 0xa786, 0x0009, 0x0110, 0xa085, 0x0001, 0x0005, 0x00e6, 0x6018, + 0x2070, 0x70a0, 0xa206, 0x00ee, 0x0005, 0x0016, 0x6004, 0xa08e, + 0x001e, 0x11a0, 0x8007, 0x6130, 0xa18c, 0x00ff, 0xa105, 0x6032, + 0x6007, 0x0085, 0x6003, 0x000b, 0x601f, 0x0005, 0x2001, 0xb3b6, + 0x2004, 0x6016, 0x080c, 0x69f6, 0x080c, 0x6e9e, 0x001e, 0x0005, + 0xe000, 0xe000, 0x0005, 0x6020, 0xd0e4, 0x0158, 0xd0cc, 0x0118, + 0x080c, 0x9b43, 0x0030, 0x080c, 0xaf00, 0x080c, 0x6866, 0x080c, + 0x82eb, 0x0005, 0xa280, 0x0007, 0x2004, 0xa084, 0x000f, 0x0002, + 0xad29, 0xad29, 0xad29, 0xad2e, 0xad29, 0xad2b, 0xad2b, 0xad29, + 0xad2b, 0xa006, 0x0005, 0x00c6, 0x2260, 0x00ce, 0xa085, 0x0001, + 0x0005, 0xa280, 0x0007, 0x2004, 0xa084, 0x000f, 0x0002, 0xad40, + 0xad40, 0xad40, 0xad40, 0xad40, 0xad40, 0xad4b, 0xad40, 0xad40, + 0x6007, 0x003b, 0x602b, 0x0009, 0x6013, 0x2a00, 0x6003, 0x0001, + 0x080c, 0x69f6, 0x0005, 0x00c6, 0x2260, 0x080c, 0xaf00, 0x603f, + 0x0000, 0x6020, 0xc0f4, 0xc0cc, 0x6022, 0x6037, 0x0000, 0x00ce, + 0x00d6, 0x2268, 0xa186, 0x0007, 0x1904, 0xada6, 0x6810, 0xa005, + 0x0138, 0xa080, 0x0013, 0x2004, 0xd0fc, 0x1110, 0x00de, 0x08c0, + 0x6007, 0x003a, 0x6003, 0x0001, 0x080c, 0x69f6, 0x080c, 0x6e9e, + 0x00c6, 0x2d60, 0x6100, 0xa186, 0x0002, 0x1904, 0xae2f, 0x6010, + 0xa005, 0x1138, 0x6000, 0xa086, 0x0007, 0x190c, 0x14fa, 0x0804, + 0xae2f, 0xa08c, 0xf000, 0x1130, 0x0028, 0x2068, 0x6800, 0xa005, + 0x1de0, 0x2d00, 0xa080, 0x0013, 0x2004, 0xa084, 0x0003, 0xa086, + 0x0002, 0x1180, 0x6010, 0x2068, 0x684c, 0xc0dc, 0xc0f4, 0x684e, + 0x6850, 0xc0f4, 0xc0fc, 0x6852, 0x2009, 0x0043, 0x080c, 0xa727, + 0x0804, 0xae2f, 0x2009, 0x0041, 0x0804, 0xae29, 0xa186, 0x0005, + 0x15f0, 0x6810, 0xa080, 0x0013, 0x2004, 0xd0bc, 0x1118, 0x00de, + 0x0804, 0xad40, 0xd0b4, 0x0128, 0xd0fc, 0x090c, 0x14fa, 0x0804, + 0xad5e, 0x6007, 0x003a, 0x6003, 0x0001, 0x080c, 0x69f6, 0x080c, + 0x6e9e, 0x00c6, 0x2d60, 0x6100, 0xa186, 0x0002, 0x0120, 0xa186, + 0x0004, 0x1904, 0xae2f, 0x2071, 0xb419, 0x7000, 0xa086, 0x0003, + 0x1128, 0x7004, 0xac06, 0x1110, 0x7003, 0x0000, 0x6810, 0xa080, + 0x0013, 0x200c, 0xc1f4, 0xc1dc, 0x2102, 0x8000, 0x200c, 0xc1f4, + 0xc1fc, 0xc1bc, 0x2102, 0x2009, 0x0042, 0x0804, 0xae29, 0x0036, + 0x00d6, 0x00d6, 0x080c, 0x15dd, 0x003e, 0x090c, 0x14fa, 0x6837, + 0x010d, 0x6803, 0x0000, 0x683b, 0x0000, 0x685b, 0x0000, 0x6b5e, + 0x6857, 0x0045, 0x2c00, 0x6862, 0x6034, 0x6872, 0x2360, 0x6020, + 0xc0dd, 0x6022, 0x6018, 0xa080, 0x0028, 0x2004, 0xa084, 0x00ff, + 0x8007, 0x6350, 0x6b4a, 0x6846, 0x684f, 0x0000, 0x6853, 0x0000, + 0x6d6a, 0x6e66, 0x686f, 0x0001, 0x080c, 0x5271, 0x2019, 0x0045, + 0x6008, 0x2068, 0x080c, 0xa8af, 0x2d00, 0x600a, 0x601f, 0x0006, + 0x6003, 0x0007, 0x6017, 0x0000, 0x603f, 0x0000, 0x00de, 0x003e, + 0x0038, 0x603f, 0x0000, 0x6003, 0x0007, 0x080c, 0xa727, 0x00ce, + 0x00de, 0x0005, 0xa186, 0x0013, 0x1128, 0x6004, 0xa082, 0x0085, + 0x2008, 0x00c2, 0xa186, 0x0027, 0x1178, 0x080c, 0x6dc1, 0x0036, + 0x00d6, 0x6010, 0x2068, 0x2019, 0x0004, 0x080c, 0xac5f, 0x00de, + 0x003e, 0x080c, 0x6e9e, 0x0005, 0xa186, 0x0014, 0x0d70, 0x080c, + 0x8331, 0x0005, 0xae5b, 0xae59, 0xae59, 0xae59, 0xae59, 0xae59, + 0xae5b, 0x080c, 0x14fa, 0x080c, 0x6dc1, 0x6003, 0x000c, 0x080c, + 0x6e9e, 0x0005, 0xa182, 0x008c, 0x1220, 0xa182, 0x0085, 0x0208, + 0x001a, 0x080c, 0x8331, 0x0005, 0xae73, 0xae73, 0xae73, 0xae73, + 0xae75, 0xae93, 0xae73, 0x080c, 0x14fa, 0x00d6, 0x2c68, 0x080c, + 0x8295, 0x01a0, 0x6003, 0x0001, 0x6007, 0x001e, 0x2009, 0xb68e, + 0x210c, 0x6136, 0x2009, 0xb68f, 0x210c, 0x613a, 0x600b, 0xffff, + 0x6918, 0x611a, 0x601f, 0x0004, 0x080c, 0x69f6, 0x2d60, 0x080c, + 0x82eb, 0x00de, 0x0005, 0x080c, 0x82eb, 0x0005, 0x00e6, 0x6018, + 0x2070, 0x7000, 0xd0ec, 0x00ee, 0x0005, 0x6010, 0xa08c, 0xf000, + 0x0904, 0xaee1, 0xa080, 0x0013, 0x200c, 0xd1ec, 0x05d0, 0x2001, + 0xb172, 0x2004, 0xd0ec, 0x05a8, 0x6003, 0x0002, 0x6020, 0xc0e5, + 0x6022, 0xd1ac, 0x0180, 0x00f6, 0x2c78, 0x080c, 0x5173, 0x00fe, + 0x0150, 0x2001, 0xb3b7, 0x2004, 0x603e, 0x2009, 0xb172, 0x210c, + 0xd1f4, 0x11e8, 0x0080, 0x2009, 0xb172, 0x210c, 0xd1f4, 0x0128, + 0x6020, 0xc0e4, 0x6022, 0xa006, 0x00a0, 0x2001, 0xb3b7, 0x200c, + 0x8103, 0xa100, 0x603e, 0x6018, 0xa088, 0x002b, 0x2104, 0xa005, + 0x0118, 0xa088, 0x0003, 0x0cd0, 0x2c0a, 0x600f, 0x0000, 0xa085, + 0x0001, 0x0005, 0x0016, 0x00c6, 0x00e6, 0x6150, 0xa2f0, 0x002b, + 0x2e04, 0x2060, 0x8cff, 0x0180, 0x84ff, 0x1118, 0x6050, 0xa106, + 0x1138, 0x600c, 0x2072, 0x080c, 0x6866, 0x080c, 0x82eb, 0x0010, + 0xacf0, 0x0003, 0x2e64, 0x0c70, 0x00ee, 0x00ce, 0x001e, 0x0005, + 0x00d6, 0x6018, 0xa0e8, 0x002b, 0x2d04, 0xa005, 0x0140, 0xac06, + 0x0120, 0x2d04, 0xa0e8, 0x0003, 0x0cb8, 0x600c, 0x206a, 0x00de, + 0x0005, 0x0026, 0x0036, 0x0156, 0x2011, 0xb127, 0x2204, 0xa084, + 0x00ff, 0x2019, 0xb68e, 0x2334, 0xa636, 0x11d8, 0x8318, 0x2334, + 0x2204, 0xa084, 0xff00, 0xa636, 0x11a0, 0x2011, 0xb690, 0x6018, + 0xa098, 0x000a, 0x20a9, 0x0004, 0x080c, 0x8d2b, 0x1150, 0x2011, + 0xb694, 0x6018, 0xa098, 0x0006, 0x20a9, 0x0004, 0x080c, 0x8d2b, + 0x1100, 0x015e, 0x003e, 0x002e, 0x0005, 0x00e6, 0x2071, 0xb100, + 0x080c, 0x4a3b, 0x080c, 0x2991, 0x00ee, 0x0005, 0x00e6, 0x6018, + 0x2070, 0x7000, 0xd0fc, 0x0108, 0x0011, 0x00ee, 0x0005, 0x6850, + 0xc0e5, 0x6852, 0x0005, 0x00e6, 0x00c6, 0x0076, 0x0066, 0x0056, + 0x0046, 0x0026, 0x0016, 0x0126, 0x2091, 0x8000, 0x2029, 0xb3e2, + 0x252c, 0x2021, 0xb3e8, 0x2424, 0x2061, 0xb800, 0x2071, 0xb100, + 0x7644, 0x7064, 0xa606, 0x0578, 0x671c, 0xa786, 0x0001, 0x0118, + 0xa786, 0x0008, 0x1500, 0x2500, 0xac06, 0x01e8, 0x2400, 0xac06, + 0x01d0, 0x080c, 0xacd6, 0x01b8, 0x080c, 0xace6, 0x11a0, 0x6000, + 0xa086, 0x0004, 0x1120, 0x0016, 0x080c, 0x190f, 0x001e, 0x080c, + 0x9a55, 0x1110, 0x080c, 0x2b99, 0x080c, 0x9a66, 0x1110, 0x080c, + 0x8890, 0x080c, 0x9a2b, 0xace0, 0x0018, 0x2001, 0xb116, 0x2004, + 0xac02, 0x1208, 0x0858, 0x012e, 0x001e, 0x002e, 0x004e, 0x005e, + 0x006e, 0x007e, 0x00ce, 0x00ee, 0x0005, 0x0126, 0x0006, 0x00e6, + 0x2091, 0x8000, 0x2071, 0xb140, 0xd5a4, 0x0118, 0x7034, 0x8000, + 0x7036, 0xd5b4, 0x0118, 0x7030, 0x8000, 0x7032, 0xd5ac, 0x0118, + 0x2071, 0xb14a, 0x0451, 0x00ee, 0x000e, 0x012e, 0x0005, 0x0126, + 0x0006, 0x00e6, 0x2091, 0x8000, 0x2071, 0xb140, 0xd5a4, 0x0118, + 0x7034, 0x8000, 0x7036, 0xd5b4, 0x0118, 0x7030, 0x8000, 0x7032, + 0xd5ac, 0x0118, 0x2071, 0xb14a, 0x0081, 0x00ee, 0x000e, 0x012e, + 0x0005, 0x0126, 0x0006, 0x00e6, 0x2091, 0x8000, 0x2071, 0xb142, + 0x0021, 0x00ee, 0x000e, 0x012e, 0x0005, 0x2e04, 0x8000, 0x2072, + 0x1220, 0x8e70, 0x2e04, 0x8000, 0x2072, 0x0005, 0x00e6, 0x2071, + 0xb140, 0x0c99, 0x00ee, 0x0005, 0x00e6, 0x2071, 0xb144, 0x0c69, + 0x00ee, 0x0005, 0x0126, 0x0006, 0x00e6, 0x2091, 0x8000, 0x2071, + 0xb140, 0x7044, 0x8000, 0x7046, 0x00ee, 0x000e, 0x012e, 0x0005, + 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080, + 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000, + 0x5790 +}; +#ifdef UNIQUE_FW_NAME +unsigned short fw2200tp_length01 = 0xa019; +#else +unsigned short risc_code_length01 = 0xa019; +#endif + diff -urN linux-2.4.10/drivers/scsi/ql2300_fw.h linux-2.4.10-lia/drivers/scsi/ql2300_fw.h --- linux-2.4.10/drivers/scsi/ql2300_fw.h Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/scsi/ql2300_fw.h Mon Jul 23 14:12:14 2001 @@ -0,0 +1,5486 @@ +/************************************************************************ + * * + * --- ISP2300 Initiator/Target Firmware --- * + * with Fabric (Public Loop), Point-point, and * + * expanded LUN addressing for FCTAPE * + * * + ************************************************************************ + Copyright (C) 2000 and 2001 Qlogic Corporation + (www.qlogic.com) + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + ************************************************************************/ +/* + * Firmware Version 3.00.24 (14:18 Jun 05, 2001) + */ + +#ifdef UNIQUE_FW_NAME +unsigned short fw2300tp_version = 3*1024+0; +#else +unsigned short risc_code_version = 3*1024+0; +#endif + +#ifdef UNIQUE_FW_NAME +unsigned char fw2300tp_version_str[] = {3, 0,24}; +#else +unsigned char firmware_version[] = {3, 0,24}; +#endif + +#ifdef UNIQUE_FW_NAME +#define fw2300tp_VERSION_STRING "3.00.24" +#else +#define FW_VERSION_STRING "3.00.24" +#endif + +#ifdef UNIQUE_FW_NAME +unsigned short fw2300tp_addr01 = 0x0800 ; +#else +unsigned short risc_code_addr01 = 0x0800 ; +#endif + +#ifdef UNIQUE_FW_NAME +unsigned short fw2300tp_code01[] = { +#else +unsigned short risc_code01[] = { +#endif + 0x0470, 0x0000, 0x0000, 0xa9b8, 0x0000, 0x0003, 0x0000, 0x0018, + 0x0017, 0x2043, 0x4f50, 0x5952, 0x4947, 0x4854, 0x2032, 0x3030, + 0x3120, 0x514c, 0x4f47, 0x4943, 0x2043, 0x4f52, 0x504f, 0x5241, + 0x5449, 0x4f4e, 0x2049, 0x5350, 0x3233, 0x3030, 0x2046, 0x6972, + 0x6d77, 0x6172, 0x6520, 0x2056, 0x6572, 0x7369, 0x6f6e, 0x2030, + 0x332e, 0x3030, 0x2e32, 0x3420, 0x2020, 0x2020, 0x2400, 0x20a9, + 0x000f, 0x2001, 0x0000, 0x400f, 0x2091, 0x2200, 0x20a9, 0x000f, + 0x2001, 0x0000, 0x400f, 0x2091, 0x2400, 0x20a9, 0x000f, 0x2001, + 0x0000, 0x400f, 0x2091, 0x2600, 0x20a9, 0x000f, 0x2001, 0x0000, + 0x400f, 0x2091, 0x2800, 0x20a9, 0x000f, 0x2001, 0x0000, 0x400f, + 0x2091, 0x2a00, 0x20a9, 0x000f, 0x2001, 0x0000, 0x400f, 0x2091, + 0x2c00, 0x20a9, 0x000f, 0x2001, 0x0000, 0x400f, 0x2091, 0x2e00, + 0x20a9, 0x000f, 0x2001, 0x0000, 0x400f, 0x2091, 0x2000, 0x2001, + 0x0000, 0x20c1, 0x0004, 0x2001, 0x017f, 0x2003, 0x0000, 0x20c9, + 0x14ff, 0x2059, 0x0000, 0x2b78, 0x7883, 0x0004, 0x2089, 0x2102, + 0x2051, 0x1100, 0x2a70, 0x20e1, 0x0001, 0x20e9, 0x0001, 0x2029, + 0x45c0, 0x2031, 0xffff, 0x2039, 0x45a9, 0x2021, 0x0200, 0x20e9, + 0x0001, 0x20a1, 0x1000, 0x900e, 0x20a9, 0x05c0, 0x4104, 0x755e, + 0x7662, 0x775a, 0x7466, 0x746a, 0x20a1, 0x15c0, 0x7160, 0x810d, + 0x810d, 0x810d, 0x810d, 0x918c, 0x000f, 0x2001, 0x0001, 0x9112, + 0x900e, 0x21a8, 0x4104, 0x8211, 0x1de0, 0x7160, 0x3400, 0x8001, + 0x9102, 0x0120, 0x0218, 0x20a8, 0x900e, 0x4104, 0x2009, 0x1100, + 0x810d, 0x810d, 0x810d, 0x810d, 0x810d, 0x918c, 0x001f, 0x2001, + 0x0001, 0x9112, 0x20e9, 0x0001, 0x20a1, 0x0800, 0x900e, 0x20a9, + 0x0800, 0x4104, 0x8211, 0x1dd8, 0x2009, 0x1100, 0x3400, 0x9102, + 0x0120, 0x0218, 0x20a8, 0x900e, 0x4104, 0x080c, 0x0e42, 0x080c, + 0x0f8f, 0x080c, 0x13a2, 0x080c, 0x0c8a, 0x080c, 0x4721, 0x080c, + 0x7ebf, 0x080c, 0x0dae, 0x080c, 0x27c1, 0x080c, 0x5a05, 0x080c, + 0x4e0f, 0x080c, 0x64ba, 0x080c, 0x1956, 0x080c, 0x6721, 0x080c, + 0x5fe8, 0x080c, 0x1768, 0x080c, 0x18cb, 0x080c, 0x194b, 0x2091, + 0x3009, 0x7883, 0x0000, 0x1004, 0x0905, 0x7880, 0x9086, 0x0002, + 0x1160, 0x7883, 0x4000, 0x7837, 0x4000, 0x7833, 0x0010, 0x0e04, + 0x08ff, 0x2091, 0x5000, 0x2091, 0x4080, 0x2a70, 0x7003, 0x0000, + 0x2a70, 0x7000, 0x908e, 0x0003, 0x1168, 0x080c, 0x3816, 0x080c, + 0x27e5, 0x080c, 0x5a60, 0x080c, 0x52b6, 0x080c, 0x64e0, 0x080c, + 0x20a5, 0x0c70, 0x000b, 0x0c88, 0x0926, 0x0927, 0x0a62, 0x0924, + 0x0b34, 0x0c87, 0x0c88, 0x0c89, 0x080c, 0x0cf1, 0x0005, 0x0126, + 0x00f6, 0x2091, 0x8000, 0x7000, 0x9086, 0x0001, 0x1904, 0x0a30, + 0x7034, 0xd0b4, 0x1130, 0x0026, 0x2011, 0x0080, 0x080c, 0x0d63, + 0x002e, 0x080c, 0x5745, 0x0150, 0x080c, 0x576b, 0x1570, 0x2079, + 0x0100, 0x7828, 0x9085, 0x1800, 0x782a, 0x0438, 0x080c, 0x5682, + 0x7000, 0x9086, 0x0001, 0x1904, 0x0a30, 0x7088, 0x9086, 0x0028, + 0x1904, 0x0a30, 0x2001, 0x0161, 0x2003, 0x0001, 0x2079, 0x0100, + 0x7827, 0xffff, 0x7a28, 0x9295, 0x1e2f, 0x7a2a, 0x2011, 0x5654, + 0x080c, 0x655b, 0x2011, 0x4586, 0x080c, 0x655b, 0x2011, 0x8030, + 0x2019, 0x0000, 0x7087, 0x0000, 0x00d8, 0x080c, 0x3e5a, 0x2079, + 0x0100, 0x7844, 0x9005, 0x1904, 0x0a30, 0x2011, 0x4586, 0x080c, + 0x655b, 0x2001, 0x0265, 0x2001, 0x0205, 0x2003, 0x0000, 0x780f, + 0x006b, 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0x190c, 0x8dfb, 0x6878, 0x787a, + 0x6890, 0x7892, 0x688c, 0x788e, 0x9d90, 0x0019, 0x9f98, 0x0019, + 0x2009, 0x0020, 0x0156, 0x21a8, 0x2304, 0x2012, 0x8318, 0x8210, + 0x1f04, 0x8f54, 0x015e, 0x00fe, 0x000e, 0x6882, 0x000e, 0x687e, + 0x001e, 0x6874, 0x0006, 0x2168, 0x080c, 0x0e06, 0x001e, 0x0804, + 0x8fd3, 0x0016, 0x00f6, 0x2178, 0x7974, 0x9184, 0x00ff, 0x90b6, + 0x0002, 0x01e0, 0x9086, 0x0028, 0x1128, 0x687b, 0x001c, 0x787b, + 0x001c, 0x00e0, 0xd1dc, 0x0158, 0x687b, 0x0015, 0x787b, 0x0015, + 0x080c, 0x9a64, 0x0118, 0x7974, 0xc1dc, 0x7976, 0x0078, 0xd1d4, + 0x0128, 0x687b, 0x0007, 0x787b, 0x0007, 0x0040, 0x687c, 0xd0ac, + 0x0128, 0x6834, 0x6938, 0x9115, 0x190c, 0x8dfb, 0x6890, 0x7892, + 0x688c, 0x788e, 0x687c, 0x787e, 0x00fe, 0x080c, 0x0e06, 0x00de, + 0x6974, 0x0016, 0x080c, 0x926a, 0x001e, 0x0468, 0x6867, 0x0103, + 0x6974, 0x9184, 0x00ff, 0x90b6, 0x0002, 0x01b0, 0x9086, 0x0028, + 0x1118, 0x687b, 0x001c, 0x00d0, 0xd1dc, 0x0148, 0x687b, 0x0015, + 0x080c, 0x9a64, 0x0118, 0x6974, 0xc1dc, 0x6976, 0x0078, 0xd1d4, + 0x0118, 0x687b, 0x0007, 0x0050, 0x687b, 0x0000, 0x687c, 0xd0ac, + 0x0128, 0x6834, 0x6938, 0x9115, 0x190c, 0x8dfb, 0x6974, 0x0016, + 0x080c, 0x4ed6, 0x001e, 0xd1e4, 0x1120, 0x080c, 0x7f1e, 0x00de, + 0x0005, 0x080c, 0x987a, 0x0cd8, 0x0005, 0x080c, 0x6c56, 0x0010, + 0x080c, 0x6cf2, 0x080c, 0x95d2, 0x01c0, 0x00d6, 0x6114, 0x2168, + 0x6867, 0x0103, 0x2009, 0x110c, 0x210c, 0xd18c, 0x11c0, 0xd184, + 0x1198, 0x6108, 0x697a, 0x918e, 0x0029, 0x1110, 0x080c, 0xad5f, + 0x6877, 0x0000, 0x080c, 0x50a5, 0x00de, 0x080c, 0x7f1e, 0x080c, + 0x6d42, 0x080c, 0x6e10, 0x0005, 0x687b, 0x0004, 0x0c88, 0x687b, + 0x0004, 0x0c70, 0x9182, 0x0040, 0x0002, 0x9020, 0x9020, 0x9020, + 0x9020, 0x9020, 0x9022, 0x9020, 0x9025, 0x9020, 0x9020, 0x9020, + 0x9020, 0x9020, 0x9020, 0x9020, 0x9020, 0x9020, 0x9020, 0x9020, + 0x080c, 0x0cf1, 0x080c, 0x7f1e, 0x0005, 0x0006, 0x0026, 0x9016, + 0x080c, 0x119a, 0x002e, 0x000e, 0x0005, 0x9182, 0x0085, 0x0002, + 0x903d, 0x903b, 0x903b, 0x9049, 0x903b, 0x903b, 0x903b, 0x903b, + 0x903b, 0x903b, 0x903b, 0x080c, 0x0cf1, 0x6003, 0x0001, 0x6106, + 0x080c, 0x6886, 0x0126, 0x2091, 0x8000, 0x080c, 0x6d42, 0x012e, + 0x0005, 0x0026, 0x0056, 0x00d6, 0x00e6, 0x2071, 0x0260, 0x7224, + 0x6216, 0x7220, 0x080c, 0x95c2, 0x01a0, 0x2268, 0x6800, 0x9086, + 0x0000, 0x0178, 0x6010, 0x6d10, 0x952e, 0x1158, 0x00c6, 0x2d60, + 0x080c, 0x9297, 0x00ce, 0x0128, 0x6803, 0x0002, 0x6007, 0x0086, + 0x0010, 0x6007, 0x0087, 0x6003, 0x0001, 0x080c, 0x6886, 0x080c, + 0x6d42, 0x9280, 0x0004, 0x2004, 0xd0bc, 0x0150, 0x6824, 0xd0ec, + 0x0138, 0x00c6, 0x2260, 0x6043, 0x0000, 0x080c, 0x98aa, 0x00ce, + 0x00ee, 0x00de, 0x005e, 0x002e, 0x0005, 0x9186, 0x0013, 0x1160, + 0x6004, 0x908a, 0x0085, 0x0a0c, 0x0cf1, 0x908a, 0x0090, 0x1a0c, + 0x0cf1, 0x9082, 0x0085, 0x0072, 0x9186, 0x0027, 0x0120, 0x9186, + 0x0014, 0x190c, 0x0cf1, 0x080c, 0x6c56, 0x080c, 0x97a3, 0x080c, + 0x6d42, 0x0005, 0x90ad, 0x90af, 0x90af, 0x90ad, 0x90ad, 0x90ad, + 0x90ad, 0x90ad, 0x90ad, 0x90ad, 0x90ad, 0x080c, 0x0cf1, 0x080c, + 0x6c56, 0x080c, 0x97a3, 0x080c, 0x6d42, 0x0005, 0x9186, 0x0013, + 0x1128, 0x6004, 0x9082, 0x0085, 0x2008, 0x04a8, 0x9186, 0x0027, + 0x11e8, 0x080c, 0x6c56, 0x080c, 0x25ad, 0x00d6, 0x6014, 0x2068, + 0x080c, 0x95d2, 0x0150, 0x6867, 0x0103, 0x6877, 0x0000, 0x687b, + 0x0029, 0x080c, 0x50a5, 0x080c, 0x9797, 0x00de, 0x080c, 0x7f1e, + 0x080c, 0x6d42, 0x0005, 0x080c, 0x7f68, 0x0ce0, 0x9186, 0x0014, + 0x1dd0, 0x080c, 0x6c56, 0x00d6, 0x6014, 0x2068, 0x080c, 0x95d2, + 0x0d60, 0x6867, 0x0103, 0x6877, 0x0000, 0x687b, 0x0006, 0x6880, + 0xc0ec, 0x6882, 0x08f0, 0x0002, 0x9101, 0x90ff, 0x90ff, 0x90ff, + 0x90ff, 0x90ff, 0x9119, 0x90ff, 0x90ff, 0x90ff, 0x90ff, 0x080c, + 0x0cf1, 0x080c, 0x6c56, 0x6034, 0x908c, 0xff00, 0x810f, 0x9186, + 0x0039, 0x0118, 0x9186, 0x0035, 0x1118, 0x2001, 0x12a6, 0x0010, + 0x2001, 0x12a7, 0x2004, 0x601a, 0x6003, 0x000c, 0x080c, 0x6d42, + 0x0005, 0x080c, 0x6c56, 0x6034, 0x908c, 0xff00, 0x810f, 0x9186, + 0x0039, 0x0118, 0x9186, 0x0035, 0x1118, 0x2001, 0x12a6, 0x0010, + 0x2001, 0x12a7, 0x2004, 0x601a, 0x6003, 0x000e, 0x080c, 0x6d42, + 0x0005, 0x9182, 0x0090, 0x1220, 0x9182, 0x0085, 0x0208, 0x001a, + 0x080c, 0x7f68, 0x0005, 0x9146, 0x9146, 0x9146, 0x9146, 0x9148, + 0x919b, 0x9146, 0x9146, 0x9146, 0x9146, 0x9146, 0x080c, 0x0cf1, + 0x00d6, 0x6010, 0x2004, 0xd0bc, 0x0168, 0x6034, 0x908c, 0xff00, + 0x810f, 0x9186, 0x0039, 0x0118, 0x9186, 0x0035, 0x1118, 0x00de, + 0x0804, 0x91ac, 0x080c, 0x9797, 0x080c, 0x95d2, 0x01c8, 0x6014, + 0x2068, 0x6867, 0x0103, 0x6880, 0xd0b4, 0x0128, 0x687b, 0x0006, + 0xc0ec, 0x6882, 0x0048, 0xd0bc, 0x0118, 0x687b, 0x0002, 0x0020, + 0x687b, 0x0005, 0x080c, 0x9849, 0x6877, 0x0000, 0x080c, 0x50a5, + 0x2c68, 0x080c, 0x7ec8, 0x01d0, 0x6003, 0x0001, 0x6007, 0x001e, + 0x600b, 0xffff, 0x2009, 0x026e, 0x210c, 0x613a, 0x2009, 0x026f, + 0x210c, 0x613e, 0x6910, 0x6112, 0x080c, 0x99cc, 0x6954, 0x6156, + 0x6023, 0x0001, 0x080c, 0x6886, 0x080c, 0x6d42, 0x2d60, 0x080c, + 0x7f1e, 0x00de, 0x0005, 0x6010, 0x2004, 0xd0bc, 0x0598, 0x6034, + 0x908c, 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0x016e, 0x0004, 0x8076, 0x0008, 0x0040, + 0x0000, 0x8072, 0x0000, 0x8000, 0x0000, 0x019f, 0x0003, 0x8076, + 0x0008, 0x0042, 0x0008, 0x016b, 0x000b, 0xbbe0, 0x0009, 0x0016, + 0x0000, 0x0d6b, 0x000b, 0x3a44, 0x0002, 0x0c09, 0x000b, 0x8072, + 0x0000, 0x8000, 0x0000, 0x8000, 0x000f, 0x0007, 0x0003, 0x8072, + 0x0000, 0x8000, 0x0000, 0x0007, 0x0003, 0x3d30, 0x000a, 0x7f00, + 0x0000, 0xbc80, 0x0001, 0x0007, 0x0000, 0x0177, 0x0003, 0x1930, + 0x000a, 0x7f00, 0x0000, 0x9880, 0x0001, 0x0007, 0x0000, 0x7f62, + 0x0008, 0x8066, 0x0000, 0x000a, 0x0008, 0x457a, 0x000b, 0x4000, + 0x000f, 0x217c, 0x0003, 0x0870, 0x0008, 0x4000, 0x000f, 0xbac0, + 0x0009, 0x0090, 0x0008, 0x0985, 0x0003, 0x8074, 0x0000, 0x0706, + 0x0000, 0x0187, 0x0003, 0x8074, 0x0000, 0x0703, 0x0000, 0x4000, + 0x000f, 0x8010, 0x0008, 0x0008, 0x0000, 0x01ad, 0x000b, 0x0173, + 0x0004, 0x8010, 0x0008, 0x0007, 0x0000, 0x017c, 0x0004, 0x1810, + 0x0000, 0x017c, 0x0004, 0x01b7, 0x0003, 0x8010, 0x0008, 0x0009, + 0x0008, 0x01ad, 0x000b, 0x8010, 0x0008, 0x0005, 0x0008, 0x01ad, + 0x000b, 0x808c, 0x0008, 0x0001, 0x0000, 0x8010, 0x0008, 0x0004, + 0x0000, 0x4143, 0x000a, 0x0840, 0x000b, 0x01ad, 0x000b, 0x8010, + 0x0008, 0x0003, 0x0008, 0x01af, 0x0003, 0x8010, 0x0008, 0x000b, + 0x0000, 0x01af, 0x0003, 0x8010, 0x0008, 0x0002, 0x0000, 0x01af, + 0x0003, 0x3a47, 0x0002, 0x0cca, 0x000b, 0x8010, 0x0008, 0x0006, + 0x0008, 0x01af, 0x0003, 0x8074, 0x0000, 0xf000, 0x0008, 0x017c, + 0x0004, 0x017f, 0x0004, 0x3a40, 0x000a, 0x0807, 0x000b, 0x8010, + 0x0008, 0x000c, 0x0008, 0x017c, 0x0004, 0x0007, 0x0003, 0x8074, + 0x0000, 0xf080, 0x0000, 0x0d30, 0x0000, 0x2e4d, 0x0002, 0x2e4d, + 0x0002, 0x09c0, 0x000b, 0x8054, 0x0008, 0x0019, 0x0000, 0x0007, + 0x0003, 0x8054, 0x0008, 0x0009, 0x0008, 0x0007, 0x0003, 0x0001, + 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080, 0x0100, + 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000, 0xbb4d +}; +#ifdef UNIQUE_FW_NAME +unsigned short fw2300tp_length01 = 0xa9b8; +#else +unsigned short risc_code_length01 = 0xa9b8; +#endif + diff -urN linux-2.4.10/drivers/scsi/qla1280.c linux-2.4.10-lia/drivers/scsi/qla1280.c --- linux-2.4.10/drivers/scsi/qla1280.c Wed Jun 27 17:10:55 2001 +++ linux-2.4.10-lia/drivers/scsi/qla1280.c Mon Aug 20 18:49:25 2001 @@ -1,162 +1,110 @@ /******************************************************************************** - * QLOGIC LINUX SOFTWARE - * - * QLogic ISP1x80/1x160 device driver for Linux 2.3.x (redhat 6.X). - * - * COPYRIGHT (C) 1999-2000 QLOGIC CORPORATION - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the Qlogic's Linux Software License. See below. - * - * This program is WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistribution's or source code must retain the above copyright - * notice, this list of conditions, and the following disclaimer, - * without modification, immediately at the beginning of the file. - * 2. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - ********************************************************************************/ - -/***************************************************************************************** - QLOGIC CORPORATION SOFTWARE - "GNU" GENERAL PUBLIC LICENSE - TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION - AND MODIFICATION - -This GNU General Public License ("License") applies solely to QLogic Linux -Software ("Software") and may be distributed under the terms of this License. - -1. You may copy and distribute verbatim copies of the Software's source code as -you receive it, in any medium, provided that you conspicuously and appropriately -publish on each copy an appropriate copyright notice and disclaimer of warranty; -keep intact all the notices that refer to this License and to the absence of any -warranty; and give any other recipients of the Software a copy of this License along -with the Software. - -You may charge a fee for the physical act of transferring a copy, and you may at your -option offer warranty protection in exchange for a fee. - -2. You may modify your copy or copies of the Software or any portion of it, thus forming -a work based on the Software, and copy and distribute such modifications or work under -the terms of Section 1 above, provided that you also meet all of these conditions: - -* a) You must cause the modified files to carry prominent notices stating that you -changed the files and the date of any change. - -* b) You must cause any work that you distribute or publish that in whole or in part -contains or is derived from the Software or any part thereof, to be licensed as a -whole at no charge to all third parties under the terms of this License. - -* c) If the modified Software normally reads commands interactively when run, you -must cause it, when started running for such interactive use in the most ordinary way, -to print or display an announcement including an appropriate copyright notice and a -notice that there is no warranty (or else, saying that you provide a warranty) and that -users may redistribute the Software under these conditions, and telling the user how to -view a copy of this License. (Exception:if the Software itself is interactive but does -not normally print such an announcement, your work based on the Software is not required -to print an announcement.) - -These requirements apply to the modified work as a whole. If identifiable sections of -that work are not derived from the Software, and can be reasonably considered independent -and separate works in themselves, then this License, and its terms, do not apply to those -sections when you distribute them as separate works. But when you distribute the same -sections as part of a whole which is a work based on the Software, the distribution of the -whole must be on the terms of this License, whose permissions for other licensees extend -to the entire whole, and thus to each and every part regardless of who wrote it. - -3. You may copy and distribute the Software (or a work based on it, under Section 2) in -object code or executable form under the terms of Sections 1 and 2 above provided that -you also do one of the following: - -* a) Accompany it with the complete corresponding machine-readable source code, which must -be distributed under the terms of Sections 1 and 2 above on a medium customarily used for -software interchange; or, - -* b) Accompany it with a written offer, valid for at least three years, to give any third -party, for a charge no more than your cost of physically performing source distribution, -a complete machine-readable copy of the corresponding source code, to be distributed under -the terms of Sections 1 and 2 above on a medium customarily used for software interchange; -or, - -* c) Accompany it with the information you received as to the offer to distribute -corresponding source code. (This alternative is allowed only for noncommercial distribution -and only if you received the Software in object code or executable form with such an offer, -in accord with Subsection b above.) - -The source code for a work means the preferred form of the work for making modifications -to it. For an executable work, complete source code means all the source code for all -modules it contains, plus any associated interface definition files, plus the scripts used -to control compilation and installation of the executable. - -If distribution of executable or object code is made by offering access to copy from a -designated place, then offering equivalent access to copy the source code from the same -place counts as distribution of the source code, even though third parties are not -compelled to copy the source along with the object code. - -4. You may not copy, modify, sublicense, or distribute the Software except as expressly -provided under this License. Any attempt otherwise to copy, modify, sublicense or -distribute the Software is void, and will automatically terminate your rights under this -License. However, parties who have received copies, or rights, from you under this License -will not have their licenses terminated so long as such parties remain in full compliance. - -5. This license grants you world wide, royalty free non-exclusive rights to modify or -distribute the Software or its derivative works. These actions are prohibited by law -if you do not accept this License. Therefore, by modifying or distributing the Software -(or any work based on the Software), you indicate your acceptance of this License to do -so, and all its terms and conditions for copying, distributing or modifying the Software -or works based on it. - -6. Each time you redistribute the Software (or any work based on the Software), the -recipient automatically receives a license from the original licensor to copy, distribute -or modify the Software subject to these terms and conditions. You may not impose any -further restrictions on the recipients' exercise of the rights granted herein. You are -not responsible for enforcing compliance by third parties to this License. - -7. If, as a consequence of a court judgment or allegation of patent infringement or for -any other reason (not limited to patent issues), conditions are imposed on you -(whether by court order, agreement or otherwise) that contradict the conditions of this -License, they do not excuse you from the conditions of this License. If you cannot -distribute so as to satisfy simultaneously your obligations under this License -and any other pertinent obligations, then as a consequence you may not distribute the -Software at all. - -If any portion of this section is held invalid or unenforceable under any particular -circumstance, the balance of the section is intended to apply and the section as a whole -is intended to apply in other circumstances. -NO WARRANTY - -11. THE SOFTWARE IS PROVIDED WITHOUT A WARRANTY OF ANY KIND. THERE IS NO -WARRANTY FOR THE SOFTWARE, TO THE EXTENT PERMITTED BY APPLICABLE LAW. -EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR -OTHER PARTIES PROVIDE THE SOFTWARE "AS IS" WITHOUT WARRANTY OF ANY KIND, -EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE -ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE SOFTWARE IS WITH YOU. -SHOULD THE SOFTWARE PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL -NECESSARY SERVICING, REPAIR OR CORRECTION. - -12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING -WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR -REDISTRIBUTE THE SOFTWARE AS PERMITTED ABOVE, BE LIABLE TO YOU FOR -DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL -DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE SOFTWARE (INCLUDING -BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR -LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE SOFTWARE TO -OPERATE WITH ANY OTHER SOFTWARES), EVEN IF SUCH HOLDER OR OTHER PARTY HAS -BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -END OF TERMS AND CONDITIONS - -*******************************************************************************************/ - +* QLOGIC LINUX SOFTWARE +* +* QLogic QLA1280 (Ultra2) and QLA12160 (Ultra3) SCSI driver +* Copyright (C) 2000 Qlogic Corporation +* (www.qlogic.com) +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of the GNU General Public License as published by the +* Free Software Foundation; either version 2, or (at your option) any +* later version. +* +* This program is distributed in the hope that it will be useful, but +* WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +* General Public License for more details. +** +******************************************************************************/ +#define QLA1280_VERSION "3.23 Beta" /**************************************************************************** Revision History: - Rev. 3.00 Jan 17, 1999 DG Qlogic + Rev 3.23 Beta January 11, 2001 BN Qlogic + - Added check of device_id when handling non + QLA12160s during detect(). + Rev 3.22 Beta January 5, 2001 BN Qlogic + - Changed queue_task() to schedule_task() + for kernels 2.4.0 and higher. + Note: 2.4.0-testxx kernels released prior to + the actual 2.4.0 kernel release on January 2001 + will get compile/link errors with schedule_task(). + Please update your kernel to released 2.4.0 level, + or comment lines in this file flagged with 3.22 + to resolve compile/link error of schedule_task(). + - Added -DCONFIG_SMP in addition to -D__SMP__ + in Makefile for 2.4.0 builds of driver as module. + Rev 3.21 Beta January 4, 2001 BN Qlogic + - Changed criteria of 64/32 Bit mode of HBA + operation according to BITS_PER_LONG rather + than HBA's NVRAM setting of >4Gig memory bit; + so that the HBA auto-configures without the need + to setup each system individually. + Rev 3.20 Beta December 5, 2000 BN Qlogic + - Added priority handling to IA-64 onboard SCSI + ISP12160 chip for kernels greater than 2.3.18. + - Added irqrestore for qla1280_intr_handler. + - Enabled /proc/scsi/qla1280 interface. + - Clear /proc/scsi/qla1280 counters in detect(). + Rev 3.19 Beta October 13, 2000 BN Qlogic + - Declare driver_template for new kernel + (2.4.0 and greater) scsi initialization scheme. + - Update /proc/scsi entry for 2.3.18 kernels and + above as qla1280 + Rev 3.18 Beta October 10, 2000 BN Qlogic + - Changed scan order of adapters to map + the QLA12160 followed by the QLA1280. + Rev 3.17 Beta September 18, 2000 BN Qlogic + - Removed warnings for 32 bit 2.4.x compiles + - Corrected declared size for request and response + DMA addresses that are kept in each ha + Rev. 3.16 Beta August 25, 2000 BN Qlogic + - Corrected 64 bit addressing issue on IA-64 + where the upper 32 bits were not properly + passed to the RISC engine. + Rev. 3.15 Beta August 22, 2000 BN Qlogic + - Modified qla1280_setup_chip to properly load + ISP firmware for greater that 4 Gig memory on IA-64 + Rev. 3.14 Beta August 16, 2000 BN Qlogic + - Added setting of dma_mask to full 64 bit + if flags.enable_64bit_addressing is set in NVRAM + Rev. 3.13 Beta August 16, 2000 BN Qlogic + - Use new PCI DMA mapping APIs for 2.4.x kernel + Rev. 3.12 July 18, 2000 Redhat & BN Qlogic + - Added check of pci_enable_device to detect() for 2.3.x + - Use pci_resource_start() instead of + pdev->resource[0].start in detect() for 2.3.x + - Updated driver version + Rev. 3.11 July 14, 2000 BN Qlogic + - Updated SCSI Firmware to following versions: + qla1x80: 8.13.08 + qla1x160: 10.04.08 + - Updated driver version to 3.11 + Rev. 3.10 June 23, 2000 BN Qlogic + - Added filtering of AMI SubSys Vendor ID devices + Rev. 3.9 + - DEBUG_QLA1280 undefined and new version BN Qlogic + Rev. 3.08b May 9, 2000 MD Dell + - Added logic to check against AMI subsystem vendor ID + Rev. 3.08 May 4, 2000 DG Qlogic + - Added logic to check for PCI subsystem ID. + Rev. 3.07 Apr 24, 2000 DG & BN Qlogic + - Updated SCSI Firmware to following versions: + qla12160: 10.01.19 + qla1280: 8.09.00 + Rev. 3.06 Apr 12, 2000 DG & BN Qlogic + - Internal revision; not released + Rev. 3.05 Mar 28, 2000 DG & BN Qlogic + - Edit correction for virt_to_bus and PROC. + Rev. 3.04 Mar 28, 2000 DG & BN Qlogic + - Merge changes from ia64 port. + Rev. 3.03 Mar 28, 2000 BN Qlogic + - Increase version to reflect new code drop with compile fix + of issue with inclusion of linux/spinlock for 2.3 kernels + Rev. 3.02 Mar 15, 2000 BN Qlogic + - Merge qla1280_proc_info from 2.10 code base + Rev. 3.01 Feb 10, 2000 BN Qlogic + - Corrected code to compile on a 2.2.x kernel. + Rev. 3.00 Jan 17, 2000 DG Qlogic - Added 64-bit support. Rev. 2.07 Nov 9, 1999 DG Qlogic - Added new routine to set target parameters for ISP12160. @@ -183,12 +131,11 @@ *****************************************************************************/ +#include #ifdef MODULE #include #endif -#define QLA1280_VERSION " 3.00-Beta" - #include #include #include @@ -207,8 +154,16 @@ #include #include #include -/* MRS #include */ +#ifndef KERNEL_VERSION +# define KERNEL_VERSION(x,y,z) (((x)<<16)+((y)<<8)+(z)) +#endif + +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,3,18) +#include +#endif + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95) +#include # include #endif #include "sd.h" @@ -216,23 +171,16 @@ #include "hosts.h" #define UNIQUE_FW_NAME #include "qla1280.h" -#include "ql12160_fw.h" /* ISP RISC code */ +#include "ql12160_fw.h" /* ISP RISC codes */ #include "ql1280_fw.h" #include -#include /* for kmalloc() */ - - -#ifndef KERNEL_VERSION -# define KERNEL_VERSION(x,y,z) (((x)<<16)+((y)<<8)+(z)) -#endif - +#include /* * Compile time Options: * 0 - Disable and 1 - Enable */ -#define QLA1280_64BIT_SUPPORT 1 /* 64-bit Support */ #define QL1280_TARGET_MODE_SUPPORT 0 /* Target mode support */ #define WATCHDOGTIMER 0 #define MEMORY_MAPPED_IO 0 @@ -244,15 +192,9 @@ #define AUTO_ESCALATE_ABORT 0 /* Automatically escalate aborts */ #define STOP_ON_ERROR 0 /* Stop on aborts and resets */ #define STOP_ON_RESET 0 -#define STOP_ON_ABORT 0 -#undef DYNAMIC_MEM_ALLOC - -#define DEBUG_QLA1280 0 /* Debugging */ -/* #define CHECKSRBSIZE */ - -/* - * These macros to assist programming - */ +#define STOP_ON_ABORT 0 +#define QLA1280_PROFILE 1 /* 3.20 */ +#define DEBUG_QLA1280 0 #define BZERO(ptr, amt) memset(ptr, 0, amt) #define BCOPY(src, dst, amt) memcpy(dst, src, amt) @@ -260,19 +202,28 @@ #define KMFREE(ip,siz) kfree((ip)) #define SYS_DELAY(x) udelay(x);barrier() #define QLA1280_DELAY(sec) mdelay(sec * 1000) -#define VIRT_TO_BUS(a) virt_to_bus((a)) -#if QLA1280_64BIT_SUPPORT + +/* 3.16 */ +#if BITS_PER_LONG > 32 +#define pci_dma_lo32(a) (a & 0xffffffff) +#define pci_dma_hi32(a) ((a >> 32) & 0xffffffff) +#else +#define pci_dma_lo32(a) (a & 0xffffffff) +#define pci_dma_hi32(a) 0 +#endif + +#define VIRT_TO_BUS(a) virt_to_bus(((void *)a)) + #if BITS_PER_LONG <= 32 -#define VIRT_TO_BUS_LOW(a) (uint32_t)virt_to_bus((a)) +#define VIRT_TO_BUS_LOW(a) (uint32_t)virt_to_bus(((void *)a)) #define VIRT_TO_BUS_HIGH(a) (uint32_t)(0x0) #else -#define VIRT_TO_BUS_LOW(a) (uint32_t)(0xffffffff & virt_to_bus((a))) -#define VIRT_TO_BUS_HIGH(a) (uint32_t)(0xffffffff & (virt_to_bus((a))>>32)) +#define VIRT_TO_BUS_LOW(a) (uint32_t)(0xffffffff & virt_to_bus((void *)(a))) +#define VIRT_TO_BUS_HIGH(a) (uint32_t)(0xffffffff & (virt_to_bus((void *)(a))>>32)) #endif -#endif /* QLA1280_64BIT_SUPPORT */ -#define STATIC +#define STATIC #define NVRAM_DELAY() udelay(500) /* 2 microsecond delay */ void qla1280_device_queue_depth(scsi_qla_host_t *, Scsi_Device *); @@ -285,11 +236,11 @@ #define LSB(x) (uint8_t)(x) #if BITS_PER_LONG <= 32 -#define LS_64BITS(x) (uint32_t)(x) -#define MS_64BITS(x) (uint32_t)(0x0) +#define LS_64BITS(x) (uint32_t)((unsigned long) x) +#define MS_64BITS(x) (uint32_t)((unsigned long) 0x0) #else -#define LS_64BITS(x) (uint32_t)(0xffffffff & (x)) -#define MS_64BITS(x) (uint32_t)(0xffffffff & ((x)>>32) ) +#define LS_64BITS(x) (uint32_t)(0xffffffff & ((unsigned long)x)) +#define MS_64BITS(x) (uint32_t)(0xffffffff & (((unsigned long)x)>>32) ) #endif /* @@ -300,9 +251,6 @@ STATIC void qla1280_putq_t(scsi_lu_t *, srb_t *); STATIC void qla1280_done_q_put(srb_t *, srb_t **, srb_t **); STATIC void qla1280_select_queue_depth(struct Scsi_Host *, Scsi_Device *); -#ifdef QLA1280_UNUSED -static void qla1280_dump_regs(struct Scsi_Host *host); -#endif #if STOP_ON_ERROR static void qla1280_panic(char *, struct Scsi_Host *host); #endif @@ -312,10 +260,7 @@ STATIC int qla1280_return_status( sts_entry_t *sts, Scsi_Cmnd *cp); STATIC void qla1280_removeq(scsi_lu_t *q, srb_t *sp); STATIC void qla1280_mem_free(scsi_qla_host_t *ha); -static void qla1280_do_dpc(void *p); -#ifdef QLA1280_UNUSED -static void qla1280_set_flags(char * s); -#endif +void qla1280_do_dpc(void *p); static char *qla1280_get_token(char *, char *); #if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,0) STATIC inline void mdelay(int); @@ -339,9 +284,7 @@ STATIC uint8_t qla1280_device_reset(scsi_qla_host_t *, uint8_t, uint32_t); STATIC uint8_t qla1280_abort_device(scsi_qla_host_t *, uint8_t, uint32_t, uint32_t); STATIC uint8_t qla1280_abort_command(scsi_qla_host_t *, srb_t *), -#if QLA1280_64BIT_SUPPORT qla1280_64bit_start_scsi(scsi_qla_host_t *, srb_t *), -#endif qla1280_32bit_start_scsi(scsi_qla_host_t *, srb_t *), qla1280_abort_isp(scsi_qla_host_t *); STATIC void qla1280_nv_write(scsi_qla_host_t *, uint16_t), @@ -374,12 +317,12 @@ qla1280_notify_ack(scsi_qla_host_t *, notify_entry_t *), qla1280_immed_notify(scsi_qla_host_t *, notify_entry_t *), qla1280_accept_io(scsi_qla_host_t *, ctio_ret_entry_t *), -#if QLA1280_64BIT_SUPPORT - qla1280_64bit_continue_io(scsi_qla_host_t *, atio_entry_t *, uint32_t, - paddr32_t *), -#endif - qla1280_32bit_continue_io(scsi_qla_host_t *, atio_entry_t *, uint32_t, - paddr32_t *), + qla1280_64bit_continue_io(scsi_qla_host_t *, + atio_entry_t *, uint32_t, + paddr32_t *), + qla1280_32bit_continue_io(scsi_qla_host_t *, + atio_entry_t *, uint32_t, + paddr32_t *), qla1280_atio_entry(scsi_qla_host_t *, atio_entry_t *), qla1280_notify_entry(scsi_qla_host_t *, notify_entry_t *); #endif /* QLA1280_TARGET_MODE_SUPPORT */ @@ -400,7 +343,7 @@ qla1280_dump_buffer(caddr_t, uint32_t); char debug_buff[80]; -#if DEBUG_QLA1280 +#if DEBUG_QLA1280 STATIC uint8_t ql_debug_print = 1; #else STATIC uint8_t ql_debug_print = 0; @@ -426,6 +369,22 @@ #endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18) +/* + * Our directory Entry in /proc/scsi for the user to + * access the driver. + */ +/* Need to add in proc_fs.h PROC_SCSI_QL1280 */ +#define PROC_SCSI_QL1280 PROC_SCSI_QLOGICISP + +struct proc_dir_entry proc_scsi_qla1280 = { + PROC_SCSI_QL1280, 7, "qla1280", + S_IFDIR | S_IRUGO | S_IXUGO, 2, + 0, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL, NULL +}; +#endif + /* We use the Scsi_Pointer structure that's included with each command * SCSI_Cmnd as a scratchpad for our SRB. * @@ -471,17 +430,17 @@ unsigned char *fwver; /* Ptr to F/W version array */ } qla_boards_t; -struct _qlaboards QLBoardTbl[NUM_OF_ISP_DEVICES] = +struct _qlaboards QL1280BoardTbl[NUM_OF_ISP_DEVICES] = { /* Name , Board PCI Device ID, Number of ports */ + {"QLA12160 ", QLA12160_DEVICE_ID, 2, + &fw12160i_code01[0], (unsigned long *)&fw12160i_length01,&fw12160i_addr01, &fw12160i_version_str[0] }, {"QLA1080 ", QLA1080_DEVICE_ID, 1, &fw1280ei_code01[0], (unsigned long *)&fw1280ei_length01,&fw1280ei_addr01, &fw1280ei_version_str[0] }, {"QLA1240 ", QLA1240_DEVICE_ID, 2, &fw1280ei_code01[0], (unsigned long *)&fw1280ei_length01,&fw1280ei_addr01, &fw1280ei_version_str[0] }, {"QLA1280 ", QLA1280_DEVICE_ID, 2, &fw1280ei_code01[0], (unsigned long *)&fw1280ei_length01,&fw1280ei_addr01, &fw1280ei_version_str[0] }, - {"QLA12160 ", QLA12160_DEVICE_ID, 2, - &fw12160i_code01[0], (unsigned long *)&fw12160i_length01,&fw12160i_addr01, &fw12160i_version_str[0] }, {"QLA10160 ", QLA10160_DEVICE_ID, 1, &fw12160i_code01[0], (unsigned long *)&fw12160i_length01,&fw12160i_addr01, &fw12160i_version_str[0] }, {" ", 0, 0} @@ -489,7 +448,7 @@ static unsigned long qla1280_verbose = 1L; static scsi_qla_host_t *qla1280_hostlist = NULL; -#ifdef QLA1280_PROFILE +#if QLA1280_PROFILE static int qla1280_buffer_size = 0; static char *qla1280_buffer = NULL; #endif @@ -567,152 +526,153 @@ * * Returns: *************************************************************************/ -#ifdef QLA1280_PROFILE -#define PROC_BUF (&qla1280_buffer[size]) -#define LUN_ID (targ_lun>>(MAX_T_BITS+MAX_L_BITS)),((targ_lun>>MAX_L_BITS)&0xf), targ_lun&0x7 -#endif +#define PROC_BUF (&qla1280_buffer[len]) int -qla1280_proc_info ( char *buffer, char **start, off_t offset, int length, - int hostno, int inout) -{ -#ifdef QLA1280_PROFILE +qla1280_proc_info( char *buffer, char **start, off_t offset, int length, + int hostno, int inout) { +#if QLA1280_PROFILE struct Scsi_Host *host; scsi_qla_host_t *ha; int size = 0; - int targ_lun; scsi_lu_t *up; - int no_devices; - - printk("Entering proc_info 0x%p,0x%lx,0x%x,0x%x\n",buffer,offset,length,hostno); + int len = 0; + qla_boards_t *bdp; + uint32_t b, t, l; + uint8_t *temp; host = NULL; - /* find the host they want to look at */ - for(ha=qla1280_hostlist; (ha != NULL) && ha->host->host_no != hostno; ha=ha->next) + + /* Find the host that was specified */ + for( ha=qla1280_hostlist; (ha != NULL) && ha->host->host_no != hostno; ha=ha->next ) ; - if (!ha) - { - size += sprintf(buffer, "Can't find adapter for host number %d\n", hostno); - if (size > length) - { + /* if host wasn't found then exit */ + if( !ha ) { + size = sprintf(buffer, "Can't find adapter for host number %d\n", hostno); + if( size > length ) { return (size); - } - else - { - return (length); + } else { + return (0); } } host = ha->host; - if (inout == TRUE) /* Has data been written to the file? */ - { - return (qla1280_set_info(buffer, length, host)); - } - /* compute number of active devices */ - no_devices = 0; - for (targ_lun = 0; targ_lun < MAX_EQ; targ_lun++) + if( inout == TRUE ) /* Has data been written to the file? */ { - if( (up = ha->dev[targ_lun]) == NULL ) - continue; - no_devices++; + printk("qla1280_proc: has data been written to the file. \n"); + return (qla1280_set_info(buffer, length, host)); } - /* size = 112 * no_devices; */ - size = 4096; - /* round up to the next page */ /* * if our old buffer is the right size use it otherwise * allocate a new one. */ - if (qla1280_buffer_size != size) - { + size = 4096; /* get a page */ + if( qla1280_buffer_size != size ) { /* deallocate this buffer and get a new one */ - if (qla1280_buffer != NULL) - { + if( qla1280_buffer != NULL ) { kfree(qla1280_buffer); qla1280_buffer_size = 0; } qla1280_buffer = kmalloc(size, GFP_KERNEL); } - if (qla1280_buffer == NULL) - { + if( qla1280_buffer == NULL ) { size = sprintf(buffer, "qla1280 - kmalloc error at line %d\n", __LINE__); return size; } + /* save the size of our buffer */ qla1280_buffer_size = size; - size = 0; - size += sprintf(PROC_BUF, "Qlogic 1280/1080 SCSI driver version: "); /* 43 bytes */ - size += sprintf(PROC_BUF, "%5s, ", QLA1280_VERSION); /* 5 */ - size += sprintf(PROC_BUF, "Qlogic Firmware version: "); /* 25 */ - size += sprintf(PROC_BUF, "%2d.%2d.%2d",_firmware_version[0], /* 8 */ - ql12_firmware_version[1], - ql12_firmware_version[2]); - size += sprintf(PROC_BUF, "\n"); /* 1 */ - - size += sprintf(PROC_BUF, "SCSI Host Adapter Information: %s\n", QLBoardTbl[ha->devnum].bdName); - size += sprintf(PROC_BUF, "Request Queue = 0x%lx, Response Queue = 0x%lx\n", - ha->request_dma, - ha->response_dma); - size += sprintf(PROC_BUF, "Request Queue count= 0x%x, Response Queue count= 0x%x\n", + /* 3.20 clear the buffer we use for proc display */ + temp = qla1280_buffer; + for (b=0 ; b < size; b++) *(temp+b) = 0; + + /* start building the print buffer */ + bdp = &QL1280BoardTbl[ha->devnum]; + size = sprintf(PROC_BUF, + "QLogic PCI to SCSI Adapter for ISP 1280/12160:\n" + " Firmware version: %2d.%02d.%02d, Driver version %s\n", bdp->fwver[0], bdp->fwver[1], bdp->fwver[2], QLA1280_VERSION); + + len += size; + + size = sprintf(PROC_BUF, "SCSI Host Adapter Information: %s\n", bdp->bdName); + len += size; + size = sprintf(PROC_BUF, "Request Queue = 0x%lx, Response Queue = 0x%lx\n", + (unsigned long) ha->request_dma, + (unsigned long) ha->response_dma); + len += size; + size = sprintf(PROC_BUF, "Request Queue count= 0x%x, Response Queue count= 0x%x\n", REQUEST_ENTRY_CNT, RESPONSE_ENTRY_CNT); - size += sprintf(PROC_BUF,"Number of pending commands = 0x%lx\n", ha->actthreads); - size += sprintf(PROC_BUF,"Number of queued commands = 0x%lx\n", ha->qthreads); - size += sprintf(PROC_BUF,"Number of free request entries = %d\n",ha->req_q_cnt); - size += sprintf(PROC_BUF, "\n"); /* 1 */ + len += size; + size = sprintf(PROC_BUF, "Number of pending commands = 0x%lx\n", ha->actthreads); + len += size; + size = sprintf(PROC_BUF, "Number of queued commands = 0x%lx\n", ha->qthreads); + len += size; + size = sprintf(PROC_BUF, "Number of free request entries = %d\n",ha->req_q_cnt); + len += size; + size = sprintf(PROC_BUF, "\n"); /* 1 */ + len += size; - size += sprintf(PROC_BUF, "Attached devices:\n"); + size = sprintf(PROC_BUF, "SCSI device Information:\n"); + len += size; /* scan for all equipment stats */ - for (targ_lun = 0; targ_lun < MAX_EQ; targ_lun++) - { - if( (up = ha->dev[targ_lun]) == NULL ) + for (b = 0; b < MAX_BUSES; b++) + for (t = 0; t < MAX_TARGETS; t++) { + for( l = 0; l < MAX_LUNS; l++ ) { + up = (scsi_lu_t *) LU_Q(ha, b, t, l); + if( up == NULL ) continue; - if( up->io_cnt == 0 ) - { - size += sprintf(PROC_BUF,"(%2d:%2d:%2d) No stats\n",LUN_ID); + /* unused device/lun */ + if( up->io_cnt == 0 || up->io_cnt < 2 ) continue; - } /* total reads since boot */ /* total writes since boot */ /* total requests since boot */ - size += sprintf(PROC_BUF, "Total requests %ld,",up->io_cnt); + size = sprintf(PROC_BUF, "(%2d:%2d:%2d): Total reqs %ld,",b,t,l,up->io_cnt); + len += size; /* current number of pending requests */ - size += sprintf(PROC_BUF, "(%2d:%2d:%2d) pending requests %d,",LUN_ID,up->q_outcnt); + size = sprintf(PROC_BUF, " Pend reqs %d,",up->q_outcnt); + len += size; +#if 0 /* avg response time */ - size += sprintf(PROC_BUF, "Avg response time %ld%%,",(up->resp_time/up->io_cnt)*100); + size = sprintf(PROC_BUF, " Avg resp time %ld%%,",(up->resp_time/up->io_cnt)*100); + len += size; /* avg active time */ - size += sprintf(PROC_BUF, "Avg active time %ld%%\n",(up->act_time/up->io_cnt)*100); + size = sprintf(PROC_BUF, " Avg active time %ld%%\n",(up->act_time/up->io_cnt)*100); +#else + size = sprintf(PROC_BUF, "\n"); +#endif + len += size; + } + if( len >= qla1280_buffer_size ) + break; } - if (size >= qla1280_buffer_size) - { + if( len >= qla1280_buffer_size ) { printk(KERN_WARNING "qla1280: Overflow buffer in qla1280_proc.c\n"); } - if (offset > size - 1) - { + if( offset > len - 1 ) { kfree(qla1280_buffer); qla1280_buffer = NULL; qla1280_buffer_size = length = 0; *start = NULL; - } - else - { + } else { *start = &qla1280_buffer[offset]; /* Start of wanted data */ - if (size - offset < length) - { - length = size - offset; + if( len - offset < length ) { + length = len - offset; } } + return (length); +#else + return (0); #endif - return (length); } - /************************************************************************** * qla1280_detect * This routine will probe for Qlogic 1280 SCSI host adapters. @@ -734,7 +694,10 @@ struct Scsi_Host *host; scsi_qla_host_t *ha, *cur_ha; struct _qlaboards *bdp; - int i, j; + int i,j; +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18) + unsigned short subsys; +#endif #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,1,95) unsigned int piobase; unsigned char pci_bus, pci_devfn, pci_irq; @@ -747,13 +710,19 @@ #else int index; #endif +#ifndef PCI_VENDOR_ID_AMI +#define PCI_VENDOR_ID_AMI 0x101e +#endif ENTER("qla1280_detect"); + if (sizeof(srb_t) > sizeof(Scsi_Pointer) ) + printk("qla1280_detect: [WARNING] srb_t Must Be Redefined"); + #ifdef CHECKSRBSIZE if (sizeof(srb_t) > sizeof(Scsi_Pointer) ) { - printk("Redefine SRB - its too big"); + printk("qla1280_detect: srb_t Must Be Redefined - its too big"); return 0; } #endif @@ -784,45 +753,174 @@ "qla1280: insmod or else it might trash certain memory areas.\n"); #endif +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18) if ((int) !pcibios_present()) +#else + if (!pci_present()) +#endif { - printk("scsi: PCI not present\n"); - return 0; - } /* end of IF */ - bdp = &QLBoardTbl[0]; + printk("scsi: PCI not present\n"); + return 0; + } + + bdp = &QL1280BoardTbl[0]; qla1280_hostlist = NULL; -#if 0 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18) template->proc_dir = &proc_scsi_qla1280; #else template->proc_name = "qla1280"; #endif + + /* 3.20 */ + /* First Initialize QLA12160 on PCI Bus 1 Dev 2 */ +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,3,18) + while ((pdev = pci_find_subsys(QLA1280_VENDOR_ID, + bdp->device_id, /* QLA12160 first in list */ + PCI_ANY_ID, + PCI_ANY_ID,pdev))) { + + /* find QLA12160 device on PCI bus=1 slot=2 */ + if ((pdev->bus->number != 1) || + (PCI_SLOT(pdev->devfn) != 2)) continue; + + if (pci_enable_device(pdev)) goto find_devices; + printk("qla1x160: Initializing ISP12160 on PCI Bus 1, Dev 2\n"); + host = scsi_register(template, sizeof(scsi_qla_host_t)); + if (!host) { + printk(KERN_WARNING "qla1280: Failed to register host, aborting.\n"); + return 0; + } + scsi_set_pci_device(host, pdev); + ha = (scsi_qla_host_t *) host->hostdata; + /* Clear our data area */ + for( j =0, cp = (char *)ha; j < sizeof(scsi_qla_host_t); j++) + *cp++ = 0; + /* Sanitize the information from PCI BIOS. */ + host->irq = pdev->irq; + host->io_port = pci_resource_start(pdev, 0); + ha->pci_bus = pdev->bus->number; + ha->pci_device_fn = pdev->devfn; + ha->pdev = pdev; + ha->device_id = bdp->device_id; /* QLA12160 first in list */ + ha->devnum = 0; // This priority ISP12160 is always devnum zero + if( qla1280_mem_alloc(ha) ) { + printk(KERN_INFO "qla1x160: Failed to get memory\n"); + } + ha->ports = bdp->numPorts; + /* following needed for all cases of OS versions */ + host->io_port &= PCI_BASE_ADDRESS_IO_MASK; + ha->iobase = (device_reg_t *) host->io_port; + ha->host = host; + ha->host_no = host->host_no; + /* 3.20 zero out /proc/scsi/qla1280 counters */ + ha->actthreads = 0; + ha->qthreads = 0; + ha->isr_count = 0; + + /* load the F/W, read paramaters, and init the H/W */ + ha->instance = num_hosts; + if (qla1280_initialize_adapter(ha)) + { + printk(KERN_INFO "qla1x160: Failed to initialize QLA12160 on PCI Bus 1 Dev 2 \n"); + qla1280_mem_free(ha); + scsi_unregister(host); + goto find_devices; + } + host->max_channel = bdp->numPorts-1; + /* Register our resources with Linux */ + if( qla1280_register_with_Linux(ha, bdp->numPorts-1) ) { + printk(KERN_INFO "qla1x160: Failed to register resources for QLA12160 on PCI Bus 1 Dev 2\n"); + qla1280_mem_free(ha); + scsi_unregister(host); + goto find_devices; + } + reg = ha->iobase; + /* Disable ISP interrupts. */ + qla1280_disable_intrs(ha); + /* Insure mailbox registers are free. */ + WRT_REG_WORD(®->semaphore, 0); + WRT_REG_WORD(®->host_cmd, HC_CLR_RISC_INT); + WRT_REG_WORD(®->host_cmd, HC_CLR_HOST_INT); + + /* Enable chip interrupts. */ + qla1280_enable_intrs(ha); + /* Insert new entry into the list of adapters */ + ha->next = NULL; + /* this preferred device will always be the first one found */ + cur_ha = qla1280_hostlist = ha; + num_hosts++; + } +#endif + +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,3,18) + find_devices: +#endif + + pdev = NULL; /* Try and find each different type of adapter we support */ - for( i=0; bdp->device_id != 0 && i < NUM_OF_ISP_DEVICES; i++, bdp++ ) { + for(i=0;bdp->device_id != 0 && i < NUM_OF_ISP_DEVICES;i++,bdp++) { #if LINUX_VERSION_CODE > KERNEL_VERSION(2,1,95) +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,3,18) + /* PCI_SUBSYSTEM_IDS supported */ + while ((pdev = pci_find_subsys(QLA1280_VENDOR_ID, + bdp->device_id, PCI_ANY_ID, PCI_ANY_ID, pdev) )) { + if (pci_enable_device(pdev)) continue; +#else while ((pdev = pci_find_device(QLA1280_VENDOR_ID, bdp->device_id, pdev ) )) { - if (pci_enable_device(pdev)) continue; -#else +#endif /* 2,3,18 */ +#else /* less than 2,1,95 */ while (!(pcibios_find_device(QLA1280_VENDOR_ID, bdp->device_id, index++, &pci_bus, &pci_devfn)) ) { -#endif +#endif /* 2,1,95 */ /* found a adapter */ +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,3,18) + /* If it's an AMI SubSys Vendor ID adapter, skip it. */ + if (pdev->subsystem_vendor == PCI_VENDOR_ID_AMI) + { + printk("qla1x160: Skip AMI SubSys Vendor ID Chip\n"); + continue; + } + + /* 3.20 and 3.23 */ + /* skip QLA12160 already initialized on PCI Bus 1 Dev 2 */ + /* since we already initialized and presented it */ + if ((bdp->device_id == QLA12160_DEVICE_ID) && + (pdev->bus->number == 1) && + (PCI_SLOT(pdev->devfn) == 2)) continue; + + printk("qla1x160: Supported Device Found VID=%x DID=%x SSVID=%x SSDID=%x\n", + pdev->vendor, pdev->device, + pdev->subsystem_vendor, pdev->subsystem_device); + +#else +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,1,95) + printk("qla1x160: Supported Device Found\n"); + pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, + &subsys); + /* Bypass all AMI SUBSYS VENDOR IDs */ + if (subsys == PCI_VENDOR_ID_AMI) + { + printk("qla1x160: Skip AMI SubSys Vendor ID Chip\n"); + continue; + } +#endif /* 2,1,95 */ +#endif /* 2,3,18 */ host = scsi_register(template, sizeof(scsi_qla_host_t)); - if (!host) { - printk(KERN_WARNING "qla1280: Failed to register host, aborting.\n"); - return 0; - } - scsi_set_pci_device(host, pdev); ha = (scsi_qla_host_t *) host->hostdata; /* Clear our data area */ for( j =0, cp = (char *)ha; j < sizeof(scsi_qla_host_t); j++) - *cp = 0; + *cp++ = 0; /* Sanitize the information from PCI BIOS. */ #if LINUX_VERSION_CODE > KERNEL_VERSION(2,1,95) host->irq = pdev->irq; +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18) + host->io_port = (unsigned int) pdev->base_address[0]; +#else host->io_port = pci_resource_start(pdev, 0); +#endif ha->pci_bus = pdev->bus->number; ha->pci_device_fn = pdev->devfn; ha->pdev = pdev; @@ -836,38 +934,38 @@ ha->pci_device_fn = pci_devfn; #endif ha->device_id = bdp->device_id; - - ha->devnum = i; + ha->devnum = i; // specifies microcode load address + if( qla1280_mem_alloc(ha) ) { - printk(KERN_INFO "qla1280: Failed to allocate memory for adapter\n"); + printk(KERN_INFO "qla1x160: Failed to get memory\n"); } ha->ports = bdp->numPorts; + /* following needed for all cases of OS versions */ + host->io_port &= PCI_BASE_ADDRESS_IO_MASK; ha->iobase = (device_reg_t *) host->io_port; ha->host = host; ha->host_no = host->host_no; /* load the F/W, read paramaters, and init the H/W */ + ha->instance = num_hosts; if (qla1280_initialize_adapter(ha)) { - - printk(KERN_INFO "qla1280: Failed to initialized adapter\n"); - qla1280_mem_free(ha); - scsi_unregister(host); - continue; + printk(KERN_INFO "qla1x160:Failed to initialize adapter\n"); + qla1280_mem_free(ha); + scsi_unregister(host); + continue; } host->max_channel = bdp->numPorts-1; - ha->instance = num_hosts; /* Register our resources with Linux */ if( qla1280_register_with_Linux(ha, bdp->numPorts-1) ) { - printk(KERN_INFO "qla1280: Failed to register our resources\n"); - qla1280_mem_free(ha); - scsi_unregister(host); - continue; + printk(KERN_INFO "qla1x160: Failed to register resources\n"); + qla1280_mem_free(ha); + scsi_unregister(host); + continue; } - reg = ha->iobase; /* Disable ISP interrupts. */ qla1280_disable_intrs(ha); @@ -924,8 +1022,11 @@ host->can_queue = 0xfffff; /* unlimited */ host->cmd_per_lun = 1; host->select_queue_depths = qla1280_select_queue_depth; - host->n_io_port = 0xFF; - host->base = (unsigned long) ha->mmpbase; +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18) + host->base = (unsigned char *) ha->mmpbase; +#else + host->base = (u_long) ha->mmpbase; +#endif host->max_channel = maxchannels; host->max_lun = MAX_LUNS-1; host->unique_id = ha->instance; @@ -1016,10 +1117,10 @@ bp = &qla1280_buffer[0]; ha = (scsi_qla_host_t *)host->hostdata; - bdp = &QLBoardTbl[ha->devnum]; + bdp = &QL1280BoardTbl[ha->devnum]; memset(bp, 0, sizeof(qla1280_buffer)); sprintf(bp, - "QLogic %sPCI to SCSI Host Adapter: bus %d device %d irq %d\n" + "QLogic %s PCI to SCSI Host Adapter: bus %d device %d irq %d\n" " Firmware version: %2d.%02d.%02d, Driver version %s", (char *)&bdp->bdName[0], ha->pci_bus, (ha->pci_device_fn & 0xf8) >> 3, host->irq, bdp->fwver[0],bdp->fwver[1],bdp->fwver[2], @@ -1051,8 +1152,8 @@ scsi_lu_t *q; u_long handle; - ENTER("qla1280_queuecommand"); - COMTRACE('C') + /*ENTER("qla1280_queuecommand"); + COMTRACE('C')*/ host = cmd->host; ha = (scsi_qla_host_t *) host->hostdata; @@ -1079,7 +1180,7 @@ { LU_Q(ha, b, t, l) = q; BZERO(q,sizeof(struct scsi_lu)); - DEBUG(sprintf(debug_buff,"Allocate new device queue 0x%x\n",q)); + DEBUG(sprintf(debug_buff,"Allocate new device queue 0x%x\n\r",q)); DEBUG(qla1280_print(debug_buff)); DRIVER_UNLOCK } @@ -1087,8 +1188,12 @@ { CMD_RESULT(cmd) = (int) (DID_BUS_BUSY << 16); qla1280_done_q_put(sp, &ha->done_q_first, &ha->done_q_last); - - schedule_task(&ha->run_qla_bh); +/* 3.22 */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0) /* 3.22 */ + queue_task(&ha->run_qla_bh,&tq_scheduler); +#else /* 3.22 */ + schedule_task(&ha->run_qla_bh); /* 3.22 */ +#endif /* 3.22 */ ha->flags.dpc_sched = TRUE; DRIVER_UNLOCK return(0); @@ -1099,15 +1204,13 @@ handle = INVALID_HANDLE; CMD_HANDLE(cmd) = (unsigned char *)handle; - /* Bookkeeping information */ - sp->r_start = jiffies; /* time the request was received */ - sp->u_start = 0; - /* add the command to our queue */ ha->qthreads++; qla1280_putq_t(q,sp); - DEBUG(sprintf(debug_buff,"qla1280_queuecmd: queue pid=%d, hndl=0x%x\n\r",cmd->pid,handle)); + DEBUG(sprintf(debug_buff, + "qla1280_QC: t=%x CDB=%x I/OSize=0x%x haQueueCount=0x%x\n\r", + t,cmd->cmnd[0],CMD_XFRLEN(cmd),ha->qthreads)); DEBUG(qla1280_print(debug_buff)); /* send command to adapter */ @@ -1117,7 +1220,7 @@ DRIVER_UNLOCK - LEAVE("qla1280_queuecommand"); + /*LEAVE("qla1280_queuecommand");*/ return (0); } @@ -1556,6 +1659,7 @@ { COMTRACE('X') printk(KERN_INFO "scsi(%d): Already in interrupt - returning \n", (int)ha->host_no); + spin_unlock_irqrestore(&io_request_lock, cpu_flags); return; } set_bit(QLA1280_IN_ISR_BIT, (int *)&ha->flags); @@ -1587,7 +1691,7 @@ ha->run_qla_bh.routine = qla1280_do_dpc; COMTRACE('P') - schedule_task(&ha->run_qla_bh); + queue_task_irq(&ha->run_qla_bh,&tq_scheduler); ha->flags.dpc_sched = TRUE; } clear_bit(QLA1280_IN_ISR_BIT, (int *)&ha->flags); @@ -1611,7 +1715,7 @@ * "host->can_queue". This can cause a panic if we were in our interrupt * code . **************************************************************************/ -static void qla1280_do_dpc(void *p) +void qla1280_do_dpc(void *p) { scsi_qla_host_t *ha = (scsi_qla_host_t *) p; #if LINUX_VERSION_CODE > KERNEL_VERSION(2,1,95) @@ -1729,6 +1833,7 @@ scsi_lu_t *q; uint32_t b, t, l; Scsi_Cmnd *cmd; + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95) unsigned long cpu_flags = 0; #endif @@ -1745,7 +1850,8 @@ *done_q_last = NULL; else (*done_q_first)->s_prev = NULL; - cmd = sp->cmd; + + cmd = sp->cmd; b = SCSI_BUS_32(cmd); t = SCSI_TCN_32(cmd); l = SCSI_LUN_32(cmd); @@ -1759,8 +1865,6 @@ q->q_flag &= ~QLA1280_QBUSY; } - q->resp_time += jiffies - sp->r_start; /* Lun bookkeeping information */ - q->act_time += jiffies - sp->u_start; q->io_cnt++; if( sp->dir & BIT_5 ) q->r_cnt++; @@ -1783,7 +1887,28 @@ default: break; } - + /* 3.13 64 and 32 bit */ + /* Release memory used for this I/O */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,18) + if (cmd->use_sg) { + DEBUG(sprintf(debug_buff, + "S/G unmap_sg cmd=%x\n\r",cmd);) + DEBUG(qla1280_print(debug_buff)); + pci_unmap_sg(ha->pdev, cmd->request_buffer, + cmd->use_sg, + scsi_to_pci_dma_dir(cmd->sc_data_direction)); + } + else if (cmd->request_bufflen) { + /*DEBUG(sprintf(debug_buff, + "No S/G unmap_single cmd=%x saved_dma_handle=%lx\n\r", + cmd,sp->saved_dma_handle);) + DEBUG(qla1280_print(debug_buff);)*/ + + pci_unmap_single(ha->pdev,sp->saved_dma_handle, + cmd->request_bufflen, + scsi_to_pci_dma_dir(cmd->sc_data_direction)); + } +#endif /* Call the mid-level driver interrupt handler */ CMD_HANDLE(sp->cmd) = (unsigned char *) 0; ha->actthreads--; @@ -1797,8 +1922,6 @@ qla1280_next(ha, q, b); } DRIVER_UNLOCK - - COMTRACE('d') LEAVE("qla1280_done"); } @@ -1970,7 +2093,7 @@ if (q->q_outcnt >= ha->bus_settings[b].hiwat) q->q_flag |= QLA1280_QBUSY; -#if QLA1280_64BIT_SUPPORT +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,18) if (ha->flags.enable_64bit_addressing) status = qla1280_64bit_start_scsi(ha, sp); else @@ -1987,7 +2110,7 @@ /* Wait for 30 sec for command to be accepted. */ for (cnt = 6000000; cnt; cnt--) { -#if QLA1280_64BIT_SUPPORT +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,18) if (ha->flags.enable_64bit_addressing) status = qla1280_64bit_start_scsi(ha, sp); else @@ -2078,7 +2201,7 @@ ENTER("qla1280_putq_t"); #endif DRIVER_LOCK - DEBUG(sprintf(debug_buff,"Adding to device 0x%p<-(0x%p)\n\r",q,sp)); + DEBUG(sprintf(debug_buff,"Adding to device q=0x%p<-(0x%p)sp\n\r",q,sp)); DEBUG(qla1280_print(debug_buff)); sp->s_next = NULL; if (!q->q_first) /* If queue empty */ @@ -2163,28 +2286,33 @@ { uint8_t status = 1; +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,3,18) + dma_addr_t dma_handle; +#endif #ifdef QL_DEBUG_LEVEL_3 ENTER("qla1280_mem_alloc"); #endif -#ifdef DYNAMIC_MEM_ALLOC - ha->request_ring = qla1280_alloc_phys(REQUEST_ENTRY_SIZE * REQUEST_ENTRY_CNT, - &ha->request_dma); - if(ha->request_ring) { - ha->response_ring = qla1280_alloc_phys(RESPONSE_ENTRY_SIZE * RESPONSE_ENTRY_CNT, - &ha->response_dma); - if(ha->response_ring) { - status = 0; - } - } -#else + /* 3.13 */ + /* get consistent memory allocated for request and response rings */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18) ha->request_ring = &ha->req[0]; ha->request_dma = VIRT_TO_BUS(&ha->req[0]); ha->response_ring = &ha->res[0]; ha->response_dma = VIRT_TO_BUS(&ha->res[0]); status = 0; -#endif +#else + ha->request_ring = pci_alloc_consistent(ha->pdev, + ((REQUEST_ENTRY_CNT+1)*(sizeof(request_t))), + &dma_handle); + ha->request_dma = dma_handle; + ha->response_ring = pci_alloc_consistent(ha->pdev, + ((RESPONSE_ENTRY_CNT+1)*(sizeof(response_t))), + &dma_handle); + ha->response_dma = dma_handle; + status = 0; +#endif if(status) { #if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3) @@ -2228,6 +2356,16 @@ ha->dev[b] = (scsi_lu_t *)NULL; } + /* 3.13 */ + /* free consistent memory allocated for request and response rings */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,18) + pci_free_consistent(ha->pdev, ((REQUEST_ENTRY_CNT+1)*(sizeof(request_t))), + ha->request_ring, ha->request_dma); + + pci_free_consistent(ha->pdev,((RESPONSE_ENTRY_CNT+1)*(sizeof(response_t))), + ha->response_ring, ha->response_dma); +#endif + LEAVE("qlc1280_mem_free"); } @@ -2488,7 +2626,7 @@ /* Verify checksum of loaded RISC code. */ mb[0] = MBC_VERIFY_CHECKSUM; /* mb[1] = ql12_risc_code_addr01; */ - mb[1] = *QLBoardTbl[ha->devnum].fwstart; + mb[1] = *QL1280BoardTbl[ha->devnum].fwstart; if (!(status = qla1280_mailbox_command(ha, BIT_1|BIT_0, &mb[0]))) { @@ -2498,7 +2636,7 @@ #endif mb[0] = MBC_EXECUTE_FIRMWARE; /* mb[1] = ql12_risc_code_addr01; */ - mb[1] = *QLBoardTbl[ha->devnum].fwstart; + mb[1] = *QL1280BoardTbl[ha->devnum].fwstart; qla1280_mailbox_command(ha, BIT_1|BIT_0, &mb[0]); } else @@ -2533,18 +2671,69 @@ qla1280_pci_config(scsi_qla_host_t *ha) { uint8_t status = 1; - uint32_t command; #if MEMORY_MAPPED_IO uint32_t page_offset, base; uint32_t mmapbase; #endif - config_reg_t *creg = 0; uint16_t buf_wd; +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18) + uint32_t command; + config_reg_t *creg = 0; +#endif + ENTER("qla1280_pci_config"); +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,18) + /* + * Set Bus Master Enable, Memory Address Space Enable and + * reset any error bits, in the command register. + */ + pci_read_config_word(ha->pdev, PCI_COMMAND, &buf_wd); + buf_wd &= ~0x7; +#if MEMORY_MAPPED_IO + DEBUG(printk("qla1280: MEMORY MAPPED IO is enabled.\n")); + buf_wd |= BIT_2 + BIT_1 + BIT_0; +#else + buf_wd |= BIT_2 + BIT_0; +#endif + pci_write_config_word(ha->pdev, PCI_COMMAND, buf_wd); + /* + * Reset expansion ROM address decode enable. + */ + pci_read_config_word(ha->pdev, PCI_ROM_ADDRESS, &buf_wd); + buf_wd &= ~PCI_ROM_ADDRESS_ENABLE; + pci_write_config_word(ha->pdev, PCI_ROM_ADDRESS, buf_wd); +#if MEMORY_MAPPED_IO + /* + * Get memory mapped I/O address. + */ + pci_read_config_word(ha->pdev, PCI_BASE_ADDRESS_1, &mmapbase); + mmapbase &= PCI_BASE_ADDRESS_MEM_MASK; + + /* + * Find proper memory chunk for memory map I/O reg. + */ + base = mmapbase & PAGE_MASK; + page_offset = mmapbase - base; + /* + * Get virtual address for I/O registers. + */ + ha->mmpbase = ioremap_nocache(base, page_offset + 256); + if( ha->mmpbase ) + { + ha->mmpbase += page_offset; + /* ha->iobase = ha->mmpbase; */ + status = 0; + } +#else /* MEMORY_MAPPED_IO */ + status = 0; +#endif /* MEMORY_MAPPED_IO */ + +#else /*LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18) */ + /* Get command register. */ - if (pci_read_config_word(ha->pdev,OFFSET(creg->command), &buf_wd) == PCIBIOS_SUCCESSFUL) + if (pcibios_read_config_word(ha->pci_bus,ha->pci_device_fn, OFFSET(creg->command), &buf_wd) == PCIBIOS_SUCCESSFUL) { command = buf_wd; /* @@ -2558,20 +2747,20 @@ #else buf_wd |= BIT_2 + BIT_0; #endif - if( pci_write_config_word(ha->pdev,OFFSET(creg->command), buf_wd) ) + if( pcibios_write_config_word(ha->pci_bus,ha->pci_device_fn, OFFSET(creg->command), buf_wd) ) { printk(KERN_WARNING "qla1280: Could not write config word.\n"); } /* Get expansion ROM address. */ - if (pci_read_config_word(ha->pdev,OFFSET(creg->expansion_rom), &buf_wd) == PCIBIOS_SUCCESSFUL) + if (pcibios_read_config_word(ha->pci_bus,ha->pci_device_fn, OFFSET(creg->expansion_rom), &buf_wd) == PCIBIOS_SUCCESSFUL) { /* Reset expansion ROM address decode enable. */ buf_wd &= ~BIT_0; - if (pci_write_config_word(ha->pdev,OFFSET(creg->expansion_rom), buf_wd) == PCIBIOS_SUCCESSFUL) + if (pcibios_write_config_word(ha->pci_bus,ha->pci_device_fn, OFFSET(creg->expansion_rom), buf_wd) == PCIBIOS_SUCCESSFUL) { #if MEMORY_MAPPED_IO /* Get memory mapped I/O address. */ - pci_read_config_dword(ha->pdev,OFFSET(cfgp->mem_base_addr), &mmapbase); + pcibios_read_config_dword(ha->pci_bus, ha->pci_device_fn,OFFSET(cfgp->mem_base_addr), &mmapbase); mmapbase &= PCI_BASE_ADDRESS_MEM_MASK; /* Find proper memory chunk for memory map I/O reg. */ @@ -2595,6 +2784,7 @@ } } } +#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,18) */ LEAVE("qla1280_pci_config"); return(status); @@ -2725,6 +2915,7 @@ * Returns: * 0 = success. */ +#define DUMP_IT_BACK 0 /* for debug of RISC loading */ STATIC uint8_t qla1280_setup_chip(scsi_qla_host_t *ha) { @@ -2733,37 +2924,52 @@ uint16_t *risc_code_address; long risc_code_size; uint16_t mb[MAILBOX_REGISTER_COUNT]; -#ifdef QLA1280_UNUSED - uint8_t *sp; - int i; -#endif uint16_t cnt; int num; +#if DUMP_IT_BACK + int i; + uint8_t *sp; uint8_t *tbuf; - u_long p_tbuf; +#if BITS_PER_LONG > 32 + dma_addr_t p_tbuf; +#else + uint32_t p_tbuf; +#endif +#endif #ifdef QL_DEBUG_LEVEL_3 ENTER("qla1280_setup_chip"); #endif - if( (tbuf = (uint8_t *)KMALLOC(8000) ) == NULL ) - { - printk("setup_chip: couldn't alloacte memory\n"); - return(1); - } - p_tbuf = VIRT_TO_BUS(tbuf); + /* 3.13 */ +#if DUMP_IT_BACK +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18) + if( (tbuf = (uint8_t *)KMALLOC(8000) ) == NULL ) + { + printk("setup_chip: couldn't alloacte memory\n"); + return(1); + } + p_tbuf = VIRT_TO_BUS(tbuf); +#else + /* get consistent memory allocated for setup_chip */ + tbuf = pci_alloc_consistent(ha->pdev, 8000, &p_tbuf); +#endif +#endif + /* Load RISC code. */ /* risc_address = ql12_risc_code_addr01; risc_code_address = &ql12_risc_code01[0]; risc_code_size = ql12_risc_code_length01; */ - risc_address = *QLBoardTbl[ha->devnum].fwstart; - risc_code_address = QLBoardTbl[ha->devnum].fwcode; - risc_code_size = (long)(*QLBoardTbl[ha->devnum].fwlen & 0xffff); - - DEBUG(printk("qla1280: DMAing RISC code (%d) words.\n",(int)risc_code_size)); - DEBUG(sprintf(debug_buff,"qla1280_setup_chip: Loading RISC code size =(%ld).\n\r",risc_code_size);) + risc_address = *QL1280BoardTbl[ha->devnum].fwstart; + risc_code_address = QL1280BoardTbl[ha->devnum].fwcode; + risc_code_size = (long)(*QL1280BoardTbl[ha->devnum].fwlen & 0xffff); + + DEBUG(printk("qla1280_setup_chip: DMA RISC code (%d) words\n", + (int)risc_code_size)); + DEBUG(sprintf(debug_buff, + "qla1280_setup_chip: DMA RISC code (%d) words\n\r",risc_code_size);) DEBUG(qla1280_print(debug_buff)); num =0; while (risc_code_size > 0 && !status) @@ -2773,29 +2979,31 @@ if ( cnt > risc_code_size ) cnt = risc_code_size; - DEBUG(sprintf(debug_buff,"qla1280_setup_chip: loading risc @ =(0x%p),%d,%d(0x%x).\n\r",risc_code_address,cnt,num,risc_address);) + DEBUG(sprintf(debug_buff, + "qla1280_setup_chip: loading risc @ =(0x%p),%d,%d(0x%x).\n\r", + risc_code_address,cnt,num,risc_address);) DEBUG(qla1280_print(debug_buff)); - DEBUG(printk("qla1280_setup_chip: loading risc @ =code=(0x%p),cnt=%d,seg=%d,addr=0x%x\n\r",risc_code_address,cnt,num,risc_address)); - BCOPY((caddr_t) risc_code_address,(caddr_t) ha->request_ring, (cnt <<1)); + BCOPY((caddr_t) risc_code_address,(caddr_t) ha->request_ring, + (cnt <<1)); + + flush_cache_all(); + mb[0] = MBC_LOAD_RAM; - /* mb[0] = MBC_LOAD_RAM_A64; */ mb[1] = risc_address; mb[4] = cnt; mb[3] = (uint16_t) ha->request_dma & 0xffff; mb[2] = (uint16_t) (ha->request_dma >> 16) & 0xffff; mb[7] = (uint16_t) (MS_64BITS(ha->request_dma) & 0xffff); mb[6] = (uint16_t) (MS_64BITS(ha->request_dma) >> 16) & 0xffff; - DEBUG(printk("qla1280_setup_chip: op=%d 0x%lx = 0x%4x,0x%4x,0x%4x,0x%4x\n",mb[0],ha->request_dma,mb[6],mb[7],mb[2],mb[3])); + DEBUG(printk("qla1280_setup_chip: op=%d 0x%p = 0x%4x,0x%4x,0x%4x,0x%4x\n",mb[0],ha->request_dma,mb[6],mb[7],mb[2],mb[3])); if( (status = qla1280_mailbox_command(ha, BIT_4|BIT_3|BIT_2|BIT_1|BIT_0, &mb[0])) ) { printk("Failed to load partial segment of f/w\n"); break; } - /* dump it back */ - -#if 0 - mb[0] = MBC_DUMP_RAM_A64; +#if DUMP_IT_BACK + mb[0] = MBC_READ_RAM_WORD; mb[1] = risc_address; mb[4] = cnt; mb[3] = (uint16_t) p_tbuf & 0xffff; @@ -2803,10 +3011,13 @@ mb[7] = (uint16_t) (p_tbuf >> 32) & 0xffff; mb[6] = (uint16_t) (p_tbuf >> 48) & 0xffff; - if( (status = qla1280_mailbox_command(ha, BIT_4|BIT_3|BIT_2|BIT_1|BIT_0, - &mb[0])) ) + if( (status = qla1280_mailbox_command(ha, + BIT_4|BIT_3|BIT_2|BIT_1|BIT_0,&mb[0])) ) { printk("Failed to dump partial segment of f/w\n"); + DEBUG(sprintf(debug_buff, + "setup_chip: Failed to dump partial segment of f/w\n\r");) + DEBUG(qla1280_print(debug_buff)); break; } sp = (uint8_t *)ha->request_ring; @@ -2814,51 +3025,20 @@ { if( tbuf[i] != sp[i] ) { - printk("qla1280 : firmware compare error @ byte (0x%x)\n",i); - break; + printk("qla1280_setup_chip: FW compare error @ byte(0x%x) loop#=%x\n",i,num); + printk("setup_chip: FWbyte=%x FWfromChip=%x\n",sp[i],tbuf[i]); + DEBUG(sprintf(debug_buff, + "qla1280_setup_chip: FW compare error @ byte(0x%x) loop#=%x\n\r",i);) + DEBUG(qla1280_print(debug_buff);) + /*break;*/ } } - #endif risc_address += cnt; risc_code_size = risc_code_size - cnt; risc_code_address = risc_code_address + cnt; num++; } -#ifdef QLA1280_UNUSED - DEBUG(ql_debug_print = 0;) - { - for (i = 0; i < ql12_risc_code_length01; i++) - { - mb[0] = 0x4; - mb[1] = ql12_risc_code_addr01 + i; - mb[2] = ql12_risc_code01[i]; - - status = qla1280_mailbox_command(ha, BIT_2|BIT_1|BIT_0, - &mb[0]); - if (status) - { - printk("qla1280 : firmware load failure\n"); - break; - } - - mb[0] = 0x5; - mb[1] = ql12_risc_code_addr01 + i; - mb[2] = 0; - - status = qla1280_mailbox_command(ha, BIT_2|BIT_1|BIT_0, - &mb[0]); - if (status) - { - printk("qla1280 : firmware dump failure\n"); - break; - } - if( mb[2] != ql12_risc_code01[i] ) - printk("qla1280 : firmware compare error @ (0x%x)\n",ql12_risc_code_addr01+i); - } - } - DEBUG(ql_debug_print = 1;) -#endif /* Verify checksum of loaded RISC code. */ if (!status) @@ -2866,22 +3046,29 @@ DEBUG(printk("qla1280_setup_chip: Verifying checksum of loaded RISC code.\n");) mb[0] = MBC_VERIFY_CHECKSUM; /* mb[1] = ql12_risc_code_addr01; */ - mb[1] = *QLBoardTbl[ha->devnum].fwstart; + mb[1] = *QL1280BoardTbl[ha->devnum].fwstart; if (!(status = qla1280_mailbox_command(ha, BIT_1|BIT_0, &mb[0]))) { /* Start firmware execution. */ DEBUG(qla1280_print("qla1280_setup_chip: start firmware running.\n\r");) mb[0] = MBC_EXECUTE_FIRMWARE; - /* mb[1] = ql12_risc_code_addr01; */ - mb[1] = *QLBoardTbl[ha->devnum].fwstart; + mb[1] = *QL1280BoardTbl[ha->devnum].fwstart; qla1280_mailbox_command(ha, BIT_1|BIT_0, &mb[0]); } else printk("qla1280_setup_chip: Failed checksum.\n"); } - KMFREE(tbuf,8000); + /* 3.13 */ +#if DUMP_IT_BACK +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18) + KMFREE(tbuf,8000); +#else + /* free consistent memory allocated for setup_chip */ + pci_free_consistent(ha->pdev, 8000, tbuf, p_tbuf); +#endif +#endif #if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3) if (status) @@ -3158,9 +3345,29 @@ /* Disable RISC load of firmware. */ ha->flags.disable_risc_code_load = nv->cntr_flags_1.disable_loading_risc_code; - /* Enable 64bit addressing. */ - ha->flags.enable_64bit_addressing = - nv->cntr_flags_1.enable_64bit_addressing; + +#if BITS_PER_LONG > 32 + /* Enable 64bit addressing for OS/System combination supporting it */ + /* actual NVRAM bit is: nv->cntr_flags_1.enable_64bit_addressing */ + /* but we will ignore it and use BITS_PER_LONG macro to setup for */ + /* 64 or 32 bit access of host memory in all x86/ia-64/Alpha systems */ + ha->flags.enable_64bit_addressing = 1; +#else + ha->flags.enable_64bit_addressing = 0; +#endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,18) + if (ha->flags.enable_64bit_addressing) { + printk("[[[ qla1x160: 64 Bit PCI Addressing Enabled ]]]\n"); + +#if BITS_PER_LONG > 32 + /* Update our PCI device dma_mask for full 64 bit mask */ + //ha->pdev->dma_mask = (pci_dma_t) 0xffffffffffffffffull; + ha->pdev->dma_mask = 0xffffffffffffffff; + +#endif + } +#endif /* Set ISP hardware DMA burst */ mb[0] = nv->isp_config.c; @@ -3844,7 +4051,7 @@ #endif } -#if QLA1280_64BIT_SUPPORT +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,3,18) /* * qla1280_64bit_start_scsi * The start SCSI is responsible for building request packets on @@ -3869,10 +4076,13 @@ uint16_t seg_cnt; struct scatterlist *sg = (struct scatterlist *) NULL; uint32_t *dword_ptr; + dma_addr_t dma_handle; -#ifdef QL_DEBUG_LEVEL_3 ENTER("qla1280_64bit_start_scsi:"); -#endif + + DEBUG(sprintf(debug_buff, + "64bit_start: cmd=%x sp=%x CDB=%x\n\r",cmd,sp,cmd->cmnd[0]);) + DEBUG(qla1280_print(debug_buff)); if( qla1280_check_for_dead_scsi_bus(ha, sp) ) { @@ -3883,9 +4093,10 @@ seg_cnt = 0; req_cnt = 1; if (cmd->use_sg) - { - seg_cnt = cmd->use_sg; + { /* 3.13 64 bit */ sg = (struct scatterlist *) cmd->request_buffer; + seg_cnt = pci_map_sg(ha->pdev,sg,cmd->use_sg, + scsi_to_pci_dma_dir(cmd->sc_data_direction)); if (seg_cnt > 2) { @@ -3896,7 +4107,7 @@ } else if (cmd->request_bufflen) /* If data transfer. */ { - DEBUG(printk("Single data transfer (0x%x)\n",cmd->request_bufflen)); + /*DEBUG(printk("Single data transfer len=0x%x\n",cmd->request_bufflen));*/ seg_cnt = 1; } @@ -3957,7 +4168,7 @@ /* Load SCSI command packet. */ pkt->cdb_len = (uint16_t)CMD_CDBLEN(cmd); BCOPY(&(CMD_CDBP(cmd)), pkt->scsi_cdb, pkt->cdb_len); - DEBUG(printk("Build packet for command[0]=0x%x\n",pkt->scsi_cdb[0])); + //DEBUG(printk("Build packet for command[0]=0x%x\n",pkt->scsi_cdb[0])); /* * Load data segments. @@ -3983,12 +4194,17 @@ /* Load command entry data segments. */ for (cnt = 0; cnt < 2 && seg_cnt; cnt++, seg_cnt--) { - DEBUG(sprintf(debug_buff,"SG Segment ap=0x%p, len=0x%x\n\r",sg->address,sg->length)); - DEBUG(qla1280_print(debug_buff)); - *dword_ptr++ = cpu_to_le32(VIRT_TO_BUS_LOW(sg->address)); - *dword_ptr++ = cpu_to_le32(VIRT_TO_BUS_HIGH(sg->address)); - *dword_ptr++ = sg->length; + /* 3.13 64 bit */ + *dword_ptr++ = cpu_to_le32(pci_dma_lo32(sg_dma_address(sg))); + *dword_ptr++ = cpu_to_le32(pci_dma_hi32(sg_dma_address(sg))); + *dword_ptr++ = cpu_to_le32(sg_dma_len(sg)); sg++; + DEBUG(sprintf(debug_buff, + "S/G Segment phys_addr=%x %x, len=0x%x\n\r", + cpu_to_le32(pci_dma_hi32(sg_dma_address(sg))), + cpu_to_le32(pci_dma_lo32(sg_dma_address(sg))), + cpu_to_le32(sg_dma_len(sg)));) + DEBUG(qla1280_print(debug_buff)); } #ifdef QL_DEBUG_LEVEL_5 qla1280_print( @@ -4005,6 +4221,10 @@ /* * Build continuation packets. */ + DEBUG(sprintf(debug_buff, + "S/G Building Continuation...seg_cnt=0x%x remains\n\r", + seg_cnt);) + DEBUG(qla1280_print(debug_buff)); while (seg_cnt > 0) { /* Adjust ring index. */ @@ -4038,10 +4258,17 @@ /* Load continuation entry data segments. */ for (cnt = 0; cnt < 5 && seg_cnt; cnt++, seg_cnt--) { - *dword_ptr++ = cpu_to_le32(VIRT_TO_BUS_LOW(sg->address)); - *dword_ptr++ = cpu_to_le32(VIRT_TO_BUS_HIGH(sg->address)); - *dword_ptr++ = sg->length; - sg++; + /* 3.13 64 bit */ + *dword_ptr++ = cpu_to_le32(pci_dma_lo32(sg_dma_address(sg))); + *dword_ptr++ = cpu_to_le32(pci_dma_hi32(sg_dma_address(sg))); + *dword_ptr++ = cpu_to_le32(sg_dma_len(sg)); + DEBUG(sprintf(debug_buff, + "S/G Segment Cont. phys_addr=%x %x, len=0x%x\n\r", + cpu_to_le32(pci_dma_hi32(sg_dma_address(sg))), + cpu_to_le32(pci_dma_lo32(sg_dma_address(sg))), + cpu_to_le32(sg_dma_len(sg)));) + DEBUG(qla1280_print(debug_buff)); + sg++; } #ifdef QL_DEBUG_LEVEL_5 qla1280_print( @@ -4058,11 +4285,21 @@ #endif } } - else /* No scatter gather data transfer */ - { - *dword_ptr++ = cpu_to_le32(VIRT_TO_BUS_LOW(cmd->request_buffer)); - *dword_ptr++ = cpu_to_le32(VIRT_TO_BUS_HIGH(cmd->request_buffer)); - *dword_ptr = (uint32_t) cmd->request_bufflen; + else /* No scatter gather data transfer */ + { /* 3.13 64 bit */ + dma_handle = pci_map_single(ha->pdev, + cmd->request_buffer, + cmd->request_bufflen, + scsi_to_pci_dma_dir(cmd->sc_data_direction)); + /* save dma_handle for pci_unmap_single */ + sp->saved_dma_handle = dma_handle; + + *dword_ptr++ = cpu_to_le32(pci_dma_lo32(dma_handle)); + *dword_ptr++ = cpu_to_le32(pci_dma_hi32(dma_handle)); + *dword_ptr = (uint32_t) cmd->request_bufflen; + /*DEBUG(sprintf(debug_buff, + "No S/G map_single saved_dma_handle=%lx\n\r",dma_handle)); + DEBUG(qla1280_print(debug_buff));*/ #ifdef QL_DEBUG_LEVEL_5 qla1280_print( "qla1280_64bit_start_scsi: No scatter/gather command packet data - c"); @@ -4077,12 +4314,12 @@ #endif } } -#ifdef QL_DEBUG_LEVEL_5 - else /* No data transfer */ + else /* No data transfer */ { *dword_ptr++ = (uint32_t) 0; *dword_ptr++ = (uint32_t) 0; *dword_ptr = (uint32_t) 0; +#ifdef QL_DEBUG_LEVEL_5 qla1280_print( "qla1280_64bit_start_scsi: No data, command packet data - c"); qla1280_print(" b "); @@ -4093,8 +4330,8 @@ qla1280_output_number((uint32_t)SCSI_LUN_32(cmd), 10); qla1280_print("\n\r"); qla1280_dump_buffer((caddr_t)pkt, REQUEST_ENTRY_SIZE); - } #endif + } /* Adjust ring index. */ ha->req_ring_index++; if (ha->req_ring_index == REQUEST_ENTRY_CNT) @@ -4106,6 +4343,10 @@ ha->request_ring_ptr++; /* Set chip new ring index. */ + DEBUG(qla1280_print("qla1280_64bit_start_scsi: Wakeup RISC for pending command\n\r")); + ha->qthreads--; + sp->flags |= SRB_SENT; + ha->actthreads++; WRT_REG_WORD(®->mailbox4, ha->req_ring_index); } else @@ -4146,7 +4387,7 @@ #endif return(status); } -#endif /* QLA1280_64BIT_SUPPORT */ +#endif /* * qla1280_32bit_start_scsi @@ -4181,8 +4422,15 @@ uint8_t *data_ptr; uint32_t *dword_ptr; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,18) + dma_addr_t dma_handle; +#endif + ENTER("qla1280_32bit_start_scsi"); + DEBUG(sprintf(debug_buff, + "32bit_start: cmd=%x sp=%x CDB=%x\n\r",cmd,sp,cmd->cmnd[0]);) + DEBUG(qla1280_print(debug_buff)); if( qla1280_check_for_dead_scsi_bus(ha, sp) ) { @@ -4199,8 +4447,15 @@ * differences and the kernel SG list uses virtual addresses where * we need physical addresses. */ - seg_cnt = cmd->use_sg; sg = (struct scatterlist *) cmd->request_buffer; + /* 3.13 32 bit */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18) + seg_cnt = cmd->use_sg; +#else + seg_cnt = pci_map_sg(ha->pdev,sg,cmd->use_sg, + scsi_to_pci_dma_dir(cmd->sc_data_direction)); +#endif + /* * if greater than four sg entries then we need to allocate * continuation entries @@ -4211,17 +4466,22 @@ if ((uint16_t)(seg_cnt - 4) % 7) req_cnt++; } - DEBUG(sprintf(debug_buff,"S/G for data transfer -num segs(%d), req blk cnt(%d)\n\r",seg_cnt,req_cnt)); + DEBUG(sprintf(debug_buff, + "S/G Transfer cmd=%x seg_cnt=0x%x, req_cnt=%x\n\r", + cmd,seg_cnt,req_cnt)); DEBUG(qla1280_print(debug_buff)); } else if (cmd->request_bufflen) /* If data transfer. */ { - DEBUG(printk("Single data transfer (0x%x)\n",cmd->request_bufflen)); + DEBUG(sprintf(debug_buff, + "No S/G transfer t=%x cmd=%x len=%x CDB=%x\n\r", + SCSI_TCN_32(cmd),cmd,cmd->request_bufflen,cmd->cmnd[0])); + DEBUG(qla1280_print(debug_buff)); seg_cnt = 1; } else { - DEBUG(printk("No data transfer \n")); + //DEBUG(printk("No data transfer \n")); seg_cnt = 0; } @@ -4238,7 +4498,8 @@ ha->req_q_cnt = REQUEST_ENTRY_CNT - (ha->req_ring_index - cnt); } - DEBUG(sprintf(debug_buff,"Number of free entries = (%d)\n\r",ha->req_q_cnt)); + DEBUG(sprintf(debug_buff,"Number of free entries=(%d) seg_cnt=0x%x\n\r", + ha->req_q_cnt,seg_cnt)); DEBUG(qla1280_print(debug_buff)); /* If room for request in request ring. */ if ((uint16_t)(req_cnt + 2) < ha->req_q_cnt) @@ -4286,20 +4547,15 @@ data_ptr = (uint8_t *) &(CMD_CDBP(cmd)); for (cnt = 0; cnt < pkt->cdb_len; cnt++) pkt->scsi_cdb[cnt] = *data_ptr++; - DEBUG(printk("Build packet for command[0]=0x%x\n",pkt->scsi_cdb[0])); + //DEBUG(printk("Build packet for command[0]=0x%x\n",pkt->scsi_cdb[0])); /* * Load data segments. */ if (seg_cnt) { - DEBUG(printk("loading data segments..\n")); /* Set transfer direction (READ and WRITE) */ /* Linux doesn't tell us */ - /* - * 3/10 dg - Normally, we should need this check with our F/W - * but because of a small issue with it we do. - * * For block devices, cmd->request.cmd has the operation * For character devices, this isn't always set properly, so * we need to check data_cmnd[0]. This catches the conditions @@ -4325,15 +4581,32 @@ /* Load command entry data segments. */ for (cnt = 0; cnt < 4 && seg_cnt; cnt++, seg_cnt--) { + /* 3.13 32 bit */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18) *dword_ptr++ = (uint32_t) cpu_to_le32(VIRT_TO_BUS(sg->address)); *dword_ptr++ = sg->length; - DEBUG(sprintf(debug_buff,"SG Segment ap=0x%p, len=0x%x\n\r",sg->address,sg->length)); + DEBUG(sprintf(debug_buff, + "S/G Segment phys_addr=0x%x, len=0x%x\n\r", + cpu_to_le32(VIRT_TO_BUS(sg->address)),sg->length)); + DEBUG(qla1280_print(debug_buff)); +#else + *dword_ptr++ = cpu_to_le32(pci_dma_lo32(sg_dma_address(sg))); + *dword_ptr++ = cpu_to_le32(sg_dma_len(sg)); + DEBUG(sprintf(debug_buff, + "S/G Segment phys_addr=0x%x, len=0x%x\n\r", + cpu_to_le32(pci_dma_lo32(sg_dma_address(sg))), + cpu_to_le32(sg_dma_len(sg)));) DEBUG(qla1280_print(debug_buff)); +#endif sg++; } /* * Build continuation packets. */ + DEBUG(sprintf(debug_buff, + "S/G Building Continuation...seg_cnt=0x%x remains\n\r", + seg_cnt);) + DEBUG(qla1280_print(debug_buff)); while (seg_cnt > 0) { /* Adjust ring index. */ @@ -4368,9 +4641,25 @@ /* Load continuation entry data segments. */ for (cnt = 0; cnt < 7 && seg_cnt; cnt++, seg_cnt--) { - *dword_ptr++ = (u_int) cpu_to_le32(VIRT_TO_BUS(sg->address)); - *dword_ptr++ = sg->length; - sg++; + /* 3.13 32 bit */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18) + *dword_ptr++ = (u_int) cpu_to_le32(VIRT_TO_BUS(sg->address)); + *dword_ptr++ = sg->length; + DEBUG(sprintf(debug_buff, + "S/G Segment Cont. phys_addr=0x%x, len=0x%x\n\r", + cpu_to_le32(pci_dma_lo32(VIRT_TO_BUS(sg->address))), + sg->length);) + DEBUG(qla1280_print(debug_buff)); +#else + *dword_ptr++ = cpu_to_le32(pci_dma_lo32(sg_dma_address(sg))); + *dword_ptr++ = cpu_to_le32(sg_dma_len(sg)); + DEBUG(sprintf(debug_buff, + "S/G Segment Cont. phys_addr=0x%x, len=0x%x\n\r", + cpu_to_le32(pci_dma_lo32(sg_dma_address(sg))), + cpu_to_le32(sg_dma_len(sg)));) + DEBUG(qla1280_print(debug_buff)); +#endif + sg++; } #ifdef QL_DEBUG_LEVEL_5 qla1280_print( @@ -4385,14 +4674,28 @@ #endif } } - else /* No scatter gather data transfer */ + else /* No S/G data transfer */ { + /* 3.13 32 bit */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18) *dword_ptr++ = (uint32_t) cpu_to_le32(VIRT_TO_BUS(cmd->request_buffer)); *dword_ptr = (uint32_t) cmd->request_bufflen; - DEBUG(printk("Single Segment ap=0x%p, len=0x%x\n",cmd->request_buffer,cmd->request_bufflen)); +#else + dma_handle = pci_map_single(ha->pdev, + cmd->request_buffer, + cmd->request_bufflen, + scsi_to_pci_dma_dir(cmd->sc_data_direction)); + sp->saved_dma_handle = dma_handle; + + *dword_ptr++ = cpu_to_le32(pci_dma_lo32(dma_handle)); + *dword_ptr = (uint32_t) cmd->request_bufflen; + /*DEBUG(sprintf(debug_buff, + "No S/G map_single saved_dma_handle=%lx\n\r",dma_handle)); + DEBUG(qla1280_print(debug_buff));*/ +#endif } } - else /* No data transfer */ + else /* No data transfer at all */ { *dword_ptr++ = (uint32_t) 0; *dword_ptr = (uint32_t) 0; @@ -4420,10 +4723,8 @@ /* Set chip new ring index. */ DEBUG(qla1280_print("qla1280_32bit_start_scsi: Wakeup RISC for pending command\n\r")); ha->qthreads--; - sp->u_start = jiffies; sp->flags |= SRB_SENT; ha->actthreads++; - /* qla1280_output_number((uint32_t)ha->actthreads++, 16); */ WRT_REG_WORD(®->mailbox4, ha->req_ring_index); } else @@ -4431,7 +4732,7 @@ status = 1; #ifdef QL_DEBUG_LEVEL_2 qla1280_print( - "qla1280_32bit_start_scsi: NO ROOM IN OUTSTANDING ARRAY\n\r"); + "qla1280_32bit_start_scsi: NO ROOM IN OUTSTANDING ARRAY\n\r"); qla1280_print(" req_q_cnt="); qla1280_output_number((uint32_t)ha->req_q_cnt, 16); qla1280_print("\n\r"); @@ -4465,6 +4766,7 @@ return(status); } + /* * qla1280_req_pkt * Function is responsible for locking ring and @@ -4895,7 +5197,7 @@ { device_reg_t *reg = ha->iobase; response_t *pkt; - srb_t *sp; + srb_t *sp = 0; uint16_t mailbox[MAILBOX_REGISTER_COUNT]; uint16_t *wptr; uint32_t index; @@ -4909,9 +5211,11 @@ /* Check for mailbox interrupt. */ mailbox[0] = RD_REG_WORD(®->semaphore); + if (mailbox[0] & BIT_0) { /* Get mailbox data. */ + //DEBUG(qla1280_print("qla1280_isr: In Get mailbox data \n\r");) wptr = &mailbox[0]; *wptr++ = RD_REG_WORD(®->mailbox0); @@ -4944,7 +5248,7 @@ { case MBA_SCSI_COMPLETION: /* Response completion */ #ifdef QL_DEBUG_LEVEL_5 - qla1280_print("qla1280_isr: mailbox response completion\n\r"); + qla1280_print("qla1280_isr: mailbox SCSI response completion\n\r"); #endif if (ha->flags.online) { @@ -4973,9 +5277,11 @@ else (*done_q_last)->s_next = sp; *done_q_last = sp; + } else { + #ifdef QL_DEBUG_LEVEL_2 qla1280_print("qla1280_isr: ISP invalid handle\n\r"); #endif @@ -5047,6 +5353,7 @@ #endif break; default: + //DEBUG(qla1280_print("qla1280_isr: default case of switch MB \n\r");) if (mailbox[0] < MBA_ASYNC_EVENT) { wptr = &mailbox[0]; @@ -5063,9 +5370,9 @@ break; } } - else + else { WRT_REG_WORD(®->host_cmd, HC_CLR_RISC_INT); - + } /* * Response ring */ @@ -5129,6 +5436,7 @@ qla1280_error_entry(ha, pkt, done_q_first, done_q_last); + /* Adjust ring index. */ ha->rsp_ring_index++; if (ha->rsp_ring_index == RESPONSE_ENTRY_CNT) @@ -5312,9 +5620,12 @@ } pkt->scsi_status = S_CKCON; pkt->option_flags |= (uint32_t)OF_SSTS | (uint32_t)OF_NO_DATA; + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,18) if (ha->flags.enable_64bit_addressing) qla1280_64bit_continue_io(ha, pkt, 0, 0); else +#endif qla1280_32bit_continue_io(ha, pkt, 0, 0); break; case 0x16: /* Requested Capability Not Available */ @@ -5673,10 +5984,12 @@ (uint32_t)OF_NO_DATA; break; } +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,18) if (ha->flags.enable_64bit_addressing) - qla1280_64bit_continue_io(ha, pkt, len, (paddr32_t *)&phy_addr); + qla1280_64bit_continue_io(ha, pkt, len, (paddr32_t *)&phy_addr); else - qla1280_32bit_continue_io(ha, pkt, len, (paddr32_t *)&phy_addr); +#endif + qla1280_32bit_continue_io(ha, pkt, len, (paddr32_t *)&phy_addr); break; default: break; @@ -5750,11 +6063,13 @@ ha->outstanding_cmds[pkt->handle] = 0; cp = sp->cmd; + /* Generate LU queue on cntrl, target, LUN */ b = SCSI_BUS_32(cp); t = SCSI_TCN_32(cp); l = SCSI_LUN_32(cp); q = LU_Q(ha, b, t, l); + if( pkt->comp_status || pkt->scsi_status ) { DEBUG(qla1280_print( "scsi: comp_status = ");) @@ -5885,7 +6200,7 @@ /* Place command on done queue. */ qla1280_done_q_put(sp, done_q_first, done_q_last); } -#if QLA1280_64BIT_SUPPORT +#if BITS_PER_LONG > 32 else if (pkt->entry_type == COMMAND_A64_TYPE) { #ifdef QL_DEBUG_LEVEL_2 @@ -5962,7 +6277,6 @@ sp->timeout += 2; */ /* Place request back on top of device queue. */ - /* sp->flags &= ~(SRB_SENT | SRB_TIMEOUT); */ sp->flags = 0; qla1280_putq_t(q, sp); } @@ -6080,7 +6394,7 @@ } } #ifdef QL_DEBUG_LEVEL_3 - qla1280_print("qla1280_restart_queues: exiting normally\n"); + qla1280_print("qla1280_restart_queues: exiting normally\n\r"); #endif } @@ -6166,13 +6480,15 @@ return(ret); } - -/* - * Declarations for load module - */ -static Scsi_Host_Template driver_template = QLA1280_LINUX_TEMPLATE; - +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0) +#ifdef MODULE +Scsi_Host_Template driver_template = QLA1280_LINUX_TEMPLATE; #include "scsi_module.c" +#endif +#else /* new kernel scsi initialization scheme */ +static Scsi_Host_Template driver_template = QLA1280_LINUX_TEMPLATE; +#include "scsi_module.c" +#endif /************************************************************************ * qla1280_check_for_dead_scsi_bus * @@ -6283,13 +6599,13 @@ #if MEMORY_MAPPED_IO ret = *port; #else - ret = inb((int)port); + ret = inb((long)port); #endif if (ql_debug_print) { qla1280_print("qla1280_getbyte: address = "); - qla1280_output_number((uint32_t)port, 16); + qla1280_output_number((unsigned long)port, 16); qla1280_print(" data = 0x"); qla1280_output_number((uint32_t)ret, 16); qla1280_print("\n\r"); @@ -6309,13 +6625,13 @@ #if MEMORY_MAPPED_IO ret = *port; #else - ret = inw((int)port); + ret = inw((unsigned long)port); #endif if (ql_debug_print) { qla1280_print("qla1280_getword: address = "); - qla1280_output_number((uint32_t)port, 16); + qla1280_output_number((unsigned long)port, 16); qla1280_print(" data = 0x"); qla1280_output_number((uint32_t)ret, 16); qla1280_print("\n\r"); @@ -6335,13 +6651,13 @@ #if MEMORY_MAPPED_IO ret = *port; #else - ret = inl((int)port); + ret = inl((unsigned long)port); #endif if (ql_debug_print) { qla1280_print("qla1280_getdword: address = "); - qla1280_output_number((uint32_t)port, 16); + qla1280_output_number((unsigned long)port, 16); qla1280_print(" data = 0x"); qla1280_output_number((uint32_t)ret, 16); qla1280_print("\n\r"); @@ -6359,13 +6675,13 @@ #if MEMORY_MAPPED_IO *port = data; #else - outb(data, (int)port); + outb(data, (unsigned long)port); #endif if (ql_debug_print) { qla1280_print("qla1280_putbyte: address = "); - qla1280_output_number((uint32_t)port, 16); + qla1280_output_number((unsigned long)port, 16); qla1280_print(" data = 0x"); qla1280_output_number((uint32_t)data, 16); qla1280_print("\n\r"); @@ -6384,14 +6700,14 @@ #ifdef _LINUX_IOPORTS outw(data, (int)port); #else - outw((int)port, data); + outw((unsigned long)port, data); #endif #endif if (ql_debug_print) { qla1280_print("qla1280_putword: address = "); - qla1280_output_number((uint32_t)port, 16); + qla1280_output_number((unsigned long)port, 16); qla1280_print(" data = 0x"); qla1280_output_number((uint32_t)data, 16); qla1280_print("\n\r"); @@ -6410,14 +6726,14 @@ #ifdef _LINUX_IOPORTS outl(data,(int)port); #else - outl((int)port, data); + outl((unsigned long)port, data); #endif #endif if (ql_debug_print) { qla1280_print("qla1280_putdword: address = "); - qla1280_output_number((uint32_t)port, 16); + qla1280_output_number((unsigned long)port, 16); qla1280_print(" data = 0x"); qla1280_output_number((uint32_t)data, 16); qla1280_print("\n\r"); @@ -6441,8 +6757,7 @@ /* * Out character to COM2 port. - * PORT must be at standard address for COM2 = 0x2F8, - * or COM1 = 0x3F8 + * PORT must be at standard address for COM1 = 0x3f8 */ #define OUTB(addr,data) outb((data),(addr)) @@ -6452,7 +6767,7 @@ #ifdef QL_DEBUG_CONSOLE printk("%c", c); #else - int com_addr = 0x2f8; + int com_addr = 0x3f8; int hardware_flow_control = 1; int software_flow_control = 0; uint8_t data; @@ -6464,7 +6779,7 @@ }while (!(data & BIT_6)); /* - * Set BAUD rate for COM2 to 19200 (0x6) + * Set BAUD rate for COM2 to 9600 (0x6) */ /* Select rate divisor. */ @@ -6660,8 +6975,6 @@ qla1280_print(debug_buff); sprintf(debug_buff," Pid=%d, SP=0x%p\n\r", (int)cmd->pid, CMD_SP(cmd)); qla1280_print(debug_buff); - sprintf(debug_buff," r_start=0x%lx, u_start=0x%lx\n\r",sp->r_start,sp->u_start); - qla1280_print(debug_buff); sprintf(debug_buff," underflow size = 0x%x, direction=0x%x, req.cmd=0x%x \n\r", cmd->underflow, sp->dir,cmd->request.cmd); qla1280_print(debug_buff); } @@ -6689,23 +7002,6 @@ } #endif -#ifdef QLA1280_UNUSED -/************************************************************************** - * ql1280_dump_regs - * - **************************************************************************/ -static void qla1280_dump_regs(struct Scsi_Host *host) -{ - printk("Mailbox registers:\n"); - printk("qla1280 : mbox 0 0x%04x \n", inw(host->io_port + 0x70)); - printk("qla1280 : mbox 1 0x%04x \n", inw(host->io_port + 0x72)); - printk("qla1280 : mbox 2 0x%04x \n", inw(host->io_port + 0x74)); - printk("qla1280 : mbox 3 0x%04x \n", inw(host->io_port + 0x76)); - printk("qla1280 : mbox 4 0x%04x \n", inw(host->io_port + 0x78)); - printk("qla1280 : mbox 5 0x%04x \n", inw(host->io_port + 0x7a)); -} -#endif - #if STOP_ON_ERROR @@ -6732,9 +7028,6 @@ printk("HA flags =0x%lx\n", *fp); DEBUG2(ql_debug_print = 1;) /* DEBUG2(ql1280_dump_device((scsi_qla_host_t *) host->hostdata)); */ -#ifdef QLA1280_UNUSED - qla1280_dump_regs(host); -#endif sti(); panic("Ooops"); /* cli(); @@ -6747,11 +7040,6 @@ } #endif -#ifdef QLA1280_UNUSED -static void qla1280_set_flags(char * s) -{ -} -#endif /************************************************************************** * qla1280_setup @@ -6765,24 +7053,6 @@ { char *end, *str, *cp; -#ifdef QLA1280_UNUSED - static struct - { - const char *name; - int siz; - void (*func)(); - int arg; - } options[] = - { - { "dump_regs", 9, &qla1280_dump_regs, 0 - }, - { "verbose", 7, &qla1280_set_flags, 0x1 - }, - { "", 0, NULL, 0 - } - }; -#endif - printk("scsi: Processing Option str = %s\n", s); end = strchr(s, '\0'); /* locate command */ @@ -6831,4 +7101,3 @@ * tab-width: 8 * End: */ - diff -urN linux-2.4.10/drivers/scsi/qla1280.h linux-2.4.10-lia/drivers/scsi/qla1280.h --- linux-2.4.10/drivers/scsi/qla1280.h Mon Sep 24 15:07:46 2001 +++ linux-2.4.10-lia/drivers/scsi/qla1280.h Mon Sep 24 23:02:31 2001 @@ -1,169 +1,35 @@ -/************************************************************************* - * QLOGIC LINUX SOFTWARE - * - * QLogic ISP1x80/1x160 device driver for Linux 2.3.x (redhat 6.x). - * - * COPYRIGHT (C) 1996-2000 QLOGIC CORPORATION - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the Qlogic's Linux Software License. - * - * This program is WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistribution's or source code must retain the above copyright - * notice, this list of conditions, and the following disclaimer, - * without modification, immediately at the beginning of the file. - * 2. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - *****************************************************************************/ - -/************************************************************************************* - QLOGIC CORPORATION SOFTWARE - "GNU" GENERAL PUBLIC LICENSE - TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION - AND MODIFICATION - -This GNU General Public License ("License") applies solely to QLogic Linux -Software ("Software") and may be distributed under the terms of this License. - -1. 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Each time you redistribute the Software (or any work based on the Software), the -recipient automatically receives a license from the original licensor to copy, distribute -or modify the Software subject to these terms and conditions. You may not impose any -further restrictions on the recipients' exercise of the rights granted herein. You are -not responsible for enforcing compliance by third parties to this License. - -7. If, as a consequence of a court judgment or allegation of patent infringement or for -any other reason (not limited to patent issues), conditions are imposed on you -(whether by court order, agreement or otherwise) that contradict the conditions of this -License, they do not excuse you from the conditions of this License. If you cannot -distribute so as to satisfy simultaneously your obligations under this License -and any other pertinent obligations, then as a consequence you may not distribute the -Software at all. - -If any portion of this section is held invalid or unenforceable under any particular -circumstance, the balance of the section is intended to apply and the section as a whole -is intended to apply in other circumstances. -NO WARRANTY - -11. THE SOFTWARE IS PROVIDED WITHOUT A WARRANTY OF ANY KIND. THERE IS NO -WARRANTY FOR THE SOFTWARE, TO THE EXTENT PERMITTED BY APPLICABLE LAW. -EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR -OTHER PARTIES PROVIDE THE SOFTWARE "AS IS" WITHOUT WARRANTY OF ANY KIND, -EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE -ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE SOFTWARE IS WITH YOU. -SHOULD THE SOFTWARE PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL -NECESSARY SERVICING, REPAIR OR CORRECTION. - -12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING -WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR -REDISTRIBUTE THE SOFTWARE AS PERMITTED ABOVE, BE LIABLE TO YOU FOR -DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL -DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE SOFTWARE (INCLUDING -BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR -LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE SOFTWARE TO -OPERATE WITH ANY OTHER SOFTWARES), EVEN IF SUCH HOLDER OR OTHER PARTY HAS -BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -END OF TERMS AND CONDITIONS +/******************************************************************************** +* QLOGIC LINUX SOFTWARE +* +* QLogic ISP1280 (Ultra2) /12160 (Ultra3) SCSI driver +* Copyright (C) 2000 Qlogic Corporation +* (www.qlogic.com) +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of the GNU General Public License as published by the +* Free Software Foundation; either version 2, or (at your option) any +* later version. +* +* This program is distributed in the hope that it will be useful, but +* WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +* General Public License for more details. +** +******************************************************************************/ -*************************************************************************************/ - - #ifndef _IO_HBA_QLA1280_H /* wrapper symbol for kernel use */ #define _IO_HBA_QLA1280_H /* subject to change without notice */ + +#ifndef LINUX_VERSION_CODE +#include +#endif /* LINUX_VERSION_CODE not defined */ + #if defined(__cplusplus) extern "C" { #endif -#include - +#ifndef HOSTS_C /* included in hosts.c */ /* * Enable define statement to ignore Data Underrun Errors, * remove define statement to enable detection. @@ -173,15 +39,18 @@ /* * Driver debug definitions. */ -/* #define QL_DEBUG_LEVEL_1 */ /* Output register accesses to COM2. */ -/* #define QL_DEBUG_LEVEL_2 */ /* Output error msgs to COM2. */ -/* #define QL_DEBUG_LEVEL_3 */ /* Output function trace msgs to COM2. */ -/* #define QL_DEBUG_LEVEL_4 */ /* Output NVRAM trace msgs to COM2. */ -/* #define QL_DEBUG_LEVEL_5 */ /* Output ring trace msgs to COM2. */ -/* #define QL_DEBUG_LEVEL_6 */ /* Output WATCHDOG timer trace to COM2. */ -/* #define QL_DEBUG_LEVEL_7 */ /* Output RISC load trace msgs to COM2. */ +/* #define QL_DEBUG_LEVEL_1 */ /* Output register accesses to COM1 */ +/* #define QL_DEBUG_LEVEL_2 */ /* Output error msgs to COM1 */ +/* #define QL_DEBUG_LEVEL_3 */ /* Output function trace msgs to COM1 */ +/* #define QL_DEBUG_LEVEL_4 */ /* Output NVRAM trace msgs to COM1 */ +/* #define QL_DEBUG_LEVEL_5 */ /* Output ring trace msgs to COM1 */ +/* #define QL_DEBUG_LEVEL_6 */ /* Output WATCHDOG timer trace to COM1 */ +/* #define QL_DEBUG_LEVEL_7 */ /* Output RISC load trace msgs to COM1 */ + +#define QL_DEBUG_CONSOLE /* Output to console instead of COM1 */ + /* comment this #define to get output of qla1280_print to COM1 */ + /* if COM1 is not connected to a host system, the driver hangs system! */ -#define QL_DEBUG_CONSOLE /* Output to console instead of COM2. */ #ifndef TRUE # define TRUE 1 @@ -206,7 +75,11 @@ * Locking */ #if LINUX_VERSION_CODE > KERNEL_VERSION(2,1,0) -# include +# if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18) +# include +# else +# include +# endif # include # define cpuid smp_processor_id() # if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95) @@ -314,12 +187,12 @@ #define WRT_REG_DWORD(addr, data) qla1280_putdword((uint32_t *)addr, data) #else /* QL_DEBUG_LEVEL_1 */ #ifdef MEMORY_MAPPED_IO - #define RD_REG_BYTE(addr) readb((unsigned long) (addr) - #define RD_REG_WORD(addr) readw((unsigned long) (addr) - #define RD_REG_DWORD(addr) readl((unsigned long) (addr) - #define WRT_REG_BYTE(addr, data) writeb((data), (unsigned long) (addr)) - #define WRT_REG_WORD(addr, data) writew((data), (unsigned long) (addr)) - #define WRT_REG_DWORD(addr, data) writel((data), (unsigned long) (addr)) + #define RD_REG_BYTE(addr) (*((volatile uint8_t *)addr)) + #define RD_REG_WORD(addr) (*((volatile uint16_t *)addr)) + #define RD_REG_DWORD(addr) (*((volatile uint32_t *)addr)) + #define WRT_REG_BYTE(addr, data) (*((volatile uint8_t *)addr) = data) + #define WRT_REG_WORD(addr, data) (*((volatile uint16_t *)addr) = data) + #define WRT_REG_DWORD(addr, data) (*((volatile uint32_t *)addr) = data) #else /* MEMORY_MAPPED_IO */ #define RD_REG_BYTE(addr) (inb((unsigned long)addr)) #define RD_REG_WORD(addr) (inw((unsigned long)addr)) @@ -372,7 +245,8 @@ /* - * SCSI Request Block structure + * SCSI Request Block structure (sp) that is placed + * on cmd->SCp location of every I/O */ typedef struct srb { @@ -381,10 +255,11 @@ struct srb *s_prev; /* (4) Previous block on LU queue */ uint8_t flags; /* (1) Status flags. */ uint8_t dir; /* direction of transfer */ - uint8_t unused[2]; - u_long r_start; /* jiffies at start of request */ - u_long u_start; /* jiffies when sent to F/W */ -}srb_t; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,18) + dma_addr_t saved_dma_handle; /* for unmap of single transfers */ +#endif + +} srb_t; /* * SRB flag definitions @@ -1562,22 +1437,35 @@ request_t req[REQUEST_ENTRY_CNT+1]; response_t res[RESPONSE_ENTRY_CNT+1]; - unsigned long request_dma; /* Physical address. */ +#if BITS_PER_LONG > 32 + dma_addr_t request_dma; /* Physical Address */ +#else + uint32_t request_dma; /* Physical address. */ +#endif request_t *request_ring; /* Base virtual address */ request_t *request_ring_ptr; /* Current address. */ uint16_t req_ring_index; /* Current index. */ uint16_t req_q_cnt; /* Number of available entries. */ - unsigned long response_dma; /* Physical address. */ +#if BITS_PER_LONG > 32 + dma_addr_t response_dma; /* Physical address. */ +#else + uint32_t response_dma; /* Physical address. */ +#endif response_t *response_ring; /* Base virtual address */ response_t *response_ring_ptr; /* Current address. */ uint16_t rsp_ring_index; /* Current index. */ #if QL1280_TARGET_MODE_SUPPORT /* Target buffer and sense data. */ +#if BITS_PER_LONG > 32 + dma_addr_t tbuf_dma; /* Physical address. */ + dma_addr_t tsense_dma; /* Physical address. */ +#else uint32_t tbuf_dma; /* Physical address. */ - tgt_t *tbuf; uint32_t tsense_dma; /* Physical address. */ +#endif + tgt_t *tbuf; uint8_t *tsense; #endif @@ -1614,8 +1502,13 @@ uint32_t dpc :1; /* 15 */ uint32_t dpc_sched :1; /* 16 */ uint32_t interrupts_on :1; /* 17 */ + uint32_t bios_enabled :1; /* 18 */ }flags; + /* needed holders for PCI ordered list of hosts */ + unsigned long io_port; + uint32_t irq; + }scsi_qla_host_t; /* @@ -1644,6 +1537,8 @@ #define QLA1280_RING_LOCK(ha) #define QLA1280_RING_UNLOCK(ha) +#endif /* HOSTS_C */ + #if defined(__cplusplus) } #endif @@ -1661,49 +1556,20 @@ int qla1280_biosparam(Disk *, kdev_t, int[]); void qla1280_intr_handler(int, void *, struct pt_regs *); void qla1280_setup(char *s, int *dummy); -#if defined(__386__) + # define QLA1280_BIOSPARAM qla1280_biosparam -#else -# define QLA1280_BIOSPARAM NULL -#endif /* * Scsi_Host_template (see hosts.h) * Device driver Interfaces to mid-level SCSI driver. */ -#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95) -/* This interface is now obsolete !!! */ -#define QLA1280_LINUX_TEMPLATE { \ - next: NULL, \ - usage_count: NULL, \ - proc_dir: NULL, \ - proc_info: NULL, \ - name: "Qlogic ISP 1280", \ - detect: qla1280_detect, \ - release: qla1280_release, \ - info: qla1280_info, \ - command: NULL, \ - queuecommand: qla1280_queuecommand, \ - abort: qla1280_abort, \ - reset: qla1280_reset, \ - slave_attach: NULL, \ - bios_param: QLA1280_BIOSPARAM, \ - can_queue: 255, /* MAX_OUTSTANDING_COMMANDS */ \ - this_id: -1, /* scsi id of host adapter */ \ - sg_tablesize: SG_ALL, \ - cmd_per_lun: 3, /* max commands per lun */ \ - present: 0, /* number of 1280s present */ \ - unchecked_isa_dma: 0, /* no memeory DMA restrictions */ \ - use_clustering: ENABLE_CLUSTERING \ -} -#else -#define QLA1280_LINUX_TEMPLATE { \ +#define QLA1280_LINUX_TEMPLATE { \ next: NULL, \ module: NULL, \ proc_dir: NULL, \ proc_info: qla1280_proc_info, \ - name: "Qlogic ISP 1280\1080", \ + name: "Qlogic ISP 1280\12160", \ detect: qla1280_detect, \ release: qla1280_release, \ info: qla1280_info, \ @@ -1723,13 +1589,14 @@ this_id: -1, /* scsi id of host adapter */\ sg_tablesize: SG_ALL, /* max scatter-gather cmds */\ cmd_per_lun: 3, /* cmds per lun (linked cmds) */\ - present: 0, /* number of 7xxx's present */\ + present: 0, /* number of 1280's present */\ unchecked_isa_dma: 0, /* no memory DMA restrictions */\ use_clustering: ENABLE_CLUSTERING, \ use_new_eh_code: 0, \ emulated: 0 \ } -#endif + #endif /* _IO_HBA_QLA1280_H */ + diff -urN linux-2.4.10/drivers/scsi/qla2x00.c linux-2.4.10-lia/drivers/scsi/qla2x00.c --- linux-2.4.10/drivers/scsi/qla2x00.c Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/scsi/qla2x00.c Mon Jul 23 14:12:22 2001 @@ -0,0 +1,12823 @@ +/******************************************************************************** +* QLOGIC LINUX SOFTWARE +* +* QLogic QLA2x00 device driver for Linux 2.2.x and 2.4.x +* Copyright (C) 2000 and 2001 Qlogic Corporation +* (www.qlogic.com) +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of the GNU General Public License as published by the +* Free Software Foundation; either version 2, or (at your option) any +* later version. +* +* This program is distributed in the hope that it will be useful, but +* WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +* General Public License for more details. +** +******************************************************************************/ +#define QLA2100_VERSION "4.31.7b" +/**************************************************************************** +Revision History: + Rev. 4.31.7b June 8, 2001 DG QLogic + - Fixed issue when loop id for target is changed to a different + loop id. + Rev. 4.31.6 June 1, 2001 DG QLogic + - Official 2200 firmware: v2.01.34 + - Official 2300 firmware: v3.00.24 + Rev. 4.31.5b May 30, 2001 DG QLogic + - Reset SRB_SENT flag in all isr routines. + - Fix displaying garbage when using /proc. + Rev. 4.31.3b May 15, 2001 DG QLogic + - Using test 2200 firmware: v204.01.33 + Rev. 4.31.2b May 15, 2001 DG QLogic + - Using test 2200 firmware: v203.01.33 + Rev. 4.31.1b May 15, 2001 DG QLogic + - Upgrade FC firmware to: 2200 v209.01.27 + - Changed logic to handle a topology of 4 after issuing the + "Get Host loop id". + Rev. 4.31b May 15, 2001 RL QLogic + - Added code to export PCI device info via a new ioctl function + in kernel 2.4.4. + - Redirect console messages to the OS messages file only. + - Additional fix in ioctl functions for node/port name endianess + problem. + Rev. 4.30b May 3, 2001 RL QLogic + - Moved the allocation of host database to outside of the adapter + structure allocation to avoid the allocation size limitation in the + scsi_register function. + Rev. 4.29b April 27, 2001 RL QLogic + - Fixed endianess of the node and port names read from the config + file for persistent binding entries. + Rev. 4.28b April 26, 2001 DG QLogic + - Fixed persistent binding of target devices. + Rev. 4.27 April 26, 2001 DG QLogic + - Fixed Mailbox timeout logic + - Fixed to compile on 2.4.x RedHat systems. + Rev. 4.25 March 15, 2001 DG QLogic + - released + Rev. 4.25 Beta March 9, 2001 DG QLogic + - incl new qlavendor.c file. + Rev. 4.24 Beta Test32 February 22, 2001 BN QLogic + - Added code for scanning of missing LUN to let the + SCSI layer skip it. + - Revised init_cb_t structure in qla2x00.h for the new + QLA2300 as well as QLA2200 devices. + - Changed criteria of 64/32 Bit mode of HBA + operation according to BITS_PER_LONG rather + than HBA's NVRAM setting of >4Gig memory bit; + so that the HBA auto-configures without the need + to setup each system individually. + - Merged changes for proper compile and operation in Alpha systems. + - Upgrade FC firmware to: QLA2300 v3.00.18 *new + and enabled FC Loopback test on QLA2300 HBAs. + - Add statistics counters and IOCTL support for + HBA Error Count, LIP Resets, and total ISR count. + - Changed qla2100_reinit on loop down after 4 minutes + specific to QLA2100 HBAs only. + - Added code and Makefile option to handle RISC code + download differently for ia-64 platforms than x86 or alpha. + Rev. 4.23 Beta January 12, 2001 BN QLogic + - Use cmd->sc_data_direction for setting of HBA data transfer + direction for 2.4.0 and higher kernels. + Note: Users must set the reply_len in sg_header. + For Writes and no data transfer; reply_len should + be the lenght of sg_header. + For Reads, reply_len should be the length of sg_header + plus the number of bytes to be read. + - Added check of SCSI_RESET_SUGGEST_BUS_RESET during + qla2100_reset() and perform BUS_RESET. + Also perform DEVICE_RESET on else of flag checking. + - Added new /proc/scsi/qla2x00/HbaApiNode for IOCTL interface + for 2.4.x kernels; so driver can be accessed with out need + to have at least one mapped scsi drive. + - Modified qla2100_mailbox_command's second parameter + to 32 bits for use by Loop-Back Diagnostic function + - Increase MAILBOX_REGISTER_COUNT to 32 + - Added Loop-Back Diagnostic function to qla2x00ioctl.c + for QLA2200 HBAs only. + - Order HBA detection as follows: + QLA2300, QLA2200, QLA2100. + - Changed queue_task() to queue_task_irq() in + qla2100_intr_handler() for proper usage. + - In qla2100_register_with_Linux() put check and getting + device iobase before registering of interrupt with Linux; + to help with driver loading/unloading when ramdisk is also loaded. + - Change IOCTL support to SDM_VERSION 5 in qla2x00ioctl.c + to be support SNIA HBA API 1.0 Library + - Upgrade FC firmware to: QLA2200 v2.01.27 *new + QLA2300 v3.00.17 *new + - Added copy of HBA Serial Number to /proc entry + - Added sigmask(SIGKILL) as second parameter to + siginitsetinv() function called during qla2100_do_dpc(); + so that the driver can be unloaded for 2.4.0 kernels. + Rev. 4.22 Beta November 22, 2000 BN QLogic + - Change IOCTL support to SDM_VERSION 4 in qla2x00_v4_ioctl.c + to be compatible with ln_rel-1.0Beta API library + Rev. 4.21 Beta November 15, 2000 BN QLogic + - Upgrade FC firmware to: 2100 v1.19.16 + 2200 v2.01.24 + 2300 v3.00.12 + - Merge of qla2x00 driver 2.19.16Beta changes. + - Updated qlavendor.c for vendor unique command + decoding. + Rev. 4.20 Beta October 17, 2000 BN QLogic + - QLA2300 Support added. + Rev. 4.14 Beta October 16, 2000 BN QLogic + - Added setting of higher address bits for + MBC_INITIALIZE_FIRMWARE operation. + - Release also contains newer qlavendor.c file + - Move to the new SCSI initialization scheme + and always declare the static driver_template + for kernels 2.4.0 and higher + Rev. 4.13 Beta September 21, 2000 BN QLogic + - Added "quiet" option to keep from printing LIP + occurred messages on systems that specify it. + - Added option to choose tp or ef, FC firmware + Rev. 4.12 Beta September 18, 2000 BN QLogic + - Added pci_set_master() to qla2100_pci_config + function to make sure all systems are supported + Rev. 4.11 Beta September 6, 2000 BN QLogic + - Enabled IOCTLs for external IOCTL and APIs + Rev. 4.10 Beta August 28, 2000 BN Qlogic + - Use new PCI DMA mapping APIs for 2.4.x kernel + - Added driver IOCTL support code; but disabled + it with #if 0 for next release + - Verified correct 64 bit addressing with NVRAM: + enable_64bit_addressing (>4GByte Addressing) + enabled in BIOS advanced settings option. + Rev. 4.0 July 24, 2000 BN Qlogic + - Added FC Tape Support by use of new FC Firmware + ql2100_fw.h must be v1.19.12 or greater + ql2200_fw.h must be v2.01.16 or greater + - Corrected HBA Node Name equal to zero + - Changed QLBoardTbl to QLBoardTbl_fc to avoid + double definition error with regards to qla1280 + on new 2.4.0 kernel build tools + Rev. 3.90 Beta July 21, 2000 BN Qlogic + - Added 64 bit OS and IA-64 hardware support + - Move to new major revision number + Rev. 2.22 July 14, 2000 BN Qlogic + - Updated 2100 FW to 1.19.10 + - Updated 2200 FW to 2.01.14 + - Move version to 2.22 for release to DVT + Rev. 2.19.8 July 11, 2000 DG Qlogic + - Fixed 2100 issue of login retry when no fabric is attached. + Rev. 2.19.7 July 6, 2000 DG + - Set queue depth per lun to 16 instead of throttle which is a + port max queue size and added an option "ql2xmaxqdepth=xx" + to allow user to change queue depth. This prevents us from + exceeding the adapter's throttle size which causes requests + to sit in the input queue for long periods of time. + Rev. 2.19.6 June 28, 2000 DG Qlogic + - GA release + - Fixed panic in putq_t routine when called from abort. + Rev. 2.19.5b7 June 27, 2000 DG + - Add logic to wait reset delay if no fabric devices are found. + Rev. 2.19.5b6 June 26, 2000 DG + - Fixed Fw ready issue. + - Clear sent flag in SRB, so we will abort commands in Lun + queue that were previously sent. + - Flush input queue when an isp_abort occurs. + Rev. 2.19.5b5 June 16, 2000 DG + - Fixed issue of not holding off request if multiple RSCN or + PORT updates occur while process the currect RSCN. + Rev. 2.19.5b4 June 16, 2000 DG + - Added lock for done_q to prevent losing requests in timer. + Rev. 2.19.5b3 June 16, 2000 DG + - Added routine to set the correct direction for vendor specific + commands. Set the new option "QLA_SCSI_VENDOR_DIR". + - Fixed issue of retrying continuously on a Missing SCSI device. + - Fixed multiple adapter issue. Only login into adapter node + once and never again. + - Change code not to use loop id 0 for Fabric nodes. + Rev. 2.19.5b2 June 15, 2000 DG + - Added code to reset port down count on good requests. + Rev. 2.19.5 June 8, 2000 DG + - Added code to display the connection type F, FL, or N. + - Reaarange code in DPC routine to put "retry login" + further down in the routine and skip is loop is down. + - Check the returned status after GAN (qla2100_sns_device) + and retry on ISP TX timeout (0x4005). + Rev. 2.19.4 June 6, 2000 DG + - Fixed for panic that occurs when system is shutdown. + Rev. 2.19.3 June 5, 2000 DG + - Fixed retry logic for user configured targets. + Rev. 2.19.2 May 31, 2000 DG + - Remove spinlock in qla2100_timer. + - Change the jiffies timer to loop timer in fw_ready. + Rev. 2.19.1 May 6, 2000 DG + - Change risc code 2200 from 2.1.12 to 2.1.13 to correct issue + of getting mailbox timeouts. + - Change mailbox timer to get correct timeout. + - Added qla2100_cmd_wait to wait for outstanding commands to + complete before querying the name server after a LIP. + Rev. 2.19 May 6, 2000 DG + - Fixed mailbox timeout recovery logic. + Rev. 2.18 May 1, 2000 DG + - Changes from Fabric testing + Rev. 2.18b4 Apr 21, 2000 DG + - Fixed login retry count to retry count. + - If the loop is down for more than 4 minutes then restart + queues and reset adpater if enabled. + - In qla2100_queuecommand we no longer return new requests + immediately back to kernel when loop is down. This causes + SYSTEM to HANG when a lot of requests are outstanding. We + now put them in the done queue and let the DPC routine + return them to kernel. + - Fixed panic cause by changing the timeout value of new request + when the loop is down. + - Cleanup qla2100_next. + Rev. 2.18b3 Apr 18, 2000 DG + - After the GAN, check returned status in resp buffer. + Rev. 2.18b2 Apr 12, 2000 DG + - Added handling of firmware bug when we use connection mode + 1 (P2P). The firmware tries to change to loop mode after + encountering some IO failures/resets. + - Added logic to reset all modules during a chip reset. + - After the GAN, if we lost devices or have a device that was + configured by the user then retry the login. This is a + work-a-round for Brocade switches. It sometimes does + not return all the devices in the port list. + Rev. 2.18b1 Apr 1, 2000 DG + - Added logic to ignore device types other than FL/F + from gan list. Mcdata switch returns a bogus port of + type 85 in the list. + - Added firmware 2.1.11 to fix issues with reusing loop ids. + Rev. 2.17 Mar 21, 2000 DG + - Fixed mailbox timeout timer. + - Added counters to record timeouts and aborts. + Rev. 2.16 Mar 8, 2000 DG + - Fixed Profiling code to reduced output of inactive devices. + - Fixed driver name in "/proc/scsi/qla2x00" instead of "qla". + - Fixed extended timeout value for loop down retries. + - Fixed code that search for target binding in command line to search + for all occurences instead of the first four. + - Disable the reinit of adapter when the LOOP is DOWN + for more than 4 minutes. It can be enabled with the command + line option "reinit_on_loopdown". + - Fixed issue of not setting HBA instance number before + calling HBA initialized. + Rev. 2.15 Feb 19, 2000 DG + - Fixed 2100 issue of driver not seeing storage when switch is connected + to loop. + Rev. 2.14 Feb 11, 2000 DG + - Added new logic to accept persistent binding information from the command line. + - Modified command parser to handle properties on the command line after + the regular options. + Rev. 2.13 Jan 27, 2000 TT + - Modify to use makefile parameter "IP=1" to enanle IP support. + - Fix SNS mailbox cmd parameter in qla2x00_register_ip_device. + - Reverse byte order on ha->port_id to match NT and fix compare bugs. + Rev. 2.12 Jan 26, 2000 TT+DG + - Updated Qlogic Linux sofware license. + - Added IP support for qla2xip driver. + - Fix host adapter structure initialization in qla2100_detect. + - Fix port name byte order in qla2100_update_fc_db. + - Fix the issue of not returning "NO_CONNECT" back to the user + when the loop is down after the loop down timer has expired. + - Added option QLA2100_EXT_TIMEOUT to extend timeout of each command. + default if OFF. + - Change device high water mark (hiwat) to execution throttle. + Rev. 2.11 Dec 8, 1999 DG + - Added Qlogic Linux sofware license. + Rev. 2.10 Oct 31, 1999 DG + - Fixed issue of not releasing requests if port is down (DPC issue). + - Ignore BIOS setting for MAX number of luns unless USE_BIOS_MAX_LUNS + is set. +*****************************************************************************/ + +/* +* Compile time Options: +* 0 - Disable and 1 - Enable +*/ +#define QL2100_TARGET_MODE_SUPPORT 0 /* Target mode support */ +#define MEMORY_MAPPED_IO 0 +#define DEBUG_QLA2100_INTR 0 +#define USE_NVRAM_DEFAULTS 0 +#define DEBUG_PRINT_NVRAM 0 +#define LOADING_RISC_ACTIVITY 0 +#define AUTO_ESCALATE_RESET 0 /* Automatically escalate resets */ +#define AUTO_ESCALATE_ABORT 0 /* Automatically escalate aborts */ +#define STOP_ON_ERROR 0 /* Stop on aborts and resets */ +#define STOP_ON_RESET 0 +#define STOP_ON_ABORT 0 +#define QLA2100_COMTRACE 0 /* One char tracing */ +#define WATCH_THREADS_SIZ 0 /* watch size of pending queue */ +#define USE_PORTNAME 1 /* option to use port names for targets */ +#define QLA2100_EXT_TIMEOUT 0 /* Extend timeout for commands up to 1 min*/ +#define LUN_MASKING 0 +#define USE_FLASH 0 +#define QLA2100_PROFILE 1 +#define QLA_SCSI_VENDOR_DIR 0 /* Decode vendor specific opcodes for direction */ +#define QLA2100_LIPTEST 0 +#define REQ_TRACE 1 + +#undef TRACECODE /* include tracing code in watchdog routines */ +#define CHECK_BINDING + +#define DEBUG_QLA2100 0 /* For Debug of qla2x00 */ +#define DEBUG_GET_FW_DUMP 0 /* also set DEBUG_QLA2100 and + use COM1 and capture it */ +#define USE_TP_FW 1 /* use tp or ef firmware */ + +/* The following WORD_FW_LOAD is defined in Makefile for ia-64 builds + and can also be decommented here for Word by Word confirmation of + RISC code download operation */ +/* #define WORD_FW_LOAD 0 */ + +/* +* String arrays +*/ +#define LINESIZE 256 +#define MAXARGS 26 + +/* +* Include files +*/ +#include +#ifdef MODULE +#include +#endif + +#ifndef LINUX_VERSION_CODE +#include +#endif /* LINUX_VERSION_CODE not defined */ + +static int num_hosts; /* ioctl related */ +static int apiHBAInstance = 0; /* ioctl related keeps track of API HBA Instance */ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +#ifndef KERNEL_VERSION +# define KERNEL_VERSION(x,y,z) (((x)<<16)+((y)<<8)+(z)) +#endif + +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,3,18) +#define APIDEV 1 +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95) +#include +# include +#else +/*#include */ + +#define __KERNEL_SYSCALLS__ + +#include +#include + +#include +#define SHUTDOWN_SIGS (sigmask(SIGKILL)|sigmask(SIGINT)|sigmask(SIGTERM)) +#endif +#include "sd.h" +#include "scsi.h" +#include "hosts.h" + +#ifdef FC_IP_SUPPORT +#include +#include "qlcommon.h" +#endif + +#include "qla2x00.h" +#define UNIQUE_FW_NAME /* unique F/W array names */ +#ifdef UNIQUE_FW_NAME +#include "ql2100_fw.h" /* ISP RISC code */ +#ifdef FC_IP_SUPPORT +#include "ql2200ip_fw.h" /* ISP RISC 2200 code */ +#include "ql2300ip_fw.h" /* ISP RISC 2300 code */ +#else +#include "ql2200_fw.h" /* ISP RISC 2200 code */ +#include "ql2300_fw.h" /* ISP RISC 2300 code */ +#endif +#else +#include "isp_fw.h" /* ISP RISC code */ +#include "isp1_fw.h" /* ISP RISC 2200 code */ +#endif +#include +#include + + +#define BZERO(ptr, amt) memset((void *)(ptr), 0, amt) +#define BCMP(s1, s2, amt) memcmp((void *)(s1), (void *)(s2), amt) +#define BCOPY(src, dst, amt) memcpy((void *)(dst), (void *)(src), amt) +#define KMALLOC(siz) kmalloc((siz), GFP_ATOMIC | GFP_DMA) +#define KMFREE(ip,siz) kfree((ip)) +#define SYS_DELAY(x) udelay(x);barrier() +#define QLA2100_DELAY(sec) mdelay(sec * HZ) + +/* 4.10 */ +#if BITS_PER_LONG > 32 +#define pci_dma_lo32(a) (a & 0xffffffff) +#define pci_dma_hi32(a) ((a >> 32) & 0xffffffff) +#else +#define pci_dma_lo32(a) (a & 0xffffffff) +#define pci_dma_hi32(a) 0 +#endif + +#define VIRT_TO_BUS(a) virt_to_bus((a)) + +#if BITS_PER_LONG <= 32 +#define VIRT_TO_BUS_LOW(a) (uint32_t)virt_to_bus(((void *)a)) +#define VIRT_TO_BUS_HIGH(a) (uint32_t)(0x0) +#else +#define VIRT_TO_BUS_LOW(a) (uint32_t)(0xffffffff & virt_to_bus((void *)(a))) +#define VIRT_TO_BUS_HIGH(a) (uint32_t)(0xffffffff & (virt_to_bus((void *)(a))>>32)) +#endif + +#define CACHE_FLUSH(a) (RD_REG_WORD(a)) +#define INVALID_HANDLE (MAX_OUTSTANDING_COMMANDS+1) + +#define STATIC + +#if BITS_PER_LONG <= 32 +#define LS_64BITS(x) (uint32_t)((unsigned long)x) +#define MS_64BITS(x) (uint32_t)((unsigned long) 0x0) +#else +#define LS_64BITS(x) (uint32_t)(0xffffffff & ((unsigned long)x)) +#define MS_64BITS(x) (uint32_t)(0xffffffff & (((unsigned long)x)>>32) ) +#endif + +#if BITS_PER_LONG <= 32 +#define MSB(x) (uint8_t)(((uint16_t)(x) >> 8) & 0xff) +#define LSB(x) (uint8_t)(x & 0xff) +#define MSW(x) (uint16_t)(((uint32_t)(x) >> 16) & 0xffff) +#define LSW(x) (uint16_t)(x & 0xffff) +#define QL21_64BITS_3RDWD(x) ((uint16_t) 0) +#define QL21_64BITS_4THWD(x) ((uint16_t) 0) +#else +#define MSB(x) (uint8_t)(((uint16_t)(x) >> 8) & 0xff) +#define LSB(x) (uint8_t)(x & 0xff) +#define MSW(x) (uint16_t)(((uint32_t)(x) >> 16) & 0xffff) +#define LSW(x) (uint16_t)(x & 0xffff) +#define QL21_64BITS_3RDWD(x) ((uint16_t) (x >> 32) & 0xffff) +#define QL21_64BITS_4THWD(x) ((uint16_t) (x >> 48) & 0xffff) +#endif + +#define OFFSET(w) (((u_long) &w) & 0xFFFF) /* 256 byte offsets */ +#define SCSI_BUS_32(scp) ((scp)->channel) +#define SCSI_TCN_32(scp) ((scp)->target) +#define SCSI_LUN_32(scp) ((scp)->lun) + +/* +* TIMER MACROS +*/ +#define QLA2100_TIMER_LOCK(ap) spin_lock_irqsave(&(ap)->retry_lock, cpu_flags); +#define QLA2100_TIMER_UNLOCK(ap) spin_unlock_irqrestore(&(ap)->retry_lock, cpu_flags); + + +#define WATCH_INTERVAL 1 /* number of seconds */ +#define START_TIMER(f, h, w) \ +{ \ +init_timer(&(h)->timer); \ +(h)->timer.expires = jiffies + w * HZ;\ +(h)->timer.data = (unsigned long) h; \ +(h)->timer.function = (void (*)(unsigned long))f; \ +(h)->flags.start_timer = FALSE; \ +add_timer(&(h)->timer); \ +(h)->timer_active = 1;\ +} + +#define RESTART_TIMER(f, h, w) \ +{ \ +(h)->timer.expires = jiffies + w * HZ;\ +(h)->flags.start_timer = FALSE; \ +add_timer(&(h)->timer); \ +} + +#define STOP_TIMER(f, h) \ +{ \ +del_timer(&(h)->timer); \ +(h)->timer_active = 0;\ +} + +#define NVRAM_DELAY() udelay(500) /* 2 microsecond delay */ + +typedef unsigned long paddr32_t; + +/* +* Qlogic Driver support Function Prototypes. +*/ +STATIC uint8_t qla2100_register_with_Linux(scsi_qla_host_t *ha, uint8_t maxchannels); +STATIC void qla2100_done(scsi_qla_host_t *, srb_t **, srb_t **), +qla2100_next(scsi_qla_host_t *, scsi_lu_t *), +qla2100_select_queue_depth(struct Scsi_Host *, Scsi_Device *); + +STATIC void qla2100_done_q_put(scsi_qla_host_t *, srb_t *, srb_t **, srb_t **), +qla2100_putq_b(scsi_lu_t *, srb_t *), +qla2100_putq_t(scsi_lu_t *, srb_t *), +qla2100_removeq(scsi_lu_t *, srb_t *), +qla2100_timer(scsi_qla_host_t *), +qla2100_timeout_insert(scsi_qla_host_t *, srb_t *), +qla2100_timeout_remove(scsi_qla_host_t *, srb_t *); + +STATIC uint8_t qla2100_mem_alloc(scsi_qla_host_t *); + +static void qla2100_dump_regs(struct Scsi_Host *host); +#if STOP_ON_ERROR +static void qla2100_panic(char *, struct Scsi_Host *host); +#endif +void qla2100_print_scsi_cmd(Scsi_Cmnd *cmd); +STATIC void qla2100_abort_queue_single(scsi_qla_host_t *,uint32_t,uint32_t,uint32_t,uint32_t); + +STATIC int qla2100_return_status(scsi_qla_host_t *ha, sts_entry_t *sts, Scsi_Cmnd *cp); +STATIC void qla2100_removeq(scsi_lu_t *q, srb_t *sp); +STATIC void qla2100_mem_free(scsi_qla_host_t *ha); +void qla2100_do_dpc(void *p); + +static inline void qla2100_callback(scsi_qla_host_t *ha, srb_t *sp, uint8_t dec), +qla2100_tgt_dealloc(scsi_qla_host_t *, tgt_t *), +qla2100_lun_dealloc(scsi_lu_t *); +static inline tgt_t *qla2100_tgt_alloc(scsi_qla_host_t *); +static inline scsi_lu_t *qla2100_lun_alloc(void); + +static inline void qla2100_enable_intrs(scsi_qla_host_t *); +static inline void qla2100_disable_intrs(scsi_qla_host_t *); +#if QLA2100_EXT_TIMEOUT +static void qla2100_extend_timeout(Scsi_Cmnd *cmd, int timeout); +#endif +static int qla2100_get_tokens(char *line, char **argv, int maxargs ); + +/* +* QLogic ISP2100 Hardware Support Function Prototypes. +*/ +STATIC uint8_t qla2100_initialize_adapter(scsi_qla_host_t *), +qla2100_isp_firmware(scsi_qla_host_t *), +qla2100_pci_config(scsi_qla_host_t *), +qla2100_set_cache_line(scsi_qla_host_t *), +qla2100_chip_diag(scsi_qla_host_t *), +qla2100_setup_chip(scsi_qla_host_t *), +qla2100_init_rings(scsi_qla_host_t *), +qla2100_fw_ready(scsi_qla_host_t *), +qla2100_nvram_config(scsi_qla_host_t *), +qla2200_nvram_config(scsi_qla_host_t *), +qla2100_mailbox_command(scsi_qla_host_t *, uint32_t, uint16_t *), +qla2100_update_device_data(scsi_qla_host_t *, device_data_t *, u_char), +qla2100_sns_device(scsi_qla_host_t *, u_char), +qla2100_update_fc_db(scsi_qla_host_t *, u_char), +qla2100_map_targets(scsi_qla_host_t *), +#if USE_FLASH +qla2100_get_database(scsi_qla_host_t *), +qla2100_save_database(scsi_qla_host_t *), +qla2100_program_flash_address(scsi_qla_host_t *, uint32_t, u_char), +qla2100_erase_flash_sector(scsi_qla_host_t *, uint32_t), +qla2100_poll_flash(scsi_qla_host_t *, uint32_t, u_char), +#endif +qla2100_loop_reset(scsi_qla_host_t *), +qla2100_device_reset(scsi_qla_host_t *, uint32_t, uint32_t), +qla2100_abort_device(scsi_qla_host_t *, uint32_t, uint32_t, uint32_t), +qla2100_abort_command(scsi_qla_host_t *, srb_t *), +qla2100_64bit_start_scsi(scsi_qla_host_t *, srb_t *), +qla2100_32bit_start_scsi(scsi_qla_host_t *, srb_t *), +qla2100_abort_isp(scsi_qla_host_t *), +qla2100_loop_resync(scsi_qla_host_t *); +STATIC uint8_t qla2100_cmd_wait(scsi_qla_host_t *ha); + +STATIC void qla2100_nv_write(scsi_qla_host_t *, uint16_t), +qla2100_nv_delay(void), +qla2100_poll(scsi_qla_host_t *), +qla2100_init_fc_db(scsi_qla_host_t *), +qla2100_init_tgt_map(scsi_qla_host_t *), +#if USE_FLASH +qla2100_flash_enable(scsi_qla_host_t *), +qla2100_flash_disable(scsi_qla_host_t *), +qla2100_write_flash_byte(scsi_qla_host_t *, uint32_t, u_char), +#endif +qla2100_reset_adapter(scsi_qla_host_t *), +qla2100_marker(scsi_qla_host_t *, uint32_t, uint32_t, uint32_t, +u_char), +qla2100_enable_lun(scsi_qla_host_t *), +qla2100_notify_ack(scsi_qla_host_t *, notify_entry_t *), +qla2100_64bit_continue_io(scsi_qla_host_t *, atio_entry_t *, + uint32_t, u_long *), +qla2100_32bit_continue_io(scsi_qla_host_t *, atio_entry_t *, + uint32_t, u_long *), +qla2100_isp_cmd(scsi_qla_host_t *), +qla2100_isr(scsi_qla_host_t *, srb_t **, srb_t **), +qla2100_rst_aen(scsi_qla_host_t *), +qla2100_atio_entry(scsi_qla_host_t *, atio_entry_t *), +qla2100_status_entry(scsi_qla_host_t *, sts_entry_t *, srb_t **, +srb_t **), +qla2100_error_entry(scsi_qla_host_t *, response_t *, srb_t **, +srb_t **), +qla2100_restart_queues(scsi_qla_host_t *, uint8_t), +qla2100_restart_watchdog_queue(scsi_qla_host_t *), +qla2100_abort_queues(scsi_qla_host_t *, uint8_t); + +STATIC uint16_t qla2100_get_nvram_word(scsi_qla_host_t *, uint32_t), +qla2100_nvram_request(scsi_qla_host_t *, uint32_t), +qla2100_read_flash_byte(scsi_qla_host_t *, uint32_t), +qla2100_debounce_register(volatile uint16_t *); + +STATIC request_t *qla2100_req_pkt(scsi_qla_host_t *); +STATIC request_t *qla2100_ms_req_pkt(scsi_qla_host_t *, srb_t *); +uint8_t qla2100_update_config(scsi_qla_host_t *ha); +STATIC uint8_t qla2100_configure_hba(scsi_qla_host_t *ha); +STATIC uint8_t qla2100_configure_loop(scsi_qla_host_t *ha, uint8_t ); +STATIC void qla2100_reset_chip(scsi_qla_host_t *ha); +#if QL2100_TARGET_MODE_SUPPORT +qla2100_enable_lun(scsi_qla_host_t *, uint8_t, uint32_t), +qla2100_notify_ack(scsi_qla_host_t *, notify_entry_t *), +qla2100_immed_notify(scsi_qla_host_t *, notify_entry_t *), +qla2100_accept_io(scsi_qla_host_t *, ctio_ret_entry_t *), +qla2100_64bit_continue_io(scsi_qla_host_t *, atio_entry_t *, uint32_t, + u_long *), +qla2100_32bit_continue_io(scsi_qla_host_t *, atio_entry_t *, uint32_t, + u_long *), +qla2100_atio_entry(scsi_qla_host_t *, atio_entry_t *), +qla2100_notify_entry(scsi_qla_host_t *, notify_entry_t *), + +#endif /* QLA2100_TARGET_MODE_SUPPORT */ +STATIC uint8_t qla2100_sns_get_name( scsi_qla_host_t *ha, device_data_t *device, uint8_t flag ); +STATIC void qla2100_display_fc_names(scsi_qla_host_t *ha); +void ql2100_dump_requests(scsi_qla_host_t *ha); +static void qla2100_get_properties(scsi_qla_host_t *ha, char *string); +STATIC uint8_t qla2100_find_propname(scsi_qla_host_t *ha, char *propname, char *propstr, char *db); +static int qla2100_get_prop_16chars(scsi_qla_host_t *ha, char *propname, char *propval, char *cmdline); +static char *qla2100_get_line(char *str, char *line); +void qla2100_check_fabric_devices(scsi_qla_host_t *ha); + +#ifdef FC_IP_SUPPORT + +/* Entry points for IP network driver */ +int qla2x00_ip_inquiry(uint16_t wAdapterNumber, BD_INQUIRY_DATA *pInquiryData); +int qla2x00_ip_enable(scsi_qla_host_t *ha, BD_ENABLE_DATA *pEnableData); +void qla2x00_ip_disable(scsi_qla_host_t *ha); +void qla2x00_add_buffers(scsi_qla_host_t *ha, uint16_t wBufferCount); +int qla2x00_send_packet(scsi_qla_host_t *ha, SEND_CB *pSendCB); + +static int qla2x00_ip_initialize(scsi_qla_host_t *ha); +static int qla2x00_add_new_ip_device(scsi_qla_host_t *ha, +uint16_t wLoopId, +uint8_t *pPortId, +uint8_t *pPortName, +int bForceAdd); +static int qla2x00_convert_to_arp(scsi_qla_host_t *ha, SEND_CB *pSendCB); +static void qla2x00_free_ip_block(scsi_qla_host_t *ha, +IP_DEVICE_BLOCK *pIpDevice); +static int qla2x00_get_ip_loopid(scsi_qla_host_t *ha, +uint8_t *pNodeName, +uint8_t *pLoopId); +static int qla2x00_send_farp_request(scsi_qla_host_t *ha, +uint8_t *pPortName); +static int qla2x00_register_ip_device(scsi_qla_host_t *ha); +static int qla2x00_reserve_ip_block(scsi_qla_host_t *ha, +PIP_DEVICE_BLOCK *pIpDevBlk); +static int qla2x00_update_ip_device_data(scsi_qla_host_t *ha, +device_data_t *pDeviceData); +static int qla2x00_reserve_loopid(scsi_qla_host_t *ha, uint16_t *pLoopId); +static void qla2x00_free_loopid(scsi_qla_host_t *ha, uint16_t wLoopId); +static int qla2x00_login_public_device(scsi_qla_host_t *ha, +uint16_t *pLoopId, +uint8_t *pPortID, +uint16_t wOptions); +static int qla2x00_logout_public_device(scsi_qla_host_t *ha, +uint16_t wLoopId, +uint16_t wOptions); +#else +/* v2.19.8 */ +static int qla2x00_login_public_device(scsi_qla_host_t *ha, +uint16_t *pLoopId, +uint8_t *pPortID, +uint16_t wOptions); +static int qla2x00_reserve_loopid(scsi_qla_host_t *ha, uint16_t *pLoopId); +static void qla2x00_free_loopid(scsi_qla_host_t *ha, uint16_t wLoopId); +#endif + +#if APIDEV +static int apidev_init(struct Scsi_Host*); +static int apidev_cleanup(void); +#endif + +void qla2100_print_q_info(scsi_lu_t *q); + +#if DEBUG_QLA2100 +#ifndef QL_DEBUG_ROUTINES +#define QL_DEBUG_ROUTINES +#endif +#endif +#ifdef QL_DEBUG_ROUTINES +/* +* Driver Debug Function Prototypes. +*/ +STATIC uint8_t qla2100_getbyte(uint8_t *); +STATIC uint16_t qla2100_getword(uint16_t *); +STATIC uint32_t qla2100_getdword(uint32_t *); +STATIC void qla2100_putbyte(uint8_t *, uint8_t), +qla2100_putword(uint16_t *, uint16_t), +qla2100_putdword(uint32_t *, uint32_t), +qla2100_print(int8_t *), +qla2100_output_number(u_long, uint8_t), +qla2100_putc(int8_t); +#endif +#if DEBUG_GET_FW_DUMP +STATIC void qla2300_dump_isp(scsi_qla_host_t *ha), +qla2100_dump_word(uint8_t *, uint32_t, uint32_t); +#endif + +/* Debug print buffer */ +char debug_buff[LINESIZE]; +#if DEBUG_QLA2100 +STATIC uint8_t ql2x_debug_print = 1; +#else +STATIC uint8_t ql2x_debug_print = 0; +#endif + +/* +* insmod needs to find the variable and make it point to something +*/ +static char *ql2xdevconf = NULL; +static int ql2xretrycount = 8; +#ifdef MODULE +static char *ql2xopts = NULL; +static int ql2xmaxqdepth = 0; +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,1,18) + +/* insmod qla2100 ql2xopts=verbose" */ +MODULE_PARM(ql2xopts, "s"); +MODULE_PARM(ql2xmaxqdepth, "i"); +#endif +/* +* Just in case someone uses commas to separate items on the insmod +* command line, we define a dummy buffer here to avoid having insmod +* write wild stuff into our code segment +*/ +static char dummy_buffer[60] = "Please don't add commas in your insmod command!!\n"; + +#endif + +/* +* Macros to change names of OS remapping routines. +*/ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,0) +#define ioremap vremap +#define iounmap vfree +#endif + + +/* +* This is the pointer to the /proc/scsi/qla2100 code. +* access the driver. +*/ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18) +#if CONFIG_PROC_FS +/* this definition is normally in proc_fs.h PROC_SCSI_QL2100 */ +#define PROC_SCSI_QL2100 PROC_SCSI_QLOGICISP + +struct proc_dir_entry proc_scsi_qla2100 = { +PROC_SCSI_QL2100, 7, "qla2x00", +S_IFDIR | S_IRUGO | S_IXUGO, 2, +0, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL, NULL +}; +#endif +#endif +static int qla2100_lip = 0; + +#include +#include + +/* multi-OS QLOGIC IOCTL definition file */ +#include "qla2x00exioct.h" + + +#if QLA_SCSI_VENDOR_DIR +/* Include routine to set direction for vendor specific commands */ +#include "qlavendor.c" +#endif +/*********************************************************************** +* We use the Scsi_Pointer structure that's included with each command +* SCSI_Cmnd as a scratchpad for our SRB. This allows us to accept +* an unlimited number of commands. +* +* SCp will always point to the SRB structure (defined in qla2100.h). +* It is defined as follows: +* - SCp.ptr -- > pointer back to the cmd +* - SCp.this_residual --> used as forward pointer to next srb +* - SCp.buffer --> used as backward pointer to next srb +* - SCp.buffers_residual --> used as flags field +* - SCp.have_data_in --> not used +* - SCp.sent_command --> not used +* - SCp.phase --> not used +***********************************************************************/ +#define CMD_SP(Cmnd) (&(Cmnd)->SCp) +#define CMD_XFRLEN(Cmnd) (Cmnd)->request_bufflen +#define CMD_CDBLEN(Cmnd) (Cmnd)->cmd_len +#define CMD_CDBP(Cmnd) (Cmnd)->cmnd +#define CMD_SNSP(Cmnd) (Cmnd)->sense_buffer +#define CMD_SNSLEN(Cmnd) (sizeof (Cmnd)->sense_buffer) +#define CMD_RESULT(Cmnd) ((Cmnd)->result) +#define CMD_HANDLE(Cmnd) ((Cmnd)->host_scribble) +#define CMD_TIMEOUT(Cmnd) ((Cmnd)->timeout_per_command) + +#define DID_RETRY DID_ERROR + + +/* +* Macros use for debugging the driver. +*/ +#ifdef QL_DEBUG_LEVEL_3 +#define ENTER(x) sprintf(debug_buff,"qla2100 : Entering %s()\n\r", x); \ +qla2100_print(debug_buff); +#define LEAVE(x) sprintf(debug_buff,"qla2100 : Leaving %s()\n\r", x); \ +qla2100_print(debug_buff); +#define ENTER_INTR(x) sprintf(debug_buff,"qla2100 : Entering %s()\n\r", x); \ +qla2100_print(debug_buff); +#define LEAVE_INTR(x) sprintf(debug_buff,"qla2100 : Leaving %s()\n\r", x); \ +qla2100_print(debug_buff); +#define DEBUG3(x) x +#else +#define ENTER(x) +#define LEAVE(x) +#define ENTER_INTR(x) +#define LEAVE_INTR(x) +#define DEBUG3(x) +#endif + +#if QLA2100_COMTRACE +#define COMTRACE(x) qla2100_putc(x); +#else +#define COMTRACE(x) +#endif + +#if DEBUG_QLA2100 +#define DEBUG(x) x +#define DEBUG4(x) +#else +#define DEBUG(x) +#define DEBUG4(x) +#endif + +#ifdef QL_DEBUG_LEVEL_2 +#define DEBUG2(x) x +#else +#define DEBUG2(x) +#endif +#ifdef QL_DEBUG_LEVEL_5 +#define DEBUG5(x) x +#else +#define DEBUG5(x) +#endif + +uint8_t copyright[48] = "Copyright 1999-2001, Qlogic Corporation"; + +/****************************************************************************/ +/* LINUX - Loadable Module Functions. */ +/****************************************************************************/ + +/*****************************************/ +/* ISP Boards supported by this driver */ +/*****************************************/ +#define QLA2100_VENDOR_ID 0x1077 +#define QLA2100_DEVICE_ID 0x2100 +#define QLA2200_DEVICE_ID 0x2200 +#define QLA2200A_DEVICE_ID 0x2200A +#define QLA2300_DEVICE_ID 0x2300 +#define QLA2200A_RISC_ROM_VER 4 + +#define NUM_OF_ISP_DEVICES 4 + +typedef struct _qlaboards +{ +unsigned char bdName[9]; /* Board ID String */ +unsigned long device_id; /* Device ID */ +int numPorts; /* number of loops on adapter */ +unsigned short *fwcode; /* pointer to FW array */ +unsigned long *fwlen; /* number of words in array */ +unsigned short *fwstart; /* start address for F/W */ +unsigned char *fwver; /* Ptr to F/W version array */ +} qla_boards_t; + + +#if USE_TP_FW +struct _qlaboards QLBoardTbl_fc[NUM_OF_ISP_DEVICES] = +{ +/* Name , Board PCI Device ID, Number of ports */ +{"QLA2300 ", QLA2300_DEVICE_ID, MAX_BUSES, +#ifdef FC_IP_SUPPORT +&fw2300ip_code01[0], (unsigned long *)&fw2300ip_length01, &fw2300ip_addr01, &fw2300ip_version_str[0] }, +#else +&fw2300tp_code01[0], (unsigned long *)&fw2300tp_length01, &fw2300tp_addr01, &fw2300tp_version_str[0] }, +#endif +{"QLA2200 ", QLA2200_DEVICE_ID, MAX_BUSES, +#ifdef FC_IP_SUPPORT +&fw2200ip_code01[0], (unsigned long *)&fw2200ip_length01, &fw2200ip_addr01, &fw2200ip_version_str[0] }, +#else +&fw2200tp_code01[0], (unsigned long *)&fw2200tp_length01, &fw2200tp_addr01, &fw2200tp_version_str[0] }, +#endif +{"QLA2100 ", QLA2100_DEVICE_ID, MAX_BUSES, +&fw2100tp_code01[0], (unsigned long *)&fw2100tp_length01,&fw2100tp_addr01, &fw2100tp_version_str[0] }, +{" ", 0, 0} +}; + +#else /* USE_TP_FW */ + +struct _qlaboards QLBoardTbl_fc[NUM_OF_ISP_DEVICES] = +{ +/* Name , Board PCI Device ID, Number of ports */ +{"QLA2300 ", QLA2300_DEVICE_ID, MAX_BUSES, +#ifdef FC_IP_SUPPORT +&fw2300ip_code01[0], (unsigned long *)&fw2300ip_length01, &fw2300ip_addr01, &fw2300ip_version_str[0] }, +#else +&fw2300ef_code01[0], (unsigned long *)&fw2300ef_length01, &fw2300ef_addr01, &fw2300ef_version_str[0] }, +#endif +{"QLA2200 ", QLA2200_DEVICE_ID, MAX_BUSES, +#ifdef FC_IP_SUPPORT +&fw2200ip_code01[0], (unsigned long *)&fw2200ip_length01, &fw2200ip_addr01, &fw2200ip_version_str[0] }, +#else +&fw2200ef_code01[0], (unsigned long *)&fw2200ef_length01, &fw2200ef_addr01, &fw2200ef_version_str[0] }, +#endif +{"QLA2100 ", QLA2100_DEVICE_ID, MAX_BUSES, +&fw2100ef_code01[0], (unsigned long *)&fw2100ef_length01,&fw2100ef_addr01, &fw2100ef_version_str[0] }, +{" ", 0, 0} +}; +#endif /* USE_TP_FW */ + +/* +* Stat info +*/ +static struct _qla2100stats { +unsigned long mboxtout; /* mailbox timeouts */ +unsigned long mboxerr; /* mailbox errors */ +unsigned long ispAbort; /* ISP aborts */ +unsigned long debugNo; +unsigned long loop_resync; +unsigned long outarray_full; +unsigned long retry_q_cnt; +unsigned long done_q_cnt; +scsi_qla_host_t *irqhba; +} qla2100_stats; + +/* +* Command line options +*/ +static unsigned long qla2100_verbose = 1L; +static unsigned long qla2100_quiet = 0L; +static unsigned long qla2100_reinit = 1L; +static unsigned long qla2100_req_dmp = 0L; +static scsi_qla_host_t *qla2100_hostlist = NULL; + +#ifdef QLA2100_PROFILE +static int qla2100_buffer_size = 0; +static char *qla2100_buffer = NULL; +#endif + +#include +#include +#include + +/************************************************************************* +* qla2100_set_info +* +* Description: +* Set parameters for the driver from the /proc filesystem. +* +* Returns: +*************************************************************************/ +int +qla2100_set_info(char *buffer, int length, struct Scsi_Host *HBAptr) { + return (-ENOSYS); /* Currently this is a no-op */ +} + + +#include "qla2x00ioctl.c" + + +/************************************************************************* +* qla2100_proc_info +* +* Description: +* Return information to handle /proc support for the driver. +* +* inout : decides on the direction of the dataflow and the meaning of the +* variables +* buffer: If inout==FALSE data is being written to it else read from it +* (ptrs to a page buffer) +* *start: If inout==FALSE start of the valid data in the buffer +* offset: If inout==FALSE offset from the beginning of the imaginary file +* from which we start writing into the buffer +* length: If inout==FALSE max number of bytes to be written into the buffer +* else number of bytes in the buffer +* Returns: +*************************************************************************/ +#define PROC_BUF (&qla2100_buffer[len]) +int +qla2100_proc_info( char *buffer, char **start, off_t offset, int length, +int hostno, int inout) { +#if QLA2100_PROFILE + struct Scsi_Host *host; + scsi_qla_host_t *ha; + int size = 0; + scsi_lu_t *up; + int len = 0; + qla_boards_t *bdp; + uint32_t t, l; + +#if REQ_TRACE + Scsi_Cmnd *cp; + srb_t *sp; + int i; +#endif + + DEBUG5(printk("Entering proc_info 0x%x,0x%lx,0x%x,0x%x\n",(int)buffer,offset,length,hostno);) + host = NULL; + + /* Find the host that was specified */ + for( ha=qla2100_hostlist; (ha != NULL) && ha->host->host_no != hostno; ha=ha->next ) + ; + + /* if host wasn't found then exit */ + if( !ha ) { + size = sprintf(buffer, "Can't find adapter for host number %d\n", hostno); + if( size > length ) { + return (size); + } else { + return (0); + } + } + + host = ha->host; + + if( inout == TRUE ) /* Has data been written to the file? */ + { + printk(KERN_INFO "qla2100_proc: has data been written to the file. \n"); + return (qla2100_set_info(buffer, length, host)); + } + + + /* + * if our old buffer is the right size use it otherwise + * allocate a new one. + */ + size = 4096; /* get a page */ + if( qla2100_buffer_size != size ) { + /* deallocate this buffer and get a new one */ + if( qla2100_buffer != NULL ) { + kfree(qla2100_buffer); + qla2100_buffer_size = 0; + } + qla2100_buffer = kmalloc(size, GFP_KERNEL); + } + if( qla2100_buffer == NULL ) { + size = sprintf(buffer, "qla2100 - kmalloc error at line %d\n", + __LINE__); + return size; + } + /* save the size of our buffer */ + qla2100_buffer_size = size; + + /* start building the print buffer */ + bdp = &QLBoardTbl_fc[ha->devnum]; + qla2100_lip = 1; + size = sprintf(PROC_BUF, + "QLogic PCI to Fibre Channel Host Adapter for ISP2100/ISP2200/ISP2300:\n" /* 72 */ + " Firmware version: %2d.%02d.%02d, Driver version %s\n", /* 66 */ + bdp->fwver[0], bdp->fwver[1], bdp->fwver[2], QLA2100_VERSION); + len += size; + +#if 0 + size = sprintf(PROC_BUF, + "FC HBA: %s; HBA Serial# %x%x%x\n", + bdp->bdName, + ha->serial0, + ha->serial1, + ha->serial2); + len += size; + + size = sprintf(PROC_BUF, + "[%c%c%c%c%c%c]; Part#%c%c%c%c%c%c%c%c; FRU#%c%c%c%c%c%c%c%c; EC#%c%c%c%c%c%c%c%c\n", + ha->oem_string[0], + ha->oem_string[1], + ha->oem_string[2], + ha->oem_string[3], + ha->oem_string[4], + ha->oem_string[5], + + ha->oem_part[0], + ha->oem_part[1], + ha->oem_part[2], + ha->oem_part[3], + ha->oem_part[4], + ha->oem_part[5], + ha->oem_part[6], + ha->oem_part[7], + + ha->oem_fru[0], + ha->oem_fru[1], + ha->oem_fru[2], + ha->oem_fru[3], + ha->oem_fru[4], + ha->oem_fru[5], + ha->oem_fru[6], + ha->oem_fru[7], + + ha->oem_ec[0], + ha->oem_ec[1], + ha->oem_ec[2], + ha->oem_ec[3], + ha->oem_ec[4], + ha->oem_ec[5], + ha->oem_ec[6], + ha->oem_ec[7]); + len += size; +#endif + + size = sprintf(PROC_BUF, "Request Queue = 0x%lx, Response Queue = 0x%lx\n", + (long unsigned int)ha->request_dma, + (long unsigned int)ha->response_dma); + len += size; + size = sprintf(PROC_BUF, "Request Queue count= %ld, Response Queue count= %ld\n", + (long)REQUEST_ENTRY_CNT, + (long)RESPONSE_ENTRY_CNT); + len += size; + size = sprintf(PROC_BUF, "Number of pending commands = 0x%lx\n", ha->actthreads); + len += size; + size = sprintf(PROC_BUF, "Number of queued commands = 0x%lx\n", ha->qthreads); + len += size; + size = sprintf(PROC_BUF, "Number of free request entries = %d\n",ha->req_q_cnt); + len += size; + size = sprintf(PROC_BUF, "Number of mailbox timeouts = %ld\n",qla2100_stats.mboxtout); + len += size; + size = sprintf(PROC_BUF, "Number of ISP aborts = %ld\n",qla2100_stats.ispAbort); + len += size; + size = sprintf(PROC_BUF, "Number of loop resyncs = %ld\n",qla2100_stats.ispAbort); + len += size; + size = sprintf(PROC_BUF, "Number of retries for empty slots = %ld\n",qla2100_stats.outarray_full); + len += size; + size = sprintf(PROC_BUF, "Number of reqs in retry_q = %ld\n",qla2100_stats.retry_q_cnt); + len += size; + size = sprintf(PROC_BUF, "Number of reqs in done_q = %ld\n",qla2100_stats.done_q_cnt); + len += size; + +#if REQ_TRACE + if ( qla2100_req_dmp ) { + size = sprintf(PROC_BUF,"Outstanding Commands on controller:\n"); + len += size; + for( i=0; i < MAX_OUTSTANDING_COMMANDS; i++ ) { + if( (sp = ha->outstanding_cmds[i]) == NULL ) + continue; + if( (cp = sp->cmd) == NULL ) + continue; + size = sprintf(PROC_BUF, + "(%d): Pid=%ld, sp flags=0x%x, cmd=0x%p, state=%x handle=%x\n\r", + i, (int)sp->cmd->pid, (long)sp->flags, + CMD_SP(sp->cmd),(int)sp->state,CMD_HANDLE(sp->cmd)); + + len += size; + if( len >= qla2100_buffer_size ) + goto profile_stop; + } + } +#endif + + /* 2.25 node/port display to proc */ + /* Display the node name for adapter */ + size = sprintf(PROC_BUF, "\nSCSI Device Information:\n"); + len += size; + size = sprintf(PROC_BUF, + "scsi-qla%d-adapter-node=%02x%02x%02x%02x%02x%02x%02x%02x;\n", + (int)ha->instance, + ha->init_cb->node_name[0], + ha->init_cb->node_name[1], + ha->init_cb->node_name[2], + ha->init_cb->node_name[3], + ha->init_cb->node_name[4], + ha->init_cb->node_name[5], + ha->init_cb->node_name[6], + ha->init_cb->node_name[7]); + len += size; + + /* display the port name for adapter */ + size = sprintf(PROC_BUF, + "scsi-qla%d-adapter-port=%02x%02x%02x%02x%02x%02x%02x%02x;\n", + (int)ha->instance, + ha->init_cb->port_name[0], + ha->init_cb->port_name[1], + ha->init_cb->port_name[2], + ha->init_cb->port_name[3], + ha->init_cb->port_name[4], + ha->init_cb->port_name[5], + ha->init_cb->port_name[6], + ha->init_cb->port_name[7]); + len += size; + + /* Print out device port names */ + for (i = 0; i < MAX_FIBRE_DEVICES; i++) { + if (ha->fc_db[i].loop_id == PORT_UNUSED) + continue; + +#if USE_PORTNAME + size = sprintf(PROC_BUF, + "scsi-qla%d-target-%d=%02x%02x%02x%02x%02x%02x%02x%02x;\n", + (int)ha->instance, i, + ha->fc_db[i].wwn[0], + ha->fc_db[i].wwn[1], + ha->fc_db[i].wwn[2], + ha->fc_db[i].wwn[3], + ha->fc_db[i].wwn[4], + ha->fc_db[i].wwn[5], + ha->fc_db[i].wwn[6], + ha->fc_db[i].wwn[7]); +#else + size = sprintf(PROC_BUF, + "scsi-qla%d-target-%d=%02x%02x%02x%02x%02x%02x%02x%02x;\n", + (int)ha->instance, i, + ha->fc_db[i].name[0], + ha->fc_db[i].name[1], + ha->fc_db[i].name[2], + ha->fc_db[i].name[3], + ha->fc_db[i].name[4], + ha->fc_db[i].name[5], + ha->fc_db[i].name[6], + ha->fc_db[i].name[7]); +#endif + len += size; + } /* 2.25 node/port display to proc */ + + size = sprintf(PROC_BUF, "\nSCSI LUN Information:\n"); + len += size; + size = sprintf(PROC_BUF, "(Id:Lun)\n"); + len += size; + /* scan for all equipment stats */ + for (t = 0; t < MAX_FIBRE_DEVICES; t++) { + /* valid target */ + if (ha->fc_db[t].loop_id == PORT_UNUSED) + continue; + /* scan all luns */ + for( l = 0; l < ha->max_luns; l++ ) { + up = (scsi_lu_t *) GET_LU_Q(ha, 0, t, l); + if( up == NULL ) + continue; + if( up->io_cnt == 0 || up->io_cnt < 5) + continue; + /* total reads since boot */ + /* total writes since boot */ + /* total requests since boot */ + size = sprintf(PROC_BUF, "(%2d:%2d): Total reqs %ld,",t,l,up->io_cnt); + len += size; + /* current number of pending requests */ + size = sprintf(PROC_BUF, " Pending reqs %d,",up->q_outcnt); + len += size; + + /* current number of pending requests */ + size = sprintf(PROC_BUF, " Queued reqs %d,",(int)up->q_incnt); + len += size; + size = sprintf(PROC_BUF, "\n"); + len += size; + if( len >= qla2100_buffer_size ) + goto profile_stop; + } + if( len >= qla2100_buffer_size ) + break; + } + + profile_stop: + if( len >= qla2100_buffer_size ) { + printk(KERN_WARNING "qla2100: Overflow buffer in qla2100_proc.c\n"); + } + + if( offset > len - 1 ) { + kfree(qla2100_buffer); + qla2100_buffer = NULL; + qla2100_buffer_size = length = 0; + *start = NULL; + } else { + if( len - offset < length ) { + length = len - offset; + } +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18) + *start = &qla2100_buffer[offset]; /* Start of wanted data */ +#else + *start = buffer; + memcpy(buffer, &qla2100_buffer[offset], length); +#endif + } + return (length); +#else + return (0); +#endif + +} + +/************************************************************************** +* qla2100_detect +* +* Description: +* This routine will probe for Qlogic FC SCSI host adapters. +* It returns the number of host adapters of a particular +* type that were found. It also initialize all data necessary for +* the driver. It is passed-in the host number, so that it +* knows where its first entry is in the scsi_hosts[] array. +* +* Input: +* template - pointer to SCSI template +* +* Returns: +* num - number of host adapters found. +**************************************************************************/ +int +qla2100_detect(Scsi_Host_Template *template) +{ + struct Scsi_Host *host; + scsi_qla_host_t *ha, *cur_ha; + struct _qlaboards *bdp; + int i, j; +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18) + unsigned short subsys; +#endif +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,1,95) + unsigned int piobase; + unsigned char pci_bus, pci_devfn, pci_irq; + config_reg_t *cfgp = 0; +#endif + device_reg_t *reg; + char *cp; +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,1,95) + struct pci_dev *pdev = NULL; +#else + int index; +#endif +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18) + struct semaphore sem = MUTEX_LOCKED; +#else + DECLARE_MUTEX_LOCKED(sem); +#endif + + unsigned long wait_switch = 0; + + ENTER("qla2100_detect"); + + if( sizeof(srb_t) > sizeof(Scsi_Pointer) ) + printk(KERN_WARNING "qla2x00: srb_t must be re-defined " + "- it's too big"); + +#ifdef CODECHECK + if( sizeof(srb_t) > sizeof(Scsi_Pointer) ) { + printk(KERN_WARNING "Redefine srb_t - its too big"); + return 0; + } +#endif + +#ifdef MODULE + DEBUG2(sprintf(debug_buff, + "DEBUG: qla2100_detect starts at address = 0x%8lx\n", + (uint32_t)qla2100_detect);) + DEBUG2(qla2100_print(debug_buff);) + /* + * If we are called as a module, the qla2100 pointer may not be null + * and it would point to our bootup string, just like on the lilo + * command line. IF not NULL, then process this config string with + * qla2100_setup + * + * Boot time Options + * To add options at boot time add a line to your lilo.conf file like: + * append="qla2100=verbose,tag_info:{{32,32,32,32},{32,32,32,32}}" + * which will result in the first four devices on the first two + * controllers being set to a tagged queue depth of 32. + */ + if( ql2xopts ) + qla2100_setup(ql2xopts, NULL); + if( dummy_buffer[0] != 'P' ) + printk(KERN_WARNING "qla2100: Please read the file " + "/usr/src/linux/drivers/scsi/README.qla2100\n" + "qla2100: to see the proper way to specify options to " + "the qla2100 module\n" + "qla2100: Specifically, don't use any commas when passing " + "arguments to\n" + "qla2100: insmod or else it might trash certain memory " + "areas.\n"); +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18) + if( (int) !pcibios_present() ) +#else + if (!pci_present()) +#endif + { + printk(KERN_WARNING "scsi: [ERROR] PCI not present\n"); + return 0; + } /* end of IF */ + + bdp = &QLBoardTbl_fc[0]; + qla2100_hostlist = NULL; +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18) + template->proc_dir = &proc_scsi_qla2100; +#else + template->proc_name = "qla2x00"; +#endif + + /* Try and find each different type of adapter we support */ + for( i=0; bdp->device_id != 0 && i < NUM_OF_ISP_DEVICES; i++, bdp++ ) { + +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,1,95) +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,3,18) + /* PCI_SUBSYSTEM_IDS supported */ + while ((pdev = pci_find_subsys(QLA2100_VENDOR_ID, + bdp->device_id, PCI_ANY_ID, PCI_ANY_ID, pdev) )) { + if (pci_enable_device(pdev)) continue; +#else + while ((pdev = pci_find_device(QLA2100_VENDOR_ID, + bdp->device_id, pdev ) )) { +#endif /* 2,3,18 */ + +#else /* less than 2,1,95 */ + while (!(pcibios_find_device(QLA2100_VENDOR_ID, + bdp->device_id, index++, &pci_bus, &pci_devfn)) ) { +#endif /* 2,1,95 */ + + /* found an adapter */ +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,3,18) + printk(KERN_INFO "qla2x00: detect() found an HBA\n"); + printk(KERN_INFO + "qla2x00: VID=%x DID=%x SSVID=%x SSDID=%x\n", + pdev->vendor, pdev->device, + pdev->subsystem_vendor, + pdev->subsystem_device); + + /* If it's an XXX SubSys Vendor ID adapter, skip it. */ + /* if (pdev->subsystem_vendor == PCI_VENDOR_ID_XXX) + { + printk(KERN_INFO "qla2x00: Skip XXX SubSys " + "Vendor ID Controller\n"); + continue; + } + */ +#else +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,1,95) + pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, + &subsys); + + /* Bypass all XXX SUBSYS VENDOR IDs */ + /* if (subsys == PCI_VENDOR_ID_XXX) + { + printk(KERN_INFO "qla2x00:Skip XXX SubSys " + "Vendor ID Controller\n"); + continue; + } + */ +#endif /* 2,1,95 */ +#endif /* 2,3,18 */ + host = scsi_register(template, sizeof(scsi_qla_host_t)); + ha = (scsi_qla_host_t *) host->hostdata; + + /* Clear our data area */ + for( j = 0, cp = (char *)ha; + j < sizeof(scsi_qla_host_t); j++, cp++ ) + *cp = 0; + + /* Sanitize the information from PCI BIOS. */ +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,1,95) + host->irq = pdev->irq; +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18) + host->io_port = (unsigned long) pdev->base_address[0]; +#else + host->io_port = pdev->resource[0].start; +#endif + ha->pci_bus = pdev->bus->number; + ha->pci_device_fn = pdev->devfn; + ha->pdev = pdev; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,4) + scsi_set_pci_device(host, pdev); +#endif +#else + pcibios_read_config_byte(pci_bus, pci_devfn, + OFFSET(cfgp->interrupt_line), &pci_irq); + pcibios_read_config_dword(pci_bus, pci_devfn, + OFFSET(cfgp->base_port), &piobase); + host->irq = pci_irq; + host->io_port = (unsigned int) piobase; + ha->pci_bus = pci_bus; + ha->pci_device_fn = pci_devfn; +#endif + ha->device_id = bdp->device_id; + host->io_port &= PCI_BASE_ADDRESS_IO_MASK; + ha->devnum = i; + if( qla2100_verbose ) { + printk(KERN_INFO "(scsi): Found a %s @ bus %d, " + "device 0x%x, irq %d, iobase 0x%lx\n", + bdp->bdName, ha->pci_bus, + (ha->pci_device_fn & 0xf8) >> 3, + host->irq, (unsigned long)host->io_port); + } + + ha->iobase = (device_reg_t *) host->io_port; + ha->iobase2300 = (device2300_reg_t *) host->io_port; + ha->host = host; + + /* 4.23 Initialize /proc/scsi/qla2x00 counters */ + ha->actthreads = 0; + ha->qthreads = 0; + ha->dump_done = 0; + ha->isp_aborts = 0; + ha->lip_count = 0; + + if( qla2100_mem_alloc(ha) ) { + printk(KERN_INFO "qla2100: Failed to allocate " + "memory for adapter\n"); + } + ha->prev_topology = 0; + ha->ports = bdp->numPorts; + ha->host_no = host->host_no; + + /* 4.10 */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18) + ha->ioctl_mem = (void *)KMALLOC(PAGE_SIZE); + ha->ioctl_mem_phys = VIRT_TO_BUS(ha->ioctl_mem); +#else + /* get consistent memory allocated for ioctl I/O + * operations + */ + ha->ioctl_mem = pci_alloc_consistent(ha->pdev, + PAGE_SIZE, &ha->ioctl_mem_phys); +#endif + + if (ha->ioctl_mem == NULL) { + printk(KERN_WARNING "qla2100: ERROR in ioctl " + "physical memory allocation\n"); + return(0); + } + + if( ha->device_id == QLA2100_DEVICE_ID ) + ha->max_targets = MAX_TARGETS_2100; + else + ha->max_targets = MAX_TARGETS_2200; + + /* load the F/W, read paramaters, and init the H/W */ + ha->instance = num_hosts; + + if( qla2100_initialize_adapter(ha) ) { + printk(KERN_WARNING + "qla2100_detect: [ERROR] Failed to " + "initialize adapter\n"); + + qla2100_mem_free(ha); + scsi_unregister(host); + continue; + } + + ha->next = NULL; + /* Mark preallocated Loop IDs in use. */ + ha->fabricid[SNS_FL_PORT].in_use = TRUE; + ha->fabricid[FABRIC_CONTROLLER].in_use = TRUE; + ha->fabricid[SIMPLE_NAME_SERVER].in_use = TRUE; + + /* Register our resources with Linux */ + if( qla2100_register_with_Linux(ha, bdp->numPorts-1) ) { + printk(KERN_WARNING + "qla2100: [ERROR] Failed to register our " + "resources\n"); + qla2100_mem_free(ha); + scsi_unregister(host); + continue; + } + + /* reg uses here in detect() are common: + * 2100/2200/2300 + */ + reg = ha->iobase; + + /* Disable ISP interrupts. */ + qla2100_disable_intrs(ha); + + /* + * Startup the kernel thread for this host adapter + */ + + ha->dpc_notify = &sem; + kernel_thread((int (*)(void *))qla2100_do_dpc, + (void *) ha, 0); + + /* + * Now wait for the kernel dpc thread to initialize + * and go to sleep. + */ + down(&sem); + ha->dpc_notify = NULL; + + /* + * These locks are used to prevent more than one + * CPU from modifying the queue at the same time. + * The higher level "io_request_lock" will reduce + * most contention for these locks. + */ + ha->retry_lock = SPIN_LOCK_UNLOCKED; + + /* Insure mailbox registers are free. */ + WRT_REG_WORD(®->semaphore, 0); + WRT_REG_WORD(®->host_cmd, HC_CLR_RISC_INT); + WRT_REG_WORD(®->host_cmd, HC_CLR_HOST_INT); + + /* Wait around max 5 secs for the devices to come + * on-line we don't want Linux scanning before we + * are ready. + */ + /* v2.19.5b6 */ + for (wait_switch = jiffies+(ha->loop_reset_delay * HZ); + wait_switch > jiffies && + !(ha->device_flags & DFLG_FABRIC_DEVICES) ; ) { + + qla2100_check_fabric_devices(ha); + } + /* just in case we turned it on */ + ha->dpc_flags &= ~COMMAND_WAIT_NEEDED; + + /* List the target we have found */ + qla2100_display_fc_names(ha); + + /* Enable chip interrupts. */ + qla2100_enable_intrs(ha); + + /* Insert new entry into the list of adapters */ + ha->next = NULL; + if( qla2100_hostlist == NULL ) { + qla2100_hostlist = ha; + } else { + cur_ha = qla2100_hostlist; + + while( cur_ha->next != NULL ) + cur_ha = cur_ha->next; + + cur_ha->next = ha; + } + num_hosts++; + } + } /* end of FOR */ + + LEAVE("qla2100_detect"); + return num_hosts; +} + +/************************************************************************** +* qla2100_register_with_Linux +* +* Description: +* Free the passed in Scsi_Host memory structures prior to unloading the +* module. +* +* Input: +* ha - pointer to host adapter structure +* maxchannels - MAX number of channels. +* +* Returns: +* 0 - Sucessfully reserved resources. +* 1 - Failed to reserved a resource. +**************************************************************************/ +STATIC uint8_t qla2100_register_with_Linux(scsi_qla_host_t *ha, uint8_t maxchannels) { + + struct Scsi_Host *host = ha->host; + char drvname[9]; + + host->can_queue = 0xfffff; /* unlimited */ + host->cmd_per_lun = 1; + host->select_queue_depths = qla2100_select_queue_depth; + host->n_io_port = 0xFF; +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18) + host->base = (unsigned char *) ha->mmpbase; +#else + host->base = (u_long) ha->mmpbase; +#endif + host->max_channel = maxchannels; + /* fix: 07/31 host->max_lun = MAX_LUNS-1; */ + host->max_lun = ha->max_luns; + host->unique_id = ha->instance; + host->max_id = ha->max_targets; + + /* set our host ID (need to do something about our two IDs) */ + host->this_id = 255; + + /* Register the I/O space with Linux */ + if( check_region(host->io_port, 0xff) ) { + printk(KERN_WARNING "qla2100 : [ERROR] Failed to reserved i/o region " + "0x%04lx-0x%04lx already in use\n", + host->io_port, host->io_port + 0xff); + /* 4.31.5 - deleted free_irq(host->irq, NULL); */ + return 1; + } + + /* ER# 4368 */ + sprintf(drvname,"qla2x00#%02d",host->unique_id); + + request_region(host->io_port, 0xff, drvname); + + + /* Register the IRQ with Linux (sharable) */ + if( request_irq(host->irq, qla2100_intr_handler, SA_INTERRUPT| SA_SHIRQ, "qla2x00", ha) ) { + printk(KERN_WARNING "qla2100 : [ERROR] Failed to reserved interrupt %d " + "already in use\n", host->irq); + return 1; + } + + /* Initialized the timer */ + START_TIMER(qla2100_timer,ha,WATCH_INTERVAL); + + return 0; +} + + +/************************************************************************** +* qla2100_release +* +* Description: +* Free the passed in Scsi_Host memory structures prior to unloading the +* module. +* +* Input: +* ha - pointer to host adapter structure +* +* Returns: +* 0 - Always returns good status +**************************************************************************/ +int +qla2100_release(struct Scsi_Host *host) { + scsi_qla_host_t *ha = (scsi_qla_host_t *) host->hostdata; + + ENTER("qla2100_release"); + /* if adpater is running and online */ + if( !ha->flags.online ) + return(0); + + /* turn-off interrupts on the card */ + qla2100_disable_intrs(ha); + + /* Detach interrupts */ + if( host->irq ) + free_irq(host->irq, ha); + + /* release io space registers */ + if( host->io_port ) + release_region(host->io_port, 0xff); + + /* Disable timer */ + if( ha->timer_active ) + STOP_TIMER(qla2100_timer,ha) + + /* Kill the kernel thread for this host */ + if( ha->dpc_handler != NULL ) { +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18) + struct semaphore sem = MUTEX_LOCKED; +#else + DECLARE_MUTEX_LOCKED(sem); +#endif + + ha->dpc_notify = &sem; + send_sig(SIGKILL, ha->dpc_handler, 1); + down(&sem); + ha->dpc_notify = NULL; + } +#if USE_FLASH + /* Move driver database to flash, if enabled. */ + if( ha->flags.enable_flash_db_update && ha->flags.updated_fc_db ) { + ha->flags.updated_fc_db = FALSE; + qla2100_save_database(ha); + } +#endif +#if MEMORY_MAPPED_IO + if( ha->mmpbase ) { + iounmap((void *) (((unsigned long) ha->mmpbase) & PAGE_MASK)); + } +#endif /* MEMORY_MAPPED_IO */ + +#if APIDEV + apidev_cleanup(); +#endif + + qla2100_mem_free(ha); + ha->flags.online = FALSE; + + LEAVE("qla2100_release"); + return(0); +} + +/************************************************************************** +* qla2100_info +* +* Description: +* +* Input: +* host - pointer to Scsi host adapter structure +* +* Returns: +* Return a text string describing the driver. +**************************************************************************/ +const char * +qla2100_info(struct Scsi_Host *host) { + static char qla2100_buffer[255]; + char *bp; + scsi_qla_host_t *ha; + qla_boards_t *bdp; + +#if APIDEV +/* We must create the api node here instead of qla2100_detect since we want + the api node to be subdirectory of /proc/scsi/qla2x00 which will not + have been created when qla2100_detect exits, but which will have been + created by this point. */ + + apidev_init(host); +#endif + bp = &qla2100_buffer[0]; + ha = (scsi_qla_host_t *)host->hostdata; + bdp = &QLBoardTbl_fc[ha->devnum]; + memset(bp, 0, sizeof(qla2100_buffer)); + sprintf(bp, + "QLogic %sPCI to Fibre Channel Host Adapter: bus %d device %d irq %d\n" + " Firmware version: %2d.%02d.%02d, Driver version %s", + (char *)&bdp->bdName[0], ha->pci_bus, (ha->pci_device_fn & 0xf8) >> 3, host->irq, + bdp->fwver[0], bdp->fwver[1], bdp->fwver[2], QLA2100_VERSION); + return(bp); +} + +/************************************************************************** +* qla1200_queuecommand +* +* Description: +* Queue a command to the controller. +* +* Input: +* cmd - pointer to Scsi cmd structure +* fn - pointer to Scsi done function +* +* Returns: +* 0 - Always +* +* Note: +* The mid-level driver tries to ensures that queuecommand never gets invoked +* concurrently with itself or the interrupt handler (although the +* interrupt handler may call this routine as part of request-completion +* handling). +**************************************************************************/ +int +qla2100_queuecommand(Scsi_Cmnd *cmd, void (*fn)(Scsi_Cmnd *)) { + scsi_qla_host_t *ha; + srb_t *sp; +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95) + unsigned long cpu_flags = 0; +#endif + struct Scsi_Host *host; + uint32_t b, t, l; + scsi_lu_t *q; + u_long handle; + + ENTER("qla2100_queuecommand"); + COMTRACE('C') + + host = cmd->host; + ha = (scsi_qla_host_t *) host->hostdata; + /* Get our SCSI request pointer + * SCp always point to it - see definition in qla2100.h. + */ + sp = (srb_t *) CMD_SP(cmd); + sp->cmd = cmd; + cmd->scsi_done = fn; + + /* If we not trying to do a recovery procedure of some sort + * then this is probably a new command. + */ + if( cmd->flags == 0 && + cmd->retries == 0 ) + sp->flags = 0; + + /* Generate LU queue on bus, target, LUN */ + b = SCSI_BUS_32(cmd); + t = SCSI_TCN_32(cmd); + l = SCSI_LUN_32(cmd); + + DEBUG5(qla2100_print_scsi_cmd(cmd);) + DEBUG5(sprintf(debug_buff,"qla2100_queuecmd: pid=%d, opcode=%d, timeout=%d\n",cmd->pid,cmd->cmnd[0],CMD_TIMEOUT(cmd));) + DEBUG5(qla2100_print(debug_buff);) + +#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3) + /*DEBUG(sprintf(debug_buff,"\n\nQC: t=%x CDB=%x Size=%x\n\r", + t,cmd->cmnd[0],CMD_XFRLEN(cmd));) + DEBUG(qla2100_print(debug_buff)); */ +#endif + /* + * We found all the devices at LIP time, and created a device + * table for them, so we only need to check the table to see + * if the device is present. if PORT_AVAILABLE or PORT_UNUSED + * then no target exists. + * + * We return DID_NO_CONNECT if the loop is down after loop down + * timer has expired. + */ + if( TGT_Q(ha,b,t) == NULL || + (TGT_Q(ha,b,t) && TGT_Q(ha,b,t)->loop_id > LAST_SNS_LOOP_ID) ) { + /* DEBUG2(printk("scsi(%2d:%2d:%2d:%2d): port unavailable\n", + (int)ha->host_no,b,t,l);) */ + CMD_RESULT(sp->cmd) = DID_NO_CONNECT << 16; + qla2100_callback(ha,sp,FALSE); + LEAVE("qla2100_queuecommand"); + return(0); + } + /* v218b4 */ + if (ha->loop_down_timer == 0 && + ha->loop_state == LOOP_DOWN ){ /* 01/21/00 DG */ + DEBUG2(printk("scsi(%2d:%2d:%2d:%2d): Loop down - returning pid=%ld \n",(int)ha->host_no,b,t,l,cmd->pid);) + CMD_RESULT(sp->cmd) = DID_NO_CONNECT << 16; + ha->flags.done_requests_needed = TRUE; + qla2100_done_q_put(ha, sp, (srb_t **)&ha->done_q_first, (srb_t **)&ha->done_q_last); + LEAVE("qla2100_queuecommand"); + return(0); + } + + /* + * Allocate a LUN/DEVICE queue from this request if we haven't + * already did it on a previous command. + */ + if( (q = GET_LU_Q(ha, b, t,l)) == NULL ) { + DRIVER_LOCK + if( (q = qla2100_lun_alloc()) == NULL ) { + CMD_RESULT(sp->cmd) = DID_RETRY << 16; + qla2100_callback(ha,sp,FALSE); + return(0); + } + LU_Q(ha, b, t, l) = q; + DEBUG(sprintf(debug_buff,"Allocate new device queue 0x%x\n",q)); + DEBUG(qla2100_print(debug_buff)); + DRIVER_UNLOCK + } + + /* Set an invalid handle until we issue the command to ISP */ + /* then we will set the real handle value. */ + handle = INVALID_HANDLE; + CMD_HANDLE(cmd) = (unsigned char *)handle; + +#if QLA2100_EXT_TIMEOUT + /* Extend timeout for this request */ + qla2100_extend_timeout(cmd,60*HZ); +#endif + + /* + * SCSI Kluge + * ======== + * Whenever, we need to wait for an event such as loop down + * (i.e. loop_down_timer ) or port down (i.e. LUN request qeueue is + * suspended) then we will recycle new commands back to the SCSI layer. + * We do this because this is normally a temporary condition and we don't + * want the mid-level scsi.c driver to get upset and start aborting + * commands. + + * The timeout value is extracted from the command minus 1-second + * and put on a retry queue (watchdog). Once the command timeout it + * is returned to the mid-level with a BUSY status, so the mid-level + * will retry it. This process continues until the LOOP DOWN time + * expires or the condition goes away. + */ + if( ha->loop_down_timer || + ha->loop_state == LOOP_DOWN || + (PORT_DOWN(ha,t) > 0) || + ha->loop_state != LOOP_READY || + (q->q_flag & QLA2100_QSUSP) ) { + /* Insert command into watchdog queue */ + qla2100_timeout_insert(ha, sp); + LEAVE("qla2100_queuecommand"); + return (0); + } + /* Set retry count if this is a new command */ + if( sp->flags == 0 && + !(q->q_flag & QLA2100_QSUSP) ) { + sp->retry_count = ha->retry_count; + if( TGT_Q(ha, b, t)->down_timer == 0 ) + sp->port_down_retry_count = ha->port_down_retry_count; + } + + /* No timeout necessary, because the upper layer is doing it for us */ + sp->wdg_time = 0; + + /* add the command to our queue */ + ha->qthreads++; + qla2100_putq_t(q,sp); + + DEBUG5(sprintf(debug_buff,"\nQC: queue pid=%d, hndl=0x%x\n\r", + cmd->pid,handle)); + DEBUG5(qla2100_print(debug_buff)); + + /* send command to adapter */ + qla2100_restart_queues(ha,FALSE); + + COMTRACE('c') + LEAVE("qla2100_queuecommand"); + return (0); +} + +/************************************************************************** +* qla1200_abort +* +* Description: +* Abort the specified SCSI command. +* +* Input: +* cmd - pointer to Scsi cmd structure +* +* Returns: +**************************************************************************/ +int +qla2100_abort(Scsi_Cmnd *cmd) { + scsi_qla_host_t *ha; + srb_t *sp; + srb_t *rp, *rp_next; +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95) + unsigned long cpu_flags = 0; +#endif + struct Scsi_Host *host; + uint32_t b, t, l; + scsi_lu_t *q; + int return_status = SCSI_ABORT_SUCCESS; + int found = 0; + int i; + u_long handle; + + uint16_t data; + + ENTER("qla2100_abort"); + COMTRACE('A') + + ha = (scsi_qla_host_t *) cmd->host->hostdata; + host = cmd->host; + +#if DEBUG_GET_FW_DUMP + if (ha->device_id == QLA2300_DEVICE_ID) + { + if (ha->dump_done != 1) { + DEBUG(sprintf(debug_buff,"\nqla2100_abort handle=%x: >>>>>>> DUMP 2300 FW <<<<<<<\n",CMD_HANDLE(cmd));) + DEBUG(qla2100_print(debug_buff);) + qla2300_dump_isp(ha); + ha->dump_done = 1; + } + } +#endif + + DRIVER_LOCK + /* Get the SCSI request ptr */ + sp = (srb_t *) CMD_SP(cmd); + + /* + * if the handle is NULL then we already completed the command. + * We always give the handle a value of "INVALID_HANDLE" when + * we received it. + */ + if( (u_long) CMD_HANDLE(cmd) == 0L ) { + + DRIVER_UNLOCK +#if STOP_ON_ABORT + qla2100_panic("qla2100_abort",ha->host); +#endif + return(SCSI_ABORT_NOT_RUNNING); /* no action - we don't have command */ + } + + /* Check for a pending interrupt. */ + if (ha->device_id == QLA2300_DEVICE_ID) + data = qla2100_debounce_register((uint16_t *)&ha->iobase2300->host_status) & RISC_2300_INT; + else data = qla2100_debounce_register(&ha->iobase->istatus) & + RISC_INT; + + /* Check for pending interrupts. */ + if( !(ha->flags.in_isr) && (data)) { + /* Add any completed commands in the done queue */ + DEBUG(qla2100_print("qla2100_abort: Calling isr\n");) + qla2100_isr(ha, (srb_t **)&ha->done_q_first, (srb_t **)&ha->done_q_last); + } + + /* + * if no LUN queue then something is very wrong!!! + */ + handle = (u_long) CMD_HANDLE(cmd); + + /* Generate LU queue on bus, target, LUN */ + b = SCSI_BUS_32(cmd); + t = SCSI_TCN_32(cmd); + l = SCSI_LUN_32(cmd); + if( (q = GET_LU_Q(ha, b, t, l)) == NULL ) { + COMTRACE('a') + + DRIVER_UNLOCK + printk(KERN_WARNING "qla2100 (%d:%d:%d): No LUN queue for the specified device\n",(int)b,(int)t,(int)l); + return(SCSI_ABORT_NOT_RUNNING); /* no action - we don't have command */ + } + +#if AUTO_ESCALATE_ABORT + if( (sp->flags & SRB_ABORTED) ) { + DRIVER_UNLOCK + DEBUG(qla2100_print("qla2100_abort: Abort escalayted - returning SCSI_ABORT_SNOOZE.\n\r")); + return(SCSI_ABORT_SNOOZE); + } +#endif + /* + * if the command ahs a abort pending then tell the upper layer + */ + if( (sp->flags & SRB_ABORT_PENDING) ) { + COMTRACE('a') + DRIVER_UNLOCK + if( qla2100_verbose ) + printk(KERN_INFO "scsi(): Command has a pending abort " + "message - ABORT_PENDING.\n"); + DEBUG(qla2100_print("qla2100: Command has a pending abort message - ABORT_PENDING.\n\r")); + return(SCSI_ABORT_PENDING); + } + + DEBUG(sprintf(debug_buff,"ABORTing command= 0x%x, sp=%x sp->state=%x\n", + (int)cmd,sp,sp->state);) + DEBUG(qla2100_print(debug_buff);) + DEBUG(qla2100_print_scsi_cmd(cmd)); + + for( rp = ha->retry_q_first; (rp); rp = rp_next ) { + rp_next = rp->s_next; + if( sp != rp ) + continue; + qla2100_timeout_remove(ha, sp); + CMD_RESULT(sp->cmd) = DID_BUS_BUSY << 16; + CMD_HANDLE(sp->cmd) = (unsigned char *) NULL; + qla2100_done_q_put(ha, sp, (srb_t **)&ha->done_q_first, (srb_t **)&ha->done_q_last); + found++; + } + + /* + * Our SP pointer points at the command we want to remove from the + * LUN queue providing we haven't already sent it to the adapter. + */ + if( found ) + return_status = SCSI_ABORT_SUCCESS; + else if( !(sp->flags&SRB_SENT) ) { + found++; + DEBUG(sprintf(debug_buff,"qla2100: Cmd in LUN queue aborted pid %d.\n\r",sp->cmd->pid);) + DEBUG(qla2100_print(debug_buff);) + /* Remove srb from SCSI LU queue. */ + qla2100_removeq(q, sp); + sp->flags |= SRB_ABORTED; + CMD_RESULT(cmd) = DID_ABORT << 16; + qla2100_done_q_put(ha, sp, &ha->done_q_first, &ha->done_q_last); + return_status = SCSI_ABORT_SUCCESS; + found++; + } else { /* find the command in our active list */ + for( i = 1; i < MAX_OUTSTANDING_COMMANDS; i++ ) { + if( sp == ha->outstanding_cmds[i] ) { + found++; + DEBUG(sprintf(debug_buff, + "qla2100: RISC aborting pid %d sp->state=%x\n\r", + sp->cmd->pid,sp->state);) + DEBUG(qla2100_print(debug_buff);) + /* DEBUG(qla2100_print_scsi_cmd(cmd)); */ + DEBUG(qla2100_print_q_info(q);) + /* v2.19.8 Ignore abort request if port is down */ + if ( qla2100_abort_command(ha,sp) ) { + DEBUG(printk("qla2100: Failed to abort pid %ld.\n",sp->cmd->pid);) + return_status = SCSI_ABORT_NOT_RUNNING; /* no action */ + } + else + return_status = SCSI_ABORT_PENDING; + break; + } + } + } + +#if STOP_ON_ABORT + qla2100_panic("qla2100_abort",ha->host); +#endif + if( found == 0 ) + return_status = SCSI_ABORT_NOT_RUNNING; /* no action */ + + DEBUG(sprintf(debug_buff, "qla2100_abort: Aborted status returned = 0x%x.\n\r",return_status)); + DEBUG(qla2100_print(debug_buff)); + /* + * Complete any commands + */ + if( ha->done_q_first ) + qla2100_done(ha, (srb_t **)&ha->done_q_first, (srb_t **)&ha->done_q_last); + + if( found ) { + qla2100_restart_queues(ha,TRUE); + } + DRIVER_UNLOCK + + LEAVE("qla2100_abort"); + COMTRACE('a') + return(return_status); +} + +/************************************************************************** +* qla1200_reset +* +* Description: +* The reset function will reset the SCSI bus and abort any executing +* commands. +* +* Input: +* cmd = Linux SCSI command packet of the command that cause the +* bus reset. +* flags = SCSI bus reset option flags (see scsi.h) +* +* Returns: +* DID_RESET in cmd.host_byte of aborted command(s) +* +* Note: +* Resetting the bus always succeeds - is has to, otherwise the +* kernel will panic! Try a surgical technique - sending a BUS +* DEVICE RESET message - on the offending target before pulling +* the SCSI bus reset line. +**************************************************************************/ +int +qla2100_reset(Scsi_Cmnd *cmd, unsigned int flags) { + scsi_qla_host_t *ha; +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95) + unsigned long cpu_flags = 0; +#endif + uint32_t b, t, l; + srb_t *sp; + typedef enum { + ABORT_DEVICE = 1, + DEVICE_RESET = 2, + BUS_RESET = 3, + ADAPTER_RESET= 4, + RESET_DELAYED= 5, + FAIL = 6 + } action_t; + action_t action = ADAPTER_RESET; + uint16_t data; + scsi_lu_t *q; + int result; + + + ENTER("qla2100_reset"); + COMTRACE('R') + if( cmd == NULL ) { + printk(KERN_WARNING "(scsi?:?:?:?) Reset called with NULL Scsi_Cmnd " + "pointer, failing.\n"); + return(SCSI_RESET_SNOOZE); + } + ha = (scsi_qla_host_t *) cmd->host->hostdata; + sp = (srb_t *) CMD_SP(cmd); + +#if STOP_ON_RESET + sprintf(debug_buff,"ABORTing command= 0x%x\n",(int)cmd); + qla2100_print(debug_buff); + qla2100_print_scsi_cmd(cmd); + qla2100_panic("qla2100_reset",ha->host); +#endif + + + DRIVER_LOCK + if (ha->device_id == QLA2300_DEVICE_ID) + data = qla2100_debounce_register((uint16_t *)&ha->iobase2300->host_status) & + RISC_2300_INT; + else data = qla2100_debounce_register(&ha->iobase->istatus) & + RISC_INT; + + /* Check for pending interrupts. */ + if( !(ha->flags.in_isr) && (data) ) { + DEBUG(qla2100_print("qla2100_reset: Calling isr\n");) + qla2100_isr(ha, (srb_t **)&ha->done_q_first, (srb_t **)&ha->done_q_last); + } + DRIVER_UNLOCK + + /* + * Determine the suggested action that the mid-level driver wants + * us to perform. + */ + if( CMD_HANDLE(cmd) == (unsigned char *) 0 ) { + /* + * if mid-level driver called reset with a orphan SCSI_Cmnd + * (i.e. a command that's not pending ), so perform the + * function specified. + */ + /* 4.23 */ + if( (flags & SCSI_RESET_SUGGEST_HOST_RESET) ) + action = ADAPTER_RESET; + else if( flags & SCSI_RESET_SUGGEST_BUS_RESET ) + action = BUS_RESET; + else + action = DEVICE_RESET; + } else { /* + * Mid-level driver has called reset with this SCSI_Cmnd and + * its pending. + */ + if( flags & SCSI_RESET_SUGGEST_HOST_RESET ) + action = ADAPTER_RESET; + else if( flags & SCSI_RESET_SUGGEST_BUS_RESET ) + action = BUS_RESET; + else + action = DEVICE_RESET; + } + + b = SCSI_BUS_32(cmd); + t = SCSI_TCN_32(cmd); + l = SCSI_LUN_32(cmd); + q = GET_LU_Q(ha, b, t, l); + +#if AUTO_ESCALATE_RESET + if( (action & DEVICE_RESET) && (q->q_flag & QLA2100_QRESET) ) { + printk(KERN_INFO "qla2100(%d): Bus device reset already sent to " "device, escalating.\n", (int)ha->host_no); + action = BUS_RESET; + } + if( (action & DEVICE_RESET) && (sp->flags & SRB_ABORT_PENDING) ) { + printk(KERN_INFO "qla2100(%d):Have already attempted to reach " "device with abort device\n", (int)ha->host_no); + printk(KERN_INFO "qla2100(%d):message, will escalate to BUS " "RESET.\n",(int) ha->host_no); + action = BUS_RESET; + } +#endif + + /* + * By this point, we want to already know what we are going to do, + * so we only need to perform the course of action. + */ + + DRIVER_LOCK + result = SCSI_RESET_ERROR; + switch( action ) { + case FAIL: + break; + + case RESET_DELAYED: + result = SCSI_RESET_PENDING; + break; + + case ABORT_DEVICE: + if( qla2100_verbose ) + printk(KERN_INFO "scsi(%d:%d:%d:%d): ABORT DEVICE ISSUED.\n", (int)ha->host_no,(int)b,(int)t,(int)l); + qla2100_abort_queue_single(ha,b,t,l,DID_ABORT); + if( !ha->loop_down_timer ) + if( qla2100_abort_device(ha, b, t, l) == 0 ) + result = SCSI_RESET_PENDING; + break; + + case DEVICE_RESET: + if( qla2100_verbose ) + printk(KERN_INFO "scsi(%d:%d:%d:%d): DEVICE RESET ISSUED.\n",(int) ha->host_no,(int)b,(int)t,(int)l); + for( l = 0; l < ha->max_luns; l++ ) + qla2100_abort_queue_single(ha,b,t,l,DID_ABORT); + if( !ha->loop_down_timer ) + if( qla2100_device_reset(ha, b, t) == 0 ) + result = SCSI_RESET_PENDING; + q->q_flag |= QLA2100_QRESET; + break; + + case BUS_RESET: + if( qla2100_verbose ) + printk(KERN_INFO "scsi(%d:%d:%d:%d): LOOP RESET ISSUED.\n",(int) ha->host_no,(int)b,(int)t,(int)l); + for( t = 0; t < ha->max_targets; t++ ) + for( l = 0; l < ha->max_luns; l++ ) + qla2100_abort_queue_single(ha,b,t,l,DID_RESET); + if( !ha->loop_down_timer ) + if( qla2100_loop_reset(ha) == 0 ) + result = SCSI_RESET_SUCCESS | SCSI_RESET_BUS_RESET; + /* + * The reset loop routine returns all the outstanding commands back + * with "DID_RESET" in the status field. + */ + if( flags & SCSI_RESET_SYNCHRONOUS ) { + CMD_RESULT(cmd) = (int) (DID_BUS_BUSY << 16); + (*(cmd)->scsi_done)(cmd); + } + + /* ha->reset_start = jiffies; */ + break; + + case ADAPTER_RESET: + default: + if( qla2100_verbose ) { + printk(KERN_INFO "scsi(%d:%d:%d:%d): ADAPTER RESET ISSUED.\n",(int) ha->host_no,(int)b,(int)t,(int)l); + } + ha->flags.reset_active = TRUE; + /* + * We restarted all of the commands automatically, so the mid-level code can expect + * completions momentitarily. + */ + if( qla2100_abort_isp(ha) == 0 ) + result = SCSI_RESET_SUCCESS | SCSI_RESET_HOST_RESET; + + ha->flags.reset_active = FALSE; + } + + if( ha->done_q_first ) + qla2100_done(ha, (srb_t **)&ha->done_q_first, (srb_t **)&ha->done_q_last); + qla2100_restart_queues(ha,TRUE); + DRIVER_UNLOCK + + COMTRACE('r') + LEAVE("qla2100_reset"); + return(result); +} + +/************************************************************************** +* qla1200_biosparam +* +* Description: +* Return the disk geometry for the given SCSI device. +**************************************************************************/ +int +qla2100_biosparam(Disk *disk, kdev_t dev, int geom[]) { + int heads, sectors, cylinders; + + heads = 64; + sectors = 32; + cylinders = disk->capacity / (heads * sectors); + if( cylinders > 1024 ) { + heads = 255; + sectors = 63; + cylinders = disk->capacity / (heads * sectors); + } + + geom[0] = heads; + geom[1] = sectors; + geom[2] = cylinders; + + return (0); +} + +/************************************************************************** +* qla2100_intr_handler +* +* Description: +* Handles the actual interrupt from the adapter. +* +* Context: Interrupt +**************************************************************************/ +void +qla2100_intr_handler(int irq, void *dev_id, struct pt_regs *regs) { +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,1,95) + unsigned long cpu_flags = 0; +#endif + scsi_qla_host_t *ha; + uint16_t data; + device_reg_t *reg; + device2300_reg_t *reg2300; + + ENTER_INTR("qla2100_intr_handler"); + COMTRACE('I') + ha = (scsi_qla_host_t *) dev_id; + if( !ha ) { + printk(KERN_INFO "qla2100_intr_handler: NULL host ptr\n"); + COMTRACE('X') + return; + } + ha->isr_count++; + qla2100_stats.irqhba = ha; + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,1,95) + /* Prevent concurrent access to adapters register */ + spin_lock_irqsave(&io_request_lock, cpu_flags); + qla2100_disable_intrs(ha); + + if (ha->device_id == QLA2300_DEVICE_ID) { + reg2300 = ha->iobase2300; + data = qla2100_debounce_register( + (uint16_t *)®2300->host_status) & RISC_2300_INT; + } else { + reg = ha->iobase; + data = qla2100_debounce_register(®->istatus) & + RISC_INT; + } + + /* Check for pending interrupts. */ + if( data ) { + /*DEBUG(qla2100_print("qla2100_intr_handler: Int active, Calling isr\n");)*/ + qla2100_isr(ha, + (srb_t **)&ha->done_q_first, + (srb_t **)&ha->done_q_last); + } + + if( ha->done_q_first ) + qla2100_done(ha, (srb_t **)&ha->done_q_first, (srb_t **)&ha->done_q_last); + + spin_unlock_irqrestore(&io_request_lock, cpu_flags); + qla2100_enable_intrs(ha); + + /* Wakeup the DPC routine */ + if( (!ha->flags.mbox_busy && (ha->flags.isp_abort_needed || + ha->flags.reset_marker || + ha->flags.update_config_needed || + ( !ha->flags.loop_resync_active && + ha->flags.loop_resync_needed) ) ) + && ha->dpc_wait && !ha->dpc_active ) { /* v2.19.4 */ + up(ha->dpc_wait); + } + +#else /* LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95) */ + + /* Prevent concurrent access to istatus register */ + if( test_bit(QLA2100_IN_ISR_BIT, (int *)&ha->flags) ) { + COMTRACE('X') + DEBUG(printk("scsi%d: Already in interrupt - returning \n", (int)ha->host_no);) + return; + } + set_bit(QLA2100_IN_ISR_BIT, (int *)&ha->flags); + qla2100_disable_intrs(ha); + + if (ha->device_id == QLA2300_DEVICE_ID) { + reg2300 = ha->iobase2300; + data = qla2100_debounce_register( + (uint16_t *)®2300->host_status) & RISC_2300_INT; + } else { + reg = ha->iobase; + data = qla2100_debounce_register(®->istatus) & + RISC_INT; + } + + /* Check for pending interrupts. */ + if( data ) { + DEBUG(qla2100_print("qla2100_intr_handler_2: Int active, Calling isr\n");) + qla2100_isr(ha, + (srb_t **)&ha->done_q_first, + (srb_t **)&ha->done_q_last); + } + + if( ha->done_q_first ) + qla2100_done(ha, (srb_t **)&ha->done_q_first, (srb_t **)&ha->done_q_last); + + + /* Schedule the DPC routine */ + if( (ha->flags.isp_abort_needed || + ha->flags.reset_marker || + ( !ha->flags.loop_resync_active && + ha->flags.loop_resync_needed) || + ha->done_q_first ) && !ha->flags.dpc_sched ) { + + ha->run_qla_bh.data = (void *) ha; + ha->run_qla_bh.routine = qla2100_do_dpc; + + COMTRACE('P') + queue_task_irq(&ha->run_qla_bh,&tq_scheduler); + ha->flags.dpc_sched = TRUE; + } + clear_bit(QLA2100_IN_ISR_BIT, (int *)&ha->flags); + qla2100_enable_intrs(ha); +#endif + + COMTRACE('i') + LEAVE_INTR("qla2100_intr_handler"); +} + +/************************************************************************** +* qla2100_do_dpc +* This kernel thread is a task that is schedule by the interrupt handler +* to perform the background processing for interrupts. +* +* Notes: +* This task always run in the context of a kernel thread. It +* is kick-off by the driver's detect code and starts up +* up one per adapter. It immediately goes to sleep and waits for +* some fibre event. When either the interrupt handler or +* the timer routine detects a event it will one of the task +* bits then wake us up. +**************************************************************************/ +void +qla2100_do_dpc(void *p) { + scsi_qla_host_t *ha = (scsi_qla_host_t *) p; +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18) + struct semaphore sem = MUTEX_LOCKED; +#else + DECLARE_MUTEX_LOCKED(sem); +#endif + unsigned long flags; + srb_t *sp, *sp_next; + uint32_t b, t, l; + scsi_lu_t *q; + int status; + + lock_kernel(); + + /* + * If we were started as result of loading a module, close all of the + * user space pages. We don't need them, and if we didn't close them + * they would be locked into memory. + */ + exit_mm(current); + +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,3,18) + + daemonize(); + +#endif + current->session = 1; + current->pgrp = 1; + /* + * FIXME(dg) this is still a child process of the one that did the insmod. + * This needs to be attached to task[0] instead. + */ + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18) + siginitsetinv(¤t->blocked, SHUTDOWN_SIGS); +#else + siginitsetinv(¤t->blocked, sigmask(SIGKILL)); +#endif + current->fs->umask = 0; + + /* + * Set the name of this process. + */ + sprintf(current->comm, "qla2100_dpc_%d", (int)ha->host_no); + + ha->dpc_wait = &sem; + ha->dpc_handler = current; + + unlock_kernel(); + + /* + * Wake up the thread that created us. + */ + DEBUG(printk("qla2100_dpc: Wake up parent %d\n", ha->dpc_notify->count.counter)); + + up(ha->dpc_notify); + + while( 1 ) { + /* + * If we get a signal, it means we are supposed to go + * away and die. This typically happens if the user is + * trying to unload a module. + */ + DEBUG(printk("qla2100 %d: DPC handler sleeping\n",(int)ha->host_no)); + down_interruptible(&sem); + + if( signal_pending(current) ) + break; /* get out */ + + DEBUG(printk("qla2100 %d: DPC handler waking up\n",(int)ha->host_no);) + + if (ha->dpc_flags & COMMAND_WAIT_NEEDED) { + /* Release task daemon lock. */ + DEBUG(printk("Waiting on commands to complete\n");) + if( qla2100_cmd_wait(ha) ) + continue; + /* Acquire task daemon lock. */ + } + spin_lock_irqsave(&io_request_lock, flags); + ha->dpc_active = 1; + + /* Determine what action is necessary */ + + /* Flush all commands in watchdog queue */ + if( ha->flags.port_restart_needed ) { + DEBUG(qla2100_print("qla2100: DPC port restarting - flushing all cmds in watchdog queue.\n");) + ha->flags.port_restart_needed = FALSE; + for( sp = ha->retry_q_first; (sp != NULL); sp = sp_next ) { + sp_next = sp->s_next; + b = SCSI_BUS_32(sp->cmd); + t = SCSI_TCN_32(sp->cmd); + l = SCSI_LUN_32(sp->cmd); + if( (q = GET_LU_Q(ha, b, t,l)) == NULL || + !(q->q_flag & QLA2100_QSUSP) ) + continue; + q->q_flag &= ~QLA2100_QSUSP; + qla2100_timeout_remove(ha, sp); + CMD_RESULT(sp->cmd) = DID_BUS_BUSY << 16; + CMD_HANDLE(sp->cmd) = (unsigned char *) NULL; + qla2100_done_q_put(ha, sp, (srb_t **)&ha->done_q_first, (srb_t **)&ha->done_q_last); + } + + /* v2.19 - We want to wait until the end to + * return all requests back to OS. + */ + /* deleted: qla2100_restart_queues(ha, FALSE); */ + ha->flags.restart_queues_needed = TRUE; + } + + /* Process any pending mailbox commands */ + if( !ha->flags.mbox_busy ) { + if( ha->flags.isp_abort_needed ) { + DEBUG(printk("dpc: qla2100_abort_isp ha = %p\n", ha);) + ha->flags.isp_abort_needed = FALSE; + qla2100_abort_isp(ha); + } + + if( ha->flags.reset_marker ) { + DEBUG(printk("dpc: qla2100_reset_marker \n");) + qla2100_rst_aen(ha); + } + + if( ha->flags.update_config_needed ) { + DEBUG(printk("dpc: qla2100_update_config\n");) + qla2100_update_config(ha); + } + + /* v2.19.8 Retry each device up to login retry count */ + if ( (ha->device_flags & RELOGIN_NEEDED) && + !ha->loop_state != LOOP_DOWN ) { /* v2.19.5 */ + DEBUG(printk("dpc: qla2100_login\n");) + ha->device_flags &= ~RELOGIN_NEEDED; + for (t = 0; t < MAX_FIBRE_DEVICES; t++) { + /* check if fabric logic retry needed */ + if ( (ha->fc_db[t].flag & DEV_PUBLIC) && + (ha->fc_db[t].flag & DEV_RELOGIN) ) { + if ( PORT_DOWN(ha,t) ) { + PORT_DOWN(ha,t)--; + if ( (status = qla2x00_login_public_device(ha, + &ha->fc_db[t].loop_id, + &ha->fc_db[t].port_id[0], + (uint16_t) MBC_NO_PLOGI_IF_LOGGED_IN)) == QL_STATUS_SUCCESS ) { + DEBUG(printk("dpc: logged in ID %x\n",ha->fc_db[t].loop_id);) + /* restart ports */ + ha->fc_db[t].flag &= ~DEV_RELOGIN; + PORT_DOWN(ha,t) = 0; + } else if ( status == QL_STATUS_FATAL_ERROR ) { + ha->flags.isp_abort_needed = TRUE; + ha->fc_db[t].flag &= ~DEV_RELOGIN; + PORT_DOWN(ha,t) = 0; + } else { + /* retry the login again */ + ha->device_flags |= RELOGIN_NEEDED; + DEBUG(printk("dpc: Retry %d logged in ID %x\n",PORT_DOWN(ha,t), + ha->fc_db[t].loop_id);) + } + } + } + } + DEBUG(printk("dpc: qla2100_login_end.\n");) + } + + /* v2.19.5 */ + if ( (ha->device_flags & LOGIN_RETRY_NEEDED) && + !ha->loop_state != LOOP_DOWN ) { /* v2.19.5 */ + ha->device_flags &= ~LOGIN_RETRY_NEEDED; + DEBUG(printk("dpc: qla2100_login_retry\n");) + qla2100_loop_resync(ha); + DEBUG(printk("dpc: qla2100_login_retry end.\n");) + } + + /* v2.19.5b5 */ + if( ha->flags.loop_resync_needed ) { + if( (ha->device_flags & RSCN_UPDATE ) ) { + DEBUG(printk("dpc: qla2100_rscn_update\n");) + ha->device_flags &= ~RSCN_UPDATE; + } + else + DEBUG(printk("dpc: qla2100_loop_resync\n");) + qla2100_loop_resync(ha); + DEBUG(printk("dpc: qla2100_loop_resync/rscn_update done\n");) + } + + if( ha->flags.restart_queues_needed ) { + DEBUG(printk("dpc: calling qla2100_restart_queues\n");) + qla2100_restart_queues(ha,FALSE); + } + + if( ha->flags.abort_queue_needed ) { + DEBUG(printk("dpc: qla2100_abort_queues\n");) + qla2100_abort_queues(ha, FALSE); + } + if( !ha->interrupts_on ) + qla2100_enable_intrs(ha); + } + + if( ha->flags.done_requests_needed ) + ha->flags.done_requests_needed = FALSE; + + if( ha->done_q_first ) { + qla2100_done(ha, (srb_t **)&ha->done_q_first, (srb_t **)&ha->done_q_last); + } + + ha->dpc_active = 0; + + /* The spinlock is really needed up to this point. (DB) */ + spin_unlock_irqrestore(&io_request_lock, flags); + } + DEBUG(qla2100_print("dpc: DPC handler exiting\n");) + + /* + * Make sure that nobody tries to wake us up again. + */ + ha->dpc_wait = NULL; + ha->dpc_handler = NULL; + ha->dpc_active = 0; + + /* + * If anyone is waiting for us to exit (i.e. someone trying to unload + * a driver), then wake up that process to let them know we are on + * the way out the door. This may be overkill - I *think* that we + * could probably just unload the driver and send the signal, and when + * the error handling thread wakes up that it would just exit without + * needing to touch any memory associated with the driver itself. + */ + if( ha->dpc_notify != NULL ) + up(ha->dpc_notify); + + +} + +/************************************************************************** +* qla2100_device_queue_depth +* Determines the queue depth for a given device. There are two ways +* a queue depth can be obtained for a tagged queueing device. One +* way is the default queue depth which is determined by whether +* If it is defined, then it is used +* as the default queue depth. Otherwise, we use either 4 or 8 as the +* default queue depth (dependent on the number of hardware SCBs). +**************************************************************************/ +STATIC void qla2100_device_queue_depth(scsi_qla_host_t *p, Scsi_Device *device) { + int default_depth = 16; + + device->queue_depth = default_depth; + if( device->tagged_supported ) { + device->tagged_queue = 1; + device->current_tag = 0; +#ifdef MODULE + if( !(ql2xmaxqdepth == 0 || ql2xmaxqdepth > 256) ) + device->queue_depth = ql2xmaxqdepth; +#endif + + printk(KERN_INFO "scsi(%d:%d:%d:%d): Enabled tagged queuing, queue depth %d.\n", + (int)p->host_no, device->channel, device->id, + device->lun, device->queue_depth); + } else { + printk(KERN_WARNING "scsi(%d:%d:%d:%d):Device does not supoort tags queuing!!!.\n", + (int)p->host_no, device->channel, device->id, + device->lun); + } +} + +/************************************************************************** +* qla2100_select_queue_depth +* +* Description: +* Sets the queue depth for each SCSI device hanging off the input +* host adapter. We use a queue depth of 2 for devices that do not +* support tagged queueing. +**************************************************************************/ +STATIC void +qla2100_select_queue_depth(struct Scsi_Host *host, Scsi_Device *scsi_devs) { + Scsi_Device *device; + scsi_qla_host_t *p = (scsi_qla_host_t *) host->hostdata; + + ENTER("qla2100_select_queue_depth"); + for( device = scsi_devs; device != NULL; device = device->next ) { + if( device->host == host ) + qla2100_device_queue_depth(p, device); + } + LEAVE("qla2100_select_queue_depth"); +} + +/************************************************************************** +* ** Driver Support Routines ** +* +* qla2100_enable_intrs +* qla2100_disable_intrs +**************************************************************************/ +static inline void qla2100_enable_intrs(scsi_qla_host_t *ha) { + device_reg_t *reg; + + reg = ha->iobase; + ha->interrupts_on = 1; + /* enable risc and host interrupts */ + WRT_REG_WORD(®->ictrl, (ISP_EN_INT+ ISP_EN_RISC)); +} + +static inline void qla2100_disable_intrs(scsi_qla_host_t *ha) { + device_reg_t *reg; + + reg = ha->iobase; + ha->interrupts_on = 0; + /* disable risc and host interrupts */ + WRT_REG_WORD(®->ictrl, 0); +} + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,0) +/************************************************************************** +* mdelay +* Delay in milliseconds +* +**************************************************************************/ +STATIC inline void +mdelay(int milliseconds) { + int i; + + for( i=0; is_next) ) + *done_q_last = NULL; + else + (*done_q_first)->s_prev = NULL; + qla2100_stats.done_q_cnt--; + DEBUG(sp->state = 5;) +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95) + DRIVER_UNLOCK +#endif + QLA2100_TIMER_UNLOCK(ha); + cmd = sp->cmd; + b = SCSI_BUS_32(cmd); + t = SCSI_TCN_32(cmd); + l = SCSI_LUN_32(cmd); + q = GET_LU_Q(ha, b, t, l); + + /* Decrement outstanding commands on device. */ + if( q->q_outcnt ) + q->q_outcnt--; + if( q->q_outcnt < ha->hiwat ) { + q->q_flag &= ~QLA2100_QBUSY; + } + + q->io_cnt++; + + switch( (CMD_RESULT(cmd)>>16) ) { + case DID_RESET: + q->q_flag &= ~QLA2100_QRESET; + /* Issue marker command. */ + qla2100_marker(ha, b, t, 0, MK_SYNC_ID); + break; + case DID_ABORT: + sp->flags &= ~SRB_ABORT_PENDING; + sp->flags |= SRB_ABORTED; + if( sp->flags & SRB_TIMEOUT ) + CMD_RESULT(sp->cmd)= DID_TIME_OUT << 16; + break; + default: + break; + } + + /* 4.10 64 and 32 bit */ + /* Release memory used for this I/O */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,18) + if (cmd->use_sg) { + /* DEBUG(sprintf(debug_buff, + "S/G unmap_sg cmd=%x\n\r",cmd);) + DEBUG(qla2100_print(debug_buff)); */ + pci_unmap_sg(ha->pdev, cmd->request_buffer, + cmd->use_sg, + scsi_to_pci_dma_dir(cmd->sc_data_direction)); + } + else if (cmd->request_bufflen) { + /* DEBUG(sprintf(debug_buff, + "No S/G unmap_single cmd=%x saved_dma_handle=%lx\n\r", + cmd,sp->saved_dma_handle);) + DEBUG(qla2100_print(debug_buff);) */ + pci_unmap_single(ha->pdev,sp->saved_dma_handle, + cmd->request_bufflen, + scsi_to_pci_dma_dir(cmd->sc_data_direction)); + } +#endif + /* Call the mid-level driver interrupt handler */ + /* DEBUG(sprintf(debug_buff," [%d] ",cmd->pid);) + DEBUG(qla2100_print(debug_buff);) */ + + qla2100_callback(ha,sp,TRUE); + qla2100_next(ha, q); + } + + + COMTRACE('d') + /* LEAVE("qla2100_done"); */ +} + +/************************************************************************** +* qla2100_return_status +* Translates a ISP error to a Linux SCSI error +**************************************************************************/ +STATIC int qla2100_return_status(scsi_qla_host_t *ha, + sts_entry_t *sts, Scsi_Cmnd *cp) { + int host_status = DID_ERROR; + int scsi_status; + int comp_status; + unsigned resid; + srb_t *sp; + uint32_t t; + uint8_t *strp; + scsi_lu_t *up; + +#if DEBUG_QLA2100_INTR + STATIC char *reason[] = { + "DID_OK", + "DID_NO_CONNECT", + "DID_BUS_BUSY", + "DID_TIME_OUT", + "DID_BAD_TARGET", + "DID_ABORT", + "DID_PARITY", + "DID_ERROR", + "DID_RESET", + "DID_BAD_INTR" + }; +#endif /* DEBUG_QLA2100_INTR */ + + ENTER("qla2100_return_status"); + +#if DEBUG_QLA2100_INTR + /* + DEBUG(printk("qla2100: compl status = 0x%04x\n", sts->comp_status)); + */ +#endif + scsi_status = sts->scsi_status; + comp_status = sts->comp_status; + sp = (srb_t *) CMD_SP(cp); + + if( (scsi_status & SS_RESIDUAL_OVER) ) + comp_status = CS_DATA_OVERRUN; + else if( (scsi_status & SS_RESPONSE_INFO_LEN_VALID) && + sts->rsp_info[3] == (uint8_t) 0 ) + comp_status = CS_COMPLETE; + + /* If scanning and missing lun then let the scsi layer skip it */ + /* 4.24 dg 01/18/2001 */ + if( cp->cmnd[0] == 0x12 && + cp->lun == 0 ) { /* inquiry */ + strp = (uint8_t *)cp->request_buffer; + up = (scsi_lu_t *) GET_LU_Q(ha, 0, cp->target, cp->lun); + if( *strp == 0x7f && up->io_cnt < 5) { + /* Make lun unassigned and wrong type */ + *strp = 0x23; + } + } + + switch( comp_status ) { + case CS_COMPLETE: + host_status = DID_OK; + /* v2.19.5b2 Reset port down retry on success. */ + sp->port_down_retry_count = ha->port_down_retry_count; + break; + case CS_PORT_UNAVAILABLE: + /* release target data structure */ + host_status = DID_NO_CONNECT; + DEBUG(sprintf(debug_buff,"scsi: Unavail port detected 0x%x-0x%x.\n", + sts->comp_status, sts->scsi_status); ) + DEBUG(qla2100_print(debug_buff);) + break; + case CS_PORT_LOGGED_OUT: + case CS_PORT_CONFIG_CHG: + case CS_PORT_BUSY: + case CS_INCOMPLETE: + host_status = DID_NO_CONNECT; + DEBUG(sprintf(debug_buff,"scsi: Port Error detected 0x%x-0x%x.\n", + sts->comp_status, sts->scsi_status); ) + DEBUG(qla2100_print(debug_buff);) + break; + case CS_RESET: + host_status = DID_RESET; + break; + case CS_ABORTED: + /* v2.19.12 - DID_ABORT does not retry the request */ + /* if we aborted this request then abort otherwise it must be a reset */ + if ( (sp->flags & SRB_ABORT_PENDING) ) + host_status = DID_ABORT; + else + host_status = DID_RESET; + break; + case CS_TIMEOUT: + host_status = DID_ERROR; + /* v2.19.8 if timeout then check to see if logout occurred*/ + t = SCSI_TCN_32(cp); + if ( (ha->fc_db[t].flag & DEV_PUBLIC) && + (sts->status_flags & IOCBSTAT_SF_LOGO) ) { + ha->fc_db[t].flag |= DEV_RELOGIN; + DEBUG(printk("scsi: Timeout occurred with Logo, status flag (%x) with public device loop id (%x), attempt new recovery\n", + sts->status_flags, ha->fc_db[t].loop_id);) + /* Suspend port */ + PORT_DOWN(ha,t) = ha->port_down_retry_count; + ha->device_flags |= RELOGIN_NEEDED; + } + break; + case CS_DATA_UNDERRUN: + resid = sts->residual_length; + /* if RISC reports underrun and target does not report it + * then we must have a lost frame, so tell upper layer + * to retry it by reporting an error. + */ + if( !(sts->scsi_status & SS_RESIDUAL_UNDER) ) { + resid = (unsigned)(CMD_XFRLEN(cp)); + } + + if( (unsigned)(CMD_XFRLEN(cp) - resid) < cp->underflow ) { + host_status = DID_ERROR; + DEBUG3(sprintf(debug_buff,"scsi: Underflow detected - retrying command.\n");) + DEBUG3(qla2100_print(debug_buff);) + } else { + /* v2.19.5b2 Reset port down retry on success. */ + sp->port_down_retry_count = ha->port_down_retry_count; + host_status = DID_OK; + } + break; + + default: + DEBUG3(printk("scsi: Error detected 0x%x-0x%x.\n", + sts->comp_status, sts->scsi_status);) + host_status = DID_ERROR; + break; + } + +#if DEBUG_QLA2100_INTR + sprintf(debug_buff, "qla2100 ISP status: host status (%s) scsi status %x\n\r", reason[host_status], scsi_status); + DEBUG(qla2100_print(debug_buff);) +#endif + + LEAVE("qla2100_return_status"); + + return ((scsi_status & STATUS_MASK) | (host_status << 16) ); +} + +/* +* qla2100_done_q_put +* Place SRB command on done queue. +* +* Input: +* ha = host pointer +* sp = srb pointer. +* done_q_first = done queue first pointer. +* done_q_last = done queue last pointer. +*/ +STATIC void +qla2100_done_q_put(scsi_qla_host_t *ha, srb_t *sp, srb_t **done_q_first, srb_t **done_q_last) { + + unsigned long cpu_flags = 0; + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_put_done_q"); +#endif +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95) + DRIVER_LOCK +#else + QLA2100_TIMER_LOCK(ha); +#endif + /* Place block on done queue */ + sp->s_next = NULL; + sp->s_prev = *done_q_last; + if( !*done_q_first ) + *done_q_first = sp; + else + (*done_q_last)->s_next = sp; + *done_q_last = sp; + + qla2100_stats.done_q_cnt++; + DEBUG(sp->state = 3;) +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95) + DRIVER_LOCK +#else + QLA2100_TIMER_UNLOCK(ha); +#endif + +#ifdef QL_DEBUG_LEVEL_3 + LEAVE("qla2100_put_done_q"); +#endif +} + + +/************************************************************************** +* qla2100_timer +* +* Description: +* One second timer +* +* Context: Interrupt +**************************************************************************/ +STATIC void +qla2100_timer(scsi_qla_host_t *ha) { + + srb_t *sp, *sp_next; + int stop_timer, kick_off = 0; + int cnt; + int t; + /* unsigned long cpu_flags = 0; */ + + + /* ENTER("qla2100_timer"); */ + + /* v2.19.02 spin_lock_irqsave(&io_request_lock, cpu_flags); */ + + stop_timer = 0; + + for( t = 0; t < ha->max_targets; t++ ) { + if( TGT_Q(ha, 0, t) == NULL ) + continue; + if( TGT_Q(ha, 0, t)->down_timer > 0 ) + TGT_Q(ha, 0, t)->down_timer--; + } + + /* Port Down Handler. */ + if( ha->queue_restart_timer > 0 ) { + ha->queue_restart_timer--; +#ifdef TRACECODE + sprintf(debug_buff,"timer: Port down time in secs %d\n",ha->queue_restart_timer); + qla2100_print(debug_buff); +#endif + /* + * When a port goes DOWN, we suspend the queue and wait 1 second + * (one timer tick) before trying to kick off the commands again. + * We will do this for "port_down_retry_count" times per + * command before giving up on the command altogether. + */ + if( !ha->queue_restart_timer ) { + ha->flags.port_restart_needed = TRUE; + DEBUG(qla2100_print("qla2100_timer: Port Down complete - restarting commands in the queues\n");) + stop_timer++; + } + } + /* Loop down handler. */ + if( ha->loop_down_timer > 0 && + !ha->flags.abort_isp_active && + ha->flags.online ) { + if( ha->loop_down_timer == LOOP_DOWN_TIME ) { + DEBUG(printk("qla2100_timer: Loop Down time expired - aborting the queues before time expire\n");) +#ifdef TRACECODE + qla2100_print("qla2100_timer: Loop Down - aborting the queues before time expire\n"); +#endif +#if 1 + ha->flags.abort_queue_needed = TRUE; +#else + qla2100_abort_queues(ha, TRUE); +#endif + } + + ha->loop_down_timer--; +#ifdef TRACECODE + sprintf(debug_buff,"qla2100_timer: Loop Down - seconds remainning %d\n",ha->loop_down_timer); + qla2100_print(debug_buff); +#endif + /* if the loop has been down for 4 minutes on QLA2100, + reinit adapter */ + if( !ha->loop_down_timer ) { +#ifdef TRACECODE + qla2100_print("qla2100_timer: Loop down for 4 mins \n"); +#endif + DEBUG(printk("qla2100_timer: Loop down exceed 4 mins -restarting queues and abort ISP.\n");) + ha->flags.restart_queues_needed = TRUE; + if ( (ha->device_id == QLA2100_DEVICE_ID) && + (qla2100_reinit == 1 )) + ha->flags.isp_abort_needed = TRUE; + stop_timer++; + } + } + + /* + * Retry Handler -- This handler will recycle queued requests until the + * temporary loop down condition terminates. + */ + if( !ha->flags.abort_isp_active ) { +#ifdef TRACECODE + if( ha->retry_q_first ) + qla2100_print("qla2100_timer: Scanning for timed out commands\n"); +#endif + for( cnt=0, sp = ha->retry_q_first; (sp); sp = sp_next ) { + if( sp->wdg_time ) + sp->wdg_time--; + sp_next = sp->s_next; + if( sp->wdg_time == 0 ) { + kick_off++; + DEBUG3(sprintf(debug_buff,"timer: CMD timeout %p, pid %d\n",sp, sp->cmd->pid);) + DEBUG3(qla2100_print(debug_buff);) + cnt++; + qla2100_timeout_remove(ha, sp); + CMD_RESULT(sp->cmd) = DID_BUS_BUSY << 16; + CMD_HANDLE(sp->cmd) = (unsigned char *) NULL; + qla2100_done_q_put(ha, sp, (srb_t **)&ha->done_q_first, (srb_t **)&ha->done_q_last); + } + } + + if( cnt > 0 ) { + DEBUG2(sprintf(debug_buff,"timer: found %d requests\n",cnt);) + DEBUG2(qla2100_print(debug_buff);) + } + } + + if( ha->done_q_first ) + ha->flags.done_requests_needed = TRUE; + + if( ha->dpc_flags & ISP_RESET_NEEDED) { + ha->dpc_flags &= ~ISP_RESET_NEEDED; + ha->flags.isp_abort_needed = TRUE; + } + + +#if QLA2100_LIPTEST + if( (ha->forceLip++) == (60*3) && qla2100_lip) { + /* qla2100_loop_reset(ha); */ + qla2100_abort_isp(ha); + ha->forceLip = 0; + } +#endif + /* v2.19.02 spin_unlock_irqrestore(&io_request_lock, cpu_flags); */ + + /* Schedule the DPC routine if needed */ + if( ( ha->flags.isp_abort_needed || + (!ha->flags.loop_resync_active && ha->flags.loop_resync_needed) || + ha->flags.restart_queues_needed || + ha->flags.port_restart_needed || + ha->flags.done_requests_needed || + (ha->device_flags & RELOGIN_NEEDED) || + (ha->dpc_flags & COMMAND_WAIT_NEEDED) || + (ha->device_flags & LOGIN_RETRY_NEEDED) || + kick_off > 0 || + ha->flags.abort_queue_needed ) && + ha->dpc_wait && !ha->dpc_active ) { /* v2.19.4 */ + up(ha->dpc_wait); + } + + /* IOCTL SCSI Pass Thru Handler. */ + if (ha->IoctlPassThru_InProgress) { + if (ha->ioctl_timer) ha->ioctl_timer--; + } + + /* IOCTL FCCT Pass Thru Handler. */ + if (ha->IoctlPassFCCT_InProgress) { + if (ha->ioctl_timer) ha->ioctl_timer--; + } + + /* ha->flags.watchdog_enabled = FALSE; */ + RESTART_TIMER(qla2100_timer,ha,WATCH_INTERVAL); + + /* LEAVE("qla2100_timer"); */ +} + +/* +* qla2100_timeout_insert +* Function used to insert a command block onto the +* watchdog timer queue. +* +* Note: Must insure that sc_time is not zero +* before calling qla2100_timeout_insert. +* +* Input: +* ha = adapter block pointer. +* sp = srb pointer. +*/ +STATIC void +qla2100_timeout_insert(scsi_qla_host_t *ha, srb_t *sp) { + unsigned long cpu_flags = 0; + uint8_t timeoutcnt; + +#ifdef QL_DEBUG_LEVEL_3 + /* ENTER("qla2100_timeout_insert"); */ +#endif + + /* Compute number of time intervals */ + timeoutcnt = (uint8_t) (CMD_TIMEOUT(sp->cmd)/(WATCH_INTERVAL * HZ)); + if( timeoutcnt >= 3 ) /* 3 or more */ + /* sp->wdg_time = timeoutcnt - 3; */ + sp->wdg_time = 3; + else + sp->wdg_time = 1; + + DEBUG3(sprintf(debug_buff,"Watchdog (insert) - pid=%d, tmo=%d \n",sp->cmd->pid,sp->wdg_time);) + DEBUG3(qla2100_print(debug_buff);) + + /* Acquire watchdoq queue specific lock */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95) + DRIVER_LOCK +#else + QLA2100_TIMER_LOCK(ha); +#endif + /* Add command to queue */ + if (ha->retry_q_first == NULL) { + ha->retry_q_first = sp; + ha->retry_q_last = sp; + } else { + ha->retry_q_last->s_next = sp; + ha->retry_q_last = sp; + } + sp->s_next = NULL; + qla2100_stats.retry_q_cnt++; + sp->state = 0xd0; + + sp->flags |= SRB_WATCHDOG; + ha->flags.watchdog_enabled = TRUE; + + /* Release watchdog queue specific lock */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95) + DRIVER_UNLOCK +#else + QLA2100_TIMER_UNLOCK(ha); +#endif + +#ifdef QL_DEBUG_LEVEL_3 + /* LEAVE("qla2100_timeout_insert"); */ +#endif +} + +/* +* qla2100_timeout_remove +* Function used to remove a command block from the +* watchdog timer queue. +* +* Note: Must insure that command is on watchdog +* list before calling qla2100_timeout_remove. +* if (sp->flags & SRB_WATCHDOG) +* +* Input: +* ha = adapter block pointer. +* sp = srb pointer. +*/ +STATIC void +qla2100_timeout_remove(scsi_qla_host_t *ha, srb_t *sp) { + unsigned long cpu_flags = 0; + srb_t *nextsp; + +#ifdef QL_DEBUG_LEVEL_3 + /* ENTER("qla2100_timeout_remove"); */ +#endif + + DEBUG3(sprintf(debug_buff,"Watchdog (remove) pid=%d time%d\n",sp->cmd->pid,sp->wdg_time);) + DEBUG3(qla2100_print(debug_buff);) + + /* Acquire watchdoq queue specific lock */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95) + DRIVER_LOCK +#else + QLA2100_TIMER_LOCK(ha); +#endif + /* Remove command block from watchdog queue. */ + if (ha->retry_q_first != NULL) { + if (ha->retry_q_first == sp) { + /* Remove from top of queue */ + ha->retry_q_first = sp->s_next; + if (ha->retry_q_first == NULL) { + + ha->retry_q_last = NULL; + ha->flags.watchdog_enabled = FALSE; + } + } else { + /* Remove from middle of queue or bottom of queue */ + for (nextsp = ha->retry_q_first; nextsp->s_next != NULL; + nextsp = nextsp->s_next) { + if (nextsp->s_next == sp) { + nextsp->s_next = sp->s_next; + if (nextsp->s_next == NULL) + ha->retry_q_last = nextsp; + break; + } + } + } + sp->flags &= ~SRB_WATCHDOG; + qla2100_stats.retry_q_cnt--; + } + + /* Release watchdog queue specific lock */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95) + DRIVER_UNLOCK +#else + QLA2100_TIMER_UNLOCK(ha); +#endif + +#ifdef QL_DEBUG_LEVEL_3 + /* LEAVE("qla2100_timeout_remove"); */ +#endif +} + +/* +* qla2100_next +* Retrieve and process next job in the queue. +* +* Input: +* ha = adapter block pointer. +* q = SCSI LU pointer. +* SCSI_LU_Q lock must be already obtained and no other locks. +* +* Output: +* Releases SCSI_LU_Q upon exit. +*/ +STATIC void +qla2100_next(scsi_qla_host_t *ha, scsi_lu_t *q) { + srb_t *sp; +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95) + unsigned long cpu_flags = 0; +#endif + uint8_t status; + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_next"); +#endif + + DRIVER_LOCK + COMTRACE('N') + while( ((sp = q->q_first) != NULL) && /* we have a pending cmds */ + !(q->q_flag & QLA2100_QBUSY) && /* device can accept more cmds */ + !((q->q_flag & QLA2100_QSUSP) && /* device queue not suspended */ + !ha->flags.abort_isp_active && /* adapter abort active */ + !ha->loop_down_timer) ) /* down timer not active */ + { + /* Remove srb from SCSI LU queue. */ + qla2100_removeq(q, sp); + sp->state = 0x32; + /* Set busy flag if reached high water mark. */ + q->q_outcnt++; + if( q->q_outcnt >= ha->hiwat ) { + q->q_flag |= QLA2100_QBUSY; + } + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,18) + if( ha->flags.enable_64bit_addressing ) + status = qla2100_64bit_start_scsi(ha, sp); + else +#endif + status = qla2100_32bit_start_scsi(ha, sp); + + if( status ) { + qla2100_putq_t(q, sp); + + if( q->q_outcnt ) + q->q_outcnt--; + if( q->q_outcnt < ha->hiwat ) + q->q_flag &= ~QLA2100_QBUSY; + break; + } + } + + COMTRACE('n') + DRIVER_UNLOCK + /* Release SCSI LU queue specific lock */ + +#ifdef QL_DEBUG_LEVEL_3 + LEAVE("qla2100_next"); +#endif +} +#if 0 +/******************************************************* +v4.10 +* This function has been de-implemented +* All DMAable memory is allocated on the spot +* according to what kernel version is in effect. +******************************************************** +* qla2100_alloc_phys +* Function used to allocate physical memory +* and zero it. +* +* Input: +* size = size in bytes. +* flag = sleep flag. +* phy_addr = physical address pointer. +* +* Returns: +* not NULL = success +*/ +STATIC void * +qla2100_alloc_phys(int siz, u_long *phy_addr) { + void *mem = NULL; + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_alloc_phys"); +#endif + mem = KMALLOC(siz); + if( mem != NULL ) { + *phy_addr = VIRT_TO_BUS(mem); + BZERO((caddr_t)mem, siz); + DEBUG5(sprintf(debug_buff,"qla2100: get phys mem =0x%lx\n\r",(long)*phy_addr)); + DEBUG5(qla2100_print(debug_buff);) + } + +#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3) + if( mem == NULL ) + qla2100_print("qla2100_alloc_phys: **** FAILED ****\n\r"); +#endif +#ifdef QL_DEBUG_LEVEL_3 + else + LEAVE("qla2100_alloc_phys"); +#endif + return(mem); +} +#endif + +/* +* qla2100_putq_t +* Add the standard SCB job to the top of standard SCB commands. +* +* Input: +* q = SCSI LU pointer. +* sp = srb pointer. +* SCSI_LU_Q lock must be already obtained. +*/ +STATIC void +qla2100_putq_t(scsi_lu_t *q, srb_t *sp) { + srb_t *srb_p; +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95) + unsigned long cpu_flags = 0; +#endif + +#ifdef QL_DEBUG_LEVEL_3 + /* ENTER("qla2100_putq_t"); */ +#endif + DRIVER_LOCK + DEBUG5(sprintf(debug_buff,"Adding to queue 0x%x<-(0x%x)\n\r",q,sp)); + DEBUG5(qla2100_print(debug_buff)); + sp->s_next = NULL; + q->q_incnt++; + sp->state = 2; + /* v2.19.6 */ + if( !q->q_first || !q->q_last) /* If queue empty */ + { + sp->s_prev = NULL; + q->q_first = sp; + q->q_last = sp; + } else { + srb_p = q->q_first; + while( srb_p ) + srb_p = srb_p->s_next; + + if( srb_p ) { + sp->s_prev = srb_p->s_prev; + if( srb_p->s_prev ) + srb_p->s_prev->s_next = sp; + else + q->q_first = sp; + srb_p->s_prev = sp; + sp->s_next = srb_p; + } else { + sp->s_prev = q->q_last; + q->q_last->s_next = sp; + q->q_last = sp; + } + } + + DRIVER_UNLOCK +#ifdef QL_DEBUG_LEVEL_3 + /* LEAVE("qla2100_putq_t"); */ +#endif +} + +/* +* qla2100_removeq +* Function used to remove a command block from the +* LU queue. +* +* Input: +* q = SCSI LU pointer. +* sp = srb pointer. +* SCSI_LU_Q lock must be already obtained. +*/ +STATIC void +qla2100_removeq(scsi_lu_t *q, srb_t *sp) { +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95) + unsigned long cpu_flags = 0; +#endif + DEBUG5(sprintf(debug_buff,"Removing from device_q (0x%x)->(0x%x)\n\r",q,sp)); + DEBUG5(qla2100_print(debug_buff)); + DRIVER_LOCK + if( sp->s_prev ) { + if( (sp->s_prev->s_next = sp->s_next) != NULL ) + sp->s_next->s_prev = sp->s_prev; + else + q->q_last = sp->s_prev; + } else if( !(q->q_first = sp->s_next) ) + q->q_last = NULL; + else + q->q_first->s_prev = NULL; + q->q_incnt--; + DRIVER_UNLOCK +} + +/* +* qla2100_callback +* Returns the completed SCSI command to LINUX. +* +* Returns: +* None +*/ +static inline void qla2100_callback(scsi_qla_host_t *ha, srb_t *sp, uint8_t dec) { +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95) + unsigned long cpu_flags = 0; +#endif + + CMD_HANDLE(sp->cmd) = (unsigned char *) NULL; + sp->flags &= ~SRB_SENT; + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95) + DRIVER_LOCK +#endif +#if 0 + if( dec ) + ha->actthreads--; +#endif + + /* v2.19.14 + * Perform internal retries, if needed. + */ + switch( (CMD_RESULT(sp->cmd)>>16) ) { + case DID_ERROR: + if( sp->retry_count > 0 ) { + sp->retry_count--; + DEBUG3(printk("qla2100: RETRY - os retry %d, drv retry %d, port retry %d\n\r",sp->cmd->retries,sp->retry_count,sp->port_down_retry_count)); + CMD_RESULT(sp->cmd) = (int) DID_BUS_BUSY << 16; + } else { + sp->retry_count = ha->retry_count; + /* all resetted commands must return with RESET */ + if(sp->cmd->flags & IS_RESETTING ) { + CMD_RESULT(sp->cmd) = (int) DID_RESET << 16; + DEBUG3(printk("qla2100: RESET cmd %p\n",sp->cmd)); + } + DEBUG3(printk("qla2100: OSerr = %p\n\r",sp->cmd)); + } + break; + default: + break; + } + + /* Call the mid-level driver interrupt handler */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95) + sti(); + (*(sp->cmd)->scsi_done)(sp->cmd); + cli(); +#else + (*(sp->cmd)->scsi_done)(sp->cmd); +#endif +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95) + DRIVER_UNLOCK +#endif +} + +/* +* qla2100_mem_alloc +* Allocates adapter memory. +* +* Returns: +* 0 = success. +* 1 = failure. +*/ +STATIC uint8_t +qla2100_mem_alloc(scsi_qla_host_t *ha) { + + uint8_t status = 1; + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_mem_alloc"); +#endif + + /* 4.10 */ + /* get consistent memory allocated for request/response rings */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18) + ha->request_ring = &ha->req[0]; + ha->request_dma = VIRT_TO_BUS(&ha->req[0]); + ha->response_ring = &ha->res[0]; + ha->response_dma = VIRT_TO_BUS(&ha->res[0]); +#ifdef FC_IP_SUPPORT + ha->pIpBufferQueue = &ha->asIpBuffers[0]; + ha->ppIpBufferQueueLow = VIRT_TO_BUS_LOW(&ha->asIpBuffers[0]); + ha->ppIpBufferQueueHigh = VIRT_TO_BUS_HIGH(&ha->asIpBuffers[0]); +#endif /* FC_IP_SUPPORT */ +#else /* KERNEL >= 2.3.18 */ + ha->request_ring = pci_alloc_consistent(ha->pdev, + ((REQUEST_ENTRY_CNT+1)*(sizeof(request_t))), + &ha->request_dma); + ha->response_ring = pci_alloc_consistent(ha->pdev, + ((RESPONSE_ENTRY_CNT+1)*(sizeof(response_t))), + &ha->response_dma); +#ifdef FC_IP_SUPPORT + /* not ported yet to new pci_alloc_consistent */ + ha->pIpBufferQueue = &ha->asIpBuffers[0]; + ha->ppIpBufferQueueLow = VIRT_TO_BUS_LOW(&ha->asIpBuffers[0]); + ha->ppIpBufferQueueHigh = VIRT_TO_BUS_HIGH(&ha->asIpBuffers[0]); +#endif +#endif + /* 4.10 */ + /* get consistent memory allocated for init control block */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18) + ha->init_cb = KMALLOC(sizeof(init_cb_t)); + if( ha->init_cb != NULL ) { + ha->init_cb_dma = VIRT_TO_BUS(ha->init_cb); + BZERO((caddr_t)ha->init_cb, sizeof(init_cb_t)); + } +#else + ha->init_cb = pci_alloc_consistent(ha->pdev, + sizeof(init_cb_t), + &ha->init_cb_dma); + BZERO((caddr_t)ha->init_cb, sizeof(init_cb_t)); +#endif + if( ha->init_cb ) status = 0; + + if( status ) + printk(KERN_WARNING "qla2100_mem_alloc: **** FAILED ****\n"); + +#ifdef QL_DEBUG_LEVEL_3 + else + LEAVE("qla2100_mem_alloc"); +#endif + return(status); +} + +/* +* qla2100_mem_free +* Frees all adapter allocated memory. +* +* Input: +* ha = adapter block pointer. +*/ +STATIC void +qla2100_mem_free(scsi_qla_host_t *ha) { + tgt_t *tgt; + uint32_t b, t; + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_mem_free"); +#endif + if( ha ) { + /* Free the target queues */ + b = 0; + for( t = 0; t < MAX_FIBRE_DEVICES; t++ ) { + tgt = TGT_Q(ha, b, t); + if( tgt ) + qla2100_tgt_dealloc(ha, tgt); + } + + /* Free host database. */ + if (ha->phost_db != NULL) { + KMFREE(ha->phost_db, sizeof(fcdev_t) * MAX_HOST_COUNT); + } + + /* 4.10 */ + /* free consistent memory allocated for request and response rings */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,18) + pci_free_consistent(ha->pdev, + ((REQUEST_ENTRY_CNT+1)*(sizeof(request_t))), + ha->request_ring, ha->request_dma); + + pci_free_consistent(ha->pdev, + ((RESPONSE_ENTRY_CNT+1)*(sizeof(response_t))), + ha->response_ring, ha->response_dma); +#endif + /* free memory allocated for ioctl operations */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18) + KMFREE(ha->ioctl_mem, PAGE_SIZE); +#else + pci_free_consistent(ha->pdev, PAGE_SIZE, + ha->ioctl_mem, ha->ioctl_mem_phys); +#endif + /* free memory allocated for init_cb */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18) + KMFREE(ha->init_cb, sizeof(init_cb_t)); +#else + pci_free_consistent(ha->pdev, sizeof(init_cb_t), + ha->init_cb, ha->init_cb_dma); +#endif + } + +#ifdef QL_DEBUG_LEVEL_3 + LEAVE("qla2100_mem_free"); +#endif +} + +/* +* qla2100_tgt_alloc +* Allocates a target queue structure. +* +* Input: +* ha = adapter block pointer. +* +* Returns +* target queue structure = success: +* NULL = otherwise +*/ +static inline tgt_t * +qla2100_tgt_alloc(scsi_qla_host_t *ha) { + tgt_t *tgt; + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_tgt_alloc"); +#endif + + tgt = (tgt_t *)KMALLOC(sizeof(tgt_t)); /* Could Sleep here */ + if( tgt != NULL ) { + BZERO(tgt,sizeof(tgt_t)); + DEBUG(sprintf(debug_buff,"Alloc Target @ %08x \n",tgt);) + DEBUG(qla2100_print(debug_buff);) + } + +#ifdef QL_DEBUG_LEVEL_3 + LEAVE("qla2100_tgt_alloc"); +#endif + return(tgt); +} + +/* +* qla2100_lun_alloc +* Allocates a logical device queue structure and lock +* +* Returns: +* SCSI LU structure pointer +*/ +STATIC inline scsi_lu_t * +qla2100_lun_alloc(void) { + scsi_lu_t *q; + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_lun_alloc"); +#endif + + q = (scsi_lu_t *)KMALLOC(sizeof(scsi_lu_t)); /* Sleep */ + BZERO(q,sizeof(struct scsi_lu)); + DEBUG(sprintf(debug_buff,"Alloc Lun @ %08x \n",q);) + DEBUG(qla2100_print(debug_buff);) + +#ifdef QL_DEBUG_LEVEL_3 + LEAVE("qla2100_lun_alloc"); +#endif + return(q); +} + +/* +* qla2100_tgt_dealloc +* Deallocates a target and all logical device queue structures. +* +* Input: +* ha = adapter block pointer. +* tgt = Target queue structure pointer +*/ +static inline void +qla2100_tgt_dealloc(scsi_qla_host_t *ha, tgt_t *tgt) { + uint32_t l; + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_tgt_dealloc"); +#endif + + if( tgt != NULL ) { + /* Insure all LUN memory is released. */ + for( l = 0; l < ha->max_luns; l++ ) { + if( tgt->luns[l] ) + qla2100_lun_dealloc(tgt->luns[l]); + } + KMFREE(tgt, sizeof(tgt_t)); + } + +#ifdef QL_DEBUG_LEVEL_3 + LEAVE("qla2100_tgt_dealloc"); +#endif +} + +/* +* qla2100_lun_dealloc +* Deallocates a logical unit queue structure. +* +* Input: +* q = SCSI LU structure pointer +*/ +static inline void +qla2100_lun_dealloc(scsi_lu_t *q) { +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_lun_dealloc"); +#endif + if( q != NULL ) { + DEBUG(sprintf(debug_buff,"Dealloc Lun @ %08x -- deleted\n",q);) + DEBUG(qla2100_print(debug_buff);) + KMFREE(q, sizeof(scsi_lu_t)); + } +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_lun_dealloc"); +#endif + +} + +/* +* qla2100_abort_queue_single +* Abort all commands on a device queues. +* +* Input: +* ha = adapter block pointer. +*/ +STATIC void qla2100_abort_queue_single(scsi_qla_host_t *ha,uint32_t b,uint32_t t,uint32_t l,uint32_t stat) { + scsi_lu_t *q; + srb_t *sp; + + ENTER("qla2100_abort_queue_single"); + /* dg - 08/23/99 + * We don't want to try and abort queues that don't exists + * (i.e. the device is not configure on the loop ) + */ + if( ha->loop_down_timer > 0 ) { + return; + } + DEBUG5(sprintf(debug_buff,"Abort queue single %2d:%2d:%2d:%2d\n", + ha->host_no,b,t,l);) + DEBUG5(qla2100_print(debug_buff);) + q = (scsi_lu_t * )GET_LU_Q(ha, b, t, l); + while( q != NULL && (sp = q->q_first) != NULL ) { + /* Acquire LU queue specific lock */ + + qla2100_removeq(q, sp); + + /* Release LU queue specific lock */ + CMD_RESULT(sp->cmd) = stat; + qla2100_done_q_put(ha, sp, (srb_t **)&ha->done_q_first, (srb_t **)&ha->done_q_last); + } + LEAVE("qla2100_abort_queue_single"); +} + +/****************************************************************************/ +/* QLogic ISP2100 Hardware Support Functions. */ +/****************************************************************************/ + +/* +* qla2100_initialize_adapter +* Initialize board. +* +* Input: +* ha = adapter block pointer. +* +* Returns: +* 0 = success +*/ +uint8_t +qla2100_initialize_adapter(scsi_qla_host_t *ha) +{ + uint8_t status = QL_STATUS_SUCCESS; + uint8_t isp_init = 0; + uint8_t restart_risc = 0; + uint8_t retry; + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_initialize_adapter"); +#endif + + /* Clear adapter flags. */ + ha->forceLip = 0; + ha->flags.online = FALSE; + ha->flags.isp_abort_needed = FALSE; + ha->flags.disable_host_adapter = FALSE; + ha->flags.loop_resync_active = FALSE; + ha->flags.reset_active = FALSE; + ha->flags.abort_isp_active = FALSE; + ha->flags.watchdog_enabled = FALSE; + ha->loop_down_timer = LOOP_DOWN_TIME; + ha->loop_state = LOOP_DOWN; + ha->flags.start_timer = FALSE; + ha->flags.done_requests_needed = FALSE; + ha->device_flags = 0; + ha->dpc_flags = 0; + ha->sns_retry_cnt = 0; + ha->host_db_ptr = 0; + ha->device_flags = 0; + /* 4.11 */ + ha->flags.managment_server_logged_in = 0; + + /* Allocate host database */ + ha->phost_db = (fcdev_t *)KMALLOC(sizeof(fcdev_t) * MAX_HOST_COUNT); + if (ha->phost_db != NULL) { + BZERO(ha->phost_db, sizeof(fcdev_t) * MAX_HOST_COUNT); + DEBUG(sprintf(debug_buff,"Alloc Host DB success. Max Cnt=%d.", + MAX_HOST_COUNT);) + DEBUG(qla2100_print(debug_buff);) + } else { + status = QL_STATUS_RESOURCE_ERROR; + } + + DEBUG(printk("Configure PCI space for adapter...\n")); + + if ( status == QL_STATUS_SUCCESS && + (status = qla2100_pci_config(ha)) == QL_STATUS_SUCCESS ) { + + qla2100_reset_chip(ha); + + /* Initialize Fibre Channel database. */ + qla2100_init_fc_db(ha); + + /* Initialize target map database. */ + qla2100_init_tgt_map(ha); + if( qla2100_verbose ) + printk(KERN_INFO + "scsi(%d): Configure NVRAM parameters...\n", + (int)ha->host_no); + + if( ha->device_id == QLA2100_DEVICE_ID ) + qla2100_nvram_config(ha); + else + qla2200_nvram_config(ha); + + /* v2.19.12 */ + ha->retry_count = ql2xretrycount; + + if( qla2100_verbose ) + printk(KERN_INFO + "scsi(%d): Verifying loaded RISC code...\n", + (int)ha->host_no); + + qla2100_set_cache_line(ha); + + /* If the user specified a device configuration on + * the command line then use it as the configuration. + * Otherwise, we scan for all devices. + */ + if ( ql2xdevconf ) { + qla2100_get_properties(ha, ql2xdevconf); + } + + retry = 10; + /* + * Try an configure the loop. + */ + do { + DEBUG(qla2100_print("qla2100_initialize_adapter: check " + "if firmware needs to be loaded\n");) + + /* If firmware needs to be loaded */ + if( qla2100_isp_firmware(ha) ) { + if( qla2100_verbose ) + printk(KERN_INFO + "scsi(%d): Verifying chip...\n", + (int)ha->host_no); + + if( (status = qla2100_chip_diag(ha)) == + QL_STATUS_SUCCESS ) + status = qla2100_setup_chip(ha); + + if( status == QL_STATUS_SUCCESS ) + DEBUG(printk("scsi(%d): Chip verified " + "and RISC loaded...\n", + (int)ha->host_no)); + } + + if ( status != QL_STATUS_SUCCESS ) + continue; + + status = qla2100_init_rings(ha); + + if ( status != QL_STATUS_SUCCESS ) + continue; + + /* dg - 7/3/1999 + * Wait for a successful LIP up to a maximum of + * (in seconds): RISC login timeout value, RISC + * retry count value, and port down retry value + * OR a minimum of 4 seconds OR If no cable, + * only 5 seconds. + */ + DEBUG(printk("scsi(%d): qla2100_init_rings OK, " + "call qla2100_fw_ready...\n", + (int)ha->host_no)); + DEBUG(qla2100_print("qla2100_init_rings OK, " + "call qla2100_fw_ready...\n");) + + if ( qla2100_fw_ready(ha) == QL_STATUS_SUCCESS ) { + ha->flags.reset_marker = FALSE; + + /* Go setup flash database devices + * with proper Loop ID's. + */ + do { + ha->flags.loop_resync_needed = FALSE; + status = qla2100_update_fc_db(ha, + FALSE); + } while( !ha->loop_down_timer && + ha->flags.loop_resync_needed ); + + /* If database was full and a device + * was not configured, try and reuse + * the slots. + */ + + if( status == QL_STATUS_FATAL_ERROR ) { + do { + ha->flags.loop_resync_needed = + FALSE; + status = + qla2100_update_fc_db(ha, + TRUE); + } while( !ha->loop_down_timer && + ha->flags.loop_resync_needed ); + } + } + if( ha->flags.update_config_needed ) { + ha->init_cb->additional_firmware_options.connection_options = ha->operating_mode; + restart_risc = 1; + } + isp_init = 1; + + } while( restart_risc && retry-- ); + + if( isp_init ) { + ha->flags.reset_marker = FALSE; + qla2100_marker(ha, 0, 0, 0, MK_SYNC_ALL); + + ha->flags.online = TRUE; + + /* Enable target response to SCSI bus. */ + if( ha->flags.enable_target_mode ) + qla2100_enable_lun(ha); + } + } + +#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3) + if ( status != QL_STATUS_SUCCESS ) + qla2100_print("qla2100_initialize_adapter: **** FAILED ****\n"); +#endif +#ifdef QL_DEBUG_LEVEL_3 + else + LEAVE("qla2100_initialize_adapter"); +#endif + + return(status); +} + +/* +* ISP Firmware Test +* Checks if present version of RISC firmware is older than +* driver firmware. +* +* Input: +* ha = adapter block pointer. +* +* Returns: +* 0 = firmware does not need to be loaded. +*/ +STATIC uint8_t +qla2100_isp_firmware(scsi_qla_host_t *ha) { + uint8_t status; + uint16_t mb[MAILBOX_REGISTER_COUNT]; + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2x00_isp_firmware"); +#endif + + if( ha->flags.disable_risc_code_load ) { + /* Verify checksum of loaded RISC code. */ + mb[0] = MBC_VERIFY_CHECKSUM; + mb[1] = *QLBoardTbl_fc[ha->devnum].fwstart; + if( !(status = qla2100_mailbox_command(ha, BIT_1|BIT_0, &mb[0])) ) { + /* Start firmware execution. */ + mb[0] = MBC_EXECUTE_FIRMWARE; + mb[1] = *QLBoardTbl_fc[ha->devnum].fwstart; + qla2100_mailbox_command(ha, BIT_1|BIT_0, &mb[0]); + } + } else + status = 1; + +#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3) + if( status ) + qla2100_print( + "qla2100_isp_firmware: **** Return status=1; RISC Load Needed ****\n"); +#endif +#ifdef QL_DEBUG_LEVEL_3 + LEAVE("qla2x00_isp_firmware"); +#endif + return(status); +} + +/* +* (08/05/99) +* +* PCI configuration +* Setup device PCI configuration registers. +* +* Input: +* ha = adapter block pointer. +* +* Returns: +* 0 = success. +*/ +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,1,95) +STATIC uint8_t +qla2100_pci_config(scsi_qla_host_t *ha) { + uint8_t status = 1; + uint32_t command; +#if MEMORY_MAPPED_IO + uint32_t page_offset, base; + uint32_t mmapbase; +#endif + config_reg_t *creg = 0; + uint16_t buf_wd; + + ENTER("qla2100_pci_config"); +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,1,95) +/* 4.12 */ + /* turn on PCI master; for system BIOSes that don't turn + it on by default */ + pci_set_master(ha->pdev); + + if (ha->device_id == QLA2300_DEVICE_ID) { + pci_read_config_word(ha->pdev,OFFSET(creg->command), &buf_wd); + buf_wd = buf_wd | + PCI_COMMAND_IO | + PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER | + PCI_COMMAND_INVALIDATE | + PCI_COMMAND_PARITY | + PCI_COMMAND_SERR; + buf_wd = buf_wd & ~PCI_COMMAND_INVALIDATE; + pci_write_config_word(ha->pdev,OFFSET(creg->command), buf_wd); + /* temporary: set upper 32 bits of 64 bit address to 0 */ + buf_wd = 0; + pci_write_config_word(ha->pdev,PCI_BASE_ADDRESS_2, buf_wd); + } +#endif + pci_read_config_word(ha->pdev,OFFSET(creg->revision_id), &buf_wd); + ha->revision = buf_wd; + if( !ha->iobase ) { + /* Get command register. */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18) + if( pci_read_config_word(ha->pdev,OFFSET(creg->command), &buf_wd) == PCIBIOS_SUCCESSFUL ) { +#else + if( pci_read_config_word(ha->pdev,OFFSET(creg->command), &buf_wd) == PCIBIOS_SUCCESSFUL ) { +#endif + command = buf_wd; + /* + * Set Bus Master Enable (bit-2), Memory Address Space Enable and + * reset any error bits. + */ + buf_wd &= ~0x7; +#if MEMORY_MAPPED_IO + DEBUG(printk("qla2100: I/O SPACE and MEMORY MAPPED IO is enabled.\n")); + buf_wd |= BIT_2 + BIT_1 + BIT_0; +#else + DEBUG(printk("qla2100: I/O SPACE Enabled and MEMORY MAPPED IO is disabled.\n")); + buf_wd |= BIT_2 + BIT_0; +#endif + if( pci_write_config_word(ha->pdev,OFFSET(creg->command), buf_wd) ) { + printk(KERN_WARNING "qla2100: Could not write config word.\n"); + } + /* Get expansion ROM address. */ + if( pci_read_config_word(ha->pdev, OFFSET(creg->expansion_rom), &buf_wd) == PCIBIOS_SUCCESSFUL ) { + /* Reset expansion ROM address decode enable. */ + buf_wd &= ~BIT_0; + if( pci_write_config_word(ha->pdev, OFFSET(creg->expansion_rom), buf_wd) == PCIBIOS_SUCCESSFUL ) { +#if MEMORY_MAPPED_IO + /* Get memory mapped I/O address. */ + pcibios_read_config_dword(ha->pci_bus, ha->pci_device_fn,OFFSET(cfgp->mem_base_addr), &mmapbase); + mmapbase &= PCI_BASE_ADDRESS_MEM_MASK; + + /* Find proper memory chunk for memory map I/O reg. */ + base = mmapbase & PAGE_MASK; + page_offset = mmapbase - base; + /* Get virtual address for I/O registers. */ + ha->mmpbase = ioremap(base,page_offset + 256); + if( ha->mmpbase ) { + ha->mmpbase += page_offset; + /* ha->iobase = ha->mmpbase; */ + status = 0; + } +#else /* MEMORY_MAPPED_IO */ + status = 0; +#endif /* MEMORY_MAPPED_IO */ + } + } + } + } else + status = 0; + + + LEAVE("qla2100_pci_config"); + return(status); +} +#else +STATIC uint8_t +qla2100_pci_config(scsi_qla_host_t *ha) { + uint8_t status = 1; + uint32_t command; +#if MEMORY_MAPPED_IO + uint32_t page_offset, base; + uint32_t mmapbase; +#endif + config_reg_t *creg = 0; + uint16_t buf_wd; + + ENTER("qla2100_pci_config"); + + pcibios_read_config_word(ha->pci_bus,ha->pci_device_fn, OFFSET(creg->revision_id), &buf_wd); + ha->revision = buf_wd; + if( !ha->iobase ) { + /* Get command register. */ + if( pcibios_read_config_word(ha->pci_bus,ha->pci_device_fn, OFFSET(creg->command), &buf_wd) == PCIBIOS_SUCCESSFUL ) { + command = buf_wd; + + /* + * Set Bus Master Enable (bit-2), Memory Address Space Enable and + * reset any error bits. + */ + buf_wd &= ~0x7; +#if MEMORY_MAPPED_IO + DEBUG(printk("qla2100: I/O SPACE and MEMORY MAPPED IO is enabled.\n")); + buf_wd |= BIT_2 + BIT_1 + BIT_0; +#else + DEBUG(printk("qla2100: I/O SPACE Enabled and MEMORY MAPPED IO is disabled.\n")); + buf_wd |= BIT_2 + BIT_0; +#endif + if( pcibios_write_config_word(ha->pci_bus,ha->pci_device_fn, OFFSET(creg->command), buf_wd) ) { + printk(KERN_WARNING "qla2100: Could not write config word.\n"); + } + /* Get expansion ROM address. */ + if( pcibios_read_config_word(ha->pci_bus,ha->pci_device_fn, OFFSET(creg->expansion_rom), &buf_wd) == PCIBIOS_SUCCESSFUL ) { + /* Reset expansion ROM address decode enable. */ + buf_wd &= ~BIT_0; + if( pcibios_write_config_word(ha->pci_bus,ha->pci_device_fn, OFFSET(creg->expansion_rom), buf_wd) == PCIBIOS_SUCCESSFUL ) { +#if MEMORY_MAPPED_IO + /* Get memory mapped I/O address. */ + pcibios_read_config_dword(ha->pci_bus, ha->pci_device_fn,OFFSET(cfgp->mem_base_addr), &mmapbase); + mmapbase &= PCI_BASE_ADDRESS_MEM_MASK; + + /* Find proper memory chunk for memory map I/O reg. */ + base = mmapbase & PAGE_MASK; + page_offset = mmapbase - base; + /* Get virtual address for I/O registers. */ + ha->mmpbase = ioremap(base,page_offset + 256); + if( ha->mmpbase ) { + ha->mmpbase += page_offset; + /* ha->iobase = ha->mmpbase; */ + status = 0; + } +#else /* MEMORY_MAPPED_IO */ + status = 0; +#endif /* MEMORY_MAPPED_IO */ + } + } + } + } else + status = 0; + + + LEAVE("qla2100_pci_config"); + return(status); +} +#endif + + +/* +* qla2100_set_cache_line +* Sets PCI cache line parameter. +* +* Input: +* ha = adapter block pointer. +* +* Returns: +* 0 = success. +*/ +STATIC uint8_t +qla2100_set_cache_line(scsi_qla_host_t *ha) { + int status = 0; + uint8_t buf; + config_reg_t *creg = 0; + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_set_cache_line"); +#endif + /* Set the cache line. */ + if( ha->flags.set_cache_line_size_1 ) { + buf = 1; + if( pcibios_write_config_byte(ha->pci_bus, + ha->pci_device_fn, + (u_long)&creg->cache_line,buf) != PCIBIOS_SUCCESSFUL ) + status = 1; + } + +#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3) + if( status ) + qla2100_print("qla2100_set_cache_line: **** FAILED ****\n\r"); +#endif +#ifdef QL_DEBUG_LEVEL_3 + else + LEAVE("qla2100_set_cache_line"); +#endif + return(status); +} + +/* +* Chip diagnostics +* Test chip for proper operation. +* +* Input: +* ha = adapter block pointer. +* +* Returns: +* 0 = success. +*/ +STATIC uint8_t +qla2100_chip_diag(scsi_qla_host_t *ha) { + device_reg_t *reg = ha->iobase; + device2300_reg_t *reg2300 = ha->iobase2300; + uint8_t status = 0; + uint16_t data; + uint32_t cnt; + uint16_t mb[MAILBOX_REGISTER_COUNT]; + + ENTER("qla2100_chip_diag"); +#ifdef QL_DEBUG_LEVEL_3 + qla2100_print("qla2100_chip_diag: testing device at "); + qla2100_output_number((u_long)®->flash_address, 16); + qla2100_print("\n"); +#endif + + /* Reset ISP chip. */ + WRT_REG_WORD(®->ctrl_status, ISP_RESET); + data = qla2100_debounce_register(®->ctrl_status); + for( cnt = 6000000 ; cnt && (data & ISP_RESET); cnt-- ) { + SYS_DELAY(5); + data = RD_REG_WORD(®->ctrl_status); + } + + if( cnt ) { +#if defined(QL_DEBUG_LEVEL_2) + qla2100_print("{{{qla2100_chip_diag: Reset register cleared by chip}}}\n\r"); +#endif + /* Reset RISC processor. */ + WRT_REG_WORD(®->host_cmd, HC_RESET_RISC); + WRT_REG_WORD(®->host_cmd, HC_RELEASE_RISC); + data = qla2100_debounce_register(®->mailbox0); + for( cnt = 6000000; cnt && (data == MBS_BUSY); cnt-- ) { + SYS_DELAY(5); + data = RD_REG_WORD(®->mailbox0); + } + + if( cnt ) { + /* Check product ID of chip */ +#if defined(QL_DEBUG_LEVEL_2) + qla2100_print("{{{qla2100_chip_diag: Checking product ID of chip}}}\n\r"); +#endif + if (ha->device_id != QLA2300_DEVICE_ID) { + if( RD_REG_WORD(®->mailbox1) != PROD_ID_1 || + (RD_REG_WORD(®->mailbox2) != PROD_ID_2 && + RD_REG_WORD(®->mailbox2) != PROD_ID_2a) || + RD_REG_WORD(®->mailbox3) != PROD_ID_3 || + qla2100_debounce_register(®->mailbox4) != PROD_ID_4 ) { + printk(KERN_WARNING "qla2100: [ERROR] Wrong product ID = 0x%x,0x%x,0x%x,0x%x\n", + RD_REG_WORD(®->mailbox1), + RD_REG_WORD(®->mailbox2), + RD_REG_WORD(®->mailbox3), + RD_REG_WORD(®->mailbox4)); + status = 1; + } else { + /* Now determine if we have a 2200A board */ + if( ( ha->device_id == QLA2200_DEVICE_ID || + ha->device_id == QLA2200A_DEVICE_ID ) && + RD_REG_WORD(®->mailbox7) == + QLA2200A_RISC_ROM_VER ) { + ha->device_id = QLA2200A_DEVICE_ID; +#if defined(QL_DEBUG_LEVEL_2) + qla2100_print("qla2100_chip_diag: Found QLA2200A chip.\n\r"); +#endif + } + } + } else { /* check prod id of 2300 here */ + if( RD_REG_WORD(®2300->mailbox1) != PROD_ID_1 || + (RD_REG_WORD(®2300->mailbox2) != PROD_ID_2 && + RD_REG_WORD(®2300->mailbox2) != PROD_ID_2a) || + RD_REG_WORD(®2300->mailbox3) != PROD_ID_3 || + qla2100_debounce_register(®2300->mailbox4) != PROD_ID_4 ) { + printk(KERN_WARNING "qla2300: [ERROR] Wrong product ID = 0x%x,0x%x,0x%x,0x%x\n", + RD_REG_WORD(®2300->mailbox1), + RD_REG_WORD(®2300->mailbox2), + RD_REG_WORD(®2300->mailbox3), + RD_REG_WORD(®2300->mailbox4)); + status = 1; + } + DEBUG(printk("qla2100_chip_diag: Do MBC_MAILBOX_REGISTER_TEST\n")); +#if defined(QL_DEBUG_LEVEL_2) + qla2100_print("qla2100_chip_diag: Do MBC_MAILBOX_REGISTER_TEST\n\r"); +#endif + /* Wrap Incoming Mailboxes Test. */ + mb[0] = MBC_MAILBOX_REGISTER_TEST; + mb[1] = 0xAAAA; + mb[2] = 0x5555; + mb[3] = 0xAA55; + mb[4] = 0x55AA; + mb[5] = 0xA5A5; + mb[6] = 0x5A5A; + mb[7] = 0x2525; + if( !(status = qla2100_mailbox_command(ha, + BIT_7|BIT_6|BIT_5|BIT_4|BIT_3|BIT_2|BIT_1|BIT_0, + &mb[0])) ) { + if( mb[1] != 0xAAAA || mb[2] != 0x5555 || + mb[3] != 0xAA55 || mb[4] != 0x55AA ) + status = 1; + if( mb[5] != 0xA5A5 || mb[6] != 0x5A5A || + mb[7] != 0x2525 ) + status = 1; + if( status ) { + printk(KERN_WARNING "qla2100_chip_diag: [ERROR] *** Failed mailbox register test ***\n\r"); + DEBUG(qla2100_print("qla2100_chip_diag: *** Failed mailbox register test ***\n\r");) + } + } else { + printk(KERN_WARNING "qla2100_chip_diag: [ERROR] failed mailbox send register test\n"); + DEBUG(qla2100_print("qla2100_chip_diag: Failed mailbox send register test\n\r");) + } + } + } else + status = 1; + } else + status = 1; + +#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3) + if( status ) + qla2100_print("qla2100_chip_diag: **** FAILED ****\n"); + else qla2100_print("qla2100_chip_diag: Returning Good Status \n"); +#endif +#ifdef QL_DEBUG_LEVEL_3 + LEAVE("qla2100_chip_diag"); +#endif + return(status); +} + +/* +* Setup chip +* Load and start RISC firmware. +* +* Input: +* ha = adapter block pointer. +* +* Returns: +* 0 = success. +*/ +STATIC uint8_t +qla2100_setup_chip(scsi_qla_host_t *ha) { + uint16_t cnt; + uint16_t risc_address; + uint16_t *risc_code_address; + long risc_code_size; + uint16_t mb[MAILBOX_REGISTER_COUNT]; + uint8_t status = 0; + int num, temp; +#ifdef WORD_FW_LOAD + uint16_t *ql21_risc_code_addr01; + uint16_t ql21_risc_code_length01; + uint8_t dump_status; +#endif + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_setup_chip"); +#endif + + /* Load RISC code. */ + risc_address = *QLBoardTbl_fc[ha->devnum].fwstart; + risc_code_address = QLBoardTbl_fc[ha->devnum].fwcode; + risc_code_size = (long)(*QLBoardTbl_fc[ha->devnum].fwlen & 0xffff); + + DEBUG(printk("qla2100_setup_chip: Loading RISC code size =(0x%lx)\n",risc_code_size);) + DEBUG(qla2100_print("qla2100_setup_chip: Loading RISC code now in silent mode!\n\r");) + num = 0; + DEBUG(sprintf(debug_buff,"virt=%x phys=%x\n\r",ha->request_ring,ha->request_dma);) + DEBUG(qla2100_print(debug_buff);) + /* go into silent mode */ + temp = ql2x_debug_print; + if( ql2x_debug_print ) ql2x_debug_print = 0; + + while( risc_code_size > 0 && !status ) { + /* for 2200A set transfer size to 128 bytes */ + if( ha->device_id == QLA2200A_DEVICE_ID ) + cnt = 128 >> 1; + else + cnt = REQUEST_ENTRY_SIZE * REQUEST_ENTRY_CNT >> 1; + if( cnt > risc_code_size ) + cnt = risc_code_size; + + DEBUG(sprintf(debug_buff,"qla2100_setup_chip:loading risc segment@ addr 0x%x, number of bytes 0x%x, offset 0x%x.\n\r",risc_code_address,cnt,risc_address);) + DEBUG(qla2100_print(debug_buff);) + + BCOPY((caddr_t) risc_code_address,(caddr_t) ha->request_ring, (cnt <<1)); + + flush_cache_all(); /* flush written firmware to the + ha->request_ring buffer before DMA */ + + mb[0] = MBC_LOAD_RAM; + mb[1] = risc_address; + mb[3] = (uint16_t)(ha->request_dma & 0xffff); + mb[2] = (uint16_t)((ha->request_dma >> 16) & 0xffff); + mb[4] = cnt; + status = qla2100_mailbox_command(ha, BIT_4|BIT_3|BIT_2|BIT_1|BIT_0, + &mb[0]); + + if( status ) { + qla2100_dump_regs(ha->host); + printk(KERN_WARNING "qla2x00: [ERROR] Failed to load segment %d of FW\n",num); + DEBUG(qla2100_print("qla2100_setup_chip: Failed to load segment of FW\n");) + break; + } + risc_address += cnt; + risc_code_size -= cnt; + risc_code_address += cnt; + num++; + } + ql2x_debug_print = temp; + +#ifdef WORD_FW_LOAD + { + int i; + uint8_t temp; + + temp = ql2x_debug_print; + if( ql2x_debug_print ) ql2x_debug_print = 0; + risc_address = *QLBoardTbl_fc[ha->devnum].fwstart; + ql21_risc_code_addr01 = QLBoardTbl_fc[ha->devnum].fwcode; + ql21_risc_code_length01= (long)(*QLBoardTbl_fc[ha->devnum].fwlen & 0xffff); + + for( i = 0; i < ql21_risc_code_length01 ; i++ ) { + + mb[0] = MBC_WRITE_RAM_WORD; + mb[1] = risc_address + i; + mb[2] = *(ql21_risc_code_addr01 + i); + + dump_status = qla2100_mailbox_command(ha,BIT_2|BIT_1|BIT_0, + &mb[0]); + if( dump_status ) { + printk(KERN_WARNING "qla2x00 : [ERROR] firmware load failure\n"); + break; + } + + mb[0] = MBC_READ_RAM_WORD; + mb[1] = risc_address + i; + mb[2] = 0; + + dump_status = qla2100_mailbox_command(ha,BIT_2|BIT_1|BIT_0, + &mb[0]); + if( dump_status ) { + printk(KERN_WARNING "qla2x00: [ERROR] RISC FW Read Failure\n"); + break; + } + if( mb[2] != *(ql21_risc_code_addr01 + i) ) + printk(KERN_WARNING "qla2x00: [ERROR] RISC FW Compare ERROR @ (0x%p)\n", + (void *) (ql21_risc_code_addr01+i)); + } + ql2x_debug_print = temp; + printk(KERN_INFO "qla2x00: RISC FW download confirmed... \n"); + } +#endif + /* Verify checksum of loaded RISC code. */ + if( !status ) { + DEBUG(printk("qla2100_setup_chip: Verifying Check Sum of loaded RISC code.\n");) + mb[0] = MBC_VERIFY_CHECKSUM; + mb[1] = *QLBoardTbl_fc[ha->devnum].fwstart; + if( !(status = qla2100_mailbox_command(ha, BIT_1|BIT_0, &mb[0])) ) { + /* Start firmware execution. */ + DEBUG(qla2100_print("qla2100_setup_chip: CS Ok, Start firmware running\n\r");) + mb[0] = MBC_EXECUTE_FIRMWARE; + mb[1]= *QLBoardTbl_fc[ha->devnum].fwstart; + status = qla2100_mailbox_command(ha, BIT_1|BIT_0, &mb[0]); + } +#if defined(QL_DEBUG_LEVEL_2) + else + qla2100_print("qla2100_setup_chip: ISP FW Failed Check Sum\n"); +#endif + } + +#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3) + if( status ) + qla2100_print("qla2100_setup_chip: **** FAILED ****\n"); + else qla2100_print("qla2100_setup_chip: Returning Good Status\n"); +#endif +#ifdef QL_DEBUG_LEVEL_3 + LEAVE("qla2100_setup_chip"); +#endif + return(status); +} + +/* +* qla2100_init_rings +* Initializes firmware. +* +* Beginning of request ring has initialization control block +* already built by nvram config routine. +* +* Input: +* ha = adapter block pointer. +* ha->request_ring = request ring virtual address +* ha->response_ring = response ring virtual address +* ha->request_dma = request ring physical address +* ha->response_dma = response ring physical address +* +* Returns: +* 0 = success. +*/ +STATIC uint8_t +qla2100_init_rings(scsi_qla_host_t *ha) { + uint8_t status; + uint16_t mb[MAILBOX_REGISTER_COUNT]; + int cnt; + device2300_reg_t *reg2300 = ha->iobase2300; + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_init_rings"); +#endif + /* Clear outstanding commands array. */ + for( cnt = 0; cnt < MAX_OUTSTANDING_COMMANDS; cnt++ ) + ha->outstanding_cmds[cnt] = 0; + +#ifdef RSCN + /* Clear RSCN queue. */ + ha->rscn_in_ptr = 0; + ha->rscn_out_ptr = 0; +#endif + + /* Initialize firmware. */ + ha->request_ring_ptr = ha->request_ring; + ha->req_ring_index = 0; + ha->req_q_cnt = REQUEST_ENTRY_CNT; + ha->response_ring_ptr = ha->response_ring; + ha->rsp_ring_index = 0; + mb[0] = MBC_INITIALIZE_FIRMWARE; + mb[3] = LSW(ha->init_cb_dma); + mb[2] = MSW(ha->init_cb_dma); + mb[4] = 0; /* set request queue in ptr for 2100/2200 */ + mb[5] = 0; /* set response queue out ptr for 2100/2200*/ + mb[7] = QL21_64BITS_3RDWD(ha->init_cb_dma); + mb[6] = QL21_64BITS_4THWD(ha->init_cb_dma); + + if (ha->device_id == QLA2300_DEVICE_ID) { + /* set request queue in ptr , response queue out ptr for 2300 */ + WRT_REG_WORD(®2300->req_q_in, 0); + WRT_REG_WORD(®2300->rsp_q_out, 0); + } + + DEBUG(qla2100_print("qla2100_init_rings: Issue MBC_INIT_FIRMWARE op\n");) + status = qla2100_mailbox_command(ha, + BIT_7|BIT_6|BIT_5|BIT_4|BIT_3|BIT_2|BIT_0, + &mb[0]); + +#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3) + if( status ) + qla2100_print("qla2100_init_rings: **** FAILED ****\n"); +#endif +#ifdef QL_DEBUG_LEVEL_3 + LEAVE("qla2100_init_rings"); +#endif + return(status); +} + +/* +* qla2100_fw_ready +* Waits for firmware ready. +* +* Input: +* ha = adapter block pointer. +* +* Returns: +* 0 = success. +*/ +STATIC uint8_t +qla2100_fw_ready(scsi_qla_host_t *ha) { + uint8_t status = 0; + uint32_t cnt, cnt1; + uint16_t mb[MAILBOX_REGISTER_COUNT]; + uint16_t timeout; + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_fw_ready"); +#endif + timeout = (ha->retry_count * ha->login_timeout) + 5; + cnt1 = 0x350; /* 25 secs */ + /* Wait for ISP to finish LIP */ + if(!qla2100_quiet) printk(KERN_INFO "scsi(%d): Waiting for LIP to complete...\n", (int)ha->host->host_no); + if( timeout ) + cnt = 36 * timeout; + else + cnt = 0x700; + + for( ; cnt; cnt-- ) { + mb[0] = MBC_GET_FIRMWARE_STATE; + if( !(status = qla2100_mailbox_command(ha, BIT_0, &mb[0])) ) { + if( ha->loop_down_timer || mb[1] != FSTATE_READY ) { + status = 1; + /* Exit if no cable connected after 10 seconds. */ + if( !cnt1-- ) + if( mb[1] == FSTATE_CONFIG_WAIT || mb[1] == FSTATE_LOSS_OF_SYNC ) { + + break; + } + } else { + DEBUG(printk("qla2100_fw_ready: F/W Ready - OK \n");) + status = 0; /* dg 09/15/99 */ + break; + } + } + + if( ha->flags.online ) { + status = 0; /* dg 09/15/99 */ + break; + } + + /* Delay for a while */ + udelay(10); + +#ifdef QL_DEBUG_LEVEL_2 +/* qla2100_print("qla2100_fw_ready: mailbox_out[1] = "); + qla2100_output_number((uint32_t)mb[1], 16); + qla2100_print("\n");*/ +#endif + } + +#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3) + if( status ) + qla2100_print("qla2100_fw_ready: **** FAILED ****\n"); +#endif +#ifdef QL_DEBUG_LEVEL_3 + else + LEAVE("qla2100_fw_ready"); +#endif + return(status); +} + +/* +* qla2100_configure_hba +* Setup adapter context. +* +* Input: +* ha = adapter state pointer. +* +* Returns: +* 0 = success +* 1 = failed +* +* Context: +* Kernel context. +*/ +STATIC uint8_t +qla2100_configure_hba(scsi_qla_host_t *ha) { + uint8_t rval; + uint16_t mb[MAILBOX_REGISTER_COUNT]; + uint8_t connect_type[22]; + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_configure_hba"); +#endif + + /* Get host addresses. */ + mb[0] = MBC_GET_ADAPTER_LOOP_ID; + rval = qla2100_mailbox_command(ha, BIT_0, &mb[0]); + if( !rval ) { + if( mb[6] == 4 ) { + printk(KERN_INFO "scsi%d: Can't get topology - retrying\n",(int)ha->host_no); + return(1); + } + ha->loop_id = mb[1]; + + /* Get loop topology. */ + if( ha->device_id == QLA2100_DEVICE_ID ) { + mb[6] = 0; + } + ha->min_external_loopid = SNS_FIRST_LOOP_ID; + ha->operating_mode = LOOP; + switch( mb[6] ) { + case 0: + ha->current_topology = ISP_CFG_NL; + strcpy((char *)&connect_type[0],"(Loop)"); + break; + case 1: + ha->current_topology = ISP_CFG_FL; + strcpy((char *)&connect_type[0],"(FL_Port)"); + break; + case 2: + ha->operating_mode = P2P; + ha->current_topology = ISP_CFG_N; + ha->min_external_loopid = 1; /* v2.19.5b3 */ + strcpy((char *)&connect_type[0],"(N_Port-to-N_Port)"); + break; + case 3: + ha->operating_mode = P2P; + ha->current_topology = ISP_CFG_F; + ha->min_external_loopid = 1; /* v2.19.5b3 */ + strcpy((char *)&connect_type[0],"(F_Port)"); + break; + default: + ha->current_topology = ISP_CFG_NL; + strcpy((char *)&connect_type[0],"(Loop)"); + break; + } + + /* Save Host port and loop ID. */ + /* Reverse byte order - TT */ + ha->port_id[2] = LSB(mb[2]); + ha->port_id[1] = MSB(mb[2]); + ha->port_id[0] = LSB(mb[3]); + if (!qla2100_quiet) printk(KERN_INFO "scsi%d: Topology - %s, Host Loop address 0x%x\n",(int)ha->host_no,connect_type, ha->loop_id); + } else + printk(KERN_WARNING "qla2100_configure_hba: [ERROR] Get host loop ID failed\n"); + +#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3) + if( rval != 0 ) + qla2100_print("qla2100_configure_hba: **** FAILED ****\n"); +#endif +#ifdef QL_DEBUG_LEVEL_3 + else + LEAVE("qla2100_configure_hba"); +#endif + return(rval); +} + +/* +* NVRAM configuration for 2100. +* +* Input: +* ha = adapter block pointer. +* ha->request_ring = request ring virtual address +* ha->response_ring = response ring virtual address +* ha->request_dma = request ring physical address +* ha->response_dma = response ring physical address +* +* Output: +* initialization control block in response_ring +* host adapters parameters in host adapter block +* +* Returns: +* 0 = success. +*/ +STATIC uint8_t +qla2100_nvram_config(scsi_qla_host_t *ha) { + uint8_t status = 0; + uint16_t cnt; + caddr_t dptr1, dptr2; + init_cb_t *icb = ha->init_cb; + nvram21_t *nv = (nvram21_t *)ha->request_ring; + uint16_t *wptr = (uint16_t *)ha->request_ring; + uint8_t chksum = 0; + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_nvram_config"); +#endif + + /* Verify valid NVRAM checksum. */ + for( cnt = 0; cnt < sizeof(nvram21_t)/2; cnt++ ) { + *wptr = qla2100_get_nvram_word(ha, cnt); + chksum += (uint8_t)*wptr; + chksum += (uint8_t)(*wptr >> 8); + wptr++; + } + +#if DEBUG_PRINT_NVRAM + qla2100_print( + "qla2100_nvram_config: Contents of NVRAM "); + qla2100_print("\n\r"); + qla2100_dump_buffer((uint8_t *)ha->request_ring, sizeof(nvram21_t)); +#endif + + /* Bad NVRAM data, set defaults parameters. */ + if( chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P' || + nv->id[3] != ' ' || nv->nvram_version < 1 ) { + /* Reset NVRAM data. */ + DEBUG(printk("Using defaults for NVRAM: \n")); + DEBUG(printk("checksum=0x%x, Id=%c, version=0x%x\n",chksum,nv->id[0],nv->nvram_version)); + wptr = (uint16_t *)ha->request_ring; + for( cnt = 0; cnt < sizeof(nvram21_t)/2; cnt++ ) + *wptr++ = 0; + + /* + * Set default initialization control block. + */ + nv->parameter_block_version = ICB_VERSION; + nv->firmware_options.enable_fairness = 1; + nv->firmware_options.enable_fast_posting = 1; + nv->firmware_options.enable_full_login_on_lip = 1; + + nv->frame_payload_size = 1024; + nv->max_iocb_allocation = 256; + nv->execution_throttle = 16; + nv->retry_count = 8; + nv->retry_delay = 1; + nv->node_name[0] = 32; + nv->node_name[3] = 224; + nv->node_name[4] = 139; + nv->login_timeout = 4; + + /* + * Set default host adapter parameters + */ + nv->host_p.enable_lip_full_login = 1; + nv->reset_delay = 5; + nv->port_down_retry_count = 8; + nv->maximum_luns_per_target = 8; + status = 1; + } + + /* + * Copy over NVRAM RISC parameter block + * to initialization control block. + */ + dptr1 = (caddr_t)icb; + dptr2 = (caddr_t)&nv->parameter_block_version; + cnt = (caddr_t)&nv->host_p - (caddr_t)&nv->parameter_block_version; + while( cnt-- ) + *dptr1++ = *dptr2++; + + /* HBA node name 0 correction */ + for (cnt=0 ; cnt<8 ; cnt++) { + if (icb->node_name[cnt] != 0) + break; + } + if (cnt == 8) { + for ( cnt= 0 ; cnt < 8 ; cnt++) + icb->node_name[cnt] = icb->port_name[cnt]; + icb->node_name[0] = icb->node_name[0] & ~BIT_0; + icb->port_name[0] = icb->port_name[0] | BIT_0; + } + + /* + * Setup driver firmware options. + */ +#if QL2100_TARGET_MODE_SUPPORT + icb->firmware_options.enable_target_mode = 1; +#else + icb->firmware_options.enable_target_mode = 0; +#endif + icb->firmware_options.disable_initiator_mode = 0; + icb->firmware_options.enable_port_update_event = 1; + icb->firmware_options.enable_full_login_on_lip = 1; + + /* + * Set host adapter parameters + */ + ha->flags.enable_target_mode = icb->firmware_options.enable_target_mode; + ha->flags.disable_luns = nv->host_p.disable_luns; + ha->flags.disable_risc_code_load = nv->host_p.disable_risc_code_load; + ha->flags.set_cache_line_size_1 = nv->host_p.set_cache_line_size_1; + ha->flags.enable_64bit_addressing = nv->host_p.enable_64bit_addressing; + +#if BITS_PER_LONG > 32 + /* Enable 64bit addressing for OS/System combination supporting it */ + /* actual NVRAM bit is: nv->cntr_flags_1.enable_64bit_addressing */ + /* but we will ignore it and use BITS_PER_LONG macro to setup for */ + /* 64 or 32 bit access of host memory in all x86/ia-64/Alpha systems */ + ha->flags.enable_64bit_addressing = 1; +#else + ha->flags.enable_64bit_addressing = 0; +#endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,18) + if (ha->flags.enable_64bit_addressing) + printk(KERN_INFO "[[[ qla2x00: 64 Bit PCI Addressing Enabled ]]]\n"); + +#if BITS_PER_LONG > 32 + /* Update our PCI device dma_mask for full 64 bit mask */ + /* ha->pdev->dma_mask = (pci_dma_t) 0xffffffffffffffffull; */ + ha->pdev->dma_mask = 0xffffffffffffffff; +#endif +#endif + ha->flags.enable_lip_reset = nv->host_p.enable_lip_reset; + ha->flags.enable_lip_full_login = nv->host_p.enable_lip_full_login; + ha->flags.enable_target_reset = nv->host_p.enable_target_reset; + ha->flags.enable_flash_db_update = nv->host_p.enable_database_storage; + + /* new for IOCTL support of APIs */ + ha->node_name[0] = icb->node_name[0]; + ha->node_name[1] = icb->node_name[1]; + ha->node_name[2] = icb->node_name[2]; + ha->node_name[3] = icb->node_name[3]; + ha->node_name[4] = icb->node_name[4]; + ha->node_name[5] = icb->node_name[5]; + ha->node_name[6] = icb->node_name[6]; + ha->node_name[7] = icb->node_name[7]; + ha->nvram_version = nv->nvram_version; + + /* empty data for QLA2100s OEM stuff */ + ha->oem_id = 0; + ha->oem_spare0 = 0; + for ( cnt= 0 ; cnt < 8 ; cnt++) { + ha->oem_string[cnt] = 0; + ha->oem_part[cnt] = 0; + ha->oem_fru[cnt] = 0; + ha->oem_ec[cnt] = 0; + } + + ha->hiwat = icb->iocb_allocation; + ha->execution_throttle = nv->execution_throttle; + + ha->retry_count = nv->retry_count; + ha->login_timeout = nv->login_timeout; + /* Set minimum login_timeout to 4 seconds. */ + if( ha->login_timeout < 4 ) + ha->login_timeout = 4; + ha->port_down_retry_count = nv->port_down_retry_count; + ha->minimum_timeout = (ha->login_timeout * ha->retry_count) + + ha->port_down_retry_count; + ha->loop_reset_delay = nv->reset_delay; + /* Will get the value from nvram. */ + ha->loop_down_timeout = LOOP_DOWN_TIMEOUT; + ha->loop_down_abort_time = LOOP_DOWN_TIME - ha->loop_down_timeout; + + /* save HBA serial number */ + ha->serial0 = nv->node_name[5]; + ha->serial1 = nv->node_name[6]; + ha->serial2 = nv->node_name[7]; + +#if USE_BIOS_MAX_LUNS + if( !nv->maximum_luns_per_target ) + ha->max_luns = MAX_LUNS-1; + else + ha->max_luns = nv->maximum_luns_per_target; +#else + ha->max_luns = MAX_LUNS-1; +#endif + + /* + * Setup ring parameters in initialization control block + */ + icb->request_q_outpointer = 0; + icb->response_q_inpointer = 0; + icb->request_q_length = REQUEST_ENTRY_CNT; + icb->response_q_length = RESPONSE_ENTRY_CNT; + icb->request_q_address[0] = LS_64BITS(ha->request_dma); + icb->request_q_address[1] = MS_64BITS(ha->request_dma); + icb->response_q_address[0] = LS_64BITS(ha->response_dma); + icb->response_q_address[1] = MS_64BITS(ha->response_dma); + +#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3) + if( status ) + qla2100_print("qla2100_nvram_config: **** FAILED ****\n"); +#endif +#ifdef QL_DEBUG_LEVEL_3 + else + LEAVE("qla2100_nvram_config"); +#endif + return(status); +} + +/* +* NVRAM configuration for the 2200. +* +* Input: +* ha = adapter block pointer. +* ha->request_ring = request ring virtual address +* ha->response_ring = response ring virtual address +* ha->request_dma = request ring physical address +* ha->response_dma = response ring physical address +* +* Output: +* initialization control block in response_ring +* host adapters parameters in host adapter block +* +* Returns: +* 0 = success. +*/ +STATIC uint8_t +qla2200_nvram_config(scsi_qla_host_t *ha) { + uint8_t status = 0; + uint16_t cnt; + caddr_t dptr1, dptr2; + init_cb_t *icb = ha->init_cb; + nvram22_t *nv = (nvram22_t *)ha->request_ring; + uint16_t *wptr = (uint16_t *)ha->request_ring; + uint8_t chksum = 0; + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2200/2300_nvram_config"); +#endif + + if( !ha->flags.nvram_config_done ) { + + /* Verify valid NVRAM checksum. */ + for( cnt = 0; cnt < sizeof(nvram22_t)/2; cnt++ ) { + *wptr = qla2100_get_nvram_word(ha, cnt); + chksum += (uint8_t)*wptr; + chksum += (uint8_t)(*wptr >> 8); + wptr++; + } + +#if DEBUG_PRINT_NVRAM + qla2100_print( + "qla2200_nvram_config: Contents of NVRAM "); + qla2100_print("\n\r"); + qla2100_dump_buffer((uint8_t *)ha->request_ring, sizeof(nvram22_t)); +#endif + + /* Bad NVRAM data, set defaults parameters. */ + if( chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P' || + nv->id[3] != ' ' || nv->nvram_version < 1 ) { + /* Reset NVRAM data. */ + DEBUG(printk("Using defaults for 2200/2300 NVRAM: \n")); + DEBUG(printk("checksum=0x%x, Id0=%c Id1=%c Id2=%x, version=0x%x\n",chksum,nv->id[0],nv->id[1],nv->id[2],nv->nvram_version)); + wptr = (uint16_t *)nv; + for( cnt = 0; cnt < sizeof(nvram21_t)/2; cnt++ ) + *wptr++ = 0; + + /* + * Set default initialization control block. + */ + nv->parameter_block_version = ICB_VERSION; + nv->firmware_options.enable_fairness = 1; + nv->firmware_options.enable_fast_posting = 1; + nv->firmware_options.enable_full_login_on_lip = 1; + nv->firmware_options.enable_name_change = 1; + nv->firmware_options.expanded_ifwcb = 1; + + nv->frame_payload_size = 1024; + nv->max_iocb_allocation = 256; + nv->execution_throttle = 16; + nv->retry_count = 8; + nv->retry_delay = 1; + nv->port_name[0] = 32; + nv->port_name[3] = 224; + nv->port_name[4] = 139; + nv->login_timeout = 4; + nv->additional_firmware_options.connection_options = P2P_LOOP; + /* + * Set default host adapter parameters + */ + nv->host_p.enable_lip_full_login = 1; + nv->reset_delay = 5; + nv->port_down_retry_count = 8; + nv->maximum_luns_per_target = 8; + status = 1; + } + + /* Reset icb data */ + BZERO((caddr_t)icb, sizeof(init_cb_t)); + /* + * Copy over NVRAM RISC parameter block + * to initialization control block. + */ + dptr1 = (caddr_t)icb; + dptr2 = (caddr_t)&nv->parameter_block_version; + cnt = (caddr_t)&nv->additional_firmware_options - (caddr_t)&nv->parameter_block_version; + while( cnt-- ) + *dptr1++ = *dptr2++; + + dptr1 += (caddr_t)&icb->additional_firmware_options - (caddr_t)&icb->request_q_outpointer; + cnt = (caddr_t)&nv->host_p - (caddr_t)&nv->additional_firmware_options; + while( cnt-- ) + *dptr1++ = *dptr2++; + + /* HBA node name 0 correction */ + for (cnt=0 ; cnt<8 ; cnt++) { + if (icb->node_name[cnt] != 0) + break; + } + if (cnt == 8) { + for ( cnt= 0 ; cnt < 8 ; cnt++) + icb->node_name[cnt] = icb->port_name[cnt]; + icb->node_name[0] = icb->node_name[0] & ~BIT_0; + icb->port_name[0] = icb->port_name[0] | BIT_0; + } + + /* + * Setup driver firmware options. + */ + icb->firmware_options.enable_full_duplex = 0; +#if QL2100_TARGET_MODE_SUPPORT + icb->firmware_options.enable_target_mode = 1; +#else + icb->firmware_options.enable_target_mode = 0; +#endif + icb->firmware_options.disable_initiator_mode = 0; + icb->firmware_options.enable_port_update_event = 1; + icb->firmware_options.enable_full_login_on_lip = 1; +#if USE_TP_FW + icb->firmware_options.enable_name_change = 1; + icb->firmware_options.expanded_ifwcb = 1; +#endif + /* + * Set host adapter parameters + */ + ha->flags.enable_target_mode = icb->firmware_options.enable_target_mode; + ha->flags.disable_luns = nv->host_p.disable_luns; + ha->flags.disable_risc_code_load = nv->host_p.disable_risc_code_load; + ha->flags.set_cache_line_size_1 = nv->host_p.set_cache_line_size_1; + ha->flags.enable_64bit_addressing = nv->host_p.enable_64bit_addressing; + +#if BITS_PER_LONG > 32 + /* Enable 64bit addressing for OS/System combination supporting it */ + /* actual NVRAM bit is: nv->cntr_flags_1.enable_64bit_addressing */ + /* but we will ignore it and use BITS_PER_LONG macro to setup for */ + /* 64 or 32 bit access of host memory in all x86/ia-64/Alpha systems */ + ha->flags.enable_64bit_addressing = 1; +#else + ha->flags.enable_64bit_addressing = 0; +#endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,18) + if (ha->flags.enable_64bit_addressing) + printk(KERN_INFO "[[[ qla2x00: 64 Bit PCI Addressing Enabled ]]]\n"); + +#if BITS_PER_LONG > 32 + /* Update our PCI device dma_mask for full 64 bit mask */ + ha->pdev->dma_mask = 0xffffffffffffffff; +#endif +#endif + ha->flags.enable_lip_reset = nv->host_p.enable_lip_reset; + ha->flags.enable_lip_full_login = nv->host_p.enable_lip_full_login; + ha->flags.enable_target_reset = nv->host_p.enable_target_reset; + ha->flags.enable_flash_db_update = nv->host_p.enable_database_storage; + ha->operating_mode = icb->additional_firmware_options.connection_options; + + /* new for IOCTL support of APIs */ + ha->node_name[0] = icb->node_name[0]; + ha->node_name[1] = icb->node_name[1]; + ha->node_name[2] = icb->node_name[2]; + ha->node_name[3] = icb->node_name[3]; + ha->node_name[4] = icb->node_name[4]; + ha->node_name[5] = icb->node_name[5]; + ha->node_name[6] = icb->node_name[6]; + ha->node_name[7] = icb->node_name[7]; + ha->nvram_version = nv->nvram_version; + + + ha->hiwat = icb->iocb_allocation; + ha->execution_throttle = nv->execution_throttle; + + ha->retry_count = nv->retry_count; + ha->login_timeout = nv->login_timeout; + /* Set minimum login_timeout to 4 seconds. */ + if( ha->login_timeout < 4 ) + ha->login_timeout = 4; + ha->port_down_retry_count = nv->port_down_retry_count; + ha->minimum_timeout = (ha->login_timeout * ha->retry_count) + + ha->port_down_retry_count; + ha->loop_reset_delay = nv->reset_delay; + /* Will get the value from nvram. */ + ha->loop_down_timeout = LOOP_DOWN_TIMEOUT; + ha->loop_down_abort_time = LOOP_DOWN_TIME - ha->loop_down_timeout; + + /* save HBA serial number */ + ha->serial0 = nv->port_name[5]; + ha->serial1 = nv->port_name[6]; + ha->serial2 = nv->port_name[7]; + + /* save OEM related items for QLA2200s and QLA2300s */ + ha->oem_id = nv->oem_id; + ha->oem_spare0 = nv->oem_spare0; + + for ( cnt= 2 ; cnt < 8 ; cnt++ ) + ha->oem_string[cnt] = nv->oem_string[cnt]; + + for ( cnt= 0 ; cnt < 8 ; cnt++ ) { + ha->oem_part[cnt] = nv->oem_part[cnt]; + ha->oem_fru[cnt] = nv->oem_fru[cnt]; + ha->oem_ec[cnt] = nv->oem_ec[cnt]; + } + +#ifdef FC_IP_SUPPORT + for (cnt = 0; cnt < 8; cnt++) + ha->acPortName[cnt] = nv->port_name[cnt]; +#endif + +#if USE_BIOS_MAX_LUNS + if( !nv->maximum_luns_per_target ) + ha->max_luns = MAX_LUNS; + else if( nv->maximum_luns_per_target < MAX_LUNS ) + ha->max_luns = nv->maximum_luns_per_target; + else + ha->max_luns = MAX_LUNS; +#else + ha->max_luns = MAX_LUNS; +#endif + + /* + * Setup ring parameters in initialization control block + */ + icb->request_q_outpointer = 0; + icb->response_q_inpointer = 0; + icb->request_q_length = REQUEST_ENTRY_CNT; + icb->response_q_length = RESPONSE_ENTRY_CNT; + icb->request_q_address[0] = LS_64BITS(ha->request_dma); + icb->request_q_address[1] = MS_64BITS(ha->request_dma); + icb->response_q_address[0] = LS_64BITS(ha->response_dma); + icb->response_q_address[1] = MS_64BITS(ha->response_dma); + + icb->lun_enables = 0; + icb->command_resource_count = 0; + icb->immediate_notify_resource_count = 0; + icb->timeout = 0; + icb->reserved_2 = 0; + + ha->flags.nvram_config_done = 1; + } + +#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3) + if( status ) + qla2100_print("qla2200_nvram_config: **** FAILED ****\n"); +#endif +#ifdef QL_DEBUG_LEVEL_3 + else + LEAVE("qla2200_nvram_config"); +#endif + return(status); +} + +/* +* Get NVRAM data word +* Calculates word position in NVRAM and calls request routine to +* get the word from NVRAM. +* +* Input: +* ha = adapter block pointer. +* address = NVRAM word address. +* +* Returns: +* data word. +*/ +STATIC uint16_t +qla2100_get_nvram_word(scsi_qla_host_t *ha, uint32_t address) { + uint32_t nv_cmd; + uint16_t data; + +#ifdef QL_DEBUG_ROUTINES + uint8_t saved_print_status = ql2x_debug_print; +#endif +#ifdef QL_DEBUG_LEVEL_4 + qla2100_print("qla2100_get_nvram_word: entered\n"); +#endif + + nv_cmd = address << 16; + nv_cmd |= NV_READ_OP; + +#ifdef QL_DEBUG_ROUTINES + ql2x_debug_print = FALSE; +#endif + data = qla2100_nvram_request(ha, nv_cmd); +#ifdef QL_DEBUG_ROUTINES + ql2x_debug_print = saved_print_status; +#endif + +#ifdef QL_DEBUG_LEVEL_4 + qla2100_print("qla2100_get_nvram_word: exiting normally NVRAM data = "); + qla2100_output_number((u_long)data, 16); + qla2100_print("\n"); +#endif + return(data); +} + +/* +* NVRAM request +* Sends read command to NVRAM and gets data from NVRAM. +* +* Input: +* ha = adapter block pointer. +* nv_cmd = Bit 26 = start bit +* Bit 25, 24 = opcode +* Bit 23-16 = address +* Bit 15-0 = write data +* +* Returns: +* data word. +*/ +STATIC uint16_t +qla2100_nvram_request(scsi_qla_host_t *ha, uint32_t nv_cmd) { + uint8_t cnt; + device_reg_t *reg = ha->iobase; + uint16_t data = 0; + uint16_t reg_data; + + /* Send command to NVRAM. */ + + nv_cmd <<= 5; + for( cnt = 0; cnt < 11; cnt++ ) { + if( nv_cmd & BIT_31 ) + qla2100_nv_write(ha, NV_DATA_OUT); + else + qla2100_nv_write(ha, 0); + nv_cmd <<= 1; + } + + /* Read data from NVRAM. */ + + for( cnt = 0; cnt < 16; cnt++ ) { + WRT_REG_WORD(®->nvram, NV_SELECT+NV_CLOCK); + /* qla2100_nv_delay(ha); */ + NVRAM_DELAY(); + data <<= 1; + reg_data = RD_REG_WORD(®->nvram); + if( reg_data & NV_DATA_IN ) + data |= BIT_0; + WRT_REG_WORD(®->nvram, NV_SELECT); + /* qla2100_nv_delay(ha); */ + NVRAM_DELAY(); + } + + /* Deselect chip. */ + + WRT_REG_WORD(®->nvram, NV_DESELECT); + /* qla2100_nv_delay(ha); */ + NVRAM_DELAY(); + + return(data); +} + +STATIC void +qla2100_nv_write(scsi_qla_host_t *ha, uint16_t data) { + device_reg_t *reg = ha->iobase; + + WRT_REG_WORD(®->nvram, data | NV_SELECT); + NVRAM_DELAY(); + /* qla2100_nv_delay(ha); */ + WRT_REG_WORD(®->nvram, data | NV_SELECT | NV_CLOCK); + /* qla2100_nv_delay(ha); */ + NVRAM_DELAY(); + WRT_REG_WORD(®->nvram, data | NV_SELECT); + /* qla2100_nv_delay(ha); */ + NVRAM_DELAY(); +} + +STATIC void +qla2100_nv_delay(void) { + SYS_DELAY(NV_DELAY_COUNT); +} + + +/* +* Mailbox Command +* Issue mailbox command and waits for completion. +* +* Input: +* ha = adapter block pointer. +* mr = mailbox registers to load. +* mb = data pointer for mailbox registers. +* +* Output: +* mb[MAILBOX_REGISTER_COUNT] = returned mailbox data. +* +* Returns: +* 0 = success +* 1 = failed (mbox status != 0x4000) +*/ +STATIC uint8_t +qla2100_mailbox_command(scsi_qla_host_t *ha, uint32_t mr, uint16_t *mb) { + device_reg_t *reg = ha->iobase; + device2300_reg_t *reg2300 = ha->iobase2300; + uint8_t status = 0; + uint32_t cnt; + uint16_t *optr, *iptr; + uint16_t data, command, intreq; + srb_t *done_q_first = 0; + srb_t *done_q_last = 0; + uint32_t longdata = 0; + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_mailbox_command"); +#endif + + /* Acquire interrupt specific lock */ + QLA2100_INTR_LOCK(ha); + + DRIVER_LOCK + ha->flags.mbox_busy = TRUE; + +#ifdef QL_DEBUG_LEVEL_5 + sprintf(debug_buff,"scsi%d ",(int)ha->host_no); + qla2100_print(debug_buff); + qla2100_print("qla2100_mailbox_command: [[Start]] mbox_out[0] = "); + qla2100_output_number((u_long)*mb, 16); + qla2100_print("\n"); +#endif + /* Load mailbox registers. */ + if (ha->device_id != QLA2300_DEVICE_ID) + optr = (uint16_t *)®->mailbox0; + else + optr = (uint16_t *)®2300->mailbox0; + +#ifdef QL_DEBUG_LEVEL_5 + qla2100_print( + "qla2100_mailbox_command: Load MB word registers (displayed in bytes) = \n"); + qla2100_dump_buffer((uint8_t *)mb, 16); + qla2100_print("\n"); + qla2100_dump_buffer(((uint8_t *)mb + 0x10), 16); + qla2100_print("\n"); + qla2100_dump_buffer(((uint8_t *)mb + 0x20), 8); + qla2100_print("\n"); + qla2100_print("qla2100_mailbox_command: I/O address = "); + qla2100_output_number((u_long)optr, 16); + qla2100_print("\n"); +#endif + iptr = mb; + command = *(mb); + for( cnt = 0; cnt < MAILBOX_REGISTER_COUNT; cnt++ ) { + if( mr & BIT_0 ) { + WRT_REG_WORD(optr, (*iptr)); + } + mr >>= 1; + optr++; + iptr++; + } +#ifdef QL_DEBUG_LEVEL_5 + qla2100_dump_regs(ha->host); +#endif + + /* Issue set host interrupt command. */ + ha->flags.mbox_int = FALSE; + WRT_REG_WORD(®->host_cmd, HC_SET_HOST_INT); + + /* Wait for 30 seconds for command to finish. */ + if (ha->device_id == QLA2300_DEVICE_ID) + data = qla2100_debounce_register((uint16_t *)®2300->host_status); + else data = qla2100_debounce_register(®->istatus); + + cnt = 0x100000*2; /* 22 secs */ + + for( ; cnt > 0 && !ha->flags.mbox_int; cnt-- ) { + /* Check for pending interrupts. */ + if (ha->device_id == QLA2300_DEVICE_ID) { + switch (*mb) { + case MBC_LOAD_RAM: + case MBC_EXECUTE_FIRMWARE: + case MBC_MAILBOX_REGISTER_TEST: + case MBC_VERIFY_CHECKSUM: + case MBC_ABOUT_FIRMWARE: + /* handle ROM commands the old way */ + data = RD_REG_WORD(®->istatus); + intreq = data & RISC_INT; + break; + default: + /* handle non-ROM commands the new way */ + data = RD_REG_WORD(®->istatus); + longdata = RD_REG_DWORD(®2300->host_status); + intreq = longdata & RISC_2300_INT; + break; + } + } else { + /* QLA2100 or QLA2200 */ + data = RD_REG_WORD(®->istatus); + intreq = data & RISC_INT; + } + if ( intreq != 0 ) { + qla2100_isr(ha, + (srb_t **)&done_q_first, + (srb_t **)&done_q_last); + /* udelay(10); */ + } + udelay(10); /* v4.27 */ + } /* for */ + + /* Check for mailbox command timeout. */ + if( !cnt ) { +#ifdef QL_DEBUG_LEVEL_2 + qla2100_print( + "qla2100_mailbox_command: **** MB Command Timeout for cmd = "); + qla2100_output_number((u_long)mb[0], 16); + qla2100_print(" ****\n"); + qla2100_print( + "qla2100_mailbox_command: **** icontrol = "); + qla2100_output_number(RD_REG_WORD(®->ictrl), 16); + qla2100_print(" ****\n"); + qla2100_print( + "qla2100_mailbox_command: **** istatus = "); + qla2100_output_number((u_long)data, 16); + qla2100_print(" ****\n"); + qla2100_print( + "qla2100_mailbox_command: **** chip mailbox[0] = "); + qla2100_output_number((u_long)RD_REG_WORD(optr), 16); + qla2100_print(" ****\n"); + qla2100_dump_regs(ha->host); +#endif + ha->flags.isp_abort_needed = TRUE; + qla2100_stats.mboxtout++; + status = 1; + } else if( ha->mailbox_out[0] != MBS_CMD_CMP ) { + qla2100_stats.mboxerr++; + status = 1; + } + + /* Load return mailbox registers. */ + optr = mb; + iptr = (uint16_t *)&ha->mailbox_out[0]; + + mr = MAILBOX_REGISTER_COUNT; + while( mr-- ) + *optr++ = *iptr++; + + /* Go check for any response interrupts pending. */ + ha->flags.mbox_busy = FALSE; + + qla2100_isr(ha,(srb_t **)&done_q_first,(srb_t **)&done_q_last); + + /* Release interrupt specific lock */ + QLA2100_INTR_UNLOCK(ha); + DRIVER_UNLOCK + + if( ha->flags.isp_abort_needed ) + qla2100_abort_isp(ha); + + if( ha->flags.reset_marker ) + qla2100_rst_aen(ha); + if( ha->flags.update_config_needed ) + qla2100_update_config(ha); + if( ha->flags.loop_resync_needed ) + qla2100_loop_resync(ha); + + if( done_q_first ) + qla2100_done(ha, (srb_t **)&done_q_first, (srb_t **)&done_q_last); + +#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3) + if( status ) { + qla2100_print("qla2100_mailbox_command: **** FAILED, mailbox0 = "); + qla2100_output_number((u_long)mb[0], 16); + qla2100_print(" ****\n"); + } else { +/* DEBUG(qla2100_print("qla2100_mbc: Completed OK operation=");) +DEBUG(qla2100_output_number((u_long)command, 16);) +DEBUG(qla2100_print(" \n");) +DEBUG(qla2100_print("qla2100_mbc: mailbox[1]=");) +DEBUG(qla2100_output_number((u_long)mb[1], 16);) +DEBUG(qla2100_print(" \n");) +DEBUG(qla2100_print("mbc: +++ rsp_q_in= ");) +DEBUG(qla2100_output_number(RD_REG_WORD(&ha->iobase2300->rsp_q_in), 16);) +DEBUG(qla2100_print(" +++ \n");) +DEBUG(qla2100_print("mbc: +++ rsp_q_out= ");) +DEBUG(qla2100_output_number(RD_REG_WORD(&ha->iobase2300->rsp_q_out), 16);) +DEBUG(qla2100_print(" +++ \n\n");) +DEBUG(printk("qla2100_mbc: Completed OK operation=%x\n\n",command);) */ + } +#endif +#ifdef QL_DEBUG_LEVEL_3 + LEAVE("qla2100_mailbox_command"); +#endif + return(status); +} + + + /* + * qla2100_poll + * Polls ISP for interrupts. + * + * Input: + * ha = adapter block pointer. + */ +STATIC void +qla2100_poll(scsi_qla_host_t *ha) { + device_reg_t *reg = ha->iobase; + device2300_reg_t *reg2300 = ha->iobase2300; + uint16_t data; + srb_t *done_q_first = 0; + srb_t *done_q_last = 0; + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_poll"); +#endif + + /* Acquire interrupt specific lock */ + QLA2100_INTR_LOCK(ha); + + /* Check for pending interrupts. */ + if (ha->device_id == QLA2300_DEVICE_ID) + data = qla2100_debounce_register((uint16_t *)®2300->host_status) & + RISC_2300_INT; + else data = qla2100_debounce_register(®->istatus) & + RISC_INT; + + /* Check for pending interrupts. */ + if( data ) { + DEBUG(qla2100_print("qla2100_poll: Calling isr\n");) + qla2100_isr(ha, + (srb_t **)&done_q_first, + (srb_t **)&done_q_last); + } + + /* Release interrupt specific lock */ + QLA2100_INTR_UNLOCK(ha); + + if( !ha->flags.mbox_busy ) { + if( ha->flags.isp_abort_needed ) + qla2100_abort_isp(ha); + if( ha->flags.reset_marker ) + qla2100_rst_aen(ha); + if( ha->flags.update_config_needed ) + qla2100_update_config(ha); + if( ha->flags.loop_resync_needed ) + qla2100_loop_resync(ha); + } + + if( done_q_first ) + qla2100_done(ha, (srb_t **)&done_q_first, (srb_t **)&done_q_last); + +#ifdef QL_DEBUG_LEVEL_3 + LEAVE("qla2100_poll"); +#endif +} + +/* +* qla2100_find_host +* This routine searches the host adapter database +* and return either TRUE or FALSE. +* +* Input: +* ha = adapter block pointer. +* device = device data pointer. +* +* Returns: +* TRUE - found +*/ +STATIC uint8_t +qla2100_find_host(scsi_qla_host_t *ha, device_data_t *device) { + fcdev_t *pdb; + uint16_t cnt; + + pdb = ha->phost_db; + for (cnt = 0; cnt < ha->host_db_ptr; cnt++) { + /* if nodename/portname in database */ +#if USE_PORTNAME + if (BCMP(device->wwn, pdb[cnt].name, 8) == 0) { +#else + if (BCMP(device->name, pdb[cnt].name, 8) == 0) { +#endif + return TRUE; + } + } + return FALSE; +} + +/* +* qla2100_update_host_data +* This routine updates the host device database +* +* Input: +* ha = adapter block pointer. +* device = device data pointer. +* +* Returns: +* 0 = success, if device found or added to database. +* 1 = error +* 2 = database was full and device was not configured. +*/ +STATIC uint8_t +qla2100_update_host_data(scsi_qla_host_t *ha, device_data_t *device, + uint8_t enable_slot_reuse) +{ + fcdev_t *pdb; + uint8_t status = 0; + uint8_t index; + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_update_host"); +#endif + + pdb = ha->phost_db; + index = ha->host_db_ptr; + if (index != MAX_HOST_COUNT) { + index++; +#if USE_PORTNAME + BCOPY(device->wwn, pdb[index].name, 8); +#else + BCOPY(device->name, pdb[index].name, 8); +#endif + } else if ( enable_slot_reuse ) { + index = 0; + printk(KERN_INFO "qla2100_update_host: Host table Full." + " Overwriting slot 0."); +#if USE_PORTNAME + BCOPY(device->wwn, pdb[index].name, 8); +#else + BCOPY(device->name, pdb[index].name, 8); +#endif + } else { + printk(KERN_INFO "qla2100_update_host: Host table Full."); + status = 2; + } + ha->host_db_ptr = index; + +#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3) + if( status ) + qla2100_print("qla2100_update_host: **** FAILED ****\n"); +#endif +#ifdef QL_DEBUG_LEVEL_3 + else + LEAVE("qla2100_update_host"); +#endif + return(status); + +} + +/* +* qla2100_update_device_data +* This routine updates the device data in the database and logs +* onto the device if necessary. +* +* Input: +* ha = adapter block pointer. +* device = device data pointer. +* +* Returns: +* 0 = success, if device found or added to database. +* 1 = error +* 2 = database was full and device was not configured. +*/ +STATIC uint8_t +qla2100_update_device_data(scsi_qla_host_t *ha, device_data_t *device, uint8_t enable_slot_reuse) { + uint8_t status = 0; + uint8_t hostflag = 0; + uint8_t dev_configured; + uint16_t cnt, i; + uint16_t mb[MAILBOX_REGISTER_COUNT]; + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_update_device"); +#endif + + dev_configured = FALSE; + if( ha->device_id == QLA2100_DEVICE_ID ) { + ha->min_external_loopid = 1; /* v2.19.5b3 */ + ha->max_public_loop_ids = LAST_SNS_LOOP_ID - SNS_FIRST_LOOP_ID + 1; + } else { + ha->max_public_loop_ids = LAST_SNS_LOOP_ID + 1; + } + + DEBUG(sprintf(debug_buff, + "qla2100: Found device - portname=%02x%02x%02x%02x%02x%02x%02x%02x," + " nodename=%02x%02x%02x%02x%02x%02x%02x%02x," + " port Id=%06lx, loop id=%04x\n", + device->wwn[0], device->wwn[1], + device->wwn[2], device->wwn[3], + device->wwn[4], device->wwn[5], + device->wwn[6], device->wwn[7], + device->name[0], device->name[1], + device->name[2], device->name[3], + device->name[4], device->name[5], + device->name[6], device->name[7], + device->port_id[0] << 16 | device->port_id[1] << 8 | device->port_id[2], device->loop_id);) + DEBUG(qla2100_print(debug_buff);) + + /* if we already login to the host adapter then skip it */ + if ( qla2100_find_host(ha, device) ) { + DEBUG(printk("update_db: Skipping host adapter..\n");) + return( status ); + } + + /* Search to see if node name is already in database. If found then change loop ID in database. */ + for( cnt = 0; cnt < MAX_FIBRE_DEVICES && !dev_configured; cnt++ ) { + /* if nodename/portname in database then replace it */ +#if USE_PORTNAME /* updated for ioctl merge */ + if (BCMP(device->wwn, ha->fc_db[cnt].wwn, 8) == 0) { +#else + if (BCMP(device->name, ha->fc_db[cnt].name, 8) == 0) { +#endif + ha->fc_db[cnt].flag &= ~DEV_MISSING; + /* if device was configured by user then find and assign a loop ID for it */ + if( ha->fc_db[cnt].loop_id == PORT_AVAILABLE ) { + DEBUG(qla2100_print("Port marked as already assigned.\n");) + /* If device found is on the public loop. */ + /* then find the next available fabric loop ID */ + if( device->loop_id == 0xffff ) { + status = 1; + /* Search the public database for first available slot. */ + for( i = ha->min_external_loopid; i < ha->max_public_loop_ids; i++ ) { + if( !ha->fabricid[i].in_use ) { + ha->fabricid[i].in_use = TRUE; + if( ha->device_id == QLA2100_DEVICE_ID ) + device->loop_id = SNS_FIRST_LOOP_ID + i; + else + device->loop_id = i; + ha->fc_db[cnt].loop_id = device->loop_id; + ha->fc_db[cnt].port_id[0] = device->port_id[0]; + ha->fc_db[cnt].port_id[1] = device->port_id[1]; + ha->fc_db[cnt].port_id[2] = device->port_id[2]; + ha->fc_db[cnt].flag |= DEV_PUBLIC; + status = 0; + break; + } + } /* end of for */ + } else { /* change the local loop ID in database */ + ha->fc_db[cnt].loop_id = device->loop_id; + } + } else /* loop id may have been previously used */ + { + /* If device is on public loop. */ + if( device->loop_id == 0xffff ) { + /* It was previously public, so use previously assigned loop id. */ + if( ha->fc_db[cnt].flag & DEV_PUBLIC ) + if( ha->device_id == QLA2100_DEVICE_ID ) + device->loop_id = ha->fc_db[cnt].loop_id; + else { + /* if the same topology and public loop */ + /* search for the next avaiable public loop ID */ + DEBUG(printk("update_db: topology prev %d, curr %d\n", + ha->prev_topology, ha->current_topology );) + if( ha->prev_topology == ha->current_topology ) { + if( (ha->min_external_loopid) && + (ha->fc_db[cnt].loop_id < ha->min_external_loopid) ) { + status = 1; + /* find a loop ID for the Public device */ + for( i = ha->min_external_loopid; i < ha->max_public_loop_ids; i++ ) + if( !ha->fabricid[i].in_use ) { + ha->fabricid[i].in_use = TRUE; + device->loop_id = i; + ha->fc_db[cnt].loop_id = device->loop_id; + status = 0; + break; + } + } else + device->loop_id = ha->fc_db[cnt].loop_id; + } else { + status = 1; + /* Find an unused loop ID */ + for( i = ha->min_external_loopid; i < ha->max_public_loop_ids; i++ ) + if( !ha->fabricid[i].in_use ) { + ha->fabricid[i].in_use = TRUE; + device->loop_id = i; + ha->fc_db[cnt].loop_id = device->loop_id; + status = 0; + break; + } + } + + } else { + /* If it moved from private to public loop, assign new public loop id. */ + status = 1; + /* Find an unused loop ID */ + for( i = ha->min_external_loopid; i < ha->max_public_loop_ids; i++ ) + if( !ha->fabricid[i].in_use ) { + ha->fabricid[i].in_use = TRUE; + if( ha->device_id == QLA2100_DEVICE_ID ) + + device->loop_id = SNS_FIRST_LOOP_ID + i; + else + device->loop_id = i; + ha->fc_db[cnt].loop_id = device->loop_id; + ha->fc_db[cnt].flag |= DEV_PUBLIC; + ha->fc_db[cnt].port_id[0] = device->port_id[0]; + ha->fc_db[cnt].port_id[1] = device->port_id[1]; + ha->fc_db[cnt].port_id[2] = device->port_id[2]; + status = 0; + break; + } + } + } else { + /* The found device is on private loop but was + previously on public loop, so free public loop id. */ + if( ha->fc_db[cnt].flag & DEV_PUBLIC ) { + ha->fc_db[cnt].flag &= ~DEV_PUBLIC; + i = ha->fc_db[cnt].loop_id - SNS_FIRST_LOOP_ID; + ha->fabricid[i].in_use = 0; + } + ha->fc_db[cnt].loop_id = device->loop_id; + } + } + + /* If public device in database */ + if( !status && (ha->fc_db[cnt].flag) & DEV_PUBLIC ) { + + + /* If public loop device, compare port id to see if + device moves to another NL/N port. */ + if( ha->fc_db[cnt].port_id[0] != device->port_id[0] || + ha->fc_db[cnt].port_id[1] != device->port_id[1] || + ha->fc_db[cnt].port_id[2] != device->port_id[2] ) { + if( ha->prev_topology == ha->current_topology ) { + /* Port id changed, log device out then log back + in with new port id but same loop id. */ + mb[0] = MBC_LOGOUT_FABRIC_PORT; + mb[1] = ha->fc_db[cnt].loop_id << 8; + qla2100_mailbox_command(ha, BIT_1|BIT_0, &mb[0]); + ha->fc_db[cnt].port_id[0] = device->port_id[0]; + ha->fc_db[cnt].port_id[1] = device->port_id[1]; + ha->fc_db[cnt].port_id[2] = device->port_id[2]; + } + } + /* + * Try and find a loop Id for the given + * fabric port. We keep trying Ids until we find + * a good one. + */ + mb[0] = 0x4008; + while( !status && mb[0] == 0x4008 ) { + DEBUG(printk("update_db: Trying Fabric Login @ loop id= %d, port id= %06x\n", device->loop_id,device->port_id);) + mb[0] = MBC_LOGIN_FABRIC_PORT; + mb[1] = device->loop_id << 8 | 0x01; + mb[2] = device->port_id[0]; + mb[3] = device->port_id[1] << 8 | device->port_id[2]; + qla2100_mailbox_command(ha, BIT_3|BIT_2|BIT_1|BIT_0, + &mb[0]); + /* Command parameter error or all IDS used */ + if ( mb[0] == 0x4006 || mb[0] == 0x4009 ) { + status = 1; + DEBUG(printk("update_db: (1) Failed Fabric login with Loop ID = %d\n", device->loop_id);) + } + /* + * if loop Id is in use then try the next Id . + */ + if( mb[0] == 0x4008 ) { + DEBUG(printk("update_db: Used Loop ID = %04x, port id=%06x - trying next id\n", device->loop_id, + ((mb[1] << 16) | (((mb[2] >>8 ) &0xff) << 8) | (mb[2] & 0xff)));) + if( device->loop_id++ <= LAST_SNS_LOOP_ID ) + ha->fabricid[device->loop_id].in_use = TRUE; + else + status = 1; + } + } + /* Login succuessful */ + if( !status ) { + /* if different host */ + if( (mb[1] & 0x1) ) { /* v2.19.05b3 */ + DEBUG(printk("update_db: Warning -- Adapter found: port id=%06x, tgt=%d\n", + ((mb[1] << 16) | (((mb[2] >>8 ) &0xff) << 8) | (mb[2] & 0xff)),cnt);) + qla2100_update_host_data(ha, device, enable_slot_reuse); + ha->fabricid[device->loop_id].in_use = FALSE; + hostflag++; + } else { + /* 4.31.8 update loop id in database */ + ha->fc_db[cnt].loop_id = device->loop_id; + } + } +#if 0 + /* Command error */ + if( !status && mb[0] != 0x4005 ) { + /* Issue Abort target command to cause RISC to + flush all commands outstanding for this device. + Commands will be returned with "Aborted" status. */ + mb[0] = MBC_ABORT_TARGET; + mb[1] = device->loop_id << 8; + mb[2] = 1; + status = qla2100_mailbox_command(ha, BIT_2|BIT_1|BIT_0, &mb[0]); + } +#endif + } + dev_configured = TRUE; + } + } + + /* Device not already in database so find */ + /* an empty slot and loop id for it. */ + if( !dev_configured ) { + DEBUG(printk("qla2100_db_update: New Device - not in database.\n");) + + /* If device is on public loop. */ + /* First find an unused Fabric loop ID */ + /* then find a slot. */ + if( device->loop_id == 0xffff ) { + status = 1; + for( i = ha->min_external_loopid; i < ha->max_public_loop_ids; i++ ) { + if( !ha->fabricid[i].in_use ) { + ha->fabricid[i].in_use = TRUE; + if( ha->device_id == QLA2100_DEVICE_ID ) + device->loop_id = SNS_FIRST_LOOP_ID + i; + else + device->loop_id = i; + status = 0; + break; + } + } + /* Preset status to Loop ID used */ + mb[0] = 0x4008; + /* Check to insure loop ID for fabric device is good */ + while( !status && mb[0] == 0x4008 ) { + DEBUG(printk("update_db: Trying Fabric Login @ loop id %d\n", device->loop_id);) + mb[0] = MBC_LOGIN_FABRIC_PORT; + mb[1] = device->loop_id << 8 | 0x01; + mb[2] = device->port_id[0]; + mb[3] = device->port_id[1] << 8 | device->port_id[2]; + qla2100_mailbox_command(ha, BIT_3|BIT_2|BIT_1|BIT_0, &mb[0]); + if ( mb[0] == 0x4006 || mb[0] == 0x4009 ) { + status = 1; + DEBUG(printk("update_db: (2) Failed Fabric login with Loop ID = %d\n", device->loop_id);) + } + if( mb[0] == 0x4008 ) { + DEBUG(printk("update_db: (2) Used Fabric Loop ID = %04x, port id=%06x\n", device->loop_id, + ((mb[1] << 16) | (((mb[2] >>8 ) &0xff) << 8) | (mb[2] & 0xff)));) + if( device->loop_id++ <= LAST_SNS_LOOP_ID ) + ha->fabricid[device->loop_id].in_use = TRUE; /* v2.19.05b3 */ + else + status = 1; + } + if( (mb[1] & 0x1) ) { /* v2.19.05b3 */ + qla2100_update_host_data(ha, device, enable_slot_reuse); + DEBUG(printk("update_db: Adapter found: port id=%06x\n", + (device->port_id[0] <<16) | + (device->port_id[1] << 8) | (device->port_id[2])) ); + ha->fabricid[device->loop_id].in_use = FALSE; + hostflag++; + } + } + } + /* Now find an empty slot for the device */ + if( !status && hostflag == 0 ) { + if( ha->device_id == QLA2100_DEVICE_ID ) + ha->min_external_loopid = SNS_FIRST_LOOP_ID; + /* Find a empty slot and add device into database. */ + for( i = 0; i < MAX_FIBRE_DEVICES; i++ ) + if( ha->fc_db[i].loop_id == PORT_UNUSED ) { + ha->fc_db[i].flag &= ~DEV_MISSING; + + /* get and set both wwnn and wwpn */ + BCOPY(device->name, ha->fc_db[i].name, 8); + BCOPY(device->wwn, ha->fc_db[i].wwn, 8); + + ha->fc_db[i].loop_id = device->loop_id; + if( device->loop_id >= ha->min_external_loopid ) { + ha->fc_db[i].flag |= DEV_PUBLIC; + ha->fc_db[i].port_id[0] = device->port_id[0]; + ha->fc_db[i].port_id[1] = device->port_id[1]; + ha->fc_db[i].port_id[2] = device->port_id[2]; + } + ha->flags.updated_fc_db = TRUE; + dev_configured = TRUE; + break; + } + if( !dev_configured ) { + if( enable_slot_reuse ) { + for( i = 0; i < MAX_FIBRE_DEVICES; i++ ) + if( ha->fc_db[i].loop_id == PORT_AVAILABLE ) { + ha->fc_db[i].flag &= ~DEV_MISSING; +#if USE_PORTNAME /* ioctl support change */ + BCOPY(device->wwn, ha->fc_db[i].wwn, 8); +#else + BCOPY(device->name, ha->fc_db[i].name, 8); +#endif + ha->fc_db[i].loop_id = device->loop_id; + if( device->loop_id >= ha->min_external_loopid ) { + ha->fc_db[i].flag |= DEV_PUBLIC; + ha->fc_db[i].port_id[0] = device->port_id[0]; + ha->fc_db[i].port_id[1] = device->port_id[1]; + ha->fc_db[i].port_id[2] = device->port_id[2]; + } + ha->flags.updated_fc_db = TRUE; + break; + } + } else { + ha->fabricid[device->loop_id].in_use = FALSE; + status = 2; + } + + } + + } + } +#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3) + if( status ) + qla2100_print("qla2100_update_device: **** FAILED ****\n"); +#endif +#ifdef QL_DEBUG_LEVEL_3 + else + LEAVE("qla2100_update_device"); +#endif + return(status); + } + +/* +* qla2100_sns_device +* Setup Simple Name Server devices with loop ID's. +* +* Input: +* ha = adapter block pointer. +* +* Returns: +* 0 = success. +* 1 = error +* 2 = database was full and device was not configured. +*/ +STATIC uint8_t +qla2100_sns_device(scsi_qla_host_t *ha, uint8_t enable_slot_reuse) { + uint8_t status = 1; + uint8_t first_port_id[3]; + uint8_t next_port_id[3]; + uint8_t host_port_id[3]; + sns_data_t *sns; +#if BITS_PER_LONG > 32 + uint64_t phys_address = 0; +#else + uint32_t phys_address = 0; +#endif + uint16_t mb[MAILBOX_REGISTER_COUNT]; + uint8_t use_gan = 1; + uint8_t retry_count = 0; + gp_idnn_t *gp_idnn; + uint16_t i; + device_data_t device; + uint8_t db_full = 0; + uint16_t public_count; + uint32_t fabric_devices = 0; + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_sns_device"); +#endif + + /* If FL port exists, then SNS is present */ + DEBUG(printk("qla2100_sns_device: Checking for Fabric.\n");) + mb[0] = MBC_GET_PORT_NAME; + mb[1] = SNS_FL_PORT << 8; /* port name */ + if( !qla2100_mailbox_command(ha, BIT_1|BIT_0, &mb[0]) ) { + +#ifdef RCSN + /* Mark devices that need re-synchronization. */ + qla2100_device_resync(ha); +#endif + + /* Fl port is present */ + host_port_id[0] = ha->port_id[0]; + host_port_id[1] = ha->port_id[1]; + host_port_id[2] = ha->port_id[2]; + + /* Calculate the max number of public ports */ + if( ha->device_id == QLA2100_DEVICE_ID ) + public_count = ha->max_public_loop_ids; + else + public_count = ha->max_public_loop_ids - ha->min_external_loopid; + + /* Register with name server as type fc4 device */ + +#ifdef FC_IP_SUPPORT + /* Register with name server as type 5 device */ + if (ha->flags.enable_ip == TRUE) { + qla2x00_register_ip_device(ha); + } + + /* If IP enable, skip GP_IDNN and just use GAN */ + if (ha->flags.enable_ip == TRUE) + goto tryGan; +#endif /* FC_IP_SUPPORT */ + + /* Find out if this is a Brocade switch, if so do GP_IDNN. */ + /* otherwise use the GAN */ + mb[0] = MBC_GET_PORT_NAME; + mb[1] = SNS_FL_PORT << 8 | BIT_0; /* node name */ + qla2100_mailbox_command(ha, BIT_1|BIT_0, &mb[0]); + if( mb[2] == 0x0010 && mb[3] == 0x6000 && + (mb[6] & 0x00FF) == 0x0069 ) { +/* 4.10 */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18) + gp_idnn = KMALLOC(GP_IDNN_LENGTH); + if ( gp_idnn != NULL ) { + phys_address = VIRT_TO_BUS(gp_idnn); + BZERO((caddr_t)gp_idnn, GP_IDNN_LENGTH); + } +#else + gp_idnn = pci_alloc_consistent(ha->pdev, + GP_IDNN_LENGTH, + &phys_address); + BZERO((caddr_t)gp_idnn, GP_IDNN_LENGTH); +#endif + if ( gp_idnn != NULL ) { + /* Retry GP_IDNN til valid list or retries done */ + while( retry_count++ < 10 ) { + /* + * Issue GP_IDNN to get list of port IDs and + * node names from name server. + */ + gp_idnn->req.buffer_length = GP_IDNN_LENGTH/2; + /* 4.10 */ + gp_idnn->req.buffer_address[0] = + LS_64BITS(phys_address); + gp_idnn->req.buffer_address[1] = + MS_64BITS(phys_address); + gp_idnn->req.subcommand_length = 6; + gp_idnn->req.subcommand = 0x173; + gp_idnn->req.length = GP_IDNN_LENGTH / 4; + gp_idnn->req.protocol = 0x08; + + mb[0] = MBC_SEND_SNS_COMMAND; + mb[1] = 14; + mb[3] = LSW(phys_address); + mb[2] = MSW(phys_address); + mb[7] = QL21_64BITS_3RDWD(phys_address); + mb[6] = QL21_64BITS_4THWD(phys_address); + if( !qla2100_mailbox_command(ha, + BIT_7|BIT_6|BIT_3|BIT_2|BIT_1|BIT_0, + &mb[0]) ) { + if( gp_idnn->rsp.response == SNS_ACCEPT ) { + DEBUG3(printk("Sns: Get all Fabric devices:\n");) + /* Go down device list and add devices to database. */ + for( i = 0; i < public_count; i++ ) { + /* if not host port id then add it to the database */ + if( gp_idnn->rsp.port_data[i].port_id[0] != host_port_id[0] || + gp_idnn->rsp.port_data[i].port_id[1] != host_port_id[1] || + gp_idnn->rsp.port_data[i].port_id[2] != host_port_id[2] ) { + BCOPY(gp_idnn->rsp.port_data[i].nodename, device.name, 8); + /* get loop id */ + device.port_id[0] = gp_idnn->rsp.port_data[i].port_id[0]; + device.port_id[1] = gp_idnn->rsp.port_data[i].port_id[1]; + device.port_id[2] = gp_idnn->rsp.port_data[i].port_id[2]; +#if USE_PORTNAME + /* Get portname */ + if( qla2100_sns_get_name(ha, &device, 0) ) { + status = 1; /* v2.19.5b4 */ + break; + } +#endif + device.loop_id = 0xffff; + /* Update device database and login to device. */ + fabric_devices++; + if( (status = qla2100_update_device_data(ha, &device, enable_slot_reuse)) ) { + if( status == 2 ) + db_full = 1; + else + break; + } + } + if( gp_idnn->rsp.port_data[i].controlbyte == 0x80 ) + break; + } + use_gan = 0; + break; + } + } + /* Wait for 100ms before retrying */ + for( i = 0; i <= 10000; i++ ) { + udelay(10); + } + } +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18) + KMFREE(gp_idnn, GP_IDNN_LENGTH); +#else + pci_free_consistent(ha->pdev, GP_IDNN_LENGTH, + gp_idnn, phys_address); +#endif + } else { + use_gan = 0; +#ifdef QL_DEBUG_LEVEL_2 + qla2100_print( + "qla2100_sns_device: Failed to allocate memory, No FL Port\n"); +#endif + } + } + /* Use the GAN (GA_NXT) Name server request to discover the ports */ + + /* + * Go through GAN list to find all fabric devices. Will perform + * necessary logout of previously existed devices that have changed + * and save new devices in a new device list. + * + */ + + if( use_gan ) { +#ifdef FC_IP_SUPPORT + tryGan: +#endif + + /* Find all registered ports in the Fabric */ +/* 4.10 */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18) + sns = KMALLOC(sizeof(sns_data_t)); + if ( sns != NULL ) { + phys_address = VIRT_TO_BUS(sns); + BZERO((caddr_t)sns, sizeof(sns_data_t)); + } +#else + sns = pci_alloc_consistent(ha->pdev, + sizeof(sns_data_t), + &phys_address); + BZERO((caddr_t)sns, sizeof(sns_data_t)); +#endif + if ( sns != NULL ) { + DEBUG(printk("qla2100_sns_device: Performing a GAN (%d)\n",public_count);) + status = 0; + /* start with port ID = 0 */ + first_port_id[0] = first_port_id[1] = first_port_id[2] = 0; + next_port_id[0] = next_port_id[1] = next_port_id[2] = 0; + mb[0] = 0; + for( i = 0; i < public_count && !ha->loop_down_timer && + !ha->flags.loop_resync_needed; i++ ) { + /* GAN Get all next entries for the selected port ID from SNS. */ + BZERO((caddr_t)sns, sizeof(sns_data_t)); + sns->p.req.hdr.buffer_length = 318; /*304*/ + sns->p.req.hdr.buffer_address[0] = + LS_64BITS(phys_address); + sns->p.req.hdr.buffer_address[1] = + MS_64BITS(phys_address); + sns->p.req.hdr.subcommand_length = 6; + sns->p.req.subcommand = 0x100; + sns->p.req.param[6] = next_port_id[2]; + sns->p.req.param[7] = next_port_id[1]; + sns->p.req.param[8] = next_port_id[0]; + + mb[0] = MBC_SEND_SNS_COMMAND; + mb[1] = 14; + mb[3] = LSW(phys_address); + mb[2] = MSW(phys_address); + mb[7] = QL21_64BITS_3RDWD(phys_address); + mb[6] = QL21_64BITS_4THWD(phys_address); + if( !qla2100_mailbox_command(ha, + BIT_7|BIT_6|BIT_3|BIT_2|BIT_1|BIT_0, + &mb[0]) ) { + if( sns->p.rsp[8] != 0x80 || /* SNS_ACCEPT */ + sns->p.rsp[9] != 0x02 ) { /* 04/18/00 */ + printk(KERN_INFO "qla2100_sns_device: SEND_SNS_COMMAND Failed - 0x%2x%2x mb_res=%x\n", + sns->p.rsp[8],sns->p.rsp[9],mb[0]); + status = 1; + break; + } + /* save next port ID */ + next_port_id[0] = sns->p.rsp[17]; + next_port_id[1] = sns->p.rsp[18]; + next_port_id[2] = sns->p.rsp[19]; + + } else { +#ifdef QL_DEBUG_LEVEL_2 + qla2100_print( + "qla2100_sns_device: MBC_SEND_SNS_COMMAND Failed, No FL Port\n"); +#endif + /* v2.19.5 */ + DEBUG(printk("qla2100_sns_device: Failed Performing a GAN mb0=0x%x, mb1=0x%x\n", + mb[0],mb[1]);) + status = 1; + break; + } + + /* Assign loop ID for device on SNS. */ + if( (next_port_id[0] != first_port_id[0] || + next_port_id[1] != first_port_id[1] || + next_port_id[2] != first_port_id[2]) + && (sns->p.rsp[284] || sns->p.rsp[285] || + sns->p.rsp[286] || sns->p.rsp[287] || + sns->p.rsp[288] || sns->p.rsp[289] || + sns->p.rsp[290] || sns->p.rsp[291]) ) { + /* if port Id local loop skip this ID */ + if( next_port_id[0] != host_port_id[0] || + next_port_id[1] != host_port_id[1] || + next_port_id[2] != host_port_id[2] ) { +#if USE_PORTNAME + /* Extract portname */ + BCOPY(&sns->p.rsp[20], device.wwn, 8); +#endif + /* Extract nodename */ + BCOPY(&sns->p.rsp[284], device.name, 8); + /* extract port ID */ + device.port_id[0] = next_port_id[0]; + device.port_id[1] = next_port_id[1]; + device.port_id[2] = next_port_id[2]; + device.loop_id = 0xffff; + + /* Update device database and login device in */ + + /* if McData, skip all port types except 1 (N_port) & 2 (NL_port) */ + if ( !( (sns->p.rsp[16] == 0x01) || + (sns->p.rsp[16] == 0x02) ) ) { + DEBUG(printk("qla2100_sns_device: Skipping port type %x\n", sns->p.rsp[16]);) + } + +#ifdef FC_IP_SUPPORT + else if (sns->p.rsp[579] & 0x20) { + fabric_devices++; + /* Update IP device */ + if (qla2x00_update_ip_device_data(ha, &device) == QL_STATUS_FATAL_ERROR) { + status = 1; + break; + } + /* Update SCSI device */ + } +#endif + else { + fabric_devices++; + if( (status = qla2100_update_device_data(ha, &device, enable_slot_reuse)) ) { + if( status == 2 ) + db_full = 1; + break; + } + } +#ifdef FC_IP_SUPPORT + } +#endif + } + + /* + * Save first port if not repeating port + * on another Loop ID. + */ + if( !(first_port_id[0] || first_port_id[1] || + first_port_id[2]) ) { + first_port_id[0] = next_port_id[0]; + first_port_id[1] = next_port_id[1]; + first_port_id[2] = next_port_id[2]; + } + } else + break; + } +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18) + KMFREE(sns, sizeof(sns_data_t)); +#else + pci_free_consistent(ha->pdev, sizeof(sns_data_t), + sns, phys_address); +#endif + + } +#ifdef QL_DEBUG_LEVEL_2 + else + qla2100_print( + "qla2100_sns_device: Failed to allocate memory, No FL Port\n"); +#endif + } + } else +#ifdef QL_DEBUG_LEVEL_2 + qla2100_print( + "qla2100_sns_device: MBC_GET_PORT_NAME Failed, No FL Port\n"); +#else + DEBUG(printk("No Fabric found.\n");) +#endif + + if( fabric_devices > 0) + ha->device_flags |= DFLG_FABRIC_DEVICES; + + if( db_full ) + status = 2; + + /* Update iff F/FL found and update O.K. */ + if( !status ) + ha->prev_topology = ha->current_topology; + +#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3) + if( status ) + qla2100_print("qla2100_sns_device: **** FAILED ****\n"); +#endif +#ifdef QL_DEBUG_LEVEL_3 + else + LEAVE("qla2100_sns_device"); +#endif + return(status); +} + +#if USE_PORTNAME +/* +* qla2100_sns_get_name +* This routine is called tot do the SNS Get Port/Name command +* of the specified port. +* +* Input: +* ha = adapter block pointer. +* flag = 0 - port name , 1 - node name +* +* Output: +* +*/ +STATIC uint8_t qla2100_sns_get_name( scsi_qla_host_t *ha, device_data_t *device, uint8_t flag ) { + uint8_t lStatus = 0; + uint16_t wRetryCount; +#if BITS_PER_LONG > 32 + uint64_t phys_address = 0; +#else + uint32_t phys_address = 0; +#endif + uint16_t mb[MAILBOX_REGISTER_COUNT]; + uint16_t subCmd, response; + sns_data_t *sns; + + /* Set retry count */ + if ( flag ) + subCmd = 0x113; + else + subCmd = 0x112; + DEBUG2(printk("qla2100_SnsGetName: Get opcode %x - name for port Id %06x\n", subCmd, + (uint32_t)(device->port_id[0] << 16 | device->port_id[1] << 8 | device->port_id[2]));) + + wRetryCount = 2; + while (wRetryCount--) { + /* Do 'Get Port/Node name' mailbox command for the FL attached device */ +/* 4.10 */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18) + sns = KMALLOC(sizeof(sns_data_t)); + if ( sns != NULL ) { + phys_address = VIRT_TO_BUS(sns); + BZERO((caddr_t)sns, sizeof(sns_data_t)); + } +#else + sns = pci_alloc_consistent(ha->pdev, + sizeof(sns_data_t), + &phys_address); + BZERO((caddr_t)sns, sizeof(sns_data_t)); +#endif + if ( sns != NULL ) { + BZERO((caddr_t)sns, sizeof(sns_data_t)); + sns->p.req.hdr.buffer_length = 12; + /* 4.10 */ + sns->p.req.hdr.buffer_address[0] = + LS_64BITS(phys_address); + sns->p.req.hdr.buffer_address[1] = + MS_64BITS(phys_address); + sns->p.req.hdr.subcommand_length = 6; + sns->p.req.subcommand = subCmd; + sns->p.req.param[6] = device->port_id[2]; + sns->p.req.param[7] = device->port_id[1]; + sns->p.req.param[8] = device->port_id[0]; + sns->p.req.param[9] = 0; + + mb[0] = MBC_SEND_SNS_COMMAND; + mb[1] = 14; + mb[3] = LSW(phys_address); + mb[2] = MSW(phys_address); + mb[7] = QL21_64BITS_3RDWD(phys_address); + mb[6] = QL21_64BITS_4THWD(phys_address); + if( !qla2100_mailbox_command(ha, + BIT_7|BIT_6|BIT_3|BIT_2|BIT_1|BIT_0, + &mb[0]) ) { + + response = sns->p.rsp[8] | (sns->p.rsp[9] << 8); + if( response == SNS_ACCEPT ) { + if ( flag ) { + BCOPY(&sns->p.rsp[16], device->name, 8); + } else { + BCOPY(&sns->p.rsp[16], device->wwn, 8); + } + } else { + printk(KERN_WARNING "qla2100_SnsGetName: [ERROR] Get Name mb cmd response is not accept - status %x\n", mb[0]); + } + } else if (mb[0] == MBS_FATAL_ERROR) { + printk(KERN_WARNING "qla2100_SnsGetName: [ERROR] Get Name mb cmd fatal error - status %x\n", mb[0]); + lStatus = 1; + break; + } else { + printk(KERN_WARNING "qla2100_SnsGetName: [ERROR] Get Name mb cmd failed - status %x\n", mb[0]); + } + + } +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18) + KMFREE(sns, sizeof(sns_data_t)); +#else + pci_free_consistent(ha->pdev, sizeof(sns_data_t), + sns, phys_address); +#endif + } + return(lStatus); + +} +#endif + +/* +* qla2100_init_fc_db +* Initializes Fibre Channel Device Database. +* +* Input: +* ha = adapter block pointer. +* +* Output: +* ha->fc_db = initialized +*/ +STATIC void +qla2100_init_fc_db(scsi_qla_host_t *ha) { + uint16_t cnt; + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_init_fc_db"); +#endif + + /* Initialize fc database if it is not initialized. */ + if( !ha->fc_db[0].loop_id && !ha->fc_db[1].loop_id ) { + ha->flags.updated_fc_db = FALSE; + + /* Initialize target database. */ + for( cnt = 0; cnt < MAX_FIBRE_DEVICES; cnt++ ) { + ha->fc_db[cnt].name[0] = 0L; + ha->fc_db[cnt].name[1] = 0L; + ha->fc_db[cnt].loop_id = PORT_UNUSED; + ha->fc_db[cnt].port_login_retry_count = 8; + ha->fc_db[cnt].flag = 0; /* v2.19.5b3 */ + ha->fc_db[cnt].port_timer = 0; /* v2.19.8 */ + } + +#if USE_FLASH + /* Move flash database to driver database. */ + qla2100_get_database(ha); +#endif + } + +#ifdef QL_DEBUG_LEVEL_3 + LEAVE("qla2100_init_fc_db"); +#endif +} + +/* +* qla2100_configure_fabric +* Setup fabric devices with loop ID's. +* +* Input: +* ha = adapter block pointer. +* enable_slot_reuse = allows the use of PORT_AVAILABLE slots. +* +* Returns: +* 0 = success. +* 1 = error. +* 2 = database was full and a device was not configured. +* +* Context: +* Kernel context. +*/ +STATIC uint8_t +qla2100_configure_fabric(scsi_qla_host_t *ha, + uint8_t enable_slot_reuse) +{ + uint8_t status = 0; + uint16_t i; + + /* get public loop devices */ + if( !ha->loop_down_timer && !ha->flags.loop_resync_needed ){ + /* Configure loop */ + if( !qla2100_configure_hba(ha) ) { + if( ha->device_id == QLA2100_DEVICE_ID ) { + ha->max_public_loop_ids = LAST_SNS_LOOP_ID - SNS_FIRST_LOOP_ID + 1; + } else { + ha->max_public_loop_ids = LAST_SNS_LOOP_ID + 1; + /* dg 09/15 */ + /* if the topology have change then make all devices available */ + if( ha->prev_topology != ha->current_topology ) { + /* Mark all fabric devices that where present as AVAILABLE */ + for( i = 0; i < ha->max_public_loop_ids; i++ ) + if( (i != SNS_FL_PORT) && (i != FABRIC_CONTROLLER) + && (i != SIMPLE_NAME_SERVER) ) + ha->fabricid[i].in_use = FALSE; + } + } + status = qla2100_sns_device(ha, enable_slot_reuse); + qla2100_restart_queues(ha,TRUE); + } + status = 1; + } + return( status ); +} + +/* +* qla2100_check_devices +* Check devices with loop ID's. +* +* Input: +* ha = adapter block pointer. +* +* Returns: +* 0 = success. +* 1 = retry needed +* +* Context: +* Kernel context. +*/ +STATIC uint8_t +qla2100_check_devices(scsi_qla_host_t *ha) { + int cnt; + uint8_t ret = 0; + uint16_t mb[MAILBOX_REGISTER_COUNT]; + + /* + * Retry any devices that wasn't found but as a WWN. + */ + /* v2.19.05b6 */ + for( cnt = 0; cnt < MAX_FIBRE_DEVICES; cnt++ ) { + if( (ha->fc_db[cnt].flag & DEV_MISSING) && + !(ha->fc_db[cnt].flag & DEV_OFFLINE) ) { + /* + * This dev was not detected but its WWN + * is valid. To handle the case where + * the switch may not be giving us the + * device list correctly, schedule for + * a login retry later if not previously + * done so. + */ + DEBUG(printk("qla2100_sns:Port login retry - target %d, count=%d\n",cnt, + ha->fc_db[cnt].port_login_retry_count); ) + if( ha->fc_db[cnt].port_login_retry_count ) + ha->fc_db[cnt].port_login_retry_count--; + + /* + * If after decrement the retry count + * becomes 0, mark this device OFFLINE so + * no more retries will be done based + * on this device. + */ + if (ha->fc_db[cnt].port_login_retry_count == 0) { + DEBUG(printk("qla2100_sns:Port set to OFFLINE - target %d\n",cnt); ) + ha->fc_db[cnt].flag |= DEV_OFFLINE; + } + ret = 1; + } + } + + /* + * Mark devices as DEV_MISSING if they were present + * before and have a loop ID. + */ + for( cnt = 0; cnt < MAX_FIBRE_DEVICES && + !ha->loop_down_timer && + !ha->flags.loop_resync_needed; cnt++ ) { + /* if this slot is used (i.e. loop ID 0 - 0xfe) */ + if( ha->fc_db[cnt].loop_id <= LAST_SNS_LOOP_ID ) { + /* Get port name */ + mb[0] = MBC_GET_PORT_NAME; + mb[1] = ha->fc_db[cnt].loop_id << 8 | BIT_0; + if( qla2100_mailbox_command(ha, BIT_1|BIT_0, &mb[0]) ) { + /* Flag as missing only once */ + if ( !(ha->fc_db[cnt].flag & DEV_MISSING) ) { + if ( ha->fc_db[cnt].port_login_retry_count ) { /* v2.19.05b3 */ + ha->fc_db[cnt].port_login_retry_count--; + ha->fc_db[cnt].flag |= DEV_MISSING; + DEBUG(printk("qla2100_sns: Missing port %d @ loop ID: %x\n", + cnt, ha->fc_db[cnt].loop_id);) + ret++; + } + } + } else if (ha->fc_db[cnt].flag & DEV_MISSING) { + ha->fc_db[cnt].flag &= ~DEV_MISSING; + ha->fc_db[cnt].flag &= ~DEV_OFFLINE; + ha->fc_db[cnt].flag |= DEV_RETURN; + ha->fc_db[cnt].port_login_retry_count = 8; + DEBUG(printk("qla2100_sns: Device %d returned\n", cnt);) + } + } + } + return( ret ); +} + +/* +* qla2100_update_fc_db +* Updates Fibre Channel Device Database with what is actually on loop. +* +* Input: +* ha = adapter block pointer. +* enable_slot_reuse = allows the use of PORT_AVAILABLE slots. +* +* Output: +* ha->fc_db = updated +* +* Returns: +* 0 = success. +* 1 = error. +* 2 = database was full and device was not configured. +*/ +STATIC uint8_t +qla2100_update_fc_db(scsi_qla_host_t *ha, uint8_t enable_slot_reuse) { + uint8_t status = 0; + uint8_t ret = 0; + uint8_t db_full = 0; + uint16_t cnt; + uint16_t mb[MAILBOX_REGISTER_COUNT]; + port_list_entry_t *gn_list, *port_entry; + device_data_t device; +#if BITS_PER_LONG > 32 + uint64_t phys_address = 0; +#else + uint32_t phys_address = 0; +#endif + uint16_t i, size; + uint16_t localdevices = 0; + int retry_needed = 0; + +#ifdef FC_IP_SUPPORT + PIP_DEVICE_BLOCK pIpDevice; +#endif + + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_update_fc_db"); +#endif + + /* Configure loop */ + if( !qla2100_configure_hba(ha) ) { + if( ha->device_id == QLA2100_DEVICE_ID ) { + ha->max_public_loop_ids = LAST_SNS_LOOP_ID - SNS_FIRST_LOOP_ID + 1; + } else { + ha->max_public_loop_ids = LAST_SNS_LOOP_ID + 1; + /* dg 09/15 */ + /* if the topology have change then make all devices available */ + if( ha->prev_topology != ha->current_topology ) { + /* Mark all fabric devices that where present as AVAILABLE */ + for( i = 0; i < ha->max_public_loop_ids; i++ ) + if( (i != SNS_FL_PORT) && (i != FABRIC_CONTROLLER) + && (i != SIMPLE_NAME_SERVER) ) + ha->fabricid[i].in_use = FALSE; + + /* Mark all local devices that where present as AVAILABLE */ + if( ha->current_topology == ISP_CFG_F ) + for( cnt = 0; cnt < MAX_FIBRE_DEVICES && !ha->loop_down_timer + && !ha->flags.loop_resync_needed; cnt++ ) + if( ha->fc_db[cnt].loop_id < SNS_FIRST_LOOP_ID ) { + ha->fc_db[cnt].loop_id = PORT_AVAILABLE; + ha->fc_db[cnt].flag &= ~DEV_PUBLIC; + } + } + } + /* v2.19.03 - Mark all devices missing if configured */ + for( cnt = 0; cnt < MAX_FIBRE_DEVICES; cnt++ ) + if( ha->fc_db[cnt].flag & DEV_CONFIGURED) + ha->fc_db[cnt].flag |= DEV_MISSING; + +#ifdef FC_IP_SUPPORT + /* Disable all IP devices in linked list */ + for (pIpDevice = ha->pIpDeviceTop; pIpDevice != NULL; + pIpDevice = pIpDevice->pNextIpDevice) { + pIpDevice->lDeviceFlags &= ~IP_DEV_FLAG_PRESENT; + } +#endif /* FC_IP_SUPPORT */ + + /* Configure local */ + /* Get the port list of devices on the local loop */ +/* 4.10 */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18) + gn_list = KMALLOC(GN_LIST_LENGTH); + if ( gn_list != NULL ) { + phys_address = VIRT_TO_BUS(gn_list); + BZERO((caddr_t)gn_list, GN_LIST_LENGTH); + } +#else + gn_list = pci_alloc_consistent(ha->pdev, + GN_LIST_LENGTH, + &phys_address); + BZERO((caddr_t)gn_list, GN_LIST_LENGTH); +#endif + if( gn_list != NULL ) { + + if( !ha->loop_down_timer && !ha->flags.loop_resync_needed ) { + /* Get port list.*/ + mb[0] = MBC_GET_PORT_LIST; +#ifdef FC_IP_SUPPORT + if (ha->flags.enable_ip == FALSE) + mb[1] = BIT_0; /* Bit 0 - return node names */ + else + mb[1] = BIT_0|BIT_1;/* Bit 0 - return node names, Bit 1 - loop IDs 0-255 */ +#else + mb[1] = BIT_0; +#endif + mb[3] = LSW(phys_address); + mb[2] = MSW(phys_address); + mb[7] = QL21_64BITS_3RDWD(phys_address); + mb[6] = QL21_64BITS_4THWD(phys_address); + if( !qla2100_mailbox_command(ha, BIT_7|BIT_6|BIT_3|BIT_2|BIT_1|BIT_0, &mb[0]) ) { + if ( mb[0] == MBS_COMMAND_COMPLETE ) { + port_entry = gn_list; + size = mb[1]; + /* dg 10/29/99 - check for empty list */ + if ( size/sizeof(port_list_entry_t) == 0 ) { + /* Local devices were present, but may not be reponding, + so retry them later */ + DEBUG(qla2100_print("qla2100_update_fc_db: local port list - empty\n");) + } else + /* Scan through the port list and add devices to the database */ + for( ; size >= sizeof(port_list_entry_t); + size -= sizeof(port_list_entry_t), port_entry++ ) { + /* Skip the known ports. */ +#ifdef FC_IP_SUPPORT + if( ((port_entry->loop_id & LOOP_ID_MASK) == SNS_FL_PORT) || + ((port_entry->loop_id & LOOP_ID_MASK) == FABRIC_CONTROLLER) || + ((port_entry->loop_id & LOOP_ID_MASK) == SIMPLE_NAME_SERVER) ) +#else + if( (port_entry->loop_id == SNS_FL_PORT) || + (port_entry->loop_id == FABRIC_CONTROLLER) || + (port_entry->loop_id == SIMPLE_NAME_SERVER) ) +#endif + continue; + + /* if we are on a public loop then logout the public devices. */ + if( ((ha->current_topology == ISP_CFG_FL) + || (ha->current_topology == ISP_CFG_F)) +#ifdef FC_IP_SUPPORT + && !(port_entry->loop_id & PLE_NOT_SCSI_DEVICE) + && ((port_entry->loop_id & LOOP_ID_MASK) >= ha->min_external_loopid)) { +#else + && (port_entry->loop_id >= ha->min_external_loopid) ) { +#endif + mb[0] = MBC_LOGOUT_FABRIC_PORT; +#ifdef FC_IP_SUPPORT + mb[1] = (port_entry->loop_id & LOOP_ID_MASK) << 8; +#else + mb[1] = port_entry->loop_id << 8; +#endif + qla2100_mailbox_command(ha, BIT_1|BIT_0, &mb[0]); + } else { + /* We are on a local loop */ + /* update the database with the loop */ + /* ID and login to the device. */ +#ifdef FC_IP_SUPPORT + device.loop_id = port_entry->loop_id & LOOP_ID_MASK; +#else + device.loop_id = port_entry->loop_id; +#endif + +#if USE_PORTNAME + /* Get port name */ + mb[0] = MBC_GET_PORT_NAME; + /* mb[1] = device.loop_id << 8 | BIT_0; */ + mb[1] = device.loop_id << 8; + if( !qla2100_mailbox_command(ha, BIT_1|BIT_0, &mb[0]) ) { + /* dg 09/15/99 */ + if ( mb[0] == MBS_COMMAND_COMPLETE ) { + /* tt 1/18/00 */ + mb[2] = (mb[2] & 0x00FF) << 8 | mb[2] >> 8; + mb[3] = (mb[3] & 0x00FF) << 8 | mb[3] >> 8; + mb[6] = (mb[6] & 0x00FF) << 8 | mb[6] >> 8; + mb[7] = (mb[7] & 0x00FF) << 8 | mb[7] >> 8; + + BCOPY(&mb[7], &device.wwn[0], 2); + BCOPY(&mb[6], &device.wwn[2], 2); + BCOPY(&mb[3], &device.wwn[4], 2); + BCOPY(&mb[2], &device.wwn[6], 2); + } else { + status = 1; + printk(KERN_WARNING "qla2100_update_fc_db: [ERROR] GET PORT NAME - bad status.\n"); + goto qla2100_update_fc_db_exit; + } + + } else { /* dg 10/29/99 */ + if ( mb[0] == MBS_FATAL_ERROR ) { + status = 1; + goto qla2100_update_fc_db_exit; + } + continue; + } +#endif + /* Get the node name */ + BCOPY(port_entry->name, device.name, 8); + + +#ifdef FC_IP_SUPPORT + if (!(port_entry->loop_id & PLE_NOT_SCSI_DEVICE)) { + /* SCSI type device */ + DEBUG(sprintf(debug_buff, "qla2100_update_fc_db: SCSI device at ID %x\n\r", + device.loop_id)); + DEBUG(qla2100_print(debug_buff)); +#endif + if( (status = qla2100_update_device_data(ha, &device, enable_slot_reuse)) ) { + /* if not configured or full */ + if( status == 2 ) + db_full = 1; + else + break; + } else + localdevices++; +#ifdef FC_IP_SUPPORT + } else if (ha->flags.enable_ip == TRUE) { + /* SCSI login failed, assume it is IP device */ + DEBUG(sprintf(debug_buff, "qla2100_update_fc_db: IP device at ID %x\n\r", + device.loop_id)); + DEBUG(qla2100_print(debug_buff)); + + /* Update IP device database */ + if (qla2x00_update_ip_device_data(ha, &device) == QL_STATUS_SUCCESS) { + localdevices++; + } else { + status = 1; + break; + } + } +#endif + } + } /* end of For */ + } + } + } +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18) + KMFREE(gn_list, GN_LIST_LENGTH); +#else + pci_free_consistent(ha->pdev, GN_LIST_LENGTH, + gn_list, phys_address); +#endif + /* + * if topology is a direct attached local loop then + * don't serach for public devices, unless its a 2100. + */ + if( ((ha->current_topology == ISP_CFG_N) || + (ha->current_topology == ISP_CFG_NL)) && + ha->device_id != QLA2100_DEVICE_ID ) { /* 2/21/00 - dg */ + ha->prev_topology = ha->current_topology; + } else { + /* dgER - we need to add logic to register + * our adapter with the Name server, so we + * can send Command Transport commands (FC4). + * (target mode) + */ + + /* get public loop devices */ + if( !ha->loop_down_timer && !ha->flags.loop_resync_needed ){ + /* v2.19.5 */ + if( (ret = qla2100_sns_device(ha, enable_slot_reuse)) == 2 ) + db_full = 1; + /* v2.19.5b3 */ + if( ret == 1 ) { + if( ha->device_id != QLA2100_DEVICE_ID ) { + status = ret; + ha->sns_retry_cnt++; + if( ha->sns_retry_cnt > 8 ) { + if( !(ha->dpc_flags & ISP_RESET_ONCE) ) + ha->dpc_flags |= ISP_RESET_NEEDED; + } + else + retry_needed++; + } + } + } + + } + + /* Set local loop devices present flag, clear retry flag */ + if (localdevices > 0 ) { + ha->device_flags |= DFLG_LOCAL_DEVICES; + ha->device_flags &= ~DFLG_RETRY_LOCAL_DEVICES; + } + + if( qla2100_check_devices(ha) ){ + DEBUG(printk("qla2100: Devices are missing or configured - retrying\n");) + retry_needed++; + } +#ifdef FC_IP_SUPPORT + /* Clean up active IP device list */ + for (pIpDevice = ha->pIpDeviceBottom; pIpDevice != NULL; + pIpDevice = pIpDevice->pLastIpDevice) { + if (!(pIpDevice->lDeviceFlags & IP_DEV_FLAG_PRESENT)) { + /* Device not present, remove it from list and free resources */ + DEBUG(sprintf(debug_buff, "qla2100_update_fc_db: removing IP device, loop ID: %x, port ID: %x\n\r", + pIpDevice->wLoopId, + pIpDevice->acPortId[0]<<16 | pIpDevice->acPortId[1]<<8 | pIpDevice->acPortId[2])); + DEBUG(qla2100_print(debug_buff)); + + if (pIpDevice->lDeviceFlags & IP_DEV_FLAG_PUBLIC_DEVICE) { + /* Do fabric logout and free loop ID */ + if (qla2x00_logout_public_device(ha, pIpDevice->wLoopId, 0) == QL_STATUS_FATAL_ERROR) { + status = 1; + break; + } + qla2x00_free_loopid(ha, pIpDevice->wLoopId); + } + qla2x00_free_ip_block(ha, pIpDevice); + } + } +#endif /* FC_IP_SUPPORT */ + + } else { +#ifdef QL_DEBUG_LEVEL_2 + qla2100_print( + "qla2100_update_fc_db: Failed to allocate memory, No local loop\n"); +#endif + status = 1; + } + /* Map the devices to target IDs */ + if( !ha->loop_down_timer && !ha->flags.loop_resync_needed ) + qla2100_map_targets(ha); + } else + status = 1; + + if( db_full ) + status = 2; + + if( retry_needed ) { + ha->device_flags |= LOGIN_RETRY_NEEDED; + /* v2.19.5 */ + status = 1; + } + + qla2100_update_fc_db_exit: + + if( status == 0 ) { + ha->loop_state = LOOP_READY; + ha->sns_retry_cnt = 0; + for( cnt = 0; cnt < MAX_FIBRE_DEVICES; cnt++ ) + ha->fc_db[cnt].port_login_retry_count = 8; + DEBUG(printk("qla2100_update_fc_db: LOOP READY\n");) + } + +#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3) + if( status ) + qla2100_print("qla2100_update_fc_db: **** FAILED ****\n"); +#endif +#ifdef QL_DEBUG_LEVEL_3 + else + LEAVE("qla2100_update_fc_db"); +#endif + return(status); +} + +/* +* qla2100_init_tgt_map +* Initializes target map. +* +* Input: +* ha = adapter block pointer. +* +* Output: +* TGT_Q initialized +*/ +STATIC void +qla2100_init_tgt_map(scsi_qla_host_t *ha) { + uint32_t b, t; + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_init_tgt_map"); +#endif + + for( b = 0; b < MAX_BUSES; b++ ) + for( t = 0; t < MAX_FIBRE_DEVICES; t++ ) + TGT_Q(ha, b, t) = (tgt_t *) NULL; + +#ifdef QL_DEBUG_LEVEL_3 + LEAVE("qla2100_init_tgt_map"); +#endif +} + +/* +* qla2100_map_targets +* Setup target queues. +* +* Input: +* ha = adapter block pointer. +* +* Returns: +* 0 = success. +*/ +STATIC uint8_t +qla2100_map_targets(scsi_qla_host_t *ha) { + tgt_t *tgt; + uint32_t b; + uint32_t t; + uint8_t status = 0; + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_map_targets"); +#endif + + b = 0; + for( t = 0; t < MAX_FIBRE_DEVICES; t++ ) { + /* if Port never been used. OR */ + /* Device does not exist on port. */ + if( ha->fc_db[t].loop_id != PORT_UNUSED && + ha->fc_db[t].loop_id != PORT_AVAILABLE ) { /* dg 10/29/99 */ + + if( (tgt = TGT_Q(ha, b, t)) != NULL ) { + DEBUG2(sprintf(debug_buff,"Target %d already allocated\n",t)); + DEBUG2(qla2100_print(debug_buff)); + } else + tgt = qla2100_tgt_alloc(ha); + DEBUG(sprintf(debug_buff,"Assigning target ID %02x:%02x @ (%08x) to loop id: 0x%04x\n",b,t,tgt,ha->fc_db[t].loop_id);) + DEBUG(qla2100_print(debug_buff)); + TGT_Q(ha, b, t) = tgt; + tgt->loop_id = ha->fc_db[t].loop_id; + tgt->down_timer = 0; + } + } + +#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3) + if( status ) + qla2100_print("qla2100_map_targets: **** FAILED ****\n"); +#endif +#ifdef QL_DEBUG_LEVEL_3 + else + LEAVE("qla2100_map_targets"); +#endif + return(status); +} +#if USE_FLASH +/* +* qla2100_get_database +* Copies and converts flash database to driver database. +* (may sleep) +* +* Input: +* ha = adapter block pointer. +* +* Returns: +* 0 = success. +*/ +STATIC uint8_t +qla2100_get_database(scsi_qla_host_t *ha) { + flash_database_t *fptr; + uint8_t status = 1; + uint32_t addr; + uint16_t cnt; + uint8_t *bptr; + uint8_t checksum; + uint32_t b, t; + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_get_database"); +#endif + + /* Default setup. */ + ha->flash_db = FLASH_DATABASE_0; + ha->flash_seq = 0; + + if( (fptr = (flash_database_t *)KMALLOC(sizeof(flash_database_t))) ) { + /* Enable Flash Read/Write. */ + qla2100_flash_enable(ha); + + /* Start with flash database with the highest sequence number. */ + b = qla2100_read_flash_byte(ha, FLASH_DATABASE_0); + b |= qla2100_read_flash_byte(ha, FLASH_DATABASE_0 + 1) << 8; + b |= qla2100_read_flash_byte(ha, FLASH_DATABASE_0 + 1) << 16; + b |= qla2100_read_flash_byte(ha, FLASH_DATABASE_0 + 1) << 24; + t = qla2100_read_flash_byte(ha, FLASH_DATABASE_1); + t |= qla2100_read_flash_byte(ha, FLASH_DATABASE_1 + 1) << 8; + t |= qla2100_read_flash_byte(ha, FLASH_DATABASE_1 + 1) << 16; + t |= qla2100_read_flash_byte(ha, FLASH_DATABASE_1 + 1) << 24; + if( t > b ) { + ha->flash_db = FLASH_DATABASE_1; + } + + /* Select the flash database with the good checksum. */ + for( t = 0; t < 2; t++ ) { + checksum = 0; + addr = ha->flash_db; + bptr = (uint8_t *)fptr; + fptr->hdr.size = sizeof(flash_database_t); + + /* Read flash database to driver. */ + for( cnt = 0; cnt < fptr->hdr.size; cnt++ ) { + *bptr = (uint8_t)qla2100_read_flash_byte(ha, addr++); + checksum += *bptr++; + if( bptr == &fptr->hdr.spares[0] && + (fptr->hdr.size > sizeof(flash_database_t) || + fptr->hdr.size < sizeof(flash_hdr_t) || + !fptr->hdr.version) ) { + checksum = 1; + break; + } + } + + if( !checksum ) { + status = 0; + break; + } + /* trying other database */ + if( ha->flash_db == FLASH_DATABASE_0 ) { + ha->flash_db = FLASH_DATABASE_1; + } else { + ha->flash_db = FLASH_DATABASE_0; + } + } + + if( !status ) { + ha->flash_seq = fptr->hdr.seq; + + /* Convert flash database to driver database format. */ + if( fptr->hdr.size -= sizeof(flash_hdr_t) ) { + for( cnt = 0; cnt < MAX_FIBRE_DEVICES; cnt++ ) { + ha->fc_db[cnt].name[0] = fptr->node[cnt].name[0]; + ha->fc_db[cnt].name[1] = fptr->node[cnt].name[1]; + cnt, + ha->fc_db[cnt].name[1], + ha->fc_db[cnt].name[0]); + + ha->fc_db[cnt].loop_id = PORT_AVAILABLE; + ha->fc_db[cnt].flag = 0; /* v2.19.05b3 */ + if( !(fptr->hdr.size -= sizeof(flash_node_t)) ) + break; + } + } + } + + qla2100_flash_disable(ha); + + KMFREE(fptr, sizeof(flash_database_t)); + } + +#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3) + if( status ) + qla2100_print("qla2100_get_database: **** FAILED ****\n"); +#endif +#ifdef QL_DEBUG_LEVEL_3 + else + LEAVE("qla2100_get_database"); +#endif + return(status); +} + +/* +* qla2100_save_database +* Copies and converts driver database to flash database. +* (may sleep) +* +* Input: +* ha = adapter block pointer. +* +* Returns: +* 0 = success. +*/ +STATIC uint8_t +qla2100_save_database(scsi_qla_host_t *ha) { + flash_database_t *fptr; + uint8_t status = 1; + uint32_t addr; + uint16_t cnt; + uint8_t *bptr; + uint8_t checksum; + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_save_database"); +#endif + + if( (fptr = (flash_database_t *)KMALLOC(sizeof(flash_database_t)) ) ) { + /* Enable Flash Read/Write. */ + qla2100_flash_enable(ha); + + fptr->hdr.seq = ++ha->flash_seq; + fptr->hdr.version = FLASH_DATABASE_VERSION; + fptr->hdr.size = sizeof(flash_hdr_t); + + /* Copy and convert driver database to flash database. */ + for( cnt = 0; cnt < MAX_FIBRE_DEVICES; cnt++ ) { + if( ha->fc_db[cnt].loop_id == PORT_UNUSED ) + break; + else { + fptr->node[cnt].name[0] = ha->fc_db[cnt].name[0]; + fptr->node[cnt].name[1] = ha->fc_db[cnt].name[1]; + fptr->hdr.size += sizeof(flash_node_t); + } + } + + /* Calculate checksum. */ + checksum = 0; + bptr = (uint8_t *)fptr; + for( cnt = 0; cnt < fptr->hdr.size; cnt++ ) + checksum += *bptr++; + fptr->hdr.checksum = ~checksum + 1; + + /* Setup next sector address for flash */ + if( ha->flash_db == FLASH_DATABASE_0 ) + addr = FLASH_DATABASE_1; + else + addr = FLASH_DATABASE_0; + ha->flash_db = addr; + + /* Erase flash sector prior to write. */ + status = qla2100_erase_flash_sector(ha, addr); + + /* Write database to flash. */ + bptr = (uint8_t *)fptr; + for( cnt = 0; cnt < fptr->hdr.size && !status; cnt++ ) + status = qla2100_program_flash_address(ha, addr++, *bptr++); + + qla2100_flash_disable(ha); + + KMFREE(fptr, sizeof(flash_database_t)); + } + +#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3) + if( status ) + qla2100_print("qla2100_save_database: **** FAILED ****\n"); +#endif +#ifdef QL_DEBUG_LEVEL_3 + else + LEAVE("qla2100_save_database"); +#endif + return(status); +} + +/* +* qla2100_program_flash_address +* Program flash address. +* +* Input: +* ha = adapter block pointer. +* addr = flash byte address. +* data = data to be written to flash. +* +* Returns: +* 0 = success. +*/ +STATIC uint8_t +qla2100_program_flash_address(scsi_qla_host_t *ha, uint32_t addr, uint8_t data) { + uint8_t status; + + /* Write Program Command Sequence */ + qla2100_write_flash_byte(ha, 0x5555, 0xaa); + qla2100_write_flash_byte(ha, 0x2aaa, 0x55); + qla2100_write_flash_byte(ha, 0x5555, 0xa0); + qla2100_write_flash_byte(ha, addr, data); + + /* Wait for write to complete. */ + status = qla2100_poll_flash(ha, addr, data); + +#ifdef QL_DEBUG_LEVEL_2 + if( status ) + qla2100_print("qla2100_program_flash_address: **** FAILED ****\n"); +#endif + return(status); +} + +/* +* qla2100_erase_flash_sector +* Erases flash sector. +* +* Input: +* ha = adapter block pointer. +* addr = sector address. +* +* Returns: +* 0 = success. +*/ +STATIC uint8_t +qla2100_erase_flash_sector(scsi_qla_host_t *ha, uint32_t addr) { + uint8_t status; + + addr &= 0x1c000; + + /* Individual Sector Erase Command Sequence */ + qla2100_write_flash_byte(ha, 0x5555, 0xaa); + qla2100_write_flash_byte(ha, 0x2aaa, 0x55); + qla2100_write_flash_byte(ha, 0x5555, 0x80); + qla2100_write_flash_byte(ha, 0x5555, 0xaa); + qla2100_write_flash_byte(ha, 0x2aaa, 0x55); + qla2100_write_flash_byte(ha, addr, 0x30); + + SYS_DELAY(150); + + /* Wait for erase to complete. */ + status = qla2100_poll_flash(ha, addr, 0x80); + +#ifdef QL_DEBUG_LEVEL_2 + if( status ) + qla2100_print("qla2100_erase_flash_sector: **** FAILED ****\n"); +#endif + return(status); +} + +/* +* qla2100_poll_flash +* Polls flash for completion. +* +* Input: +* ha = adapter block pointer. +* addr = flash byte address. +* data = data to be polled. +* +* Returns: +* 0 = success. +*/ +STATIC uint8_t +qla2100_poll_flash(scsi_qla_host_t *ha, uint32_t addr, uint8_t poll_data) { + uint8_t status = 1; + uint8_t flash_data; + uint32_t cnt; + + poll_data &= BIT_7; + + /* Wait for 30 seconds for command to finish. */ + for( cnt = 3000000; cnt; cnt-- ) { + flash_data = (uint8_t)qla2100_read_flash_byte(ha, addr); + + if( (flash_data & BIT_7) == poll_data ) { + status = 0; + break; + } + if( flash_data & BIT_5 && cnt > 2 ) + cnt = 2; + SYS_DELAY(10); + } + + return(status); +} + +/* +* qla2100_flash_enable +* Setup flash for reading/writing. +* +* Input: +* ha = adapter block pointer. +*/ +STATIC void +qla2100_flash_enable(scsi_qla_host_t *ha) { + device_reg_t *reg = ha->iobase; + + /* Setup bit 16 of flash address. */ + WRT_REG_WORD(®->nvram, NV_SELECT); + + /* Enable Flash Read/Write. */ + WRT_REG_WORD(®->ctrl_status, ISP_FLASH_ENABLE); + + /* Read/Reset Command Sequence */ + qla2100_write_flash_byte(ha, 0x5555, 0xaa); + qla2100_write_flash_byte(ha, 0x2aaa, 0x55); + qla2100_write_flash_byte(ha, 0x5555, 0xf0); + qla2100_read_flash_byte(ha, FLASH_DATABASE_0); +} + +/* +* qla2100_flash_disable +* Disable flash and allow RISC to run. +* +* Input: +* ha = adapter block pointer. +*/ +STATIC void +qla2100_flash_disable(scsi_qla_host_t *ha) { + device_reg_t *reg = ha->iobase; + + /* Restore chip registers. */ + WRT_REG_WORD(®->ctrl_status, 0); + WRT_REG_WORD(®->nvram, 0); +} + +/* +* qla2100_write_flash_byte +* Write byte to flash. +* +* Input: +* ha = adapter block pointer. +* addr = flash byte address. +* data = data to be written. +*/ +STATIC void +qla2100_write_flash_byte(scsi_qla_host_t *ha, uint32_t addr, uint8_t data) { + device_reg_t *reg = ha->iobase; + + WRT_REG_WORD(®->flash_address, (uint16_t)addr); + WRT_REG_WORD(®->flash_data, (uint16_t)data); +} + +/* +* qla2100_read_flash_byte +* Reads byte from flash, but must read a word from chip. +* +* Input: +* ha = adapter block pointer. +* addr = flash byte address. +* +* Returns: +* byte from flash. +*/ +STATIC uint16_t +qla2100_read_flash_byte(scsi_qla_host_t *ha, uint32_t addr) { + device_reg_t *reg = ha->iobase; + uint16_t data; + + WRT_REG_WORD(®->flash_address, (uint16_t)addr); + data = qla2100_debounce_register(®->flash_data); + + return(data); +} +#endif + +/* +* qla2100_reset_adapter +* Reset adapter. +* +* Input: +* ha = adapter block pointer. +*/ +STATIC void +qla2100_reset_adapter(scsi_qla_host_t *ha) { + device_reg_t *reg = ha->iobase; + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_reset_adapter"); +#endif + + ha->flags.online = FALSE; + qla2100_disable_intrs(ha); + /* WRT_REG_WORD(®->ictrl, 0); */ + /* Reset RISC processor. */ + WRT_REG_WORD(®->host_cmd, HC_RESET_RISC); + WRT_REG_WORD(®->host_cmd, HC_RELEASE_RISC); +#ifdef QL_DEBUG_LEVEL_3 + LEAVE("qla2100_reset_adapter"); +#endif +} + +/* +* qla2100_loop_reset +* Issue loop reset. +* +* Input: +* ha = adapter block pointer. +* +* Returns: +* 0 = success +*/ +STATIC uint8_t +qla2100_loop_reset(scsi_qla_host_t *ha) { + uint8_t status = 0; + uint16_t mb[MAILBOX_REGISTER_COUNT]; + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_loop_reset"); +#endif + + if( ha->flags.enable_lip_reset ) { + mb[0] = MBC_LIP_RESET; + mb[1] = 0xff00; + mb[2] = ha->loop_reset_delay; + status |= qla2100_mailbox_command(ha, BIT_2|BIT_1|BIT_0, &mb[0]); + } + if( ha->flags.enable_target_reset ) { + mb[0] = MBC_TARGET_RESET; + mb[1] = ha->loop_reset_delay; + status |= qla2100_mailbox_command(ha, BIT_1|BIT_0, &mb[0]); + } + if( (!ha->flags.enable_target_reset && !ha->flags.enable_lip_reset ) || + ha->flags.enable_lip_full_login ) { + mb[0] = MBC_LIP_FULL_LOGIN; + status |= qla2100_mailbox_command(ha, BIT_0, &mb[0]); + } + + /* Issue marker command. */ + qla2100_marker(ha, 0, 0, 0, MK_SYNC_ALL); + +#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3) + if( status ) + qla2100_print("qla2100_loop_reset: **** FAILED ****\n"); +#endif +#ifdef QL_DEBUG_LEVEL_3 + else + LEAVE("qla2100_loop_reset"); +#endif + return(status); +} + +/* +* qla2100_device_reset +* Issue bus device reset message to the target. +* +* Input: +* ha = adapter block pointer. +* b = BUS number. +* t = SCSI ID. +* +* Returns: +* 0 = success +*/ +STATIC uint8_t +qla2100_device_reset(scsi_qla_host_t *ha, uint32_t b, uint32_t t) { + tgt_t *tgt; + uint8_t status; + uint16_t mb[MAILBOX_REGISTER_COUNT]; + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_device_reset"); +#endif + + tgt = TGT_Q(ha, b, t); + + mb[0] = MBC_ABORT_TARGET; + mb[1] = tgt->loop_id << 8; + mb[2] = 1; + status = qla2100_mailbox_command(ha, BIT_2|BIT_1|BIT_0, &mb[0]); + + /* Issue marker command. */ + qla2100_marker(ha, b, t, 0, MK_SYNC_ID); + +#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3) + if( status ) + qla2100_print("qla2100_device_reset: **** FAILED ****\n"); +#endif +#ifdef QL_DEBUG_LEVEL_3 + else + LEAVE("qla2100_device_reset"); +#endif + return(status); +} + +/* +* qla2100_abort_device +* Issue an abort message to the device +* +* Input: +* ha = adapter block pointer. +* b = BUS number. +* t = SCSI ID. +* l = SCSI LUN. +* +* Returns: +* 0 = success +*/ +STATIC uint8_t +qla2100_abort_device(scsi_qla_host_t *ha, uint32_t b, uint32_t t, uint32_t l) { + tgt_t *tgt; + uint8_t status; + uint16_t mb[MAILBOX_REGISTER_COUNT]; + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_abort_device"); +#endif + + tgt = TGT_Q(ha, b, t); + + mb[0] = MBC_ABORT_DEVICE; + mb[1] = tgt->loop_id << 8; + mb[2] = l; + status = qla2100_mailbox_command(ha, BIT_2|BIT_1|BIT_0, &mb[0]); + + /* Issue marker command. */ + qla2100_marker(ha, b, t, l, MK_SYNC_ID_LUN); + +#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3) + if( status ) + qla2100_print("qla2100_abort_device: **** FAILED ****\n"); +#endif +#ifdef QL_DEBUG_LEVEL_3 + else + LEAVE("qla2100_abort_device"); +#endif + return(status); +} + +/* +* qla2100_abort_command +* Abort command aborts a specified IOCB. +* +* Input: +* ha = adapter block pointer. +* sp = SB structure pointer. +* +* Returns: +* 0 = success +*/ +STATIC uint8_t +qla2100_abort_command(scsi_qla_host_t *ha, srb_t *sp) { + uint8_t status; + uint16_t mb[MAILBOX_REGISTER_COUNT]; + uint32_t b, t, l; + uint32_t handle; + tgt_t *tgt; + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_abort_command"); +#endif + /* v2.19.8 */ + t = SCSI_TCN_32(sp->cmd); + if( ha->loop_state == LOOP_DOWN || + PORT_DOWN(ha,t) > 0 ) { + return(0); + } + + /* Locate handle number. */ + for( handle = 0; handle < MAX_OUTSTANDING_COMMANDS; handle++ ) + if( ha->outstanding_cmds[handle] == sp ) + break; + + DEBUG(qla2100_print("qla2100_abort_command: Sending Abort Command for Handle = ");) + DEBUG(qla2100_output_number((u_long) handle, 16);) + DEBUG(qla2100_print("\n");) + + /* Get a pointer to the SCSI address */ + b = SCSI_BUS_32(sp->cmd); + l = SCSI_LUN_32(sp->cmd); + + tgt = TGT_Q(ha, b, t); + + mb[0] = MBC_ABORT_COMMAND; + mb[1] = tgt->loop_id << 8; + mb[2] = (uint16_t)handle; + mb[3] = handle >> 16; + mb[6] = l; + if( !(status = qla2100_mailbox_command(ha, BIT_6|BIT_3|BIT_2|BIT_1|BIT_0, + &mb[0])) ) + sp->flags |= SRB_ABORT_PENDING; + + +#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3) + if( status ) + qla2100_print("qla2100_abort_command: **** FAILED ****\n"); +#endif +#ifdef QL_DEBUG_LEVEL_3 + else + LEAVE("qla2100_abort_command"); +#endif + return(status); +} + +/* +* Issue marker command. +* Function issues marker IOCB. +* +* Input: +* ha = adapter block pointer. +* b = BUS number. +* t = SCSI ID +* l = SCSI LUN +* type = marker modifier +*/ +STATIC void +qla2100_marker(scsi_qla_host_t *ha, uint32_t b, uint32_t t, uint32_t l, uint8_t type) { + mrk_entry_t *pkt; + tgt_t *tgt; + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_marker"); +#endif + + tgt = TGT_Q(ha, b, t); + + /* Get request packet. */ + if( (pkt = (mrk_entry_t *)qla2100_req_pkt(ha) ) ) { + pkt->entry_type = MARKER_TYPE; + pkt->modifier = type; + + if( type == MK_SYNC_LIP ) + pkt->sequence_number = ha->lip_seq; + else if( type != MK_SYNC_ALL ) { + pkt->lun = l; + pkt->target = (uint8_t)tgt->loop_id; + } + + /* Issue command to ISP */ + qla2100_isp_cmd(ha); + } + +#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3) + if( !pkt ) + qla2100_print("qla2100_marker: **** FAILED ****\n"); +#endif +#ifdef QL_DEBUG_LEVEL_3 + else + LEAVE("qla2100_marker"); +#endif +} + +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,3,18) +/* +* qla2100_64bit_start_scsi +* The start SCSI is responsible for building request packets on +* request ring and modifying ISP input pointer. +* +* Input: +* ha = adapter block pointer. +* sp = SB structure pointer. +* +* Returns: +* 0 = success, was able to issue command. +*/ +STATIC uint8_t +qla2100_64bit_start_scsi(scsi_qla_host_t *ha, srb_t *sp) { + device_reg_t *reg = ha->iobase; + device2300_reg_t *reg2300 = ha->iobase2300; + uint8_t status = 0; + Scsi_Cmnd *cmd = sp->cmd; + uint32_t cnt; + cmd_a64_entry_t *pkt; + uint16_t req_cnt; + uint16_t seg_cnt; + uint16_t cdb_len,temp; + struct scatterlist *sg = (struct scatterlist *) NULL; + uint32_t timeout; + caddr_t data_ptr; + uint32_t *dword_ptr; + uint64_t dma_handle; + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_64bit_start_scsi:"); +#endif + DEBUG(sprintf(debug_buff, + "64bit_start: cmd=%x sp=%x CDB=%x\n\r",cmd,sp,cmd->cmnd[0]);) + DEBUG(qla2100_print(debug_buff)); + + /* Calculate number of entries and segments required. */ + seg_cnt = 0; + req_cnt = 1; + if ( cmd->use_sg ) { + /* 4.10 64 bit S/G Data Transfer */ + sg = (struct scatterlist *) cmd->request_buffer; + seg_cnt = pci_map_sg(ha->pdev, + sg,cmd->use_sg, + scsi_to_pci_dma_dir(cmd->sc_data_direction)); + + if( seg_cnt > 2 ) { + req_cnt += (uint16_t)(seg_cnt - 2) / 5; + if( (uint16_t)(seg_cnt - 2) % 5 ) + req_cnt++; + } + } else if( cmd->request_bufflen ) + { /* no S/G Data Transfer */ + /* DEBUG5(printk("Single data transfer (0x%x)\n", + cmd->request_bufflen)); */ + seg_cnt = 1; + } + + /* Acquire ring specific lock */ + QLA2100_RING_LOCK(ha); + + if( (uint16_t)(req_cnt + 2) >= ha->req_q_cnt ) { + /* Calculate number of free request q out entries. */ + if (ha->device_id == QLA2300_DEVICE_ID) cnt = RD_REG_WORD(®2300->req_q_out); + else cnt = RD_REG_WORD(®->mailbox4); + if( ha->req_ring_index < cnt ) + ha->req_q_cnt = cnt - ha->req_ring_index; + else + ha->req_q_cnt = REQUEST_ENTRY_CNT - (ha->req_ring_index - cnt); + } + + /* If room for request in request ring. */ + if( (uint16_t)(req_cnt + 2) < ha->req_q_cnt ) { + /* Check for room in outstanding command list. */ + for( cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS && + ha->outstanding_cmds[cnt] != 0; cnt++ ) + ; + + if( cnt < MAX_OUTSTANDING_COMMANDS ) { + ha->outstanding_cmds[cnt] = sp; + ha->req_q_cnt -= req_cnt; + CMD_HANDLE(sp->cmd) = (unsigned char *) (u_long) cnt; + + /* + * Build command packet. + */ + pkt = ha->request_ring_ptr; + + pkt->entry_type = COMMAND_A64_TYPE; + pkt->entry_count = (uint8_t)req_cnt; + pkt->sys_define = (uint8_t)ha->req_ring_index; + pkt->control_flags= 0; + pkt->entry_status = 0; + pkt->handle = (uint32_t)cnt; + + /* Zero out remaining portion of packet. */ + dword_ptr = (uint32_t *)pkt + 2; + for( cnt = 2; cnt < REQUEST_ENTRY_SIZE/4; cnt++ ) + *dword_ptr++ = 0; + + /* + * We subtract 2 sec. from the timeout value to insure + * the ISP time-out before the mid-level or the driver. + */ + timeout = (uint32_t) CMD_TIMEOUT(cmd)/HZ; + if( timeout > 2 ) + pkt->timeout = (uint16_t) timeout - 2; + else + pkt->timeout = (uint16_t) timeout; + + /* Set device target ID and LUN */ + pkt->target = TGT_Q(ha, SCSI_BUS_32(cmd), + SCSI_TCN_32(cmd))->loop_id; + pkt->lun = SCSI_LUN_32(cmd); + + /* Enable simple tag queuing if device supports it. */ + if ( cmd->device->tagged_queue ) { + switch (cmd->tag) { + case SIMPLE_QUEUE_TAG: + pkt->control_flags = CF_SIMPLE_TAG; + break; + case HEAD_OF_QUEUE_TAG: + pkt->control_flags = CF_HEAD_TAG; + break; + case ORDERED_QUEUE_TAG: + pkt->control_flags = CF_ORDERED_TAG; + break; + default: + pkt->control_flags = CF_SIMPLE_TAG; + } + } else + pkt->control_flags = CF_SIMPLE_TAG; + + if (ha->device_id == QLA2300_DEVICE_ID) + pkt->control_flags |= CF_NO_FAST_POSTING; + + /* Load SCSI command packet. */ + cdb_len = (uint16_t)CMD_CDBLEN(cmd); + if (cdb_len > MAX_CMDSZ) cdb_len = MAX_CMDSZ; + data_ptr = (uint8_t *) &(CMD_CDBP(cmd)); + for( cnt = 0; cnt < cdb_len; cnt++ ) + pkt->scsi_cdb[cnt] = *data_ptr++; + pkt->byte_count = (uint32_t) CMD_XFRLEN(cmd); + + /* + * Load data segments. + */ + if( seg_cnt ) /* If data transfer. */ + { + switch( cmd->data_cmnd[0] ) { + case FORMAT_UNIT: + case WRITE_6: + case MODE_SELECT: + case SEND_DIAGNOSTIC: + case WRITE_10: + case WRITE_BUFFER: + case WRITE_LONG: + case WRITE_SAME: + case MODE_SELECT_10: + case WRITE_12: + case WRITE_VERIFY_12: + case SEND_VOLUME_TAG: + pkt->control_flags |= BIT_6; /* WRITE */ + break; + default: +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0) +#if QLA_SCSI_VENDOR_DIR + qla2100_set_vend_direction(ha, cmd, pkt); +#else + pkt->control_flags |= BIT_5; /* READ */ +#endif +#else /* kernel version is 2.4.0 or higher */ + if (cmd->sc_data_direction == SCSI_DATA_WRITE) + pkt->control_flags |= BIT_6;/*WRITE*/ + else + pkt->control_flags |= BIT_5;/*READ*/ +#endif /* kernel version 2.4.0 */ + break; + } + sp->dir = pkt->control_flags & (BIT_5|BIT_6); + + /* Set total data segment count. */ + pkt->dseg_count = seg_cnt; + + /* Setup packet address segment pointer. */ + dword_ptr = (uint32_t *)&pkt->dseg_0_address; + + if( cmd->use_sg ) /* If scatter gather */ + { + /* Load command entry data segments. */ + for( cnt = 0; cnt < 2 && seg_cnt; cnt++, seg_cnt-- ) { + /* 4.10 64 bit */ + *dword_ptr++ = cpu_to_le32(pci_dma_lo32(sg_dma_address(sg))); + *dword_ptr++ = cpu_to_le32(pci_dma_hi32(sg_dma_address(sg))); + *dword_ptr++ = cpu_to_le32(sg_dma_len(sg)); + sg++; + /* DEBUG(sprintf(debug_buff, + "S/G Segment phys_addr=%x %x, len=0x%x\n\r", + cpu_to_le32(pci_dma_hi32(sg_dma_address(sg))), + cpu_to_le32(pci_dma_lo32(sg_dma_address(sg))), + cpu_to_le32(sg_dma_len(sg)));) + DEBUG(qla2100_print(debug_buff)); */ + } +#ifdef QL_DEBUG_LEVEL_5 + qla2100_print( + "qla2x00_64bit_start_scsi: Scatter/gather command packet data - "); + qla2100_print("b"); + qla2100_output_number((uint32_t)SCSI_BUS_32(cmd), 10); + qla2100_print("t"); + qla2100_output_number((uint32_t)SCSI_TCN_32(cmd), 10); + qla2100_print("d"); + qla2100_output_number((uint32_t)SCSI_LUN_32(cmd), 10); + qla2100_print("\n\r"); + qla2100_dump_buffer((caddr_t)pkt, REQUEST_ENTRY_SIZE); +#endif + /* + * Build continuation packets. + */ + while( seg_cnt > 0 ) { + /* Adjust ring index. */ + ha->req_ring_index++; + if( ha->req_ring_index == REQUEST_ENTRY_CNT ) { + ha->req_ring_index = 0; + ha->request_ring_ptr = ha->request_ring; + } else + ha->request_ring_ptr++; + + pkt = (cmd_a64_entry_t *)ha->request_ring_ptr; + + /* Zero out packet. */ + dword_ptr = (uint32_t *)pkt; + for( cnt = 0;cnt < REQUEST_ENTRY_SIZE/4; cnt++ ) + *dword_ptr++ = 0; + + /* Load packet defaults. */ + ((cont_a64_entry_t *)pkt)->entry_type = + CONTINUE_A64_TYPE; + ((cont_a64_entry_t *)pkt)->entry_count = 1; + ((cont_a64_entry_t *)pkt)->sys_define = (uint8_t) + ha->req_ring_index; + + /* Setup packet address segment pointer. */ + dword_ptr = (uint32_t *) + &((cont_a64_entry_t *)pkt)->dseg_0_address; + + /* Load continuation entry data segments. */ + for( cnt = 0; cnt < 5 && seg_cnt; cnt++, seg_cnt-- ) { + /* 4.10 64 bit */ + *dword_ptr++ = cpu_to_le32(pci_dma_lo32(sg_dma_address(sg))); + *dword_ptr++ = cpu_to_le32(pci_dma_hi32(sg_dma_address(sg))); + *dword_ptr++ = cpu_to_le32(sg_dma_len(sg)); + sg++; + /* DEBUG(sprintf(debug_buff, + "S/G Segment Cont. phys_addr=%x %x, len=0x%x\n\r", + cpu_to_le32(pci_dma_hi32(sg_dma_address(sg))), + cpu_to_le32(pci_dma_lo32(sg_dma_address(sg))), + cpu_to_le32(sg_dma_len(sg)));) + DEBUG(qla2100_print(debug_buff)); */ + } +#ifdef QL_DEBUG_LEVEL_5 + qla2100_print( + "qla2x00_64bit_start_scsi: continuation packet data - c"); + qla2100_print("b"); + qla2100_output_number((u_long)SCSI_BUS_32(cmd), 10); + + qla2100_print("t"); + qla2100_output_number((u_long)SCSI_TCN_32(cmd), 10); + qla2100_print("d"); + qla2100_output_number((u_long)SCSI_LUN_32(cmd), 10); + qla2100_print("\n\r"); + qla2100_dump_buffer((caddr_t)pkt, REQUEST_ENTRY_SIZE); +#endif + } + } else /* No scatter gather data transfer */ + { /* 4.10 64 bit */ + dma_handle = pci_map_single(ha->pdev, + cmd->request_buffer, + cmd->request_bufflen, + scsi_to_pci_dma_dir(cmd->sc_data_direction)); + /* save dma_handle for pci_unmap_single */ + sp->saved_dma_handle = dma_handle; + + *dword_ptr++ = cpu_to_le32(pci_dma_lo32(dma_handle)); + *dword_ptr++ = cpu_to_le32(pci_dma_hi32(dma_handle)); + *dword_ptr = (uint32_t) cmd->request_bufflen; + /* DEBUG(sprintf(debug_buff, + "64_bit: No S/G map_single saved_dma_handle=%lx len=%x \n\r",dma_handle, cmd->request_bufflen)); + DEBUG(qla2100_print(debug_buff)); */ +#ifdef QL_DEBUG_LEVEL_5 + qla2100_print( + "qla2x00_64bit_start_scsi: No scatter/gather command packet data - c"); + qla2100_print("b"); + qla2100_output_number((uint32_t)SCSI_BUS_32(cmd), 10); + qla2100_print("t"); + qla2100_output_number((uint32_t)SCSI_TCN_32(cmd), 10); + qla2100_print("d"); + qla2100_output_number((uint32_t)SCSI_LUN_32(cmd), 10); + qla2100_print("\n\r"); + qla2100_dump_buffer((caddr_t)pkt, REQUEST_ENTRY_SIZE); +#endif + } + } + else /* No data transfer */ + { + *dword_ptr++ = (uint32_t) 0; + *dword_ptr++ = (uint32_t) 0; + *dword_ptr = (uint32_t) 0; +#ifdef QL_DEBUG_LEVEL_5 + qla2100_print( + "qla2x00_64bit_start_scsi: No data, command packet data - c"); + qla2100_print("b"); + qla2100_output_number((u_long)SCSI_BUS_32(cmd), 10); + qla2100_print("t"); + qla2100_output_number((u_long)SCSI_TCN_32(cmd), 10); + qla2100_print("d"); + qla2100_output_number((u_long)SCSI_LUN_32(cmd), 10); + qla2100_print("\n\r"); + qla2x00_dump_buffer((caddr_t)pkt, REQUEST_ENTRY_SIZE); +#endif + } + DEBUG4(qla2100_print("\nqla2100_64bit_start_scsi: Wakeup RISC for pending command\n\r")); + /* Adjust ring index. */ + ha->req_ring_index++; + if( ha->req_ring_index == REQUEST_ENTRY_CNT ) { + ha->req_ring_index = 0; + ha->request_ring_ptr = ha->request_ring; + } else + ha->request_ring_ptr++; + + /* Set chip new ring index. */ +#if WATCH_THREADS_SIZE + DEBUG3(qla2100_output_number((uint32_t)ha->actthreads, 16)); +#endif + if (ha->device_id == QLA2300_DEVICE_ID) { + temp = CACHE_FLUSH(®2300->req_q_in); + WRT_REG_WORD(®2300->req_q_in, ha->req_ring_index); + } else { + temp = CACHE_FLUSH(®->mailbox4); + WRT_REG_WORD(®->mailbox4, ha->req_ring_index); + } + } else { + status = 1; +#ifdef QL_DEBUG_LEVEL_2 + qla2100_print( + "qla2x00_64bit_start_scsi: NO ROOM IN OUTSTANDING ARRAY\n\r"); + qla2100_print(" req_q_cnt="); + qla2100_output_number((u_long)ha->req_q_cnt, 16); +#endif + } + } else { + status = 1; +#ifdef QL_DEBUG_LEVEL_2 + qla2100_print("qla2x00_64bit_start_scsi: in-ptr="); + qla2100_output_number((u_long)ha->req_ring_index, 16); + qla2100_print(" req_q_cnt="); + qla2100_output_number((u_long)ha->req_q_cnt, 16); + qla2100_print(" req_cnt="); + qla2100_output_number((u_long)req_cnt, 16); + qla2100_print("\n\r"); +#endif + } + + /* Release ring specific lock */ + QLA2100_RING_UNLOCK(ha); + +#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3) + if( status ) + qla2100_print("qla2x00_64bit_start_scsi: **** FAILED ****\n\r"); +#endif +#ifdef QL_DEBUG_LEVEL_3 + else + qla2100_print("qla2x00_64bit_start_scsi: exiting normally\n\r"); +#endif + return(status); +} +#endif + +/* +* qla2100_32bit_start_scsi +* The start SCSI is responsible for building request packets on +* request ring and modifying ISP input pointer. +* +* The Qlogic firmware interface allows every queue slot to have a SCSI +* command and up to 4 scatter/gather (SG) entries. If we need more +* than 4 SG entries, then continuation entries are used that can +* hold another 7 entries each. The start routine determines if there +* is eought empty slots then build the combination of requests to +* fulfill the OS request. +* +* Input: +* ha = adapter block pointer. +* sp = SCSI Request Block structure pointer. +* +* Returns: +* 0 = success, was able to issue command. +*/ +STATIC uint8_t +qla2100_32bit_start_scsi(scsi_qla_host_t *ha, srb_t *sp) { + device_reg_t *reg = ha->iobase; + device2300_reg_t *reg2300 = ha->iobase2300; + uint8_t status = 0; + Scsi_Cmnd *cmd = sp->cmd; + uint16_t cdb_len, temp; + uint32_t cnt; + cmd_entry_t *pkt; + uint16_t req_cnt; + uint16_t seg_cnt; + struct scatterlist *sg = (struct scatterlist *) NULL; + caddr_t data_ptr; + uint32_t *dword_ptr; + uint32_t timeout; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,18) + uint64_t dma_handle; +#endif + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_32bit_start_scsi"); +#endif + +#if defined(QL_DEBUG_LEVEL_5) || defined(QL_DEBUG_LEVEL_3) + printk( + "32bit_start BEGIN: cmd=%x sp=%x CDB=%x\n\r", + cmd,sp,cmd->cmnd[0]); +#endif +#ifdef NEW + /* + * Send marker if required. + */ + if (ha->marker_needed != 0) { + if (qla2200_marker(ha, 0, 0, MK_SYNC_ALL) != 0) { + RING_UNLOCK(ha); + return (1); + } + } +#endif + COMTRACE('S') + /* Calculate number of entries and segments required. */ + seg_cnt = 0; + req_cnt = 1; + if( cmd->use_sg ) { + sg = (struct scatterlist *) cmd->request_buffer; + /* 4.10 32 bit S/G Data Transfer */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18) + seg_cnt = cmd->use_sg; +#else + seg_cnt = pci_map_sg(ha->pdev,sg,cmd->use_sg, + scsi_to_pci_dma_dir(cmd->sc_data_direction)); +#endif + /* + * if greater than four sg entries then we need to allocate + * continuation entries + */ + if( seg_cnt > 2 ) { + req_cnt += (uint16_t)(seg_cnt - 3) / 7; + if( (uint16_t)(seg_cnt - 3) % 7 ) + req_cnt++; + } + DEBUG5(sprintf(debug_buff, + "S/G for data transfer -num segs(%d), req blk cnt(%d)\n\r",seg_cnt,req_cnt)); + DEBUG5(qla2100_print(debug_buff)); + } else if( CMD_XFRLEN(cmd) ) /* If data transfer. */ + { /* no S/G Data Transfer */ + /* DEBUG5(printk("Single data transfer (0x%x)\n", + cmd->request_bufflen));*/ + seg_cnt = 1; + } + + /* Acquire ring specific lock */ + QLA2100_RING_LOCK(ha); + + if( (uint16_t)(req_cnt + 2) >= ha->req_q_cnt ) { + /* Calculate number of free request entries. */ + if (ha->device_id == QLA2300_DEVICE_ID) + cnt = qla2100_debounce_register(®2300->req_q_out); + else + cnt = qla2100_debounce_register(®->mailbox4); + + if( ha->req_ring_index < cnt ) + ha->req_q_cnt = cnt - ha->req_ring_index; + else + ha->req_q_cnt = REQUEST_ENTRY_CNT - (ha->req_ring_index - cnt); + } + + DEBUG5(sprintf(debug_buff, + "Number of free entries = (%d)\n\r",ha->req_q_cnt)); + DEBUG5(qla2100_print(debug_buff)); + /* If room for request in request ring. */ + if( (uint16_t)(req_cnt + 2) < ha->req_q_cnt ) { + /* Check for room in outstanding command list. */ + for( cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS && + (ha->outstanding_cmds[cnt] != 0); cnt++ ) + ; + + if( cnt < MAX_OUTSTANDING_COMMANDS ) { + ha->outstanding_cmds[cnt] = sp; + ha->req_q_cnt -= req_cnt; + /* save the handle -- helps if we want to abort it */ + CMD_HANDLE(sp->cmd) = (unsigned char *) (u_long) cnt; + + /* + * Build command packet. + */ + pkt = (cmd_entry_t *)ha->request_ring_ptr; + + pkt->entry_type = COMMAND_TYPE; + pkt->entry_count = (uint8_t)req_cnt; + pkt->sys_define = (uint8_t)ha->req_ring_index; + pkt->entry_status = 0; + pkt->control_flags= 0; + pkt->handle = (uint32_t)cnt; + + /* Zero out remaining portion of packet. */ + dword_ptr = (uint32_t *)pkt + 2; + for( cnt = 2; cnt < REQUEST_ENTRY_SIZE/4; cnt++ ) + *dword_ptr++ = 0; + + /* + * v2.19.8 + * We subtract 5 sec. from the timeout value to insure + * the ISP time-out before the mid-level or the driver. + */ + timeout = (uint32_t) CMD_TIMEOUT(cmd)/HZ; + if( timeout > 5 ) + pkt->timeout = (uint16_t) timeout - 5; + else + pkt->timeout = (uint16_t) timeout; + + /* Set device target ID and LUN */ + pkt->target = TGT_Q(ha, + SCSI_BUS_32(cmd), SCSI_TCN_32(cmd))->loop_id; + pkt->lun = SCSI_LUN_32(cmd); + + /* Enable simple tag queuing if device supports it. */ + if ( cmd->device->tagged_queue ) { + switch (cmd->tag) { + case SIMPLE_QUEUE_TAG: + pkt->control_flags = CF_SIMPLE_TAG; + break; + case HEAD_OF_QUEUE_TAG: + pkt->control_flags = CF_HEAD_TAG; + break; + case ORDERED_QUEUE_TAG: + pkt->control_flags = CF_ORDERED_TAG; + break; + default: + pkt->control_flags = CF_SIMPLE_TAG; + } + } else + pkt->control_flags = CF_SIMPLE_TAG; + + if (ha->device_id == QLA2300_DEVICE_ID) + pkt->control_flags |= CF_NO_FAST_POSTING; + + /* Load SCSI command packet. */ + cdb_len = (uint16_t)CMD_CDBLEN(cmd); + if( cdb_len > MAX_CMDSZ ) + cdb_len = MAX_CMDSZ; + data_ptr = (uint8_t *) &(CMD_CDBP(cmd)); + for( cnt = 0; cnt < cdb_len; cnt++ ) + pkt->scsi_cdb[cnt] = *data_ptr++; + DEBUG3(sprintf(debug_buff, + "qla2100: Packet has command[0]=0x%x, hndl=0x%x\n",pkt->scsi_cdb[0],pkt->handle);) + DEBUG3(qla2100_print(debug_buff);) + pkt->byte_count = (uint32_t) CMD_XFRLEN(cmd); + + /* + * Load data segments. + */ + if( seg_cnt ) { + /* Set transfer direction (READ and WRITE) */ + /* Linux doesn't tell us */ + + switch( cmd->data_cmnd[0] ) { + case FORMAT_UNIT: + case WRITE_6: + case MODE_SELECT: + case SEND_DIAGNOSTIC: + case WRITE_10: + case WRITE_BUFFER: + case WRITE_LONG: + case WRITE_SAME: + case MODE_SELECT_10: + case WRITE_12: + case WRITE_VERIFY_12: + case SEND_VOLUME_TAG: + pkt->control_flags |= BIT_6; /* WRITE */ + break; + default: +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0) +#if QLA_SCSI_VENDOR_DIR + qla2100_set_vend_direction(ha, cmd, pkt); +#else + pkt->control_flags |= BIT_5; /* READ */ +#endif +#else /* kernel version is 2.4.0 or higher */ + if (cmd->sc_data_direction == SCSI_DATA_WRITE) + pkt->control_flags |= BIT_6;/*WRITE*/ + else + pkt->control_flags |= BIT_5;/*READ*/ +#endif /* kernel version 2.4.0 */ + break; + } + sp->dir = pkt->control_flags & (BIT_5|BIT_6); + + /* Set total data segment count. */ + pkt->dseg_count = seg_cnt; + + /* Setup packet address segment pointer. */ + dword_ptr = (uint32_t *)&pkt->dseg_0_address; + + if( cmd->use_sg ) /* If scatter gather */ + { + DEBUG5(qla2100_print("Building S/G data segments..\n\r")); + DEBUG5(qla2100_dump_buffer((caddr_t)sg, 4*16)); + /* Load command entry data segments. */ + for( cnt = 0; cnt < 3 && seg_cnt; cnt++, seg_cnt-- ) { +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18) + *dword_ptr++ = (uint32_t) cpu_to_le32(VIRT_TO_BUS(sg->address)); + *dword_ptr++ = sg->length; + /* DEBUG(sprintf(debug_buff, + "S/G Segment phys_addr=0x%x, len=0x%x\n\r", + cpu_to_le32(VIRT_TO_BUS(sg->address)),sg->length)); + DEBUG(qla2100_print(debug_buff)); */ +#else + *dword_ptr++ = cpu_to_le32(pci_dma_lo32(sg_dma_address(sg))); + *dword_ptr++ = cpu_to_le32(sg_dma_len(sg)); + /* DEBUG(sprintf(debug_buff, + "S/G Segment phys_addr=0x%x, len=0x%x\n\r", + cpu_to_le32(pci_dma_lo32(sg_dma_address(sg))), + cpu_to_le32(sg_dma_len(sg)));) + DEBUG(qla2100_print(debug_buff)); */ +#endif + sg++; + } +#ifdef QL_DEBUG_LEVEL_5 + qla2100_print( + "qla2100_32bit_start_scsi: Scatter/gather command packet data - "); + qla2100_output_number((u_long)ha->host_no, 10); + qla2100_print(":"); + qla2100_output_number((u_long)SCSI_BUS_32(cmd), 10); + qla2100_print(":"); + qla2100_output_number((u_long)SCSI_TCN_32(cmd), 10); + qla2100_print(":"); + qla2100_output_number((u_long)SCSI_LUN_32(cmd), 10); + qla2100_print("\n"); + qla2100_dump_buffer((uint8_t *)pkt, REQUEST_ENTRY_SIZE); +#endif + /* + * Build continuation packets. + */ + while( seg_cnt > 0 ) { + /* Adjust ring index. */ + ha->req_ring_index++; + if( ha->req_ring_index == REQUEST_ENTRY_CNT ) { + ha->req_ring_index = 0; + ha->request_ring_ptr = ha->request_ring; + } else + ha->request_ring_ptr++; + + pkt = (cmd_entry_t *)ha->request_ring_ptr; + + /* Zero out packet. */ + dword_ptr = (uint32_t *)pkt; + for( cnt = 0;cnt < REQUEST_ENTRY_SIZE/4; cnt++ ) + *dword_ptr++ = 0; + + /* Load packet defaults. */ + ((cont_entry_t *)pkt)->entry_type = CONTINUE_TYPE; + ((cont_entry_t *)pkt)->entry_count = 1; + ((cont_entry_t *)pkt)->sys_define = (uint8_t) + ha->req_ring_index; + + /* Setup packet address segment pointer. */ + dword_ptr = (uint32_t *) + &((cont_entry_t *)pkt)->dseg_0_address; + + /* Load continuation entry data segments. */ + for( cnt = 0; cnt < 7 && seg_cnt; cnt++, seg_cnt-- ) { + /* 4.10 32 bit */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18) + *dword_ptr++ = (u_int) cpu_to_le32(VIRT_TO_BUS(sg->address)); + *dword_ptr++ = sg->length; + /* DEBUG(sprintf(debug_buff, + "S/G Segment Cont. phys_addr=0x%x, len=0x%x\n\r", + cpu_to_le32(pci_dma_lo32(VIRT_TO_BUS(sg->address))),sg->length);) + DEBUG(qla2100_print(debug_buff)); */ +#else + *dword_ptr++ = cpu_to_le32(pci_dma_lo32(sg_dma_address(sg))); + *dword_ptr++ = cpu_to_le32(sg_dma_len(sg)); + /* DEBUG(sprintf(debug_buff, + "S/G Segment Cont. phys_addr=0x%x, len=0x%x\n\r", + cpu_to_le32(pci_dma_lo32(sg_dma_address(sg))), + cpu_to_le32(sg_dma_len(sg)));) + DEBUG(qla2100_print(debug_buff)); */ +#endif + sg++; + } +#ifdef QL_DEBUG_LEVEL_5 + qla2100_print( + "qla2100_32bit_start_scsi: continuation packet data - "); + qla2100_output_number((u_long)ha->host_no, 10); + qla2100_print(":"); + qla2100_output_number((u_long)SCSI_BUS_32(cmd), 10); + qla2100_print(":"); + qla2100_output_number((u_long)SCSI_TCN_32(cmd), 10); + qla2100_print(":"); + qla2100_output_number((u_long)SCSI_LUN_32(cmd), 10); + qla2100_print("\n"); + qla2100_dump_buffer((uint8_t *)pkt, + REQUEST_ENTRY_SIZE); +#endif + } + } else /* No scatter gather data transfer */ + { + /* 4.10 32 bit */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18) + *dword_ptr++ = (uint32_t) cpu_to_le32(VIRT_TO_BUS(cmd->request_buffer)); + *dword_ptr = (uint32_t) cmd->request_bufflen; +#else + dma_handle = pci_map_single(ha->pdev, + cmd->request_buffer, + cmd->request_bufflen, + scsi_to_pci_dma_dir(cmd->sc_data_direction)); + sp->saved_dma_handle = dma_handle; + + *dword_ptr++ = cpu_to_le32(pci_dma_lo32(dma_handle)); + *dword_ptr = (uint32_t) cmd->request_bufflen; + /* DEBUG(sprintf(debug_buff, + "32_bit: No S/G map_single dma_handle=%lx len=%x\n\r",dma_handle,cmd->request_bufflen)); + DEBUG(qla2100_print(debug_buff)); */ +#endif + /* DEBUG5(printk("Single Segment ap=0x%x, len=0x%x\n",cmd->request_buffer,cmd->request_bufflen));*/ + +#ifdef QL_DEBUG_LEVEL_5 + qla2100_print("qla2100_32bit_start_scsi: No scatter/gather command packet data - "); + qla2100_output_number((u_long)ha->host_no, 10); + qla2100_print(":"); + qla2100_output_number((u_long)SCSI_BUS_32(cmd), 10); + qla2100_print(":"); + qla2100_output_number((u_long)SCSI_TCN_32(cmd), 10); + qla2100_print(":"); + qla2100_output_number((u_long)SCSI_LUN_32(cmd), 10); + qla2100_print("\n"); + qla2100_dump_buffer((uint8_t *)pkt, REQUEST_ENTRY_SIZE); +#endif + } + } + else /* No data transfer */ + { + *dword_ptr++ = (uint32_t) 0; + *dword_ptr = (uint32_t) 0; +#ifdef QL_DEBUG_LEVEL_5 + qla2100_print( + "qla2100_32bit_start_scsi: No data, command packet data - "); + qla2100_output_number((u_long)ha->host_no, 10); + qla2100_print(":"); + qla2100_output_number((u_long)SCSI_BUS_32(cmd), 10); + qla2100_print(":"); + qla2100_output_number((u_long)SCSI_TCN_32(cmd), 10); + qla2100_print(":"); + qla2100_output_number((u_long)SCSI_LUN_32(cmd), 10); + qla2100_print("\n"); + qla2100_dump_buffer((uint8_t *)pkt, REQUEST_ENTRY_SIZE); +#endif + } + /* Adjust ring index. */ + ha->req_ring_index++; + if( ha->req_ring_index == REQUEST_ENTRY_CNT ) { + ha->req_ring_index = 0; + ha->request_ring_ptr = ha->request_ring; + } else + ha->request_ring_ptr++; + + /* Set chip new ring index. */ + DEBUG4(qla2100_print("\nqla2100_32bit_start_scsi: Wakeup RISC for pending command\n\r")); + ha->qthreads--; + sp->flags |= SRB_SENT; + sp->state = 0xde; + ha->actthreads++; + + /* DEBUG(sprintf(debug_buff," Start(pid=%d) ",cmd->pid);) + DEBUG(qla2100_print(debug_buff);) */ + +#if WATCH_THREADS_SIZE + DEBUG3(qla2100_output_number((u_long)ha->actthreads, 16)); +#endif + if (ha->device_id == QLA2300_DEVICE_ID) { + temp = CACHE_FLUSH(®2300->req_q_in); + WRT_REG_WORD(®2300->req_q_in, ha->req_ring_index); + } else { + temp = CACHE_FLUSH(®->mailbox4); + WRT_REG_WORD(®->mailbox4, ha->req_ring_index); + } + } else { + status = 1; + qla2100_stats.outarray_full++; +#ifdef QL_DEBUG_LEVEL_8 + qla2100_print( + "qla2100_32bit_start_scsi: NO ROOM IN OUTSTANDING ARRAY\n"); +#endif + } + } else { + status = 1; +#ifdef QL_DEBUG_LEVEL_8 + qla2100_print("qla2100_32bit_start_scsi: in-ptr="); + qla2100_output_number((u_long)ha->req_ring_index, 16); + qla2100_print(" req_q_cnt="); + qla2100_output_number((u_long)ha->req_q_cnt, 16); + qla2100_print(" req_cnt="); + qla2100_output_number((u_long)req_cnt, 16); + qla2100_print("\n"); +#endif + } + + /* Release ring specific lock */ + QLA2100_RING_UNLOCK(ha); + +#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3) + if( status ) + qla2100_print("qla2100_32bit_start_scsi: **** FAILED ****\n"); +#ifdef QL_DEBUG_LEVEL_3 + else qla2100_print("qla2100_32bit_start_scsi: exiting normally\n\n\r"); +#endif +#endif +#ifdef QL_DEBUG_LEVEL_3 + LEAVE("qla2100_32bit_start_scsi"); +#endif + COMTRACE('s') + return(status); +} + +/* +* qla2100_ms_req_pkt +* Function is responsible for locking ring and +* getting a zeroed out Managment Server request packet. +* +* Input: +* ha = adapter block pointer. +* sp = srb_t pointer to handle post function call +* Returns: +* 0 = failed to get slot. +*/ +STATIC request_t * +qla2100_ms_req_pkt(scsi_qla_host_t *ha, srb_t *sp) { + device_reg_t *reg = ha->iobase; + device2300_reg_t *reg2300 = ha->iobase2300; + request_t *pkt = 0; + uint16_t cnt,i; + uint32_t *dword_ptr; + uint32_t timer; + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_ms_req_pkt"); +#endif + + /* Wait for 30 seconds for slot. */ + for( timer = 3000000; timer; timer-- ) { + /* Acquire ring specific lock */ + QLA2100_RING_LOCK(ha); + + if( !ha->req_q_cnt ) { + /* Calculate number of free request entries. */ + if (ha->device_id == QLA2300_DEVICE_ID) cnt = qla2100_debounce_register(®2300->req_q_out); + else cnt = qla2100_debounce_register(®->mailbox4); + if( ha->req_ring_index < cnt ) + ha->req_q_cnt = cnt - ha->req_ring_index; + else + ha->req_q_cnt = REQUEST_ENTRY_CNT - (ha->req_ring_index - cnt); + } + + /* Check for room in outstanding command list. */ + for( cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS && + (ha->outstanding_cmds[cnt] != 0); cnt++ ) + ; + + if( (cnt < MAX_OUTSTANDING_COMMANDS) && + ( ha->req_q_cnt != 0 )) { + + pkt = ha->request_ring_ptr; + + /* Zero out packet. */ + dword_ptr = (uint32_t *)pkt; + for( i = 0; i < REQUEST_ENTRY_SIZE/4; i++ ) + *dword_ptr++ = 0; + + DEBUG(sprintf(debug_buff, + "qla2100_ms_req: putting sp=%x in outstanding_cmds[%x]\n",sp,cnt)); + DEBUG(qla2100_print(debug_buff)); + + ha->outstanding_cmds[cnt] = sp; + /* save the handle */ + CMD_HANDLE(sp->cmd) = (unsigned char *) (u_long) cnt; + + ha->req_q_cnt--; + pkt->handle = (uint32_t)cnt; + + /* Set system defined field. */ + pkt->sys_define = (uint8_t)ha->req_ring_index; + pkt->entry_status = 0; + + break; + } + + /* Release ring specific lock */ + QLA2100_RING_UNLOCK(ha); + + SYS_DELAY(2); + + /* Check for pending interrupts. */ + qla2100_poll(ha); + } + +#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3) + if( !pkt ) + qla2100_print("qla2100_ms_req_pkt: **** FAILED ****\n"); +#endif +#ifdef QL_DEBUG_LEVEL_3 + else + LEAVE("qla2100_ms_req_pkt"); +#endif + return(pkt); +} + + +/* +* qla2100_req_pkt +* Function is responsible for locking ring and +* getting a zeroed out request packet. +* +* Input: +* ha = adapter block pointer. +* +* Returns: +* 0 = failed to get slot. +*/ +STATIC request_t * +qla2100_req_pkt(scsi_qla_host_t *ha) { + device_reg_t *reg = ha->iobase; + device2300_reg_t *reg2300 = ha->iobase2300; + request_t *pkt = 0; + uint16_t cnt; + uint32_t *dword_ptr; + uint32_t timer; + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_req_pkt"); +#endif + + /* Wait for 30 seconds for slot. */ + for( timer = 3000000; timer; timer-- ) { + /* Acquire ring specific lock */ + QLA2100_RING_LOCK(ha); + + if( !ha->req_q_cnt ) { + /* Calculate number of free request entries. */ + if (ha->device_id == QLA2300_DEVICE_ID) cnt = qla2100_debounce_register(®2300->req_q_out); + else cnt = qla2100_debounce_register(®->mailbox4); + if( ha->req_ring_index < cnt ) + ha->req_q_cnt = cnt - ha->req_ring_index; + else + ha->req_q_cnt = REQUEST_ENTRY_CNT - (ha->req_ring_index - cnt); + } + + /* Found empty request ring slot? */ + if( ha->req_q_cnt ) { + ha->req_q_cnt--; + pkt = ha->request_ring_ptr; + + /* Zero out packet. */ + dword_ptr = (uint32_t *)pkt; + for( cnt = 0; cnt < REQUEST_ENTRY_SIZE/4; cnt++ ) + *dword_ptr++ = 0; + + /* Set system defined field. */ + pkt->sys_define = (uint8_t)ha->req_ring_index; + + /* Set entry count. */ + pkt->entry_count = 1; + + break; + } + + /* Release ring specific lock */ + QLA2100_RING_UNLOCK(ha); + + SYS_DELAY(2); /* 10 */ + + /* Check for pending interrupts. */ + qla2100_poll(ha); + } + +#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3) + if( !pkt ) + qla2100_print("qla2100_req_pkt: **** FAILED ****\n"); +#endif +#ifdef QL_DEBUG_LEVEL_3 + else + LEAVE("qla2100_req_pkt"); +#endif + return(pkt); +} + +/* +* qla2100_isp_cmd +* Function is responsible for modifying ISP input pointer. +* Releases ring lock. +* +* Input: +* ha = adapter block pointer. +*/ +STATIC void +qla2100_isp_cmd(scsi_qla_host_t *ha) { + device_reg_t *reg = ha->iobase; + device2300_reg_t *reg2300 = ha->iobase2300; + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_isp_cmd"); +#endif + +#ifdef QL_DEBUG_LEVEL_5 + qla2100_print("qla2100_isp_cmd: IOCB data:\n"); + qla2100_dump_buffer((uint8_t *)ha->request_ring_ptr, REQUEST_ENTRY_SIZE); +#endif + + /* Adjust ring index. */ + ha->req_ring_index++; + if( ha->req_ring_index == REQUEST_ENTRY_CNT ) { + ha->req_ring_index = 0; + ha->request_ring_ptr = ha->request_ring; + } else + ha->request_ring_ptr++; + + /* Set chip new ring index. */ + if (ha->device_id == QLA2300_DEVICE_ID) WRT_REG_WORD(®2300->req_q_in, ha->req_ring_index); + else WRT_REG_WORD(®->mailbox4, ha->req_ring_index); + + /* Release ring specific lock */ + QLA2100_RING_UNLOCK(ha); + +#ifdef QL_DEBUG_LEVEL_3 + LEAVE("qla2100_isp_cmd"); +#endif +} + +/* +* qla2100_enable_lun +* Issue enable LUN entry IOCB. +* +* Input: +* ha = adapter block pointer. +*/ +STATIC void +qla2100_enable_lun(scsi_qla_host_t *ha) { + elun_entry_t *pkt; + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_enable_lun"); +#endif + + /* Get request packet. */ + if( (pkt = (elun_entry_t *)qla2100_req_pkt(ha)) != NULL ) { + pkt->entry_type = ENABLE_LUN_TYPE; + pkt->command_count = 32; + pkt->immed_notify_count = 1; + pkt->timeout = 0xffff; + + /* Issue command to ISP */ + qla2100_isp_cmd(ha); + } + +#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3) + if( !pkt ) + qla2100_print("qla2100_enable_lun: **** FAILED ****\n"); +#endif +#ifdef QL_DEBUG_LEVEL_3 + else + LEAVE("qla2100_enable_lun"); +#endif +} + + + +#if QL2100_TARGET_MODE_SUPPORT +/****************************************************************************/ +/* Target Mode Support Functions. */ +/****************************************************************************/ + + +/* +* qla2100_notify_ack +* Issue notify acknowledge IOCB. +* If sequence ID is zero, acknowledgement of +* SCSI bus reset or bus device reset is assumed. +* +* Input: +* ha = adapter block pointer. +* inotify = immediate notify entry pointer. +*/ +STATIC void +qla2100_notify_ack(scsi_qla_host_t *ha, notify_entry_t *inotify) { + nack_entry_t *pkt; + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_notify_ack: entered\n"); +#endif + + /* Get request packet. */ + if( pkt = (nack_entry_t *)qla2100_req_pkt(ha) ) { + pkt->entry_type = NOTIFY_ACK_TYPE; + pkt->initiator_id = inotify->initiator_id; + pkt->target_id = inotify->target_id; + + if( (pkt->status = inotify->status) == 0xe ) + /* Reset LIP occurred. */ + pkt->flags = OF_RESET; + else + /* Increment Immediate Notify Resource Count. */ + pkt->flags = OF_INC_RC; + + pkt->task_flags = inotify->task_flags; + pkt->seq_id = inotify->seq_id; + + /* Issue command to ISP */ + qla2100_isp_cmd(ha); + } + +#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3) + if( !pkt ) + qla2100_print("qla2100_notify_ack: **** FAILED ****\n"); +#endif +#ifdef QL_DEBUG_LEVEL_3 + else + LEAVE("qla2100_notify_ack: exiting normally\n"); +#endif +} + +/* +* qla2100_64bit_continue_io +* Issue continue target I/O IOCB. +* +* Input: +* ha = adapter block pointer. +* atio = atio pointer. +* len = total bytecount. +* addr = physical address pointer. +*/ +STATIC void +qla2100_64bit_continue_io(scsi_qla_host_t *ha, atio_entry_t *atio, uint32_t len, + u_long *addr) { + ctio_a64_entry_t *pkt; + uint32_t *dword_ptr; + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_64bit_continue_io: entered\n"); +#endif + + /* Get request packet. */ + if( pkt = (ctio_a64_entry_t *)qla2100_req_pkt(ha) ) { + pkt->entry_type = CTIO_A64_TYPE; + pkt->initiator_id = atio->initiator_id; + pkt->exchange_id = atio->exchange_id; + pkt->flags = atio->flags | OF_FAST_POST; + pkt->scsi_status = atio->scsi_status; + + if( len ) { + pkt->dseg_count = 1; + pkt->transfer_length = len; + pkt->dseg_0_length = len; + dword_ptr = (uint32_t *)addr; + pkt->dseg_0_address[0] = *dword_ptr++; + pkt->dseg_0_address[1] = *dword_ptr; + } + + /* Issue command to ISP */ + qla2100_isp_cmd(ha); + } + +#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3) + if( !pkt ) + qla2100_print("qla2100_64bit_continue_io: **** FAILED ****\n"); +#endif +#ifdef QL_DEBUG_LEVEL_3 + else + LEAVE("qla2100_64bit_continue_io: exiting normally\n"); +#endif +} + +/* +* qla2100_32bit_continue_io +* Issue continue target I/O IOCB. +* +* Input: +* ha = adapter block pointer. +* atio = atio pointer. +* len = total bytecount. +* addr = physical address pointer. +*/ +STATIC void +qla2100_32bit_continue_io(scsi_qla_host_t *ha, atio_entry_t *atio, uint32_t len, + u_long *addr) { + ctio_entry_t *pkt; + uint32_t *dword_ptr; + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_continue_io: entered\n"); +#endif + + /* Get request packet. */ + if( pkt = (ctio_entry_t *)qla2100_req_pkt(ha) ) { + pkt->entry_type = CONTINUE_TGT_IO_TYPE; + pkt->initiator_id = atio->initiator_id; + pkt->exchange_id = atio->exchange_id; + pkt->flags = atio->flags | OF_FAST_POST; + pkt->scsi_status = atio->scsi_status; + + if( len ) { + pkt->dseg_count = 1; + pkt->transfer_length = len; + pkt->dseg_0_length = len; + dword_ptr = (uint32_t *)addr; + pkt->dseg_0_address = *dword_ptr; + } + + /* Issue command to ISP */ + qla2100_isp_cmd(ha); + } + +#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3) + if( !pkt ) + qla2100_print("qla2100_32bit_continue_io: **** FAILED ****\n"); +#endif +#ifdef QL_DEBUG_LEVEL_3 + else + LEAVE("qla2100_32bit_continue_io: exiting normally\n"); +#endif +} +#endif /* QL2100_TARGET_MODE_SUPPORT */ + + + +/****************************************************************************/ +/* Interrupt Service Routine. */ +/****************************************************************************/ + +/* +* qla2100_isr +* Calls I/O done on command completion. +* +* Input: +* ha = adapter block pointer. +* done_q_first = done queue first pointer. +* done_q_last = done queue last pointer. +* INTR_LOCK must be already obtained. +*/ +STATIC void +qla2100_isr(scsi_qla_host_t *ha, srb_t **done_q_first, srb_t **done_q_last) { + device_reg_t *reg = ha->iobase; + device2300_reg_t *reg2300 = ha->iobase2300; + response_t *pkt, response_entry; + srb_t *sp; + uint16_t mailbox[MAILBOX_REGISTER_COUNT]; + uint16_t *wptr, status2 = 0; + uint32_t index, longstatus, *dptr1, *dptr2; + unsigned long cpu_flags = 0; + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_isr"); +#endif + if (ha->device_id != QLA2300_DEVICE_ID) { + /* Check for 2100/2200 mailbox interrupt (semaphore set) */ + longstatus = RD_REG_WORD(®->semaphore); + if (longstatus & BIT_0) status2 = SEMAPHORE_SET; + } else { + /* Get 2300's Interrupt Status byte */ + longstatus = RD_REG_DWORD(®2300->host_status); +/*#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3) + DEBUG(qla2100_print("qla2100_isr: +++ 2300 RISC_TO_HOST reg= ");) + DEBUG(qla2100_output_number((u_long)longstatus, 16);) + DEBUG(qla2100_print(" +++ \n");) +#endif */ + switch(longstatus & 0xff) { + case 0x1: + case 0x2: + case 0x10: + case 0x11: + case 0x12: + case 0x14: + case 0x15: + case 0x16: + case 0x17: + status2 = SEMAPHORE_SET; + break; + case 0x13: + default: + status2 = 0; + break; + } + } + + if ( status2 == SEMAPHORE_SET ) { + + /* Get mailbox data. */ + wptr = &mailbox[0]; + if (ha->device_id != QLA2300_DEVICE_ID) { + *wptr++ = qla2100_debounce_register(®->mailbox0); + *wptr++ = RD_REG_WORD(®->mailbox1); + *wptr = RD_REG_WORD(®->mailbox2); + } else { + *wptr++ = qla2100_debounce_register(®2300->mailbox0); + *wptr++ = RD_REG_WORD(®2300->mailbox1); + *wptr = RD_REG_WORD(®2300->mailbox2); + } + + WRT_REG_WORD(®->host_cmd, HC_CLR_RISC_INT); + +#if defined(QL_DEBUG_LEVEL_4) +DEBUG(qla2100_print("qla2100_isr: SEMAPHORE SET Processing, mailbox[0]=");) +DEBUG(qla2100_output_number((u_long)mailbox[0], 16);) +DEBUG(qla2100_print(" \n");) +DEBUG(qla2100_print("qla2100_isr: mailbox[1]=");) +DEBUG(qla2100_output_number((u_long)mailbox[1], 16);) +DEBUG(qla2100_print(" \n");) +DEBUG(qla2100_print("qla2100_isr: mailbox[2]=");) +DEBUG(qla2100_output_number((u_long)mailbox[2], 16);) +DEBUG(qla2100_print(" \n");) +DEBUG(qla2100_print("qla2100_isr: mailbox[3]=");) +DEBUG(qla2100_output_number((u_long)mailbox[3], 16);) +DEBUG(qla2100_print(" \n");) +#endif + +#ifdef FC_IP_SUPPORT /*******************************************/ + /* Handle IP send fast post */ + if (mailbox[0] == MBA_IP_TRANSMIT_COMPLETE) { + SEND_CB *pSendCB; + + /* Clear the semaphore lock , if it was set */ + if (RD_REG_WORD(®->semaphore) & BIT_0) + WRT_REG_WORD(®->semaphore, 0); + + /* Validate cmd handle and get packet pointer */ + if (mailbox[1] < MAX_SEND_PACKETS) { + if ((pSendCB = (SEND_CB *)ha->apActiveIpQueue[mailbox[1]]) != NULL) { + ha->apActiveIpQueue[mailbox[1]] = NULL; + + /* Complete backdoor command */ + (*ha->pSendCompletionRoutine)(pSendCB); + + return; + } + } + + /* Invalid handle from RISC, reset RISC firmware */ + printk(KERN_WARNING "qla2100_isr: bad IP send fast post handle %x\n", + mailbox[1]); + ha->flags.isp_abort_needed = TRUE; + return; + } + + /* Handle IP receive fast post */ + else if (mailbox[0] == MBA_IP_RECEIVE_COMPLETE || + mailbox[0] == MBA_IP_RECEIVE_COMPLETE_SPLIT) { + PBUFFER_CB pBufferCB, pNextBufferCB; + uint32_t lTagVal; + uint32_t lPacketSize; + uint32_t lReceiveBufferSize; + volatile uint16_t *pNextMailbox; + uint16_t wBufferCount; + + pNextMailbox = ®->mailbox10; + + /* If split buffer, set header size for 1st buffer */ + if (mailbox[0] == MBA_IP_RECEIVE_COMPLETE_SPLIT) + lReceiveBufferSize = ha->wHeaderSize; + else + lReceiveBufferSize = ha->lReceiveBufferSize; + + if ((lTagVal = RD_REG_WORD(pNextMailbox)) >= ha->wReceiveBufferCount) { + goto InvalidIpBufferHandle; + } + + pBufferCB = &ha->pReceiveBufferCBs[lTagVal]; + + if (!(pBufferCB->lFlags & BCB_FLAGS_RISC_OWNS_BUFFER)) { + goto InvalidIpBufferHandle; + } + + /* Set buffer belongs to driver now */ + pBufferCB->lFlags &= ~BCB_FLAGS_RISC_OWNS_BUFFER; + + lPacketSize = RD_REG_WORD(®->mailbox3); + pBufferCB->lPacketSize = lPacketSize; + pNextBufferCB = pBufferCB; + + for (wBufferCount = 1; ; wBufferCount++) { + if (lPacketSize > lReceiveBufferSize) { + pNextBufferCB->lBufferSize = lReceiveBufferSize; + lPacketSize -= lReceiveBufferSize; + + /* If split buffer, only use header size on 1st buffer */ + lReceiveBufferSize = ha->lReceiveBufferSize; + + pNextMailbox++; + if ((lTagVal = RD_REG_WORD(pNextMailbox)) >= + ha->wReceiveBufferCount) { + InvalidIpBufferHandle: + printk(KERN_WARNING "qla2100_isr: bad IP receive fast post handle %x\n", + lTagVal); + ha->flags.isp_abort_needed = TRUE; + return; + } + + pNextBufferCB->pNextBufferCB = &ha->pReceiveBufferCBs[lTagVal]; + pNextBufferCB = pNextBufferCB->pNextBufferCB; + + if (!(pNextBufferCB->lFlags & BCB_FLAGS_RISC_OWNS_BUFFER)) { + goto InvalidIpBufferHandle; + } + + /* Set buffer belongs to driver now */ + pNextBufferCB->lFlags &= ~BCB_FLAGS_RISC_OWNS_BUFFER; + } else { + pNextBufferCB->lBufferSize = lPacketSize; + pNextBufferCB->pNextBufferCB = NULL; + break; + } + } + + /* Clear the semaphore lock , if it was set */ + if (RD_REG_WORD(®->semaphore) & BIT_0) + WRT_REG_WORD(®->semaphore, 0); + + /* Pass received packet to IP driver */ + pBufferCB->wBufferCount = wBufferCount; + + (*ha->pReturnReceivePacketsRoutine) + (ha->pReturnReceivePacketsContext, + pBufferCB); + + /* Keep track of RISC buffer pointer (for IP reinit) */ + ha->wIpBufferOut += wBufferCount; + if (ha->wIpBufferOut >= IP_BUFFER_QUEUE_DEPTH) + ha->wIpBufferOut -= IP_BUFFER_QUEUE_DEPTH; + + return; + } +#endif /* FC_IP_SUPPORT ****************************************8*/ + + if( mailbox[0] != MBA_SCSI_COMPLETION ) { +#ifdef QL_DEBUG_LEVEL_4 + qla2100_print("qla2100_isr: non MBA_SCSI_COMPLETION ; Saving mailbox data\n"); +#endif + wptr++; + if (ha->device_id != QLA2300_DEVICE_ID) { + *wptr++ = RD_REG_WORD(®->mailbox3); + *wptr++ = qla2100_debounce_register(®->mailbox4); + *wptr++ = qla2100_debounce_register(®->mailbox5); + *wptr++ = RD_REG_WORD(®->mailbox6); + *wptr = RD_REG_WORD(®->mailbox7); + } else { + *wptr++ = RD_REG_WORD(®2300->mailbox3); + *wptr++ = qla2100_debounce_register(®2300->mailbox4); + *wptr++ = qla2100_debounce_register(®2300->mailbox5); + *wptr++ = RD_REG_WORD(®2300->mailbox6); + *wptr = RD_REG_WORD(®2300->mailbox7); + } + } + + /* Clear the semaphore lock , if it was set */ + if (RD_REG_WORD(®->semaphore) & BIT_0) + WRT_REG_WORD(®->semaphore, 0); + +#ifdef QL_DEBUG_LEVEL_4 + qla2100_print("qla2100_isr: +++ mailbox interrupt mailbox[0] = "); + qla2100_output_number((u_long)mailbox[0], 16); + qla2100_print("+++ \n"); + #endif + /* Handle asynchronous (0x80xx) and + mailbox command completion (0x400x) events */ + switch( mailbox[0] ) { + case MBA_SCSI_COMPLETION: /* 0x8020 */ + if( ha->flags.online ) { + /* Get outstanding command index. */ + index = (uint32_t)(mailbox[2] << 16 | mailbox[1]); + /* Validate handle. */ + if( index < MAX_OUTSTANDING_COMMANDS ) { + sp = ha->outstanding_cmds[index]; + } else + sp = 0; + + if( sp ) { + /* Free outstanding command slot. */ + ha->outstanding_cmds[index] = 0; + + /* Save ISP completion status */ + CMD_RESULT(sp->cmd) = DID_OK; + sp->flags &= ~SRB_SENT; + /* v2.19.5b2 Reset port down retry on success. */ + sp->port_down_retry_count = ha->port_down_retry_count; + + QLA2100_TIMER_LOCK(ha); + ha->actthreads--; + /* Place block on done queue */ + qla2100_stats.done_q_cnt++; + DEBUG(sp->state = 3;) + + sp->s_next = NULL; + sp->s_prev = *done_q_last; + if( !(*done_q_first) ) + *done_q_first = sp; + else + (*done_q_last)->s_next = sp; + *done_q_last = sp; + QLA2100_TIMER_UNLOCK(ha); + } else { +#ifdef QL_DEBUG_LEVEL_2 + qla2100_print("qla2100_isr: ISP invalid handle\n"); +#endif + ha->flags.isp_abort_needed = TRUE; + } + } + break; + case MBA_RESET: /* Reset 0x8001*/ +#ifdef QL_DEBUG_LEVEL_2 + qla2100_print("qla2100_isr: asynchronous RESET\n"); +#endif + ha->flags.reset_marker = TRUE; + break; + case MBA_SYSTEM_ERR: /* System Error 0x8002 */ +#ifdef QL_DEBUG_LEVEL_2 + qla2100_print("qla2100_isr: ISP System Error - mbx1="); + qla2100_output_number((u_long)mailbox[1], 16); + qla2100_print(", mbx2="); + qla2100_output_number((u_long)mailbox[2], 16); + qla2100_print(", mbx3="); + qla2100_output_number((u_long)mailbox[3], 16); + qla2100_print("\n"); +#endif + printk(KERN_WARNING + "!qla2100_isr: ISP System Error - mbx1=%xh, mbx2=%xh, mbx3=%xh", + mailbox[1], mailbox[2], mailbox[3]); + ha->flags.isp_abort_needed = TRUE; + break; + case MBA_REQ_TRANSFER_ERR: /* Request Transfer Error */ +#ifdef QL_DEBUG_LEVEL_2 + qla2100_print("qla2100_isr: ISP Request Transfer Error\n"); +#endif + printk(KERN_WARNING "qla2100: ISP Request Transfer Error\n"); + ha->flags.isp_abort_needed = TRUE; + break; + case MBA_RSP_TRANSFER_ERR: /* Response Transfer Error */ +#ifdef QL_DEBUG_LEVEL_2 + qla2100_print("qla2100_isr: ISP Response Transfer Error\n"); +#endif + printk(KERN_WARNING "qla2100: ISP Response Transfer Error\n"); + ha->flags.isp_abort_needed = TRUE; + break; + case MBA_WAKEUP_THRES: /* Request Queue Wake-up */ +#ifdef QL_DEBUG_LEVEL_2 + qla2100_print("qla2100_isr: asynchronous WAKEUP_THRES\n"); +#endif + break; + case MBA_LIP_OCCURRED: /* Loop Initialization Procedure */ + if(!qla2100_quiet) printk(KERN_INFO "scsi(%d): LIP occurred.\n",(int)ha->host_no); + DEBUG(sprintf(debug_buff,"\n\nscsi(%d): LIP occurred.\n",(int)ha->host_no);) + DEBUG(qla2100_print(debug_buff)); +#ifdef QL_DEBUG_LEVEL_2 + qla2100_print( + "qla2100_isr: asynchronous MBA_LIP_OCCURRED\n"); +#endif + ha->dpc_flags = ha->dpc_flags | COMMAND_WAIT_NEEDED; + /* Save LIP sequence. */ + ha->lip_seq = mailbox[1]; + if( ha->loop_state != LOOP_DOWN ) { + ha->loop_state = LOOP_DOWN; + ha->loop_down_timer = LOOP_DOWN_TIME; + } + ha->lip_count++; + break; + case MBA_LOOP_UP: + printk(KERN_INFO "scsi(%d): LOOP UP detected\n",(int)ha->host_no); +#ifdef QL_DEBUG_LEVEL_2 + qla2100_print("qla2100_isr: asynchronous MBA_LOOP_UP\n"); +#endif + ha->loop_state = LOOP_UP; + break; + case MBA_LOOP_DOWN: + printk(KERN_INFO "scsi(%d): LOOP DOWN detected\n",(int)ha->host_no); +#ifdef QL_DEBUG_LEVEL_2 + qla2100_print("qla2100_isr: asynchronous MBA_LOOP_DOWN\n"); +#endif + ha->dpc_flags = ha->dpc_flags | COMMAND_WAIT_NEEDED; + if( ha->loop_state != LOOP_DOWN ) { + ha->loop_state = LOOP_DOWN; + ha->loop_down_timer = LOOP_DOWN_TIME; + } + break; + case MBA_LIP_RESET: /* LIP reset occurred. */ + if(!qla2100_quiet) printk(KERN_INFO "scsi(%d): LIP reset occurred\n",(int)ha->host_no); +#ifdef QL_DEBUG_LEVEL_2 + qla2100_print( + "qla2100_isr: asynchronous MBA_LIP_RESET\n"); +#endif + ha->dpc_flags = ha->dpc_flags | COMMAND_WAIT_NEEDED; + ha->flags.reset_marker = TRUE; + ha->loop_down_timer = LOOP_DOWN_TIME; + ha->loop_state = LOOP_DOWN; + ha->operating_mode = LOOP; + break; + case MBA_LINK_MODE_UP: /* Link mode up. */ + DEBUG(printk(KERN_INFO "scsi(%d): Link node is up\n",(int)ha->host_no);) +#ifdef QL_DEBUG_LEVEL_2 + qla2100_print( + "qla2100_isr: asynchronous MBA_LINK_MODE_UP\n"); +#endif + ha->dpc_flags = ha->dpc_flags | COMMAND_WAIT_NEEDED; + break; + case MBA_UPDATE_CONFIG: /* Update Configuration. */ + printk(KERN_INFO "scsi(%d): Configuration change detected: value %d.\n",(int)ha->host_no,mailbox[1]); +#ifdef QL_DEBUG_LEVEL_2 + qla2100_print( + "qla2100_isr: asynchronous MBA_UPDATE_CONFIG\n"); +#endif + ha->flags.update_config_needed = 1; + ha->loop_state = LOOP_DOWN; /* dg - 03/30 */ + ha->flags.isp_abort_needed = TRUE; + break; + case MBA_PORT_UPDATE: /* Port database update occurred. */ + DEBUG(printk("scsi(%d): Port database changed\n",(int)ha->host_no);) +#ifdef QL_DEBUG_LEVEL_2 + qla2100_print( + "qla2100_isr: asynchronous MBA_PORT_UPDATE\n"); +#endif + ha->loop_down_timer = 0; + ha->flags.loop_resync_needed = TRUE; + ha->loop_state = LOOP_UPDATE; + break; + case MBA_SCR_UPDATE: /* State Change Registration. */ +#ifdef QL_DEBUG_LEVEL_2 + qla2100_print( + "qla2100_isr: asynchronous MBA_RSCR_UPDATE\n"); +#endif + mailbox[1] = RD_REG_WORD(®->mailbox1); + mailbox[2] = RD_REG_WORD(®->mailbox2); + + DEBUG(printk("scsi(%d): RSCN database changed - 0x%x,0x%x\n",(int)ha->host_no,mailbox[1],mailbox[2]);) +#ifdef RCSN + index = ha->rscn_in_ptr + 1; + if (index == MAX_RSCN_COUNT) + index = 0; + if (index != ha->rscn_out_ptr) { + ha->rscn_queue[ha->rscn_in_ptr].format = + MSB(mb[1]); + ha->rscn_queue[ha->rscn_in_ptr].d_id.b.domain = + LSB(mb[1]); + ha->rscn_queue[ha->rscn_in_ptr].d_id.b.area = + MSB(mb[2]); + ha->rscn_queue[ha->rscn_in_ptr].d_id.b.al_pa = + LSB(mb[2]); + ha->rscn_in_ptr = (uint8_t)index; + } else { + ha->device_flags |= RSCN_QUEUE_OVERFLOW; + } +#endif + ha->device_flags |= RSCN_UPDATE; + ha->loop_down_timer = 0; + ha->flags.loop_resync_needed = TRUE; + ha->loop_state = LOOP_UPDATE; + /* ha->dpc_flags = ha->dpc_flags | COMMAND_WAIT_NEEDED; */ + break; + case MBA_CTIO_COMPLETION: +#ifdef QL_DEBUG_LEVEL_2 + qla2100_print( + "qla2100_isr: asynchronous MBA_CTIO_COMPLETION\n"); +#endif + break; + default: + if( mailbox[0] < MBA_ASYNC_EVENT /* 0x8000 */) { + wptr = &mailbox[0]; + ha->mailbox_out[0] = *wptr++; + ha->mailbox_out[1] = *wptr++; + ha->mailbox_out[2] = *wptr++; + ha->mailbox_out[3] = *wptr++; + ha->mailbox_out[4] = *wptr++; + ha->mailbox_out[5] = *wptr++; + ha->mailbox_out[6] = *wptr++; + ha->mailbox_out[7] = *wptr; + ha->flags.mbox_int = TRUE; +#ifdef QL_DEBUG_LEVEL_2 + if (mailbox[0] != 0x4000) { + qla2100_print("qla2100_isr: MBA Switch Default mailbox[0]= "); + qla2100_output_number(mailbox[0] , 16); + qla2100_print("\n"); + } +#endif +#ifdef QL_DEBUG_LEVEL_4 + qla2100_print("qla2100_isr: Setting flags.mbox_int=1 in Default mailbox[0]= "); + qla2100_output_number(mailbox[0] , 16); + qla2100_print("\n"); +#endif + } + break; + } /* switch */ + } else { /* not a SEMAPHORE Set Completion */ + if (ha->device_id != QLA2300_DEVICE_ID) + mailbox[5]=qla2100_debounce_register(®->mailbox5); + else + mailbox[5]=qla2100_debounce_register(®2300->rsp_q_in); + + WRT_REG_WORD(®->host_cmd, HC_CLR_RISC_INT); + /* + * Response Ring Update + */ + /* Clear mailbox busy flag for 2300s; + so we don't ignore its Respose Ring Updates + during send of mailbox command */ + if (ha->device_id == QLA2300_DEVICE_ID) + ha->flags.mbox_busy = FALSE; + + if( ha->flags.online && !(ha->flags.mbox_busy) ) { + if( mailbox[5] < RESPONSE_ENTRY_CNT ) { + while( ha->rsp_ring_index != mailbox[5] ) { + pkt = ha->response_ring_ptr; + +#ifdef QL_DEBUG_LEVEL_5 + qla2100_print("qla2100_isr: ha->rsp_ring_index = "); + qla2100_output_number((u_long)ha->rsp_ring_index, 16); + qla2100_print(" mailbox[5] = "); + qla2100_output_number((u_long)mailbox[5], 16); + qla2100_print("\n"); + qla2100_print("\nqla2100_isr: response packet data\n"); + qla2100_dump_buffer((uint8_t *)pkt, RESPONSE_ENTRY_SIZE); +#endif + +#ifdef FC_IP_SUPPORT /************************************************/ + /* Handle IP send completion */ + if (pkt->entry_type == ET_IP_COMMAND_64) { + uint32_t lTagVal; + SEND_CB *pSendCB; + + /* Set packet pointer from queue entry handle */ + if ((lTagVal = pkt->handle) < MAX_SEND_PACKETS) { + if ((pSendCB = (SEND_CB *)ha->apActiveIpQueue[lTagVal]) != NULL) { + ha->apActiveIpQueue[lTagVal] = NULL; + + /* Return send packet to IP driver */ + (*ha->pSendCompletionRoutine)(pSendCB); + } else { + /* Invalid handle from RISC, reset RISC firmware */ + printk(KERN_WARNING "qla2100_isr: bad IP send handle %x\n", lTagVal); + ha->flags.isp_abort_needed = TRUE; + } + } else { + /* Invalid handle from RISC, reset RISC firmware */ + printk(KERN_WARNING "qla2100_isr: bad IP send handle %x\n", lTagVal); + ha->flags.isp_abort_needed = TRUE; + } + + /* Adjust ring index. */ + ha->rsp_ring_index++; + if( ha->rsp_ring_index == RESPONSE_ENTRY_CNT ) { + ha->rsp_ring_index = 0; + ha->response_ring_ptr = ha->response_ring; + } else + ha->response_ring_ptr++; + if (ha->device_id != QLA2300_DEVICE_ID) + WRT_REG_WORD(®->mailbox5, ha->rsp_ring_index); + else + WRT_REG_WORD(®2300->rsp_q_out, ha->rsp_ring_index); + continue; + } + + /* Handle IP receive packet */ + else if (pkt->entry_type == ET_IP_RECEIVE) { + PIP_RECEIVE_ENTRY pIpReceiveEntry = (PIP_RECEIVE_ENTRY)pkt; + PBUFFER_CB pBufferCB, pNextBufferCB; + uint32_t lTagVal; + uint32_t lPacketSize; + uint16_t wBufferCount; + uint32_t lReceiveBufferSize; + + /* If split buffer, set header size for 1st buffer */ + if (pIpReceiveEntry->wCompletionStatus & IP_REC_STATUS_SPLIT_BUFFER) + lReceiveBufferSize = ha->wHeaderSize; + else + lReceiveBufferSize = ha->lReceiveBufferSize; + + if ((lTagVal = pIpReceiveEntry->waBufferHandle[0]) >= + ha->wReceiveBufferCount) { + /* Invalid handle from RISC, reset RISC firmware */ + printk(KERN_WARNING "qla2100_isr: bad IP buffer handle %x\n", lTagVal); + ha->flags.isp_abort_needed = TRUE; + goto InvalidIpHandle; + } + pBufferCB = &ha->pReceiveBufferCBs[lTagVal]; + + if (!(pBufferCB->lFlags & BCB_FLAGS_RISC_OWNS_BUFFER)) { + /* Invalid handle from RISC, reset RISC firmware */ + printk(KERN_WARNING "qla2100_isr: bad IP buffer handle %x\n", lTagVal); + ha->flags.isp_abort_needed = TRUE; + goto InvalidIpHandle; + } + + /* Set buffer belongs to driver now */ + pBufferCB->lFlags &= ~BCB_FLAGS_RISC_OWNS_BUFFER; + + lPacketSize = pIpReceiveEntry->wSequenseLength; + pBufferCB->lPacketSize = lPacketSize; + pNextBufferCB = pBufferCB; + + for (wBufferCount = 1; ; wBufferCount++) { + if (lPacketSize > lReceiveBufferSize) { + pNextBufferCB->lBufferSize = lReceiveBufferSize; + lPacketSize -= lReceiveBufferSize; + + /* If split buffer, only use header size on 1st buffer */ + lReceiveBufferSize = ha->lReceiveBufferSize; + + if ((lTagVal = pIpReceiveEntry->waBufferHandle[wBufferCount]) >= + ha->wReceiveBufferCount) { + /* Invalid handle from RISC, reset RISC firmware */ + printk(KERN_WARNING "qla2100_isr: bad IP buffer handle %x\n", lTagVal); + ha->flags.isp_abort_needed = TRUE; + goto InvalidIpHandle; + } + pNextBufferCB->pNextBufferCB = &ha->pReceiveBufferCBs[lTagVal];; + pNextBufferCB = pNextBufferCB->pNextBufferCB; + + if (!(pNextBufferCB->lFlags & BCB_FLAGS_RISC_OWNS_BUFFER)) { + /* Invalid handle from RISC, reset RISC firmware */ + printk(KERN_WARNING "qla2100_isr: bad IP buffer handle %x\n", lTagVal); + ha->flags.isp_abort_needed = TRUE; + goto InvalidIpHandle; + } + + /* Set buffer belongs to driver now */ + pNextBufferCB->lFlags &= ~BCB_FLAGS_RISC_OWNS_BUFFER; + } else { + pNextBufferCB->lBufferSize = lPacketSize; + pNextBufferCB->pNextBufferCB = NULL; + break; + } + } + + /* Check for incoming ARP packet with matching IP address */ + if (pIpReceiveEntry->wServiceClass == 0) { + PPACKET_HEADER pPacket = (PPACKET_HEADER)pBufferCB->pBuffer; + PIP_DEVICE_BLOCK pIpDevice; + uint8_t acPortId[3]; + + /* Scan list of IP devices to see if login needed */ + for (pIpDevice = ha->pIpDeviceTop; pIpDevice != NULL; + pIpDevice = pIpDevice->pNextIpDevice) { + if (*(uint16_t *)(&pIpDevice->acWorldWideName[2]) == + pPacket->sNetworkHeader.wSourceAddrHigh && + *(uint32_t *)(&pIpDevice->acWorldWideName[4]) == + pPacket->sNetworkHeader.lSourceAddrLow) { + /* Device already in IP list, skip login */ + goto SkipDeviceLogin; + } + } + + /* Device not in list, need to do login */ + acPortId[0] = pIpReceiveEntry->cS_IDHigh; + acPortId[1] = (uint8_t)(pIpReceiveEntry->wS_IDLow >> 8); + acPortId[2] = (uint8_t)pIpReceiveEntry->wS_IDLow; + + /* Make sure its not a local device */ + if (acPortId[0] == ha->port_id[0] && + acPortId[1] == ha->port_id[1]) { + goto SkipDeviceLogin; + } + + if (qla2x00_add_new_ip_device(ha, PUBLIC_LOOP_DEVICE, + acPortId, + (uint8_t *)&pPacket->sNetworkHeader.wSourceNAA, + TRUE) == QL_STATUS_FATAL_ERROR) { + /* Fatal error, reinitialize */ + ha->flags.isp_abort_needed = TRUE; + } + } + SkipDeviceLogin: + /* Pass received packet to IP driver */ + pBufferCB->wBufferCount = wBufferCount; + + (*ha->pReturnReceivePacketsRoutine) + (ha->pReturnReceivePacketsContext, + pBufferCB); + + /* Keep track of RISC buffer pointer (for IP reinit) */ + ha->wIpBufferOut += wBufferCount; + if (ha->wIpBufferOut >= IP_BUFFER_QUEUE_DEPTH) + ha->wIpBufferOut -= IP_BUFFER_QUEUE_DEPTH; + InvalidIpHandle: + /* Adjust ring index. */ + ha->rsp_ring_index++; + if( ha->rsp_ring_index == RESPONSE_ENTRY_CNT ) { + ha->rsp_ring_index = 0; + ha->response_ring_ptr = ha->response_ring; + } else + ha->response_ring_ptr++; + if (ha->device_id != QLA2300_DEVICE_ID) + WRT_REG_WORD(®->mailbox5, ha->rsp_ring_index); + else + WRT_REG_WORD(®2300->rsp_q_out, ha->rsp_ring_index); + continue; + } + + /* Handle IP FARP request */ + else if (pkt->entry_type == ET_IP_FARP_REQUEST) { + PIP_FARP_REQUEST_ENTRY pIpFarpRequestEntry; + uint8_t acPortId[3]; + uint8_t acPortName[8]; + + pIpFarpRequestEntry = (PIP_FARP_REQUEST_ENTRY)pkt; + acPortId[0] = pIpFarpRequestEntry->cRequesterPortIdHigh; + acPortId[1] = (uint8_t)(pIpFarpRequestEntry->wRequesterPortIdLow >> 8); + acPortId[2] = (uint8_t)pIpFarpRequestEntry->wRequesterPortIdLow; + acPortName[0] = pIpFarpRequestEntry->acRequesterPortName[7]; + acPortName[1] = pIpFarpRequestEntry->acRequesterPortName[6]; + acPortName[2] = pIpFarpRequestEntry->acRequesterPortName[5]; + acPortName[3] = pIpFarpRequestEntry->acRequesterPortName[4]; + acPortName[4] = pIpFarpRequestEntry->acRequesterPortName[3]; + acPortName[5] = pIpFarpRequestEntry->acRequesterPortName[2]; + acPortName[6] = pIpFarpRequestEntry->acRequesterPortName[1]; + acPortName[7] = pIpFarpRequestEntry->acRequesterPortName[0]; + + /* Login and add device to IP database */ + if (qla2x00_add_new_ip_device(ha, PUBLIC_LOOP_DEVICE, + acPortId, + acPortName, + TRUE) == QL_STATUS_FATAL_ERROR) { + /* Fatal error, reinitialize */ + ha->flags.isp_abort_needed = TRUE; + } + + /* Adjust ring index. */ + ha->rsp_ring_index++; + if( ha->rsp_ring_index == RESPONSE_ENTRY_CNT ) { + ha->rsp_ring_index = 0; + ha->response_ring_ptr = ha->response_ring; + } else + ha->response_ring_ptr++; + if (ha->device_id != QLA2300_DEVICE_ID) + WRT_REG_WORD(®->mailbox5, ha->rsp_ring_index); + else + WRT_REG_WORD(®2300->rsp_q_out, ha->rsp_ring_index); + + continue; + } +#endif /* FC_IP_SUPPORT *******************************************/ + + if( pkt->entry_type == STATUS_TYPE || + pkt->entry_status ) { + ha->actthreads--; + if( pkt->entry_type == STATUS_TYPE ) { + qla2100_status_entry(ha, (sts_entry_t *)pkt, + done_q_first, done_q_last); + /* DEBUG(printk("qla2100_isr: RespRingUpdate STATUS TYPE\n");) */ + } else { + qla2100_error_entry(ha, pkt, + done_q_first, done_q_last); + /* DEBUG(printk("qla2100_isr: RespRingUpdate ERROR TYPE \n");)*/ + } + /* Adjust ring index. */ + ha->rsp_ring_index++; + if( ha->rsp_ring_index == RESPONSE_ENTRY_CNT ) { + ha->rsp_ring_index = 0; + ha->response_ring_ptr = ha->response_ring; + } else + ha->response_ring_ptr++; + if (ha->device_id != QLA2300_DEVICE_ID) + WRT_REG_WORD(®->mailbox5, ha->rsp_ring_index); + else + WRT_REG_WORD(®2300->rsp_q_out, ha->rsp_ring_index); + } else { + pkt = &response_entry; + + /* Copy packet. */ + dptr1 = (uint32_t *)ha->response_ring_ptr; + dptr2 = (uint32_t *)pkt; + for( index = 0; index < RESPONSE_ENTRY_SIZE/4; + index++ ) + *dptr2++ = *dptr1++; + + /* Adjust ring index. */ + ha->rsp_ring_index++; + if( ha->rsp_ring_index == RESPONSE_ENTRY_CNT ) { + ha->rsp_ring_index = 0; + ha->response_ring_ptr = ha->response_ring; + } else + ha->response_ring_ptr++; + if (ha->device_id != QLA2300_DEVICE_ID) + WRT_REG_WORD(®->mailbox5, ha->rsp_ring_index); + else + WRT_REG_WORD(®2300->rsp_q_out, ha->rsp_ring_index); + + /* Release interrupt specific lock */ + QLA2100_INTR_UNLOCK(ha); + +#if QLA2100_TARGET_MODE_SUPPORT + switch( pkt->entry_type ) { + case ACCEPT_TGT_IO_TYPE: + qla2100_atio_entry(ha, (atio_entry_t *)pkt); + break; + case IMMED_NOTIFY_TYPE: + qla2100_notify_ack(ha, (notify_entry_t *)pkt); + break; + default: + break; + } +#endif /**** FC_TARGET_MODE_SUPPORT */ + + /* Acquire interrupt specific lock */ + QLA2100_INTR_LOCK(ha); + } + } + } else { + ha->flags.isp_abort_needed = TRUE; +#ifdef QL_DEBUG_LEVEL_2 + qla2100_print("qla2100_isr: $$$ Response Pointer Error $$$ mb5=\n"); + qla2100_output_number((u_long)mailbox[5], 16); + qla2100_print(" \n"); + printk(KERN_WARNING "qla2100_isr: [ERROR] Response pointer Error mailbox[5]=%x\n",mailbox[5]); +#endif + } + } + } + +#ifdef QL_DEBUG_LEVEL_3 + LEAVE("qla2100_isr"); +#endif +} + + + +/* +* qla2100_rst_aen +* Processes asynchronous reset. +* +* Input: +* ha = adapter block pointer. +*/ +STATIC void +qla2100_rst_aen(scsi_qla_host_t *ha) { +#if QL2100_TARGET_MODE_SUPPORT + notify_entry_t nentry; +#endif /* QL2100_TARGET_MODE_SUPPORT */ + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_rst_aen"); +#endif + + if( ha->flags.online && !ha->flags.reset_active && + !ha->loop_down_timer && !ha->flags.abort_isp_active ) { + ha->flags.reset_active = TRUE; + do { + ha->flags.reset_marker = FALSE; + + /* Issue marker command. */ + qla2100_marker(ha, 0, 0, 0, MK_SYNC_ALL); + +#if QL2100_TARGET_MODE_SUPPORT + if( !ha->loop_down_timer && !ha->flags.reset_marker ) { + /* Issue notify acknowledgement command. */ + BZERO((caddr_t)&nentry, sizeof(notify_entry_t)); + nentry.initiator_id = ha->id; + /* dg 7/3/99 nentry.target_id = ha->id; */ + nentry.task_flags = BIT_13; + qla2100_notify_ack(ha, &nentry); + } +#endif /* QL2100_TARGET_MODE_SUPPORT */ + }while( !ha->loop_down_timer && ha->flags.reset_marker ); + ha->flags.reset_active = FALSE; + } + +#ifdef QL_DEBUG_LEVEL_3 + LEAVE("qla2100_rst_aen"); +#endif +} + +#if QLA2100_TARGET_MODE_SUPPORT +/* +* qla2100_atio_entry +* Processes received ISP accept target I/O entry. +* +* Input: +* ha = adapter block pointer. +* pkt = entry pointer. +*/ +STATIC void +qla2100_atio_entry(scsi_qla_host_t *ha, atio_entry_t *pkt) { + uint64_t *a64; + uint64_t *end_a64; + u_long phy_addr[2]; + u_long end_addr[2]; + uint32_t len; + uint32_t offset; + uint8_t t; + uint8_t *sense_ptr; + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_atio_entry: entered\n"); +#endif + + t = pkt->initiator_id; + sense_ptr = ha->tsense + t * TARGET_SENSE_SIZE; + a64 = (uint64_t *)&phy_addr[0]; + end_a64 = (uint64_t *)&end_addr[0]; + + switch( pkt->status & ~BIT_7 ) { + case 7: /* Path invalid */ +#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3) + qla2100_print("qla2100_atio_entry: Path invalid\n"); +#endif + break; + case 0x16: /* Requested Capability Not Available */ +#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3) + qla2100_print( + "qla2100_atio_entry: Requested Capability Not Available\n"); +#endif + break; + case 0x17: /* Bus Device Reset Message Received */ +#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3) + qla2100_print( + "qla2100_atio_entry: Bus Device Reset Message Received\n"); +#endif + break; + case 0x3D: /* CDB Received */ + + /* Check for invalid LUN */ + if( pkt->lun && pkt->cdb[0] != SS_INQUIR && + pkt->cdb[0] != SS_REQSEN ) + pkt->cdb[0] = SS_TEST; + + switch( pkt->cdb[0] ) { + case SS_TEST: +#ifdef QL_DEBUG_LEVEL_3 + qla2100_print("qla2100_atio_entry: SS_TEST\n"); +#endif + BZERO(sense_ptr, TARGET_SENSE_SIZE); + len = 0; + if( pkt->lun == 0 ) + pkt->scsi_status = S_GOOD; + else { + *sense_ptr = 0x70; + *(sense_ptr+2) = SD_ILLREQ; + *(sense_ptr+7) = TARGET_SENSE_SIZE-8; + *(sense_ptr+12) = SC_INVLUN; + pkt->scsi_status = S_CKCON; + } + pkt->flags = (uint16_t)(OF_SSTS | OF_INC_RC | OF_NO_DATA); + break; + case SS_REQSEN: +#ifdef QL_DEBUG_LEVEL_3 + qla2100_print("qla2100_atio_entry: SS_REQSEN\n"); +#endif + phy_addr[0] = ha->tsense_dma; + phy_addr[1] = 0; + *a64 += t * TARGET_SENSE_SIZE; + if( pkt->cdb[4] > TARGET_SENSE_SIZE ) + len = TARGET_SENSE_SIZE; + else + len = pkt->cdb[4]; + pkt->scsi_status = S_GOOD; + pkt->flags = (uint16_t)(OF_SSTS | OF_INC_RC | OF_DATA_IN); + break; + case SS_INQUIR: +#ifdef QL_DEBUG_LEVEL_3 + qla2100_print("qla2100_atio_entry: SS_INQUIR\n"); +#endif + BZERO(sense_ptr, TARGET_SENSE_SIZE); + phy_addr[0] = ha->tbuf_dma; + phy_addr[1] = 0; + *a64 += TARGET_INQ_OFFSET; + + if( pkt->lun == 0 ) { + ha->tbuf->inq.id_type = ID_PROCESOR; + ha->tbuf->inq.id_pqual = ID_QOK; + } else { + ha->tbuf->inq.id_type = ID_NODEV; + ha->tbuf->inq.id_pqual = ID_QNOLU; + } + + if( pkt->cdb[4] > sizeof(struct ident) ) + len = sizeof(struct ident); + else + len = pkt->cdb[4]; + pkt->scsi_status = S_GOOD; + pkt->flags = (uint16_t)(OF_SSTS | OF_INC_RC | OF_DATA_IN); + break; + case SM_WRDB: + BZERO(sense_ptr, TARGET_SENSE_SIZE); + offset = pkt->cdb[5]; + offset |= pkt->cdb[4] << 8; + offset |= pkt->cdb[3] << 16; + len = pkt->cdb[8]; + len |= pkt->cdb[7] << 8; + len |= pkt->cdb[6] << 16; + end_addr[0] = phy_addr[0] = ha->tbuf_dma; + end_addr[1] = phy_addr[1] = 0; + *end_a64 += TARGET_DATA_OFFSET + TARGET_DATA_SIZE; + switch( pkt->cdb[1] & 7 ) { + case RW_BUF_HDATA: +#ifdef QL_DEBUG_LEVEL_3 + qla2100_print("qla2100_atio_entry: SM_WRDB, RW_BUF_HDATA\n"); +#endif + if( len > TARGET_DATA_SIZE + 4 ) { +#ifdef QL_DEBUG_LEVEL_2 + qla2100_print("qla2100_atio_entry: SM_WRDB, length > buffer size\n"); +#endif + *sense_ptr = 0x70; + *(sense_ptr+2) = SD_ILLREQ; + *(sense_ptr+7) = TARGET_SENSE_SIZE-8; + *(sense_ptr+12) = SC_ILLCDB; + pkt->scsi_status = S_CKCON; + pkt->flags = (uint16_t)(OF_SSTS | OF_INC_RC | + OF_NO_DATA); + len = 0; + } else if( len ) { + pkt->scsi_status = S_GOOD; + pkt->flags =(uint16_t)(OF_SSTS | OF_INC_RC | + OF_DATA_OUT); + } else { +#ifdef QL_DEBUG_LEVEL_2 + qla2100_print("qla2100_atio_entry: SM_WRDB, zero length\n"); +#endif + pkt->scsi_status = S_GOOD; + pkt->flags = (uint16_t)(OF_SSTS | OF_INC_RC | + OF_NO_DATA); + } + + break; + case RW_BUF_DATA: +#ifdef QL_DEBUG_LEVEL_3 + qla2100_print("qla2100_atio_entry: SM_WRDB, RW_BUF_DATA\n"); +#endif + *a64 += offset + TARGET_DATA_OFFSET; + if( pkt->cdb[2] != 0 || *a64 >= *end_a64 || + *a64 + len > *end_a64 ) { +#ifdef QL_DEBUG_LEVEL_2 + qla2100_print("qla2100_atio_entry: SM_WRDB, RW_BUF_DATA BAD\n"); + qla2100_print("buf_id="); + qla2100_output_number((u_long)pkt->cdb[2], 16); + qla2100_print(", offset="); + qla2100_output_number((u_long)offset, 16); + qla2100_print(", length="); + qla2100_output_number((u_long)len, 16); + qla2100_print("\n"); +#endif + *sense_ptr = 0x70; + *(sense_ptr+2) = SD_ILLREQ; + *(sense_ptr+7) = TARGET_SENSE_SIZE-8; + *(sense_ptr+12) = SC_ILLCDB; + len = 0; + pkt->scsi_status = S_CKCON; + pkt->flags = (uint16_t)(OF_SSTS | OF_INC_RC | + OF_NO_DATA); + } else if( len ) { + pkt->scsi_status = S_GOOD; + pkt->flags =(uint16_t)(OF_SSTS | OF_INC_RC | + OF_DATA_OUT); + } else { +#ifdef QL_DEBUG_LEVEL_2 + qla2100_print("qla2100_atio_entry: SM_WRDB, zero length\n"); +#endif + pkt->scsi_status = S_GOOD; + pkt->flags = (uint16_t)(OF_SSTS | OF_INC_RC | + OF_NO_DATA); + } + break; + default: +#ifdef QL_DEBUG_LEVEL_2 + qla2100_print("qla2100_atio_entry: SM_WRDB unknown mode\n"); +#endif + *sense_ptr = 0x70; + *(sense_ptr+2) = SD_ILLREQ; + *(sense_ptr+7) = TARGET_SENSE_SIZE-8; + *(sense_ptr+12) = SC_ILLCDB; + len = 0; + pkt->scsi_status = S_CKCON; + pkt->flags = (uint16_t)(OF_SSTS | OF_INC_RC | + OF_NO_DATA); + break; + } + break; + case SM_RDDB: + BZERO(sense_ptr, TARGET_SENSE_SIZE); + offset = pkt->cdb[5]; + offset |= pkt->cdb[4] << 8; + offset |= pkt->cdb[3] << 16; + len = pkt->cdb[8]; + len |= pkt->cdb[7] << 8; + len |= pkt->cdb[6] << 16; + end_addr[0] = phy_addr[0] = ha->tbuf_dma; + end_addr[1] = phy_addr[1] = 0; + *end_a64 += TARGET_DATA_OFFSET + TARGET_DATA_SIZE; + switch( pkt->cdb[1] & 7 ) { + case RW_BUF_HDATA: +#ifdef QL_DEBUG_LEVEL_3 + qla2100_print("qla2100_atio_entry: SM_RDDB, RW_BUF_HDATA\n"); +#endif + if( len ) { + ha->tbuf->hdr[0] = 0; + ha->tbuf->hdr[1] = + (uint8_t)(TARGET_DATA_SIZE >> 16); + ha->tbuf->hdr[2] = + (uint8_t)(TARGET_DATA_SIZE >> 8); + ha->tbuf->hdr[3] = (uint8_t)TARGET_DATA_SIZE; + if( len > TARGET_DATA_SIZE + 4 ) + len = TARGET_DATA_SIZE + 4; + pkt->scsi_status = S_GOOD; + pkt->flags = (uint16_t)(OF_SSTS | OF_INC_RC | + OF_DATA_IN); + } else { +#ifdef QL_DEBUG_LEVEL_2 + qla2100_print("qla2100_atio_entry: SM_RDDB, zero length\n"); +#endif + pkt->scsi_status = S_GOOD; + pkt->flags = (uint16_t)(OF_SSTS | OF_INC_RC | + OF_NO_DATA); + } + break; + case RW_BUF_DATA: +#ifdef QL_DEBUG_LEVEL_3 + qla2100_print("qla2100_atio_entry: SM_RDDB, RW_BUF_DATA\n"); +#endif + *a64 += offset + TARGET_DATA_OFFSET; + if( pkt->cdb[2] != 0 || *a64 >= *end_a64 ) { +#ifdef QL_DEBUG_LEVEL_2 + qla2100_print("qla2100_atio_entry: SM_RDDB, RW_BUF_DATA BAD\n"); + qla2100_print("buf_id="); + qla2100_output_number((u_long)pkt->cdb[2], 16); + qla2100_print(", offset="); + qla2100_output_number((u_long)offset, 16); + qla2100_print("\n"); +#endif + *sense_ptr = 0x70; + *(sense_ptr+2) = SD_ILLREQ; + *(sense_ptr+7) = TARGET_SENSE_SIZE-8; + *(sense_ptr+12) = SC_ILLCDB; + len = 0; + pkt->scsi_status = S_CKCON; + pkt->flags = (uint16_t)(OF_SSTS | OF_INC_RC | + OF_NO_DATA); + } else { + if( *a64 + len > *end_a64 ) + len = *end_a64 - *a64; + if( len ) { + pkt->scsi_status = S_GOOD; + pkt->flags = (uint16_t)(OF_SSTS | + OF_INC_RC | OF_DATA_IN); + } else { +#ifdef QL_DEBUG_LEVEL_2 + qla2100_print("qla2100_atio_entry: SM_RDDB, zero length\n"); +#endif + pkt->scsi_status = S_GOOD; + pkt->flags = (uint16_t)(OF_SSTS | + OF_INC_RC | OF_NO_DATA); + } + } + break; + case RW_BUF_DESC: +#ifdef QL_DEBUG_LEVEL_3 + qla2100_print("qla2100_atio_entry: SM_RDDB, RW_BUF_DESC\n"); +#endif + if( len ) { + if( len > 4 ) + len = 4; + + ha->tbuf->hdr[0] = 0; + if( pkt->cdb[2] != 0 ) { + ha->tbuf->hdr[1] = 0; + ha->tbuf->hdr[2] = 0; + ha->tbuf->hdr[3] = 0; + } else { + ha->tbuf->hdr[1] = + (uint8_t)(TARGET_DATA_SIZE >> 16); + ha->tbuf->hdr[2] = + (uint8_t)(TARGET_DATA_SIZE >> 8); + ha->tbuf->hdr[3] = + (uint8_t)TARGET_DATA_SIZE; + } + pkt->scsi_status = S_GOOD; + pkt->flags = (uint16_t)(OF_SSTS | OF_INC_RC | + OF_DATA_IN); + } else { +#ifdef QL_DEBUG_LEVEL_2 + qla2100_print("qla2100_atio_entry: SM_RDDB, zero length\n"); +#endif + pkt->scsi_status = S_GOOD; + pkt->flags = (uint16_t)(OF_SSTS | OF_INC_RC | + OF_NO_DATA); + } + break; + default: +#ifdef QL_DEBUG_LEVEL_2 + qla2100_print("qla2100_atio_entry: SM_RDDB unknown mode\n"); +#endif + *sense_ptr = 0x70; + *(sense_ptr+2) = SD_ILLREQ; + *(sense_ptr+7) = TARGET_SENSE_SIZE-8; + *(sense_ptr+12) = SC_ILLCDB; + len = 0; + pkt->scsi_status = S_CKCON; + pkt->flags = (uint16_t)(OF_SSTS | OF_INC_RC | + OF_NO_DATA); + break; + } + break; + default: +#ifdef QL_DEBUG_LEVEL_2 + qla2100_print("qla2100_atio_entry: Unknown SCSI command\n"); + qla2100_dump_buffer((uint8_t *)&pkt->cdb[0], MAX_CMDSZ); +#endif + BZERO(sense_ptr, TARGET_SENSE_SIZE); + *sense_ptr = 0x70; + *(sense_ptr+2) = SD_ILLREQ; + *(sense_ptr+7) = TARGET_SENSE_SIZE-8; + *(sense_ptr+12) = SC_INVOPCODE; + len = 0; + pkt->scsi_status = S_CKCON; + pkt->flags = (uint16_t)(OF_SSTS | OF_INC_RC | OF_NO_DATA); + break; + } +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,18) + if ( ha->flags.enable_64bit_addressing ) + qla2100_64bit_continue_io(ha, pkt, len, &phy_addr); + else +#endif + qla2100_32bit_continue_io(ha, pkt, len, &phy_addr); + break; + default: + break; + } + +#ifdef QL_DEBUG_LEVEL_3 + LEAVE("qla2100_atio_entry: exiting normally\n"); +#endif +} +#endif /* QLA2100_TARGET_MODE_SUPPORT */ + +/* +* qla2100_status_entry +* Processes received ISP status entry. +* +* Input: +* ha = adapter block pointer. +* pkt = entry pointer. +* done_q_first = done queue first pointer. +* done_q_last = done queue last pointer. +*/ +STATIC void +qla2100_status_entry(scsi_qla_host_t *ha, sts_entry_t *pkt, srb_t **done_q_first, + srb_t **done_q_last) { + uint32_t b, t, l; + uint8_t sense_sz = 0; + srb_t *sp, *sp2; + scsi_lu_t *q; + Scsi_Cmnd *cp; + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_status_entry"); +#endif + /* Validate handle. */ + if( pkt->handle < MAX_OUTSTANDING_COMMANDS ) + sp = ha->outstanding_cmds[pkt->handle]; + else + sp = 0; + + if( sp ) { + /* Free outstanding command slot. */ + ha->outstanding_cmds[pkt->handle] = 0; + cp = sp->cmd; + sp->ccode = pkt->comp_status; + sp->scode = pkt->scsi_status; + + sp->flags &= ~SRB_SENT; + /* Generate LU queue on cntrl, target, LUN */ + b = SCSI_BUS_32(cp); + t = SCSI_TCN_32(cp); + l = SCSI_LUN_32(cp); + q = GET_LU_Q(ha, b, t, l); + + /* Target busy */ + if( pkt->scsi_status & SS_BUSY_CONDITION && + (uint8_t)pkt->scsi_status != SS_RESERVE_CONFLICT ) { +#ifdef QL_DEBUG_LEVEL_2 + qla2100_print("qla2100_status_entry: SCSI busy status, scsi("); + qla2100_output_number((u_long)ha->host_no, 10); + qla2100_print(":"); + qla2100_output_number((u_long)b, 10); + qla2100_print(":"); + qla2100_output_number((u_long)t, 10); + qla2100_print(":"); + qla2100_output_number((u_long)l, 10); + qla2100_print(")\n"); +#endif + sp->retry_count--; + CMD_RESULT(cp) = (int) (DID_BUS_BUSY << 16) | + (pkt->scsi_status & 0xff); + + } +#if 0 + /* dg - 03/30 */ + else if( ha->loop_down_timer ) { +#endif + else if( ha->loop_down_timer || + ha->loop_state != LOOP_READY ) { +#ifdef QL_DEBUG_LEVEL_3 + qla2100_print("scsi("); + qla2100_output_number((u_long)ha->host_no, 10); + qla2100_print(":"); + qla2100_output_number((u_long)b, 10); + qla2100_print(":"); + qla2100_output_number((u_long)t, 10); + qla2100_print(":"); + qla2100_output_number((u_long)l, 10); + qla2100_print("): Loop Not ready - pid ="); + qla2100_output_number((u_long)sp->cmd->pid, 16); + qla2100_print("\n"); +#endif + CMD_RESULT(cp) = (int) (DID_BUS_BUSY << 16); + } else if( sp->port_down_retry_count > 1 && + (pkt->comp_status == CS_PORT_UNAVAILABLE || + pkt->comp_status == CS_PORT_LOGGED_OUT || + pkt->comp_status == CS_PORT_CONFIG_CHG || + pkt->comp_status == CS_PORT_BUSY) ) { + /* if the port is unavaliable and we haven't exceeded the port down count */ + /* then send command back to the mid-level. */ +#ifdef QL_DEBUG_LEVEL_2 + qla2100_print("scsi("); + qla2100_output_number((u_long)ha->host_no, 10); + qla2100_print(":"); + qla2100_output_number((u_long)b, 10); + qla2100_print(":"); + qla2100_output_number((u_long)t, 10); + qla2100_print(":"); + qla2100_output_number((u_long)l, 10); + qla2100_print("): Port Down Retry Cnt =("); + qla2100_output_number((u_long)sp->port_down_retry_count, 10); + qla2100_print("): , pid ="); + qla2100_output_number((u_long)sp->cmd->pid, 16); + qla2100_print(", status ="); + qla2100_output_number((u_long)pkt->comp_status, 16); + qla2100_print("\n"); +#endif + sp->port_down_retry_count--; + + /* dg 08/17/99 + * Force the SCSI layer to keep retrying until our + * port_down_retry_count expire. They will normally + * try and reset the bus after half the retries + * have completed, so double the count. + */ + CMD_RESULT(sp->cmd) = DID_BUS_BUSY << 16; + + /* Acquire target queue lock */ + if( !(q->q_flag & QLA2100_QSUSP) ) { + q->q_flag |= QLA2100_QSUSP; /* suspend starting new commands */ + + /* Decrement port down count on all pending commands. */ + /* and return them back to OS. */ + for( sp2 = q->q_first; sp2; sp2 = sp2->s_next ) { +#if 0 + if( sp2->port_down_retry_count ) /* dg - v4.31.4 */ + sp2->port_down_retry_count--; +#endif + /* v2.19.14 - unconditionally retry these + * requests. + */ + CMD_RESULT(sp2->cmd) = DID_BUS_BUSY << 16; + qla2100_callback(ha,sp2, TRUE); + } + q->q_first = q->q_last = NULL; + /* if port timer is not active then start it */ + if( !ha->queue_restart_timer ) { + ha->queue_restart_timer = PORT_RETRY_TIME; + } + if( TGT_Q(ha, b, t)->down_timer == 0 ) { + TGT_Q(ha, b, t)->down_timer = + ha->port_down_retry_count * PORT_RETRY_TIME; + } + } + + /* Release LU queue specific lock */ + } else { +#ifdef QL_DEBUG_LEVEL_2 + if( pkt->comp_status ) { + qla2100_print( + "qla2100_status_entry: Compl error = "); + qla2100_output_number((u_long)pkt->comp_status, 16); + qla2100_print(", scsi("); + qla2100_output_number((u_long)ha->host_no, 10); + qla2100_print(":"); + qla2100_output_number((u_long)b, 10); + qla2100_print(":"); + qla2100_output_number((u_long)t, 10); + qla2100_print(":"); + qla2100_output_number((u_long)l, 10); + qla2100_print("), retry count= "); + qla2100_output_number((u_long)sp->port_down_retry_count, 10); + qla2100_print(", pid = "); + qla2100_output_number((u_long)cp->pid, 16); + qla2100_print("\n"); + } +#endif + /* Set ISP completion status and target status byte. */ + CMD_RESULT(cp) = qla2100_return_status(ha, pkt, cp); + + memset((caddr_t)cp->sense_buffer, 0,sizeof(cp->sense_buffer)); + if( pkt->scsi_status & SS_CHECK_CONDITION ) { + /* Mid-level always zero sense buffer before giving it to us */ + if( pkt->scsi_status & SS_SENSE_LEN_VALID ) { + if( pkt->req_sense_length < CMD_SNSLEN(cp) ) + sense_sz = pkt->req_sense_length; + else + sense_sz = CMD_SNSLEN(cp) - 1; + + BCOPY((caddr_t)&pkt->req_sense_data, cp->sense_buffer, sense_sz); + + } + +#ifdef QL_DEBUG_LEVEL_2 + qla2100_print( + "qla2100_status_entry: Check condition Sense data, scsi("); + qla2100_output_number((u_long)ha->host_no, 10); + qla2100_print(":"); + qla2100_output_number((u_long)b, 10); + qla2100_print(":"); + qla2100_output_number((u_long)t, 10); + qla2100_print(":"); + qla2100_output_number((u_long)l, 10); + qla2100_print(")\n"); + if( sense_sz ) + qla2100_dump_buffer(cp->sense_buffer, sense_sz); +#endif + } + } + /* Place command on done queue. */ + qla2100_done_q_put(ha, sp, done_q_first, done_q_last); + } else { +#ifdef QL_DEBUG_LEVEL_2 + qla2100_print("qla2100_status_entry: ISP Invalid handle\n"); +#endif + printk(KERN_WARNING "!qla2100: Status Entry invalid handle"); + ha->flags.isp_abort_needed = TRUE; + } +#ifdef QL_DEBUG_LEVEL_3 + LEAVE("qla2100_status_entry"); +#endif +} + +/* +* qla2100_error_entry +* Processes error entry. +* +* Input: +* ha = adapter block pointer. +* pkt = entry pointer. +* done_q_first = done queue first pointer. +* done_q_last = done queue last pointer. +*/ +STATIC void +qla2100_error_entry(scsi_qla_host_t *ha, response_t *pkt, srb_t **done_q_first, + srb_t **done_q_last) { + srb_t *sp; + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_error_entry"); +#endif + +#ifdef QL_DEBUG_LEVEL_2 + if( pkt->entry_status & BIT_5 ) + qla2100_print("qla2100_error_entry: Invalid Entry Order\n"); + else if( pkt->entry_status & BIT_4 ) + qla2100_print("qla2100_error_entry: Invalid Entry Count\n"); + else if( pkt->entry_status & BIT_3 ) + qla2100_print("qla2100_error_entry: Invalid Entry Parameter\n"); + else if( pkt->entry_status & BIT_2 ) + qla2100_print("qla2100_error_entry: Invalid Entry Type\n"); + else if( pkt->entry_status & BIT_1 ) + qla2100_print("qla2100_error_entry: Busy\n"); + else + qla2100_print("qla2100_error_entry: UNKNOWN flag error\n"); +#endif + + /* Validate handle. */ + if( pkt->handle < MAX_OUTSTANDING_COMMANDS ) + sp = ha->outstanding_cmds[pkt->handle]; + else + sp = 0; + + if( sp ) { + /* Free outstanding command slot. */ + ha->outstanding_cmds[pkt->handle] = 0; + + sp->flags &= ~SRB_SENT; + /* Bad payload or header */ + if( pkt->entry_status & (BIT_5 + BIT_4 + BIT_3 + BIT_2) ) { + /* Bad payload or header, set error status. */ + CMD_RESULT(sp->cmd) = (int) DID_ERROR << 16; + + } else if( pkt->entry_status & BIT_1 && sp->retry_count ) /* FULL flag */ + { + sp->retry_count--; + CMD_RESULT(sp->cmd) = (int) DID_BUS_BUSY << 16; + } else { + /* Set error status. */ + CMD_RESULT(sp->cmd) =(int) DID_ERROR << 16; + } + /* Place command on done queue. */ + qla2100_done_q_put(ha, sp, done_q_first, done_q_last); + } else if( pkt->entry_type == COMMAND_A64_TYPE || + pkt->entry_type == COMMAND_TYPE ) { +#ifdef QL_DEBUG_LEVEL_2 + qla2100_print("qla2100_error_entry: ISP Invalid handle\n"); +#endif + printk(KERN_WARNING "!qla2100: Error Entry invalid handle"); + ha->flags.isp_abort_needed = TRUE; + } + +#ifdef QL_DEBUG_LEVEL_3 + LEAVE("qla2100_error_entry"); +#endif +} + +/* +* qla2100_abort_isp +* Resets ISP and aborts all outstanding commands. +* +* Input: +* ha = adapter block pointer. +* +* Returns: +* 0 = success +*/ +STATIC uint8_t +qla2100_abort_isp(scsi_qla_host_t *ha) { + uint16_t cnt; + srb_t *sp; + scsi_lu_t *q; + uint32_t b, t, l; +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95) + unsigned long cpu_flags = 0; +#endif + uint8_t status = 0; + + ENTER("qla2100_abort_isp"); + + DRIVER_LOCK + ha->flags.isp_abort_needed = FALSE; + if( !ha->flags.abort_isp_active && ha->flags.online ) { + ha->flags.abort_isp_active = TRUE; + ha->flags.online = FALSE; + ha->dpc_flags &= ~COMMAND_WAIT_NEEDED; + ha->dpc_flags &= ~COMMAND_WAIT_ACTIVE; + qla2100_stats.ispAbort++; + ha->isp_aborts++; + ha->sns_retry_cnt = 0; + printk(KERN_INFO + "qla2100: Performing ISP error recovery - ha= %p\n", + (void *) ha); + qla2100_reset_chip(ha); + + if( ha->loop_state != LOOP_DOWN ) { + ha->loop_state = LOOP_DOWN; + ha->loop_down_timer = LOOP_DOWN_TIME; + } + +#ifdef FC_IP_SUPPORT + /* Return all IP send packets */ + for (cnt = 0; cnt < MAX_SEND_PACKETS; cnt++) { + if (ha->apActiveIpQueue[cnt] != NULL) { + (*ha->pSendCompletionRoutine)(ha->apActiveIpQueue[cnt]); + + ha->apActiveIpQueue[cnt] = NULL; + } + } +#endif + + /* Requeue all commands in outstanding command list. */ + for( cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++ ) { + sp = ha->outstanding_cmds[cnt]; + if( sp ) { + ha->outstanding_cmds[cnt] = 0; + /* Generate LU queue on controller, target, LUN */ + b = SCSI_BUS_32(sp->cmd); + t = SCSI_TCN_32(sp->cmd); + l = SCSI_LUN_32(sp->cmd); + if ((q = (scsi_lu_t *)GET_LU_Q(ha, b, t, l))) { + /* Reset outstanding command count. */ + q->q_outcnt = 0; + q->q_flag &= ~QLA2100_QBUSY; + } + /* sp->flags &= ~(SRB_SENT | SRB_TIMEOUT); */ + sp->flags = 0; + /* we need to send the command back to OS */ + CMD_RESULT(sp->cmd) = DID_BUS_BUSY << 16; + CMD_HANDLE(sp->cmd) = (unsigned char *) NULL; + qla2100_done_q_put(ha, sp, (srb_t **)&ha->done_q_first, (srb_t **)&ha->done_q_last); + } + } + + if( ha->device_id == QLA2100_DEVICE_ID ) + qla2100_nvram_config(ha); + else + qla2200_nvram_config(ha); + + /* v2.19.12 */ + ha->retry_count = ql2xretrycount; + if( !qla2100_configure_loop(ha, TRUE) ) { + ha->flags.reset_marker = FALSE; + + if( !ha->loop_down_timer ) + qla2100_marker(ha, 0, 0, 0, MK_SYNC_ALL); + + ha->flags.online = TRUE; + + /* Enable target response to SCSI bus. */ + if( ha->flags.enable_target_mode ) + qla2100_enable_lun(ha); + +#ifdef FC_IP_SUPPORT + /* Reenable IP support */ + if (ha->flags.enable_ip) + qla2x00_ip_initialize(ha); +#endif + /* Enable ISP interrupts. */ + qla2100_enable_intrs(ha); + + /* v2.19.5b6 Return all commands */ + qla2100_abort_queues(ha, TRUE); + + /* Restart queues that may have been stopped. */ + ha->flags.abort_isp_active = FALSE; + /* 6/9 if( !ha->loop_down_timer ) */ + qla2100_restart_queues(ha,TRUE); + } else { + printk(KERN_WARNING + "qla2100: ISP error recovery failed, board disabled"); + qla2100_reset_adapter(ha); + qla2100_abort_queues(ha, FALSE); + } + } + +#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3) + if( status ) + qla2100_print("qla2100_abort_isp: **** FAILED ****\n"); +#endif +#ifdef QL_DEBUG_LEVEL_3 + else + LEAVE("qla2100_abort_isp"); +#endif + return(status); +} +/* +* qla2100_restart_watchdog_queue +* Restart device queues. +* +* Input: +* ha = adapter block pointer. +*/ +STATIC void +qla2100_restart_watchdog_queue(scsi_qla_host_t *ha) { + srb_t *sp, *sp_next; + + for( sp = ha->retry_q_first; (sp); sp = sp_next ) { + sp_next = sp->s_next; + /* when time expire return request back to OS as BUSY */ + qla2100_timeout_remove(ha, sp); + CMD_RESULT(sp->cmd) = DID_BUS_BUSY << 16; + CMD_HANDLE(sp->cmd) = (unsigned char *) NULL; + qla2100_done_q_put(ha, sp, (srb_t **)&ha->done_q_first, (srb_t **)&ha->done_q_last); + } + +} + +/* +* qla2100_restart_queues +* Restart device queues. +* +* Input: +* ha = adapter block pointer. +*/ +STATIC void +qla2100_restart_queues(scsi_qla_host_t *ha, uint8_t flush) { + scsi_lu_t *q; + uint32_t b, t, l; + srb_t *sp, *sp_next; + srb_t *done_q_first = (srb_t *) NULL; + srb_t *done_q_last = (srb_t *) NULL; + int cnt; + unsigned long cpu_flags = 0; + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_restart_queues"); +#endif + + ha->flags.restart_queues_needed = FALSE; + + /* + * start all queues working again. + */ + for( b = 0; b < MAX_BUSES; b++ ) + for( t = 0; t < ha->max_targets; t++ ) { + if( TGT_Q(ha, b, t) == NULL ) + continue; + for( l = 0; l < ha->max_luns; l++ ) { + q = (scsi_lu_t *) GET_LU_Q(ha, b, t, l); + if( q != NULL ) { + q->q_flag &= ~QLA2100_QSUSP; + if( q->q_first ) + qla2100_next(ha, q); + } + } + } + + /* + * Clear out our retry queue + */ + if( flush ) { + for( sp = ha->retry_q_first; (sp); sp = sp_next ) { + sp_next = sp->s_next; + /* when time expire return request back to OS as BUSY */ + qla2100_timeout_remove(ha, sp); + CMD_RESULT(sp->cmd) = DID_BUS_BUSY << 16; + CMD_HANDLE(sp->cmd) = (unsigned char *) NULL; + qla2100_done_q_put(ha, sp, (srb_t **)&done_q_first, (srb_t **)&done_q_last); + } + + /* Callback everything in done queue */ + cnt = 0; + while( done_q_first ) { + QLA2100_TIMER_LOCK(ha); + /* remove command from done list */ + sp = done_q_first; + if( !(done_q_first = sp->s_next) ) + done_q_last = NULL; + else + (done_q_first)->s_prev = NULL; + cnt++; + qla2100_stats.done_q_cnt--; + DEBUG(sp->state = 5;) + QLA2100_TIMER_UNLOCK(ha); + /* DEBUG(sprintf(debug_buff, + "qla2100_restart_queues: callback pid %d\n", + sp->cmd->pid);) + DEBUG(qla2100_print(debug_buff);) */ + qla2100_callback(ha,sp,FALSE); + } + DEBUG(sprintf(debug_buff,"qla2100_restart_queues: callback %d commands.\n",cnt);) + DEBUG(qla2100_print(debug_buff);) + } + +#ifdef QL_DEBUG_LEVEL_3 + LEAVE("qla2100_restart_queues"); +#endif +} + +/* +* qla2100_abort_queues +* Abort all commands on device queues. +* +* Input: +* ha = adapter block pointer. +*/ +STATIC void +qla2100_abort_queues(scsi_qla_host_t *ha, uint8_t doneqflg) { + scsi_lu_t *q; + uint32_t b, t, l; + srb_t *sp, *sp_next; + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_abort_queues"); +#endif + ha->flags.abort_queue_needed = FALSE; + + for( b = 0; b < MAX_BUSES; b++ ) + for( t = 0; t < ha->max_targets; t++ ) { + if( TGT_Q(ha, b, t) == NULL ) + continue; + for( l = 0; l < MAX_LUNS; l++ ) { + q = GET_LU_Q(ha, b, t, l); + if( q != NULL ) { + /* Try to acquire LU queue specific lock */ + /* if( queue is not busy ) + { */ + sp = q->q_first; + q->q_first = q->q_last = NULL; + + while( sp ) { + q->q_incnt--; + sp_next = sp->s_next; + CMD_RESULT(sp->cmd) = DID_BUS_BUSY << 16; + if ( doneqflg ) { + CMD_HANDLE(sp->cmd) = (unsigned char *) NULL; + qla2100_done_q_put(ha, sp, (srb_t **)&ha->done_q_first, (srb_t **)&ha->done_q_last); + } else + qla2100_callback(ha,sp,FALSE); + sp = sp_next; + } + /* } + else + ha->flags.abort_queue_needed = TRUE; + */ + } + } + } + +#ifdef QL_DEBUG_LEVEL_3 + LEAVE("qla2100_abort_queues"); +#endif +} + +/* +* qla2100_update_config +* Restart RISC in order to update the connection mode. +* +* Input: +* ha = adapter block pointer. +* +* Returns: +* 0 = success +*/ +uint8_t +qla2100_update_config(scsi_qla_host_t *ha) { + uint8_t status = 0; + +#ifdef QL_DEBUG_LEVEL_3 + qla2100_print("qla2100_update_config: entered\n"); +#endif + /* Turn-off flag, so we don't get called again */ + ha->flags.update_config_needed = FALSE; + + /* get the new topology */ + qla2100_configure_hba(ha); + + ha->init_cb->additional_firmware_options.connection_options = ha->operating_mode; + DEBUG(printk("qla2100_update_config: Setting new topology to %d\n" , ha->operating_mode);) + + qla2100_reset_chip(ha); + + if( ha->loop_state != LOOP_DOWN ) { + ha->loop_state = LOOP_DOWN; + ha->loop_down_timer = LOOP_DOWN_TIME; + } + + if( !(status = qla2100_configure_loop(ha, TRUE)) ) { + ha->flags.reset_marker = FALSE; + if( !ha->loop_down_timer ) + qla2100_marker(ha, 0, 0, 0, MK_SYNC_ALL); + + ha->flags.online = TRUE; + + /* Enable target response to SCSI bus. */ + if( ha->flags.enable_target_mode ) + qla2100_enable_lun(ha); + + } + + /* Enable ISP interrupts. */ + qla2100_enable_intrs(ha); + /* WRT_REG_WORD(®->ictrl, ISP_EN_INT + ISP_EN_RISC); */ +#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3) + if( status ) + qla2100_print("qla2100_update_config: **** FAILED ****\n"); +#endif +#ifdef QL_DEBUG_LEVEL_3 + else + qla2100_print("qla2100_update_config: exiting normally\n"); +#endif + return(status); +} + +/* +* qla2100_loop_resync +* Resync with fibre channel devices. +* +* Input: +* ha = adapter block pointer. +* +* Returns: +* 0 = success +*/ +STATIC uint8_t +qla2100_loop_resync(scsi_qla_host_t *ha) { + uint8_t status; + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_loop_resync"); +#endif + + ha->loop_state = LOOP_UPDATE; + if( ha->flags.online && !ha->flags.loop_resync_active && + !ha->flags.abort_isp_active ) { + ha->flags.loop_resync_active = TRUE; + if( !(status = qla2100_fw_ready(ha)) ) { + do { + ha->flags.loop_resync_needed = FALSE; + /* v2.19.05b6 */ + ha->loop_state = LOOP_UPDATE; + + /* Issue marker command. */ + qla2100_marker(ha, 0, 0, 0, MK_SYNC_ALL); + + /* Remap devices on Loop. */ + qla2100_update_fc_db(ha, TRUE); + + }while( !ha->loop_down_timer && ha->flags.loop_resync_needed ); + } + ha->flags.loop_resync_active = FALSE; + /* v2.19 - we don't want to call this if we are already + * in the loop resync code + */ + qla2100_restart_queues(ha,TRUE); + } else + status = 0; + + /* Restart queues that may have been stopped. */ + /* 04/10 if( !ha->loop_down_timer ) { + qla2100_restart_queues(ha,TRUE); + } */ + /* v2.19 */ + /* deleted qla2100_restart_queues(ha,TRUE); */ + +#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3) + if( status ) + qla2100_print("qla2100_loop_resync: **** FAILED ****\n"); +#endif +#ifdef QL_DEBUG_LEVEL_3 + else + LEAVE("qla2100_loop_resync"); +#endif + return(status); +} + +/* +* qla2100_debounce_register +* Debounce register. +* +* Input: +* port = register address. +* +* Returns: +* register value. +*/ +STATIC uint16_t +qla2100_debounce_register(volatile uint16_t *addr) { + volatile uint16_t ret; + volatile uint16_t ret2; + + do { + ret = RD_REG_WORD(addr); + ret2 = RD_REG_WORD(addr); + }while( ret != ret2 ); + + return(ret); +} + +/* qla2100_cmd_wait +* Stall driver until all outstanding commands are returned. +* +* Input: +* ha = adapter state pointer. +* +* Return; +* 0 -- Done +* 1 -- continue; +* +* Context: +* Kernel context. +*/ +STATIC uint8_t +qla2100_cmd_wait(scsi_qla_host_t *ha) { + uint16_t index; + uint8_t stat = 1; + + ENTER("qla2200_cmd_wait: started\n"); + + /* Wait for all outstanding commands to be returned. */ + for (index = 1; index < MAX_OUTSTANDING_COMMANDS; index++) { + if (ha->outstanding_cmds[index] == NULL) + continue; + + /* if command not completed then wait for it */ + if (ha->flags.isp_abort_needed){ + stat = 0; + break; + } + + if( (ha->dpc_flags & COMMAND_WAIT_ACTIVE) && + ha->cmd_wait_cnt-- == 0 ) { + ha->flags.isp_abort_needed = TRUE; + DEBUG(printk("qla2200_cmd_wait: ISP abort %d\n",index);) + } else { + ha->cmd_wait_cnt = 30; + ha->dpc_flags |= COMMAND_WAIT_ACTIVE; + } + + DEBUG5( if( (ha->dpc_flags & COMMAND_WAIT_ACTIVE) ) ) + DEBUG5(printk("qla2200_cmd_wait: on handle %d - cnt %d\n",index,ha->cmd_wait_cnt);) + + } + + if (index == MAX_OUTSTANDING_COMMANDS || + ha->flags.isp_abort_needed) { + ha->dpc_flags &= ~COMMAND_WAIT_NEEDED; + ha->dpc_flags &= ~COMMAND_WAIT_ACTIVE; + stat = 0; + } + return( stat ); +} + +/* +* qla2100_reset_chip +* Reset ISP chip. +* +* Input: +* ha = adapter block pointer. +*/ +STATIC void +qla2100_reset_chip(scsi_qla_host_t *ha) { + uint32_t cnt; + device_reg_t *reg = ha->iobase; + +#ifdef QL_DEBUG_LEVEL_3 + ENTER("qla2100_reset_chip"); +#endif + + /* Disable ISP interrupts. */ + qla2100_disable_intrs(ha); + /* WRT_REG_WORD(®->ictrl, 0); */ + +#if 1 + /* Pause RISC. */ + WRT_REG_WORD(®->host_cmd, HC_PAUSE_RISC); + for (cnt = 0; cnt < 30000; cnt++) { + if ((RD_REG_WORD(®->host_cmd) & HC_RISC_PAUSE) != 0) + break; + else + udelay(100); + } + + /* Select FPM registers. */ + WRT_REG_WORD(®->ctrl_status, 0x20); + + /* FPM Soft Reset. */ + WRT_REG_WORD(®->fpm_diag_config, 0x100); + + /* Select frame buffer registers. */ + WRT_REG_WORD(®->ctrl_status, 0x10); + + /* Reset frame buffer FIFOs. */ + WRT_REG_WORD(®->fb_cmd, 0xa000); + + /* Select RISC module registers. */ + WRT_REG_WORD(®->ctrl_status, 0); + + /* Reset RISC module. */ + WRT_REG_WORD(®->host_cmd, HC_RESET_RISC); + + /* Reset ISP semaphore. */ + WRT_REG_WORD(®->semaphore, 0); + + /* Release RISC module. */ + WRT_REG_WORD(®->host_cmd, HC_RELEASE_RISC); + + /* Wait for RISC to recover from reset. */ + for (cnt = 0; cnt < 30000; cnt++) { + if (RD_REG_WORD(®->mailbox0) != MBS_BUSY) + break; + else + udelay(100); + } + + /* Disable RISC pause on FPM parity error. */ + WRT_REG_WORD(®->host_cmd, HC_DISABLE_PARITY_PAUSE); +#else + /* Insure mailbox registers are free. */ + WRT_REG_WORD(®->semaphore, 0); + WRT_REG_WORD(®->host_cmd, HC_CLR_RISC_INT); + WRT_REG_WORD(®->host_cmd, HC_CLR_HOST_INT); + + /* clear mailbox busy */ + ha->flags.mbox_busy = FALSE; + + /* Reset ISP chip. */ + WRT_REG_WORD(®->ctrl_status, ISP_RESET); + + /* + * Delay after reset, for chip to recover. + * Otherwise causes system PANIC + */ + mdelay(2); + + for( cnt = 30000; cnt; cnt-- ) { + if( !(RD_REG_WORD(®->ctrl_status) & ISP_RESET) ) + break; + udelay(100); + } + + /* Reset RISC processor. */ + WRT_REG_WORD(®->host_cmd, HC_RESET_RISC); + WRT_REG_WORD(®->host_cmd, HC_RELEASE_RISC); + for( cnt = 30000; cnt; cnt-- ) { + if( RD_REG_WORD(®->mailbox0) != MBS_BUSY ) + break; + udelay(100); + } +#endif + +#ifdef QL_DEBUG_LEVEL_3 + LEAVE("qla2100_reset_chip"); +#endif +} + + +#ifdef RCSN +/* +* qla2100_device_resync +* Marks devices in the database that needs resynchronization. +* +* Input: +* ha = adapter block pointer. +* +* Context: +* Kernel context. +*/ +STATIC void +qla2100_device_resync(scsi_qla_host_t *ha) { + uint16_t index; + uint32_t mask; + rscn_t dev; + port_id_t p; + + ENTERT("qla2100_device_resync:"); + while (ha->rscn_out_ptr != ha->rscn_in_ptr || + ha->device_flags & RSCN_QUEUE_OVERFLOW) { + INTR_LOCK(ha); + BCOPY(&ha->rscn_queue[ha->rscn_out_ptr], + &dev, sizeof (rscn_t)); + + ha->rscn_out_ptr++; + if (ha->rscn_out_ptr == MAX_RSCN_COUNT) + ha->rscn_out_ptr = 0; + + /* Queue overflow, set switch default case. */ + if (ha->device_flags & RSCN_QUEUE_OVERFLOW) { + dev.format = 3; + ha->device_flags = ha->device_flags & ~RSCN_QUEUE_OVERFLOW; + } + + switch (dev.format) { + case 0: + mask = 0xffffff; + break; + case 1: + mask = 0xffff00; + break; + case 2: + mask = 0xff0000; + break; + default: + mask = 0x0; + dev.d_id.b24 = 0; + ha->rscn_out_ptr = ha->rscn_in_ptr; + break; + } + INTR_UNLOCK(ha); + + for (index = 0; index < MAX_FIBRE_DEVICES; index++) { + p.b.b24 = dev.d_id.b24; + if (ha->fc_db[index].flags & DEV_PUBLIC && + ha->fc_db[index].port_id[2] == p.r.port_id[2] && + ha->fc_db[index].port_id[1] == p.r.port_id[1] && + ha->fc_db[index].port_id[0] == p.r.port_id[0] ) + if (ha->fc_db[index].loop_id <= SNS_LAST_LOOP_ID) + printk(KERN_INFO "qla2100_device_resync: %d:%d:%d\n", + ha->fc_db[index].port_id[2] , + ha->fc_db[index].port_id[1] , + ha->fc_db[index].port_id[0] ) + ha->fc_db[index].flags |= DEV_MISSING; + } + } + } + + LEAVE("qla2100_device_resync: exiting normally"); +} +#endif /* RCSN */ + +#ifdef GET_PORT_INFO + +/* +* qla2100_get_port_database +* Issue enhanced get port database mailbox command +* and copy device name as necessary. +* +* Input: +* ha = adapter state pointer. +* dev = structure pointer. +* opt = mailbox 1 option byte. +* +* Returns: +* qla2100 local function return status code. +* +* Context: +* Kernel context. +*/ +STATIC int +qla2100_get_port_database(scsi_qla_host_t *ha, fcdev_t *dev, uint8_t opt) { + int rval = 0; + port_database_t *pd; + u_long phys_address = 0; + uint16_t mb[MAILBOX_REGISTER_COUNT]; + + ENTER("qla2200_get_port_database:"); +/* 4.10 */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18) + pd = KMALLOC(PORT_DATABASE_SIZE); + if ( pd != NULL ) { + phys_address = VIRT_TO_BUS(pd); + BZERO((caddr_t)pd, PORT_DATABASE_SIZE); + } +#else + pd = pci_alloc_consistent(ha->pdev, + PORT_DATABASE_SIZE, + &phys_address); + BZERO((caddr_t)pd, PORT_DATABASE_SIZE); +#endif + if( pd == NULL ) { + return 2; + } + BZERO((caddr_t)pd, PORT_DATABASE_SIZE); + + mb[0] = MBC_GET_PORT_DATABASE; + mb[1] = dev->loop_id << 8 | opt; + mb[2] = MSW(phys_address); + mb[3] = LSW(phys_address); + mb[6] = 0; + mb[7] = 0; + if( !qla2100_mailbox_command(ha, + BIT_7|BIT_6|BIT_3|BIT_2|BIT_1|BIT_0, + &mb[0]) ) { + /* Get d_id of device. */ + /* + dev->d_id.b.al_pa = pd->port_id[2]; + dev->d_id.b.area = pd->port_id[3]; + dev->d_id.b.domain = pd->port_id[0]; + dev->d_id.b.rsvd_1 = 0; + */ + + /* Get initiator status of device. */ + pd->prli_svc_param_word_3[0] & BIT_5 ? + (dev->flags = dev->flags | DEV_INITIATOR) : + (dev->flags = dev->flags & ~DEV_INITIATOR); + } else { + printk(KERN_WARNING "qla2200_get_port_database: [ERROR] failed"); + rval = 1; + } +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18) + KMFREE(pd, PORT_DATABASE_SIZE); +#else + pci_free_consistent(ha->pdev, PORT_DATABASE_SIZE, + pd, phys_address); +#endif + LEAVE("qla2200_get_port_database:"); + + return (rval); +} +#endif + +/* +* qla2100_configure_loop +* Resync with fibre channel devices. +* +* Input: +* ha = adapter block pointer. +* +* Returns: +* 0 = success +*/ + +STATIC uint8_t qla2100_configure_loop(scsi_qla_host_t *ha, uint8_t reuse) { + uint8_t status = 0; + + /* If firmware needs to be loaded */ + if( qla2100_isp_firmware(ha) ) { + ha->flags.online = FALSE; + if( !(status = qla2100_chip_diag(ha)) ) + status = qla2100_setup_chip(ha); + } + + if( !status && !(status = qla2100_init_rings(ha)) ) { + if( !qla2100_fw_ready(ha) ) { + ha->flags.reset_marker = FALSE; + do { + ha->flags.loop_resync_needed = FALSE; + /* remap devices on loop */ + qla2100_update_fc_db(ha, reuse); + }while( !ha->loop_down_timer && ha->flags.loop_resync_needed ); + } + } + return(status); +} + +/* + * This routine will wait for fabric devices for + * the reset delay. + */ +void qla2100_check_fabric_devices(scsi_qla_host_t *ha) { + uint16_t mb[MAILBOX_REGISTER_COUNT]; + + mb[0] = MBC_GET_FIRMWARE_STATE; + qla2100_mailbox_command(ha, BIT_0, &mb[0]); +} + +#if QLA2100_EXT_TIMEOUT +/* +* qla2100_extend_timeout +* This routine will extend the timeout to the specified value. +* +* Input: +* cmd = SCSI command structure +* +* Returns: +* None. +*/ +static void qla2100_extend_timeout(Scsi_Cmnd *cmd, int timeout) { + del_timer(&cmd->eh_timeout); + cmd->eh_timeout.expires = jiffies + timeout; + add_timer(&cmd->eh_timeout); +} +#endif +/* +* qla2100_display_fc_names +* This routine will the node names of the different devices found +* after port inquiry. +* +* Input: +* cmd = SCSI command structure +* +* Returns: +* None. +*/ +STATIC void qla2100_display_fc_names(scsi_qla_host_t *ha) { + uint16_t index; + + /* Display the node name for adapter */ + printk(KERN_INFO + "scsi-qla%d-adapter-node=%02x%02x%02x%02x%02x%02x%02x%02x;\n", + (int)ha->instance, + ha->init_cb->node_name[0], + ha->init_cb->node_name[1], + ha->init_cb->node_name[2], + ha->init_cb->node_name[3], + ha->init_cb->node_name[4], + ha->init_cb->node_name[5], + ha->init_cb->node_name[6], + ha->init_cb->node_name[7]); + + /* display the port name for adapter */ + printk(KERN_INFO + "scsi-qla%d-adapter-port=%02x%02x%02x%02x%02x%02x%02x%02x;\n", + (int)ha->instance, + ha->init_cb->port_name[0], + ha->init_cb->port_name[1], + ha->init_cb->port_name[2], + ha->init_cb->port_name[3], + ha->init_cb->port_name[4], + ha->init_cb->port_name[5], + ha->init_cb->port_name[6], + ha->init_cb->port_name[7]); + + /* Print out device port names */ + for (index = 0; index < MAX_FIBRE_DEVICES; index++) { + if (ha->fc_db[index].loop_id == PORT_UNUSED || + ha->fc_db[index].loop_id == PORT_AVAILABLE ) + continue; + +#if USE_PORTNAME + printk(KERN_INFO + "scsi-qla%d-target-%d=%02x%02x%02x%02x%02x%02x%02x%02x;\n", + (int)ha->instance, index, + ha->fc_db[index].wwn[0], + ha->fc_db[index].wwn[1], + ha->fc_db[index].wwn[2], + ha->fc_db[index].wwn[3], + ha->fc_db[index].wwn[4], + ha->fc_db[index].wwn[5], + ha->fc_db[index].wwn[6], + ha->fc_db[index].wwn[7]); +#else + printk(KERN_INFO + "scsi-qla%d-target-%d=%02x%02x%02x%02x%02x%02x%02x%02x;\n", + (int)ha->instance, index, + ha->fc_db[index].name[0], + ha->fc_db[index].name[1], + ha->fc_db[index].name[2], + ha->fc_db[index].name[3], + ha->fc_db[index].name[4], + ha->fc_db[index].name[5], + ha->fc_db[index].name[6], + ha->fc_db[index].name[7]); +#endif + } +} + +/* +* qla2100_find_propname +* Get property in database. +* +* Input: +* ha = adapter structure pointer. +* db = pointer to database +* propstr = pointer to dest array for string +* propname = name of property to search for. +* +* Returns: +* 0 = no property +* value = index of property value. +* +* Context: +* Kernel context. +*/ +STATIC uint8_t +qla2100_find_propname(scsi_qla_host_t *ha, + char *propname, char *propstr, char *db) { + char *np, *cp; + int i,k,l; + + /* find the specified string */ + for( l=0, cp = db; (*cp) && l < strlen(db) ; cp = np, l++ ) { + np = qla2100_get_line(cp, propstr); + DEBUG5(printk("qla2100_find_propname: %d - Searching for {%s} in cmd substr: {%s}, next line: {%s} \n",l,propname,propstr, np);) + /* find the property name */ + k = strlen(propname); + for ( i = 0; (propstr[i]) && i < strlen(db); i++ ) { + if( BCMP(propname,&propstr[i],k) == 0) { + DEBUG5(printk("qla2100_find_propname: found at index = %d\n",i+k );) + return (i+k); /* match */ + } + } + } + return (0); +} + + + +/* +* qla2100_get_prop_16chars +* Get an 8-byte property value for the specified property name by +* converting from the property string found in the configuration file. +* The resulting converted value is in big endian format (MSB at byte0). +* +* Input: +* ha = adapter state pointer. +* propname = property name pointer. +* propval = pointer to location for the converted property val. +* db = pointer to database +* +* Returns: +* 0 = value returned successfully. +* +* Context: +* Kernel context. +*/ +static int +qla2100_get_prop_16chars(scsi_qla_host_t *ha, char *propname, + char *propval, char *db) { + char *propstr; + int i, k; + int rval; + uint8_t nval; + uint8_t *pchar; + uint8_t *ret_byte; + uint8_t *tmp_byte; + uint8_t *retval = (uint8_t*)propval; + uint8_t tmpval[8] = {0, 0, 0, 0, 0, 0, 0, 0}; + uint16_t max_byte_cnt = 8; /* 16 chars = 8 bytes */ + uint16_t max_strlen = 16; + char buf[LINESIZE]; + + rval = qla2100_find_propname(ha, propname, buf, db); + if ( rval >= LINESIZE ) + rval = 0; + + propstr = &buf[rval]; + if ( *propstr == '=' ) + propstr++; /* ignore equal sign */ + + if (rval == 0 ) { + return (1); + } + + if (strlen(propstr) != max_strlen) { + printk(KERN_INFO + "qla2x00: Failed to find prop for %s - rval=%d, " + "strlen(propstr)=%d->(16), val=%s.\n", + propname, rval, (int)strlen(propstr),propstr); + return (1); + } + + /* Convert string to numbers. */ + + pchar = (uint8_t *)propstr; + tmp_byte = (uint8_t *)tmpval; + + rval = 0; + for (i = 0; i < max_strlen; i++) { + /* + * Check for invalid character, two at a time, + * then convert them starting with first byte. + */ + + if ((pchar[i] >= '0') && (pchar[i] <= '9')) { + nval = pchar[i] - '0'; + } else if ((pchar[i] >= 'A') && (pchar[i] <= 'F')) { + nval = pchar[i] - 'A' + 10; + } else if ((pchar[i] >= 'a') && (pchar[i] <= 'f')) { + nval = pchar[i] - 'a' + 10; + } else { + /* invalid character */ + rval = 1; + break; + } + + if (i & BIT_0) { + *tmp_byte = *tmp_byte | nval; + tmp_byte++; + } else { + *tmp_byte = *tmp_byte | nval << 4; + } + } + + if (rval != 0) { + /* Encountered invalid character. */ + return (rval); + } + + /* Copy over the converted value. */ + + ret_byte = retval; + tmp_byte = tmpval; + + i = max_byte_cnt; + k = 0; + while (i--) { + *ret_byte++ = *tmp_byte++; + } + + /* big endian retval[0]; */ + return (0); +} + +/* +* qla2100_get_properties +* Find all properties for the specified adapeter in +* command line. +* +* Input: +* ha = adapter block pointer. +* cmdline = pointer to command line string +* +* Context: +* Kernel context. +*/ +static void +qla2100_get_properties(scsi_qla_host_t *ha, char *cmdline) { + char propbuf[LINESIZE]; + int tmp_rval; + uint16_t tgt; + uint8_t tmp_name[8]; + + /* Adapter FC node names. */ + sprintf(propbuf, "scsi-qla%d-adapter-node", (int) ha->instance); + qla2100_get_prop_16chars (ha, propbuf, + (caddr_t)(&ha->init_cb->node_name), cmdline); + + sprintf(propbuf, "scsi-qla%d-adapter-port", (int) ha->instance); + + /* DG 04/07 check portname of adapter */ + qla2100_get_prop_16chars (ha, propbuf, + (caddr_t)(tmp_name), cmdline); + if (BCMP(&ha->init_cb->port_name[0], &tmp_name[0], 8) != 0) { + /* + * Adapter port name is WWN, and cannot be changed. + * Inform users of the mismatch, then just continue driver + * loading using the original adapter port name in NVRAM. + */ + printk(KERN_WARNING + "qla2x00: qla%ld found mismatch in adapter port names.\n", + ha->instance); + printk(KERN_INFO + " qla%ld port name found in NVRAM -> %02x%02x%02x%02x%02x%02x%02x%02x\n", + ha->instance, + ha->init_cb->port_name[0], + ha->init_cb->port_name[1], + ha->init_cb->port_name[2], + ha->init_cb->port_name[3], + ha->init_cb->port_name[4], + ha->init_cb->port_name[5], + ha->init_cb->port_name[6], + ha->init_cb->port_name[7]); + printk(KERN_INFO + " qla%ld port name found on command line -> %02x%02x%02x%02x%02x%02x%02x%02x\n", + ha->instance, + tmp_name[0], + tmp_name[1], + tmp_name[2], + tmp_name[3], + tmp_name[4], + tmp_name[5], + tmp_name[6], + tmp_name[7]); + printk(KERN_INFO + " Using port name from NVRAM.\n"); + } + + /* FC name for devices */ + for (tgt = 0; tgt < MAX_FIBRE_DEVICES; tgt++) { + sprintf(propbuf, "scsi-qla%d-target-%d", + (int) ha->instance, tgt); + + tmp_rval = qla2100_get_prop_16chars (ha, propbuf, + tmp_name, cmdline); + if ( tmp_rval == 0 ) { + /* Got a name for this ID. */ + + /* Save to appropriate fields. */ +#if USE_PORTNAME /* updated for ioctl merge */ + BCOPY(tmp_name, ha->fc_db[tgt].wwn, 8); +#else + BCOPY(tmp_name, ha->fc_db[tgt].name, 8); +#endif + ha->fc_db[tgt].loop_id = PORT_AVAILABLE; + ha->fc_db[tgt].flag = 0; /* v2.19.05b3 */ + ha->fc_db[tgt].flag |= DEV_CONFIGURED; + DEBUG(printk("Target %d - configured by user: ",tgt);) + DEBUG(printk("scsi-target=\"%08x%08x\"\n", + tmp_name[1], + tmp_name[0]);)/*ioctl support change*/ + } + } + +} + +/* +* Declarations for load module +*/ + +/* 2.19.15 */ +#ifndef FC_IP_SUPPORT +/************************************************************************/ +/* qla2x00_reserve_loopid */ +/* This routine reserves an unused public loop ID. */ +/* */ +/* Arguments: */ +/* ha - adapter block pointer */ +/* pLoopID - pointer to word for returning loop ID */ +/* */ +/* Return Value: */ +/* QL_STATUS_SUCCESS if no error */ +/* QL_STATUS_RESOURCE_ERROR if out of loop IDs */ +/************************************************************************/ + +static int qla2x00_reserve_loopid(scsi_qla_host_t *ha, uint16_t *pLoopId) +{ + int i; + + /* Look for unused loop ID */ + for (i = ha->min_external_loopid; i < ha->max_public_loop_ids; i++) + { + if (!ha->fabricid[i].in_use) + { + /* Found free loop ID */ + ha->fabricid[i].in_use = TRUE; + *pLoopId = i; + + DEBUG(sprintf(debug_buff, "qla2x00_reserve_loopid: assigned loop ID %x\n\r", *pLoopId)); + DEBUG(qla2100_print(debug_buff)); + return QL_STATUS_SUCCESS; + } + } + + /* Out of loop IDs */ + *pLoopId = ha->max_public_loop_ids + 1; /* Set out of range */ + DEBUG(qla2100_print("qla2x00_reserve_loopid: out of loop IDs\n\r")); + return QL_STATUS_RESOURCE_ERROR; +} /* qla2x00_reserve_loopid */ + + +/************************************************************************/ +/* qla2x00_free_loopid */ +/* This routine frees a public loop ID. */ +/* */ +/* Arguments: */ +/* ha - adapter block pointer */ +/* wLoopID - loop ID to free */ +/* */ +/* Return Value: */ +/* none */ +/************************************************************************/ + +static void qla2x00_free_loopid(scsi_qla_host_t *ha, uint16_t wLoopId) +{ + if (wLoopId < ha->max_public_loop_ids) + { + ha->fabricid[wLoopId].in_use = FALSE; + DEBUG(sprintf(debug_buff, "qla2x00_free_loopid: free loop ID %x\n\r", wLoopId)); + DEBUG(qla2100_print(debug_buff)); + } + else + { + DEBUG(sprintf(debug_buff, "qla2x00_free_loopid: loop ID %x out of range\n\r", wLoopId)); + DEBUG(qla2100_print(debug_buff)); + } +} /* qla2x00_free_loopid */ + + +/************************************************************************/ +/* qla2x00_login_public_device */ +/* This routine issues mailbox command to login fabric port. */ +/* */ +/* Arguments: */ +/* ha - adapter block pointer */ +/* wLoopID - public loop ID for device */ +/* pPortID - pointer to port ID for fabric login */ +/* wOptions - MBC_NO_PLOGI_IF_LOGGED_IN (bit 0) */ +/* MBC_NO_PROCESS_LOGIN (bit 1) */ +/* */ +/* Return Value: */ +/* QL_STATUS_SUCCESS if no error */ +/* QL_STATUS_ERROR if any other error */ +/* QL_STATUS_RESOURCE_ERROR if out of loop IDs */ +/* QL_STATUS_FATAL_ERROR if fatal error */ +/************************************************************************/ + +static int qla2x00_login_public_device(scsi_qla_host_t *ha, + uint16_t *pLoopId, + uint8_t *pPortID, + uint16_t wOptions) +{ + int status = QL_STATUS_SUCCESS; + int wRetryCount; + uint16_t mb[MAILBOX_REGISTER_COUNT]; + + /* Set retry count */ + wRetryCount = 2; + + while (wRetryCount--) + { + DEBUG(sprintf(debug_buff, "qla2x00_login_public_device: login loop ID: %x port ID: %x, option: %x\n\r", + *pLoopId, *pPortID << 16 | *(pPortID+1) << 8 | *(pPortID+2), wOptions )); + DEBUG(qla2100_print(debug_buff)); + + /* Issue fabric login request */ + mb[0] = MBC_LOGIN_FABRIC_PORT; + mb[1] = (uint16_t)(*pLoopId << 8 | (wOptions & 0x00FF)); + mb[2] = (uint16_t)(*pPortID); + mb[3] = (uint16_t)(*(pPortID+1) << 8 | *(pPortID+2)); + if (qla2100_mailbox_command(ha, BIT_3|BIT_2|BIT_1|BIT_0, &mb[0]) == 0) + { + /* Login successful */ + status = QL_STATUS_SUCCESS; + break; + } + + /* Login failed, check status */ + if (mb[0] == MBS_FATAL_ERROR) + { + DEBUG(qla2100_print("qla2x00_login_public_device: LOGIN_FABRIC_PORT fatal error\n\r")); + status = QL_STATUS_FATAL_ERROR; + break; + } + else if (mb[0] == MBS_LOOP_ID_IN_USE) + { + DEBUG(sprintf(debug_buff, "qla2x00_login_public_device: loop ID %x in use by port ID %x (4008)\n\r", + *pLoopId, mb[1] << 16 | mb[2])); + DEBUG(qla2100_print(debug_buff)); + + /* Allocate another loop ID and retry */ + if ((status = qla2x00_reserve_loopid(ha, pLoopId)) == QL_STATUS_SUCCESS) + { + wRetryCount++; + } + else + { + break; + } + } + else if (mb[0] == MBS_PORT_ID_IN_USE) + { + DEBUG(sprintf(debug_buff, "qla2x00_login_public_device: port ID already assigned to loop ID %x (4007)\n\r", + mb[1])); + DEBUG(qla2100_print(debug_buff)); + + /* Free loop ID and use one assigned by RISC */ + qla2x00_free_loopid(ha, *pLoopId); + *pLoopId = mb[1]; + + /* Must reissue login mailbox command with new loop ID */ + wRetryCount++; + } + else + { + DEBUG(sprintf(debug_buff, "qla2x00_login_public_device: login error status %x, MB1: %x, MB2: %x\n\r", + mb[0], mb[1], mb[2])); + DEBUG(qla2100_print(debug_buff)); + status = QL_STATUS_ERROR; + } + } + return(status); +} /* qla2x00_login_public_device */ + + +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0) +#ifdef MODULE +Scsi_Host_Template driver_template = QLA2100_LINUX_TEMPLATE; +#include "scsi_module.c" +#endif +#else /* new kernel scsi initialization scheme */ +static Scsi_Host_Template driver_template = QLA2100_LINUX_TEMPLATE; +#include "scsi_module.c" +#endif + +#ifdef QL_DEBUG_ROUTINES +/****************************************************************************/ +/* Driver Debug Functions. */ +/****************************************************************************/ + + /* + * Get byte from I/O port + */ +STATIC uint8_t +qla2100_getbyte(uint8_t *port) { + uint8_t ret; + +#ifdef MEMORY_MAPPED_IO + ret = *port; +#else + ret = inb((int)port); +#endif + + if( ql2x_debug_print ) { + qla2100_print("qla2100_getbyte: address = "); + qla2100_output_number((u_long)port, 16); + qla2100_print(" data = 0x"); + qla2100_output_number((u_long)ret, 16); + qla2100_print("\n"); + } + + return(ret); +} + + /* + * Get word from I/O port + */ +STATIC uint16_t +qla2100_getword(uint16_t *port) { + uint16_t ret; + +#ifdef MEMORY_MAPPED_IO + ret = *port; +#else + ret = inw((int)port); +#endif + + if( ql2x_debug_print ) { + qla2100_print("qla2100_getword: address = "); + qla2100_output_number((u_long)port, 16); + qla2100_print(" data = 0x"); + qla2100_output_number((u_long)ret, 16); + qla2100_print("\n"); + } + + return(ret); +} + + /* + * Get double word from I/O port + */ +STATIC uint32_t +qla2100_getdword(uint32_t *port) { + uint32_t ret; + +#ifdef MEMORY_MAPPED_IO + ret = *port; +#else + ret = inl((int)port); +#endif + + if( ql2x_debug_print ) { + qla2100_print("qla2100_getdword: address = "); + qla2100_output_number((u_long)port, 16); + qla2100_print(" data = 0x"); + qla2100_output_number((u_long)ret, 16); + qla2100_print("\n"); + } + + return(ret); +} + + /* + * Send byte to I/O port + */ +STATIC void +qla2100_putbyte(uint8_t *port, uint8_t data) { +#ifdef MEMORY_MAPPED_IO + *port = data; +#else + outb(data, (int)port); +#endif + + if( ql2x_debug_print ) { + qla2100_print("qla2100_putbyte: address = "); + qla2100_output_number((u_long)port, 16); + qla2100_print(" data = 0x"); + qla2100_output_number((u_long)data, 16); + qla2100_print("\n"); + } +} + + /* + * Send word to I/O port + */ +STATIC void +qla2100_putword(uint16_t *port, uint16_t data) { +#ifdef MEMORY_MAPPED_IO + *port = data; +#else +#ifdef _LINUX_IOPORTS + outw(data, (int)port); +#else + outw((int)port, data); +#endif +#endif + + if( ql2x_debug_print ) { + qla2100_print("qla2100_putword: address = "); + qla2100_output_number((u_long)port, 16); + qla2100_print(" data = 0x"); + qla2100_output_number((u_long)data, 16); + qla2100_print("\n"); + } +} + + /* + * Send double word to I/O port + */ +STATIC void +qla2100_putdword(uint32_t *port, uint32_t data) { +#ifdef MEMORY_MAPPED_IO + *port = data; +#else +#ifdef _LINUX_IOPORTS + outl(data,(int)port); +#else + outl((int)port, data); +#endif +#endif + + if( ql2x_debug_print ) { + qla2100_print("qla2100_putdword: address = "); + qla2100_output_number((u_long)port, 16); + qla2100_print(" data = 0x"); + qla2100_output_number((u_long)data, 16); + qla2100_print("\n"); + } +} + + /* + * Dummy function to prevent warnings for + * declared and unused debug functions + */ +void +qla2100_debug(void) { + qla2100_getbyte(0); + qla2100_getword(0); + qla2100_getdword(0); + qla2100_putbyte(0, 0); + qla2100_putword(0, 0); + qla2100_putdword(0, 0); +} + + /* + * Out character to COM1 port. + * PORT must be at standard address for COM1 = 0x3F8 + * This port is available on both Lion and ia32 systems + */ +#define OUTB(addr,data) outb((data),(addr)) +STATIC void +qla2100_putc(int8_t c) { +#ifdef QL_DEBUG_CONSOLE + + printk("%c",c); + +#else /* QL_DEBUG_CONSOLE */ + + uint8_t data; + int com_addr = 0x3f8; /* COM1 */ + int hardware_flow_control = 1; + int software_flow_control = 0; + uint8_t loop = TRUE; + + do { + + /* Wait for transmitter holding and shift registers for empty. */ + do { + data = inb(com_addr+5); + }while( !(data & BIT_6) ); + + /* + * Set BAUD rate for COM1 to 9600 + */ + + /* BAUD rate divisor LSB. */ + OUTB(com_addr+3, 0x83); + + /* BAUD rate divisor MSB. */ + OUTB(com_addr, 0xc); /* 0xC = 9600 baud */ + + /* Set No parity, 8 bits, 1 stop bit and + select interrupt enable register. */ + OUTB(com_addr+3, 3); + + /* Disable interrupts. */ + OUTB(com_addr+1, 0); + + /* Set data terminal ready and request to send */ + OUTB(com_addr+1, 0); + + if( hardware_flow_control ) { + /* Wait for clear-to-send and data-set-ready */ + do { + data = inb(com_addr+6) & (BIT_5 + BIT_4); + }while( data != (BIT_5 + BIT_4) ); + } else if( software_flow_control ) { + /* Test for data ready. */ + data = inb(com_addr+5); + if( data & BIT_0 ) { + /* If XOFF */ + data = inb(com_addr); + if( data == '\023' ) { + /* Wait for XON */ + do { + /* Wait for int8_t */ + do { + data = inb(com_addr+5); + }while( !(data & BIT_0) ); + data = inb(com_addr); + }while( data != '\021' ); + } + } + } + + /* Output character. */ + OUTB(com_addr, c); + + /* Add return. */ + if( c == '\n' ) + c = '\r'; + else + loop = FALSE; + + }while( loop ); +#endif /* QL_DEBUG_CONSOLE */ +} + + /* + * Out NULL terminated string to COM port. + */ +STATIC void +qla2100_print(int8_t *s) { + if( ql2x_debug_print ) { +#ifdef QL_DEBUG_CONSOLE + printk("%s",s); +#else + /* Output string. */ + while( *s ) + qla2100_putc(*s++); +#endif + } +} + + /* + * Output long number to COM port. + */ +STATIC void + qla2100_output_number(u_long n, uint8_t base) { + int8_t str[12]; + int8_t *s = &str[11]; + uint8_t output = 0; + uint8_t hex = FALSE; + + if( ql2x_debug_print ) { + if( base == 10 || base == 16 ) { + if( base == 16 && n > 9 ) + hex = TRUE; + + *s = 0; + do { + s--; + *s = n % base; + if( *s > 9 ) + *s += 55; + else + *s += '0'; + n /= base; + }while( n ); + + for( ; *s; s++ ) { + if( *s != '0' ) + output = 1; + if( output ) + qla2100_putc(*s); + } + if( !output ) + qla2100_putc(*--s); + + if( hex ) + qla2100_putc('h'); + } + } +} + +STATIC void +qla2100_dump_buffer(uint8_t *b, uint32_t size) { + uint32_t cnt; + uint8_t c; + + if( ql2x_debug_print ) { + qla2100_print( + " 0 1 2 3 4 5 6 7 8 9 Ah Bh Ch Dh Eh Fh\n"); + qla2100_print( + "---------------------------------------------------------------\n"); + + for( cnt = 0; cnt < size; ) { + c = *b++; + if( c < 16 ) + qla2100_putc(' '); + qla2100_output_number((uint32_t)c, 16); + cnt++; + if( !(cnt % 16) ) + qla2100_print("\n"); + else if( c < 10 ) + qla2100_print(" "); + else + qla2100_putc(' '); + } + if( cnt % 16 ) + qla2100_print("\n"); + } +} + /************************************************************************** + * ql2100_print_scsi_cmd + * + **************************************************************************/ +void qla2100_print_scsi_cmd(Scsi_Cmnd *cmd) { + scsi_qla_host_t *ha; + struct Scsi_Host *host = cmd->host; + srb_t *sp; + + int i; + ha = (scsi_qla_host_t *) host->hostdata; + + ql2x_debug_print = 1; + sp = (srb_t *) CMD_SP(cmd); + sprintf(debug_buff,"SCSI Command=0x%p, Handle=0x%08lx pid=%x\n\r", cmd, (u_long)CMD_HANDLE(cmd),cmd->pid); + qla2100_print(debug_buff); + sprintf(debug_buff," chan=%d, target = 0x%02x, lun = 0x%02x, cmd_len = 0x%02x\n\r", + cmd->channel, cmd->target, cmd->lun, cmd->cmd_len); + qla2100_print(debug_buff); + qla2100_print(" CDB = "); + for( i = 0; i < cmd->cmd_len; i++ ) { + sprintf(debug_buff,"0x%02x ", cmd->cmnd[i]); + qla2100_print(debug_buff); + } + + sprintf(debug_buff,"\n\r seg_cnt =%d, retries=%d, serial_number_at_timeout=0x%lx\n\r",cmd->use_sg,cmd->retries,cmd->serial_number_at_timeout); + qla2100_print(debug_buff); + sprintf(debug_buff," request buffer=0x%p, request buffer len=0x%x\n\r",cmd->request_buffer,cmd->request_bufflen); + qla2100_print(debug_buff); + sprintf(debug_buff," tag=%d, flags=0x%x, transfersize=0x%x \n\r", + cmd->tag, cmd->flags,cmd->transfersize); + qla2100_print(debug_buff); + sprintf(debug_buff," Pid=%d, SP=0x%x\n\r", (int)cmd->pid, CMD_SP(cmd)); + + qla2100_print(debug_buff); + sprintf(debug_buff," sp flags=0x%lx, sp state=%x, wdgtime=%d\n\r",sp->flags,sp->state,sp->wdg_time); + qla2100_print(debug_buff); +} + + +void qla2100_print_q_info(scsi_lu_t *q) { + sprintf(debug_buff,"Queue info: queue in =%d, queue out= %d, flags=0x%lx\n\r", q->q_incnt, q->q_outcnt, q->q_flag); + qla2100_print(debug_buff); +} +#endif + + + + + /************************************************************************** + * ql2100_dump_regs + * + **************************************************************************/ +static void qla2100_dump_regs(struct Scsi_Host *host) { + printk("Mailbox registers:\n"); + printk("qla2100 : mbox 0 0x%04x \n", inw(host->io_port + 0x10)); + printk("qla2100 : mbox 1 0x%04x \n", inw(host->io_port + 0x12)); + printk("qla2100 : mbox 2 0x%04x \n", inw(host->io_port + 0x14)); + printk("qla2100 : mbox 3 0x%04x \n", inw(host->io_port + 0x16)); + printk("qla2100 : mbox 4 0x%04x \n", inw(host->io_port + 0x18)); + printk("qla2100 : mbox 5 0x%04x \n", inw(host->io_port + 0x1a)); +#ifdef TRACECODE + sprintf(debug_buff,"qla2100 : mbox 0 0x%04x \n\r", inw(host->io_port + 0x10)); + qla2100_print(debug_buff); + sprintf(debug_buff,"qla2100 : mbox 1 0x%04x \n\r", inw(host->io_port + 0x12)); + qla2100_print(debug_buff); + sprintf(debug_buff,"qla2100 : mbox 2 0x%04x \n\r", inw(host->io_port + 0x14)); + qla2100_print(debug_buff); + sprintf(debug_buff,"qla2100 : mbox 3 0x%04x \n\r", inw(host->io_port + 0x16)); + qla2100_print(debug_buff); + sprintf(debug_buff,"qla2100 : mbox 4 0x%04x \n\r", inw(host->io_port + 0x18)); + qla2100_print(debug_buff); + sprintf(debug_buff,"qla2100 : mbox 5 0x%04x \n\r", inw(host->io_port + 0x1a)); + qla2100_print(debug_buff); +#endif +} + + +#if STOP_ON_ERROR + /************************************************************************** + * ql2100_panic + * + **************************************************************************/ +static void qla2100_panic(char *cp, struct Scsi_Host *host) { + scsi_qla_host_t *ha; + long *fp; + + ha = (scsi_qla_host_t *) host->hostdata; + DEBUG2(ql2x_debug_print = 1;) + sprintf(debug_buff,"qla2100 - PANIC: %s\n",cp); + qla2100_print(debug_buff); + sprintf(debug_buff,"Current time=0x%lx\n", jiffies); + qla2100_print(debug_buff); + sprintf(debug_buff,"Number of pending commands =0x%lx\n", ha->actthreads); + qla2100_print(debug_buff); + sprintf(debug_buff,"Number of queued commands =0x%lx\n", ha->qthreads); + qla2100_print(debug_buff); + sprintf(debug_buff,"Number of free entries = (%d)\n",ha->req_q_cnt); + qla2100_print(debug_buff); + sprintf(debug_buff,"Request Queue @ 0x%lx, Response Queue @ 0x%lx\n", + ha->request_dma, + ha->response_dma); + qla2100_print(debug_buff); + sprintf(debug_buff,"Request In Ptr %d\n", ha->req_ring_index); + qla2100_print(debug_buff); + fp = (long *) &ha->flags; + sprintf(debug_buff,"HA flags =0x%lx\n", *fp); + qla2100_print(debug_buff); + ql2100_dump_requests(ha); + qla2100_dump_regs(host); + cli(); + for( ;; ) { + QLA2100_DELAY(2); barrier(); + } + sti(); +} +#endif +#if 0 + static void qla2100_set_flags(int flag) { + + switch( flag ) { + case 0x1: + qla2100_verbose = 1L; + + } + + } +#endif + /************************************************************************** + * ql2100_dump_requests + * + **************************************************************************/ +void +ql2100_dump_requests(scsi_qla_host_t *ha) { + + Scsi_Cmnd *cp; + srb_t *sp; + int i; +#ifdef QL_DEBUG_ROUTINES + qla2100_print("Outstanding Commands on controller:\n\r"); +#else + printk(KERN_INFO "Outstanding Commands on controller:\n"); +#endif + for( i=0; i < MAX_OUTSTANDING_COMMANDS; i++ ) { + if( (sp = ha->outstanding_cmds[i]) == NULL ) + continue; + if( (cp = sp->cmd) == NULL ) + continue; + sprintf(debug_buff,"(%d): Pid=%ld, sp flags=0x%x, cmd=0x%p\n\r", i, (int)sp->cmd->pid, (long)sp->flags,CMD_SP(sp->cmd)); + +#ifdef QL_DEBUG_ROUTINES + qla2100_print(debug_buff); +#else + printk(KERN_INFO "%s",debug_buff); +#endif + } + +} + + + /************************************************************************** + * qla2100_setup + * + * Handle Linux boot parameters. This routine allows for assigning a value + * to a parameter with a ';' between the parameter and the value. + * ie. qla2x00=arg0;arg1;...;argN; OR + * via the command line. + * ie. qla2x00 ql2xopts=arg0;arg1;...;argN; + **************************************************************************/ +void qla2100_setup(char *s, int *dummy) { + char *cp, *np; + char *slots[MAXARGS]; + char **argv = &slots[0]; + char buf[LINESIZE]; + int argc, opts; + + /* + * Determine if we have any properties. + */ + cp = s; + opts = 1; + while( *cp && (np = qla2100_get_line(cp, buf)) != NULL ) { + if( BCMP("scsi-qla",buf,8) == 0 ) { + DEBUG(printk("qla2100: devconf=%s\n",cp);) + ql2xdevconf = cp; + (opts > 0)? opts-- : 0; + break; + } + opts++; + cp = np; + } + /* + * Parse the args before the properties + */ + if( opts ) { + opts = (opts > MAXARGS-1)? MAXARGS-1: opts; + argc = qla2100_get_tokens(s, argv, opts); + while (argc > 0 ) { + cp = *argv; + DEBUG(printk("scsi: found cmd arg =[%s]\n", cp);) + if( strcmp(cp, "verbose") == 0 ) { + DEBUG(printk("qla2100: verbose\n");) + qla2100_verbose++; + } else if (strcmp(cp, "quiet") == 0) { + qla2100_quiet = 1; + } else if( strcmp(cp, "reinit_on_loopdown") == 0 ) { + qla2100_reinit++; + DEBUG(printk("qla2100: reinit_on_loopdown\n");) + } + argc--, argv++; + } + } + +} + + /********************** qla2100_get_line ********************* + * qla2100_get_line + * Copy a substring from the specified string. The substring + * consists of any number of chars seperated by white spaces (i.e. spaces) + * and ending with a newline '\n' or a semicolon ';'. + * + * Enter: + * str - orig string + * line - substring + * + * Returns: + * cp - pointer to next string + * or + * null - End of string + *************************************************************/ +static char *qla2100_get_line(char *str, char *line) { + register char *cp = str; + register char *sp = line; + + /* skip preceeding spaces */ + while( *cp && *cp == ' ' ) + ++cp; + while ( (*cp) && *cp != '\n' && *cp != ';' ) /* end of line */ + *sp++ = *cp++; + + *sp = '\0'; + DEBUG5(printk("qla2100_get_line: %s\n",line);) + if( (*cp) ) { + cp++; + return( cp ); + } + return( NULL ); +} + + + /**************************** get_tokens ********************* + * Parse command line into argv1, argv2, ... argvX + * Arguments are seperated by white spaces and colons and end + * with a NULL. + *************************************************************/ +static int qla2100_get_tokens(char *line, char **argv, int maxargs ) { + register char *cp = line; + int count = 0; + + while( *cp && count < maxargs ) { + /* skip preceeding spaces */ + while((*cp) && *cp == ' ') + ++cp; + /* symbol starts here */ + argv[count++] = cp; + /* skip symbols */ + while ( (*cp) && !( *cp == ' ' || *cp == ';' || *cp == ':' ) ) + cp++; + /* replace comma or space with a null */ + if( (*cp) && (*cp ==' ' ) && argv[count-1] != cp ) + *cp++ = '\0'; + } + return( count ); +} + +#ifdef FC_IP_SUPPORT + /* Include routines for supporting IP */ +#include "qla2100ip.c" +#endif /* FC_IP_SUPPORT */ + +#if APIDEV +/****************************************************************************/ +/* Create character driver "HbaApiDev" w dynamically allocated major number */ +/* and create "/proc/scsi/qla2x00/HbaApiNode" as the device node associated */ +/* with the major number. */ +/****************************************************************************/ + +#define APIDEV_NODE "HbaApiNode" +#define APIDEV_NAME "HbaApiDev" + +static int apidev_major = 0; +static struct Scsi_Host *apidev_host = 0; + +static int apidev_open(struct inode *inode, struct file *file) +{ + printk (KERN_INFO "qla2100_apidev: open MAJOR number = %d, MINOR number = %d\n", MAJOR (inode->i_rdev), MINOR (inode->i_rdev)); + return 0; +} +static int apidev_close(struct inode *inode, struct file *file) +{ + printk (KERN_INFO "qla2100_apidev: closed\n"); + return 0; +} + +static int apidev_ioctl(struct inode *inode, struct file *fp, unsigned int cmd, unsigned long arg) +{ + Scsi_Device fake_scsi_device; + fake_scsi_device.host = apidev_host; + return(qla2100_ioctl(&fake_scsi_device, (int)cmd, (void*)arg)); +} + +static struct file_operations apidev_fops = { + ioctl: apidev_ioctl, + open: apidev_open, + release: apidev_close +}; + +static int apidev_init(struct Scsi_Host *host) +{ + if(apidev_host) return 0; + if (0 > (apidev_major = register_chrdev(0, APIDEV_NAME, &apidev_fops))) + { + DEBUG(printk("qla2100_apidev: register_chrdev rc=%d\n",apidev_major);) + return apidev_major; + } + apidev_host = host; + DEBUG(printk("qla2x00: Created /proc/scsi/qla2x00/%s major=%d\n",APIDEV_NODE,apidev_major);) + proc_mknod(APIDEV_NODE, 0777+S_IFCHR,host->hostt->proc_dir,(kdev_t)MKDEV(apidev_major,0)); + return 0; +} + +static int apidev_cleanup() +{ + if(!apidev_host) return 0; + unregister_chrdev(apidev_major,APIDEV_NAME); + remove_proc_entry(APIDEV_NODE,apidev_host->hostt->proc_dir); + apidev_host = 0; + return 0; +} +#endif /* APIDEV */ + +#ifdef QL_DEBUG_ROUTINES +#if DEBUG_GET_FW_DUMP +#include "x2300dbg.c" +#endif +#endif + + +/* +* Overrides for Emacs so that we almost follow Linus's tabbing style. +* Emacs will notice this stuff at the end of the file and automatically +* adjust the settings for this buffer only. This must remain at the end +* of the file. +* --------------------------------------------------------------------------- +* Local variables: +* c-indent-level: 2 +* c-brace-imaginary-offset: 0 +* c-brace-offset: -2 +* c-argdecl-indent: 2 +* c-label-offset: -2 +* c-continued-statement-offset: 2 +* c-continued-brace-offset: 0 +* indent-tabs-mode: nil +* tab-width: 8 +* End: +*/ diff -urN linux-2.4.10/drivers/scsi/qla2x00.h linux-2.4.10-lia/drivers/scsi/qla2x00.h --- linux-2.4.10/drivers/scsi/qla2x00.h Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/scsi/qla2x00.h Mon Jul 23 14:12:30 2001 @@ -0,0 +1,2492 @@ +/******************************************************************************** +* QLOGIC LINUX SOFTWARE +* +* QLogic ISP2x00 device driver for Linux 2.2.x and 2.4.x +* Copyright (C) 2000 and 2001 Qlogic Corporation +* (www.qlogic.com) +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of the GNU General Public License as published by the +* Free Software Foundation; either version 2, or (at your option) any +* later version. +* +* This program is distributed in the hope that it will be useful, but +* WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +* General Public License for more details. +** +******************************************************************************/ + +#ifndef _IO_HBA_QLA2100_H /* wrapper symbol for kernel use */ +#define _IO_HBA_QLA2100_H /* subject to change without notice */ + +#ifndef LINUX_VERSION_CODE +#include +#endif /* LINUX_VERSION_CODE not defined */ + +#ifndef HOSTS_C + +#if defined(__cplusplus) +extern "C" { +#endif + +#ifndef ISP2200 +#define ISP2200 +#endif + + +/* + * Driver debug definitions. + */ +/* #define QL_DEBUG_LEVEL_1 */ /* Output register accesses to COM1 */ +/* #define QL_DEBUG_LEVEL_2 */ /* Output error msgs to COM1 */ +/* #define QL_DEBUG_LEVEL_3 */ /* Output function trace msgs to COM1 */ +/* #define QL_DEBUG_LEVEL_4 */ /* Output NVRAM trace msgs to COM1 */ +/* #define QL_DEBUG_LEVEL_5 */ /* Output ring trace msgs to COM1 */ +/* #define QL_DEBUG_LEVEL_6 */ /* Output WATCHDOG timer trace to COM1 */ +/* #define QL_DEBUG_LEVEL_7 */ /* Output RISC load trace msgs to COM1 */ +/* #define QL_DEBUG_LEVEL_8 */ /* Output ring saturation msgs to COM1 */ + +#define QL_DEBUG_CONSOLE /* Output to console instead of COM1 */ + /* comment this #define to get output of qla2100_print to COM1 */ + /* if COM1 is not connected to a host system, the driver hangs system! */ + +/* + * Data bit definitions. + */ +#define BIT_0 0x1 +#define BIT_1 0x2 +#define BIT_2 0x4 +#define BIT_3 0x8 +#define BIT_4 0x10 +#define BIT_5 0x20 +#define BIT_6 0x40 +#define BIT_7 0x80 +#define BIT_8 0x100 +#define BIT_9 0x200 +#define BIT_10 0x400 +#define BIT_11 0x800 +#define BIT_12 0x1000 +#define BIT_13 0x2000 +#define BIT_14 0x4000 +#define BIT_15 0x8000 +#define BIT_16 0x10000 +#define BIT_17 0x20000 +#define BIT_18 0x40000 +#define BIT_19 0x80000 +#define BIT_20 0x100000 +#define BIT_21 0x200000 +#define BIT_22 0x400000 +#define BIT_23 0x800000 +#define BIT_24 0x1000000 +#define BIT_25 0x2000000 +#define BIT_26 0x4000000 +#define BIT_27 0x8000000 +#define BIT_28 0x10000000 +#define BIT_29 0x20000000 +#define BIT_30 0x40000000 +#define BIT_31 0x80000000 + +/* + * Common size type definitions + */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,0) +typedef unsigned char uint8_t; +typedef unsigned short uint16_t; +typedef unsigned long uint32_t; +typedef char int8_t; +typedef short int16_t; +typedef long int32_t; +#endif + +/* + * Local Macro Definitions. + */ +#if defined(QL_DEBUG_LEVEL_1) || defined(QL_DEBUG_LEVEL_2) || \ + defined(QL_DEBUG_LEVEL_3) || defined(QL_DEBUG_LEVEL_4) || \ + defined(QL_DEBUG_LEVEL_5) || defined(QL_DEBUG_LEVEL_6) || \ + defined(QL_DEBUG_LEVEL_7) || defined(QL_DEBUG_LEVEL_8) + #define QL_DEBUG_ROUTINES +#endif + +#ifndef TRUE + #define TRUE 1 +#endif + +#ifndef FALSE + #define FALSE 0 +#endif +#ifndef KERNEL_VERSION +# define KERNEL_VERSION(x,y,z) (((x)<<16)+((y)<<8)+(z)) +#endif + +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,1,92) +# if defined(__sparc_v9__) || defined(__powerpc__) +# error "PPC and Sparc platforms are only support under 2.1.92 and above" +# endif +#endif + + +/* + * Locking + */ +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,1,0) +# if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18) +# include +# else +# include +# endif +# include +# define cpuid smp_processor_id() +# if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95) +# define DRIVER_LOCK_INIT \ + spin_lock_init(&ha->spin_lock); +# define DRIVER_LOCK \ + if(!ha->cpu_lock_count[cpuid]) { \ + spin_lock_irqsave(&ha->spin_lock, cpu_flags); \ + ha->cpu_lock_count[cpuid]++; \ + } else { \ + ha->cpu_lock_count[cpuid]++; \ + } +# define DRIVER_UNLOCK \ + if(--ha->cpu_lock_count[cpuid] == 0) \ + spin_unlock_irqrestore(&ha->spin_lock, cpu_flags); +# else +# define DRIVER_LOCK_INIT +# define DRIVER_LOCK +# define DRIVER_UNLOCK +# endif +#else +# define cpuid 0 +# define DRIVER_LOCK_INIT +# define DRIVER_LOCK \ + save_flags(cpu_flags); \ + cli(); +# define DRIVER_UNLOCK \ + restore_flags(cpu_flags); +# define le32_to_cpu(x) (x) +# define cpu_to_le32(x) (x) +#endif + + +/* + * I/O register +*/ +/* #define MEMORY_MAPPED_IO */ /* Enable memory mapped I/O */ +#undef MEMORY_MAPPED_IO /* Disable memory mapped I/O */ +#define LINUX_IOPORTS /* Linux in/out routines are define*/ + /* differently from other OSs */ + +#ifdef QL_DEBUG_LEVEL_1 + #define RD_REG_BYTE(addr) qla2100_getbyte((uint8_t *)addr) + #define RD_REG_WORD(addr) qla2100_getword((uint16_t *)addr) + #define RD_REG_DWORD(addr) qla2100_getdword((uint32_t *)addr) + #define WRT_REG_BYTE(addr, data) qla2100_putbyte((uint8_t *)addr, data) + #define WRT_REG_WORD(addr, data) qla2100_putword((uint16_t *)addr, data) + #define WRT_REG_DWORD(addr, data) qla2100_putdword((uint32_t *)addr, data) +#else /* QL_DEBUG_LEVEL_1 */ +#ifdef MEMORY_MAPPED_IO +#define RD_REG_BYTE(addr) (*((volatile uint8_t *)addr)) +#define RD_REG_WORD(addr) (*((volatile uint16_t *)addr)) +#define RD_REG_DWORD(addr) (*((volatile uint32_t *)addr)) +#define WRT_REG_BYTE(addr, data) (*((volatile uint8_t *)addr) = data) +#define WRT_REG_WORD(addr, data) (*((volatile uint16_t *)addr) = data) +#define WRT_REG_DWORD(addr, data) (*((volatile uint32_t *)addr) = data) +#else /* MEMORY_MAPPED_IO */ +#define RD_REG_BYTE(addr) (inb((unsigned long)addr)) +#define RD_REG_WORD(addr) (inw((unsigned long)addr)) +#define RD_REG_DWORD(addr) (inl((unsigned long)addr)) +#define WRT_REG_BYTE(addr, data) (outb(data,(unsigned long)addr)) +#define WRT_REG_WORD(addr, data) (outw(data,(unsigned long)addr)) +#define WRT_REG_DWORD(addr, data) (outl(data,(unsigned long)addr)) +#endif /* MEMORY_MAPPED_IO */ +#endif /* QL_DEBUG_LEVEL_1 */ + +#define MAX_FIBRE_DEVICES 256 +#define MAX_RSCN_COUNT 10 +#define MAX_HOST_COUNT 16 + +/* + * Host adapter default definitions. + */ +#define MAX_BUSES 1 /* We only have one bus today */ +#define MAX_TARGETS_2100 255 +#define MAX_TARGETS_2200 255 +#define MAX_LUNS 255 + +/* + * Fibre Channel device definitions. + */ +#define LAST_LOCAL_LOOP_ID 0x7d +#define SNS_FL_PORT 0x7e +#define FABRIC_CONTROLLER 0x7f +#define SIMPLE_NAME_SERVER 0x80 +#define SNS_FIRST_LOOP_ID 0x81 +#define LAST_SNS_LOOP_ID 0xfe +#define MANAGEMENT_SERVER 0xfe +#define BROADCAST 0xff +#define SNS_ACCEPT 0x0280 /* 8002 swapped */ +#define SNS_REJECT 0x0180 /* 8001 swapped */ + +/* Loop ID's used as database flags, must be higher than any valid Loop ID */ +#define PORT_UNUSED 0x100 /* Port never been used. */ +#define PORT_AVAILABLE 0x101 /* Device does not exist on port. */ + +/* + * Timeout timer counts in seconds + */ +#define QLA2100_WDG_TIME_QUANTUM 1 /* In seconds */ +#define PORT_RETRY_TIME 2 +#define LOOP_DOWN_TIMEOUT 60 +#define LOOP_DOWN_TIME 240 /* 240 */ + +/* Maximum outstanding commands in ISP queues (1-65535) */ +#define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30) + +/* Maximum outstanding commands in ISP queues (1-65535) */ +#define MAX_OUTSTANDING_COMMANDS 512*2 + +#define REQUEST_ENTRY_CNT 256 /* # of request entries, was 512 */ +#define RESPONSE_ENTRY_CNT 256 /* # of response entries, was 16 */ + +/* + * UnixWare required definitions. + */ +#define HBA_PREFIX qla2100 + +/* Physical DMA memory requirements */ +#define QLA2100_MEMALIGN 4 +#define QLA2100_BOUNDARY 0x80000000 /* 2GB */ + +/* Number of segments 1 - 65535 */ +#define SG_SEGMENTS 32 /* Cmd entry + 6 continuations */ + +/* + * SCSI Request Block + */ +typedef struct srb +{ + Scsi_Cmnd *cmd; /* (4) SCSI command block */ + struct srb *s_next; /* (4) Next block on LU queue */ + struct srb *s_prev; /* (4) Previous block on LU queue */ + uint8_t flags; /* (1) Status flags. */ + uint8_t dir; /* direction of transfer */ + uint8_t retry_count; /* Retry count. */ + uint8_t port_down_retry_count; /* Port down retry count. */ + uint8_t ccode; /* risc completion code */ + uint8_t scode; /* scsi status code */ + uint8_t wdg_time; /* watchdog time in seconds */ + uint8_t state; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,18) + uint64_t saved_dma_handle; /* for unmap of single transfers */ +#endif +}srb_t; + +/* + * SRB flag definitions + */ +#define SRB_TIMEOUT BIT_0 /* Command timed out */ +#define SRB_SENT BIT_1 /* Command sent to ISP */ +#define SRB_WATCHDOG BIT_2 /* Command on watchdog list */ +#define SRB_ABORT_PENDING BIT_3 /* Command abort sent to device */ +#define SRB_ABORTED BIT_4 /* Command aborted command already */ +#define SRB_RETRY BIT_5 /* Command aborted command already */ + +/* + * LUN - Logical Unit Queue structure + */ +typedef struct scsi_lu +{ + srb_t *q_first; /* First block on LU queue */ + srb_t *q_last; /* Last block on LU queue */ + u_char q_flag; /* LU queue state flags */ + u_short q_outcnt; /* Pending jobs for this LU */ + u_long q_incnt; /* queued jobs for this LU */ + u_long io_cnt; /* total xfer count */ + u_long resp_time; /* total response time (start - finish) */ + u_long act_time; /* total actived time (minus queuing time) */ + u_long w_cnt; /* total writes */ + u_long r_cnt; /* total reads */ +#if QLA2X00_TARGET_MODE_SUPPORT + void (*q_func)(); /* Target driver event handler */ + long q_param; /* Target driver event param */ +#endif +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,1,0) + spinlock_t *q_spin_lock; /* Device Queue Lock */ +#endif + volatile unsigned char cpu_lock_count[NR_CPUS]; + u_long q_timeout; /* total command timeouts */ +}scsi_lu_t; + +/* + * Logical Unit q_flag definitions + */ +#define QLA2100_QBUSY BIT_0 +#define QLA2100_QWAIT BIT_1 +#define QLA2100_QSUSP BIT_2 +#define QLA2100_QRESET BIT_4 +#define QLA2100_QHBA BIT_5 +#define QLA2100_BSUSP BIT_6 /* controller is suspended */ +#define QLA2100_BREM BIT_7 /* controller is removed */ + +/* + * ISP PCI Configuration Register Set + */ +typedef volatile struct +{ + uint16_t vendor_id; /* 0x0 */ + uint16_t device_id; /* 0x2 */ + uint16_t command; /* 0x4 */ + uint16_t status; /* 0x6 */ + uint8_t revision_id; /* 0x8 */ + uint8_t programming_interface; /* 0x9 */ + uint8_t sub_class; /* 0xa */ + uint8_t base_class; /* 0xb */ + uint8_t cache_line; /* 0xc */ + uint8_t latency_timer; /* 0xd */ + uint8_t header_type; /* 0xe */ + uint8_t bist; /* 0xf */ + uint32_t base_port; /* 0x10 */ + uint32_t mem_base_addr; /* 0x14 */ + uint32_t base_addr[4]; /* 0x18-0x24 */ + uint32_t reserved_1[2]; /* 0x28-0x2c */ + uint16_t expansion_rom; /* 0x30 */ + uint32_t reserved_2[2]; /* 0x34-0x38 */ + uint8_t interrupt_line; /* 0x3c */ + uint8_t interrupt_pin; /* 0x3d */ + uint8_t min_grant; /* 0x3e */ + uint8_t max_latency; /* 0x3f */ +}config_reg_t; + + +/* + * 2100/2200 ISP I/O Register Set structure definitions. + */ +typedef volatile struct +{ + uint16_t flash_address; /* Flash BIOS address */ + uint16_t flash_data; /* Flash BIOS data */ + uint16_t unused_1[1]; /* Gap */ + uint16_t ctrl_status; /* Control/Status */ + #define ISP_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */ + #define ISP_RESET BIT_0 /* ISP soft reset */ + uint16_t ictrl; /* Interrupt control */ + #define ISP_EN_INT BIT_15 /* ISP enable interrupts. */ + #define ISP_EN_RISC BIT_3 /* ISP enable RISC interrupts. */ + uint16_t istatus; /* Interrupt status @0xa*/ + #define RISC_INT BIT_3 /* RISC interrupt */ + uint16_t semaphore; /* Semaphore */ + uint16_t nvram; /* NVRAM register. @0xe */ + #define NV_DESELECT 0 + #define NV_CLOCK BIT_0 + #define NV_SELECT BIT_1 + #define NV_DATA_OUT BIT_2 + #define NV_DATA_IN BIT_3 + + /* 2100 and 2200 */ + uint16_t mailbox0; /* Mailbox 0 @0x10 */ + uint16_t mailbox1; /* Mailbox 1 */ + uint16_t mailbox2; /* Mailbox 2 */ + uint16_t mailbox3; /* Mailbox 3 */ + uint16_t mailbox4; /* Mailbox 4 */ + uint16_t mailbox5; /* Mailbox 5 */ + uint16_t mailbox6; /* Mailbox 6 */ + uint16_t mailbox7; /* Mailbox 7 */ + + uint16_t unused_2[0x3b]; /* Gap */ + uint16_t fpm_diag_config; + uint16_t unused_3[0x6]; /* Gap */ + uint16_t pcr; /* Processor Control Register. */ + uint16_t unused_4[0x5]; /* Gap */ + uint16_t mctr; /* Memory Configuration and Timing. */ + uint16_t unused_5[0x3]; /* Gap */ + uint16_t fb_cmd; + uint16_t unused_6[0x3]; /* Gap */ + uint16_t host_cmd; /* Host command and control */ + + #define HOST_INT BIT_7 /* host interrupt bit */ +#ifdef FC_IP_SUPPORT + uint16_t unused_3[0x0F]; /* Gap */ + uint16_t mailbox8; /* Mailbox 8 */ + uint16_t mailbox9; /* Mailbox 9 */ + uint16_t mailbox10; /* Mailbox 10 */ + uint16_t mailbox11; /* Mailbox 11 */ + uint16_t mailbox12; /* Mailbox 12 */ + uint16_t mailbox13; /* Mailbox 13 */ + uint16_t mailbox14; /* Mailbox 14 */ + uint16_t mailbox15; /* Mailbox 15 */ + uint16_t mailbox16; /* Mailbox 16 */ + uint16_t mailbox17; /* Mailbox 17 */ + uint16_t mailbox18; /* Mailbox 18 */ + uint16_t mailbox19; /* Mailbox 19 */ + uint16_t mailbox20; /* Mailbox 20 */ + uint16_t mailbox21; /* Mailbox 21 */ + uint16_t mailbox22; /* Mailbox 22 */ + uint16_t mailbox23; /* Mailbox 23 */ +#endif + +}device_reg_t; + +/* + * 2300 ISP I/O Register Set structure definitions. + */ +typedef volatile struct +{ + uint16_t flash_address; /* Flash BIOS address */ + uint16_t flash_data; /* Flash BIOS data */ + uint16_t unused_1[1]; /* Gap */ + uint16_t ctrl_status; /* Control/Status */ + #define ISP_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */ + #define ISP_RESET BIT_0 /* ISP soft reset */ + uint16_t ictrl; /* Interrupt control */ + #define ISP_EN_INT BIT_15 /* ISP enable interrupts. */ + #define ISP_EN_RISC BIT_3 /* ISP enable RISC interrupts. */ + uint16_t istatus; /* Interrupt status @0xa*/ + #define RISC_2300_INT BIT_15 /* 2300 RISC int for non-ROM cmds */ + uint16_t semaphore; /* Semaphore */ + uint16_t nvram; /* NVRAM register. @0xf */ + #define NV_DESELECT 0 + #define NV_CLOCK BIT_0 + #define NV_SELECT BIT_1 + #define NV_DATA_OUT BIT_2 + #define NV_DATA_IN BIT_3 + /* 2300 */ + uint16_t req_q_in /* @0x10 */; + uint16_t req_q_out /* @0x12 */; + uint16_t rsp_q_in /* @0x14 */; + uint16_t rsp_q_out /* @0x16 */; + uint32_t host_status /* @0x18 */; + uint16_t unused3[0x12]; + uint16_t mailbox0; /* Mailbox 0 @0x40 */ + uint16_t mailbox1; /* Mailbox 1 */ + uint16_t mailbox2; /* Mailbox 2 */ + uint16_t mailbox3; /* Mailbox 3 */ + uint16_t mailbox4; /* Mailbox 4 */ + uint16_t mailbox5; /* Mailbox 5 */ + uint16_t mailbox6; /* Mailbox 6 */ + uint16_t mailbox7; /* Mailbox 7 @0x4E */ + uint16_t mailbox8; /* Mailbox 8 */ + uint16_t mailbox9; /* Mailbox 9 */ + uint16_t mailbox10; /* Mailbox 10 */ + uint16_t mailbox11; /* Mailbox 11 */ + uint16_t mailbox12; /* Mailbox 12 */ + uint16_t mailbox13; /* Mailbox 13 */ + uint16_t mailbox14; /* Mailbox 14 */ + uint16_t mailbox15; /* Mailbox 15 */ + uint16_t mailbox16; /* Mailbox 16 */ + uint16_t mailbox17; /* Mailbox 17 */ + uint16_t mailbox18; /* Mailbox 18 */ + uint16_t mailbox19; /* Mailbox 19 */ + uint16_t mailbox20; /* Mailbox 20 */ + uint16_t mailbox21; /* Mailbox 21 */ + uint16_t mailbox22; /* Mailbox 22 */ + uint16_t mailbox23; /* Mailbox 23 */ + uint16_t mailbox24; /* Mailbox 24 */ + uint16_t mailbox25; /* Mailbox 25 */ + uint16_t mailbox26; /* Mailbox 26 */ + uint16_t mailbox27; /* Mailbox 27 */ + uint16_t mailbox28; /* Mailbox 28 */ + uint16_t mailbox29; /* Mailbox 29 */ + uint16_t mailbox30; /* Mailbox 30 */ + uint16_t mailbox31; /* Mailbox 31 @0x7E */ + uint16_t unused4[0xb]; /* gap */ + + uint16_t fpm_diag_config; + uint16_t unused_3[0x6]; /* Gap */ + uint16_t pcr; /* Processor Control Register. */ + uint16_t unused_4[0x5]; /* Gap */ + uint16_t mctr; /* Memory Configuration and Timing. */ + uint16_t unused_5[0x3]; /* Gap */ + uint16_t fb_cmd; + uint16_t unused_6[0x3]; /* Gap */ + uint16_t host_cmd; /* Host command and control */ + + #define HOST_INT BIT_7 /* host interrupt bit */ +#ifdef FC_IP_SUPPORT + uint16_t unused_3[0x0F]; /* Gap */ + uint16_t mailbox8; /* Mailbox 8 */ + uint16_t mailbox9; /* Mailbox 9 */ + uint16_t mailbox10; /* Mailbox 10 */ + uint16_t mailbox11; /* Mailbox 11 */ + uint16_t mailbox12; /* Mailbox 12 */ + uint16_t mailbox13; /* Mailbox 13 */ + uint16_t mailbox14; /* Mailbox 14 */ + uint16_t mailbox15; /* Mailbox 15 */ + uint16_t mailbox16; /* Mailbox 16 */ + uint16_t mailbox17; /* Mailbox 17 */ + uint16_t mailbox18; /* Mailbox 18 */ + uint16_t mailbox19; /* Mailbox 19 */ + uint16_t mailbox20; /* Mailbox 20 */ + uint16_t mailbox21; /* Mailbox 21 */ + uint16_t mailbox22; /* Mailbox 22 */ + uint16_t mailbox23; /* Mailbox 23 */ +#endif + +}device2300_reg_t; + + +#define MAILBOX_REGISTER_COUNT 32 + +/* + * ISP product identification definitions in mailboxes after reset. + */ +#define PROD_ID_1 0x4953 +#define PROD_ID_2 0x0000 +#define PROD_ID_2a 0x5020 +#define PROD_ID_3 0x2020 +#define PROD_ID_4 0x1 + +/* + * ISP host command and control register command definitions + */ +#define HC_RESET_RISC 0x1000 /* Reset RISC */ +#define HC_PAUSE_RISC 0x2000 /* Pause RISC */ +#define HC_RELEASE_RISC 0x3000 /* Release RISC from reset. */ +#define HC_SET_HOST_INT 0x5000 /* Set host interrupt */ +#define HC_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */ +#define HC_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */ +#define HC_RISC_PAUSE BIT_5 +#define HC_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */ + +#define SEMAPHORE_SET 0x1234 + +/* + * ISP mailbox Self-Test status codes + */ +#define MBS_FRM_ALIVE 0 /* Firmware Alive. */ +#define MBS_CHKSUM_ERR 1 /* Checksum Error. */ +#define MBS_BUSY 4 /* Busy. */ + +/* + * ISP mailbox command complete status codes + */ +#define MBS_CMD_CMP 0x4000 /* Command Complete. */ +#define MBS_INV_CMD 0x4001 /* Invalid Command. */ +#define MBS_HOST_INF_ERR 0x4002 /* Host Interface Error. */ +#define MBS_TEST_FAILED 0x4003 /* Test Failed. */ +#define MBS_CMD_ERR 0x4005 /* Command Error. */ +#define MBS_CMD_PARAM_ERR 0x4006 /* Command Parameter Error. */ +#define MBS_FATAL_ERROR 0xF000 /* Command Fatal Error. */ + +#define MBS_FIRMWARE_ALIVE 0x0000 +#define MBS_COMMAND_COMPLETE 0x4000 +#define MBS_INVALID_COMMAND 0x4001 + +/* QLogic subroutine status definitions */ +#define QL_STATUS_SUCCESS 0 +#define QL_STATUS_ERROR 1 +#define QL_STATUS_FATAL_ERROR 2 +#define QL_STATUS_RESOURCE_ERROR 3 +#define QL_STATUS_LOOP_ID_IN_USE 4 +#define QL_STATUS_NO_DATA 5 + +/* + * ISP mailbox asynchronous event status codes + */ +#define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */ +#define MBA_RESET 0x8001 /* Reset Detected. */ +#define MBA_SYSTEM_ERR 0x8002 /* System Error. */ +#define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */ +#define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */ +#define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */ +#define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */ + /* occurred. */ +#define MBA_LOOP_UP 0x8011 /* FC Loop UP. */ +#define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */ +#define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */ +#define MBA_PORT_UPDATE 0x8014 /* Port Database update. */ +#define MBA_SCR_UPDATE 0x8015 /* State Change Registration. */ +#define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */ +#define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */ +#ifdef ISP2200 +#define MBA_LINK_MODE_UP 0x8030 /* FC Link Mode UP. */ +#define MBA_UPDATE_CONFIG 0x8036 /* FC Update Configuration. */ +#endif + +/* + * ISP mailbox commands + */ +#define MBC_LOAD_RAM 1 /* Load RAM. */ +#define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */ +#define MBC_WRITE_RAM_WORD 4 /* Write RAM word. */ +#define MBC_READ_RAM_WORD 5 /* Read RAM word. */ +#define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */ +#define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */ +#define MBC_ABOUT_FIRMWARE 8 /* Get firmware revision. */ +#define MBC_DUMP_RAM 0xA /* READ BACK FW */ +#define MBC_DUMP_SRAM 0xC /* Dump SRAM */ +#define MBC_IOCB_EXECUTE 0x12 /* Execute an IOCB command */ +#define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */ +#define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */ +#define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */ +#define MBC_TARGET_RESET 0x18 /* Target reset. */ +#define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2100. */ +#define MBC_SET_TARGET_PARAMATERS 0x38 /* Set target parameters. */ +#define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Perform LoopBack diagnostic */ +#define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */ +#define MBC_INITIATE_LIP 0x62 /* Initiate Loop Initialization */ + /* Procedure */ +#define MBC_GET_PORT_DATABASE 0x64 /* Get port database. */ +#define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */ +#define MBC_GET_PORT_NAME 0x6a /* Get port name. */ +#define MBC_LIP_RESET 0x6c /* LIP reset. */ +#define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server command. */ +#define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */ +#define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */ +#define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */ +#define MBC_GET_PORT_LIST 0x75 /* Get port list. */ + +/* + * Firmware state codes from get firmware state mailbox command + */ +#define FSTATE_CONFIG_WAIT 0 +#define FSTATE_WAIT_AL_PA 1 +#define FSTATE_WAIT_LOGIN 2 +#define FSTATE_READY 3 +#define FSTATE_LOSS_OF_SYNC 4 +#define FSTATE_ERROR 5 +#define FSTATE_REINIT 6 +#define FSTATE_NON_PART 7 + +#define FSTATE_CONFIG_CORRECT 0 +#define FSTATE_P2P_RCV_LIP 1 +#define FSTATE_P2P_CHOOSE_LOOP 2 +#define FSTATE_P2P_RCV_UNIDEN_LIP 3 +#define FSTATE_FATAL_ERROR 4 +#define FSTATE_LOOP_BACK_CONN 5 + +/* + * ISP Initialization Control Block. + */ +typedef struct +{ + uint8_t version; + #define ICB_VERSION 1 + uint8_t reserved_1; + struct + { + uint8_t enable_hard_loop_id :1; /* bit 0 */ + uint8_t enable_fairness :1; + uint8_t enable_full_duplex :1; + uint8_t enable_fast_posting :1; + uint8_t enable_target_mode :1; + uint8_t disable_initiator_mode :1; + uint8_t enable_adisc :1; + uint8_t enable_lun_response :1; /* bit 7 */ + uint8_t enable_port_update_event :1; + uint8_t disable_initial_lip :1; + uint8_t enable_decending_soft_assign :1; + uint8_t previous_assigned_addressing :1; + uint8_t enable_stop_q_on_full :1; + uint8_t enable_full_login_on_lip :1; + uint8_t enable_name_change :1; + uint8_t expanded_ifwcb :1; /* bit 15 */ + }firmware_options; + uint16_t frame_length; + uint16_t iocb_allocation; + uint16_t execution_throttle; + uint8_t retry_count; + uint8_t retry_delay; +#ifdef ISP2200 + uint8_t port_name[8]; +#else + uint8_t node_name[8]; +#endif + uint16_t adapter_hard_loop_id; + uint8_t inquiry_data; + uint8_t login_timeout; +#ifdef ISP2200 + uint8_t node_name[8]; +#else + uint8_t reserved_1[8]; +#endif + uint16_t request_q_outpointer; + uint16_t response_q_inpointer; + uint16_t request_q_length; + uint16_t response_q_length; + uint32_t request_q_address[2]; + uint32_t response_q_address[2]; + uint16_t lun_enables; + uint8_t command_resource_count; + uint8_t immediate_notify_resource_count; + uint16_t timeout; + uint16_t reserved_2; + struct + { + uint8_t operation_mode :4; /* Bits 0 1 2 3 */ + uint8_t connection_options :3; /* Bits 4 5 6 */ + #define LOOP 0 + #define P2P 1 + #define LOOP_P2P 2 + #define P2P_LOOP 3 + uint8_t nonpart_if_hard_addr_failed :1; /* Bit 7 */ + uint8_t enable_class2 :1; /* Bit 8 */ + uint8_t enable_ack0 :1; /* Bit 9 */ + uint8_t unused_10 :1; /* bit 10 */ + uint8_t unused_11 :1; /* bit 11 */ + uint8_t enable_fc_tape :1; /* bit 12 */ + uint8_t enable_fc_confirm :1; /* bit 13 */ + uint8_t enable_cmd_q_target_mode :1; /* bit 14 */ + uint8_t unused_15 :1; /* bit 15 */ + }additional_firmware_options; + uint8_t response_accum_timer; + uint8_t interrupt_delay_timer; + struct + { + uint8_t enable_read_xfr_rdy :1; /* Bit 0 */ + uint8_t soft_id_only :1; /* Bit 1 */ + uint8_t unused_2 :1; /* Bit 2 */ + uint8_t unused_3 :1; /* Bit 3 */ + uint8_t fcp_rsp_payload :2; /* Bits 4 5 */ + #define send_24_bytes_0 0 + #define send_12_bytes_0 1 + #define second_send_24_bytes_0 2 + #define send_32_bytes_0 3 + uint8_t unused_6 :1; /* Bit 6 */ + uint8_t unused_7 :1; /* Bit 7 */ + uint8_t unused_8 :1; /* Bit 8 */ + uint8_t unused_9 :1; /* Bit 9 */ + uint8_t unused_10 :1; /* Bit 10 */ + uint8_t unused_11 :1; /* Bit 11 */ + uint8_t unused_12 :1; /* Bit 12 */ + uint8_t set_50_ohms_term_enable :1; /* Bit 13 */ + uint8_t data_rate :2; /* Bits 14 15 */ + #define set_1_gig_rate 0 + #define set_2_gig_rate 1 + #define auto_negotiate 2 + }special_options; + uint16_t reserved_3[13]; +}init_cb_t; + +/* + * ISP Get/Set Target Parameters mailbox command control flags. + */ + +/* + * NVRAM Command values. + */ +#define NV_START_BIT BIT_2 +#define NV_WRITE_OP (BIT_26+BIT_24) +#define NV_READ_OP (BIT_26+BIT_25) +#define NV_ERASE_OP (BIT_26+BIT_25+BIT_24) +#define NV_MASK_OP (BIT_26+BIT_25+BIT_24) +#define NV_DELAY_COUNT 10 + +/* + * ISP2200 NVRAM structure definitions. + */ +typedef struct +{ + /* + * NVRAM header + */ + + uint8_t id[4]; + uint8_t nvram_version; + uint8_t reserved_0; + + /* + * NVRAM RISC parameter block + */ + + uint8_t parameter_block_version; + uint8_t reserved_1; + + struct + { + uint8_t enable_hard_loop_id :1; + uint8_t enable_fairness :1; + uint8_t enable_full_duplex :1; + uint8_t enable_fast_posting :1; + uint8_t enable_target_mode :1; + uint8_t disable_initiator_mode :1; + uint8_t enable_adisc :1; + uint8_t enable_lun_response :1; + uint8_t enable_port_update_event :1; + uint8_t disable_initial_lip :1; + uint8_t enable_decending_soft_assign :1; + uint8_t previous_assigned_addressing :1; + uint8_t enable_stop_q_on_full :1; + uint8_t enable_full_login_on_lip :1; + uint8_t enable_name_change :1; + uint8_t expanded_ifwcb :1; + }firmware_options; + + uint16_t frame_payload_size; + uint16_t max_iocb_allocation; + uint16_t execution_throttle; + uint8_t retry_count; + uint8_t retry_delay; + uint8_t port_name[8]; + uint16_t adapter_hard_loop_id; + uint8_t inquiry_data; + uint8_t login_timeout; + + uint8_t node_name[8]; + + /* Expanded RISC parameter block */ + struct + { + uint8_t operation_mode :4; + uint8_t connection_options :3; + uint8_t nonpart_if_hard_addr_failed :1; + uint8_t enable_class2 :1; + uint8_t enable_ack0 :1; + uint8_t unused_10 :1; + uint8_t unused_11 :1; + uint8_t enable_fc_tape :1; + uint8_t enable_fc_confirm :1; + uint8_t enable_command_reference_num :1; + }additional_firmware_options; + + uint8_t response_accum_timer; + uint8_t interrupt_delay_timer; + uint16_t reserved_2[14]; + + /* + * NVRAM host parameter block + */ + + struct + { + uint8_t unused_0 :1; + uint8_t disable_bios :1; + uint8_t disable_luns :1; + uint8_t enable_selectable_boot :1; + uint8_t disable_risc_code_load :1; + uint8_t set_cache_line_size_1 :1; + uint8_t pci_parity_disable :1; + uint8_t enable_extended_logging :1; + uint8_t enable_64bit_addressing :1; + uint8_t enable_lip_reset :1; + uint8_t enable_lip_full_login :1; + uint8_t enable_target_reset :1; + uint8_t enable_database_storage :1; + uint8_t unused_13 :1; + uint8_t unused_14 :1; + uint8_t unused_15 :1; + }host_p; + + uint8_t boot_node_name[8]; + uint8_t boot_lun_number; + uint8_t reset_delay; + uint8_t port_down_retry_count; + uint8_t reserved_3; + + uint16_t maximum_luns_per_target; + + uint16_t reserved_6[7]; + + /* Offset 100 */ + uint16_t reserved_7[25]; + + /* Offset 150 */ + uint16_t reserved_8[25]; + + /* Offset 200 */ + uint8_t oem_id; + + uint8_t oem_spare0; + + uint8_t oem_string[6]; + + uint8_t oem_part[8]; + + uint8_t oem_fru[8]; + + uint8_t oem_ec[8]; + + + /* Offset 232 */ + struct + { + uint8_t external_gbic :1; + uint8_t risc_ram_parity :1; + uint8_t buffer_plus_module :1; + uint8_t multi_chip_hba :1; + uint8_t unused_1 :1; + uint8_t unused_2 :1; + uint8_t unused_3 :1; + uint8_t unused_4 :1; + uint8_t unused_5 :1; + uint8_t unused_6 :1; + uint8_t unused_7 :1; + uint8_t unused_8 :1; + uint8_t unused_9 :1; + uint8_t unused_10 :1; + uint8_t unused_11 :1; + uint8_t unused_12 :1; + }hba_features; + + uint16_t reserved_9; + uint16_t reserved_10; + uint16_t reserved_11; + + uint16_t reserved_12; + uint16_t reserved_13; + + /* Subsystem ID must be at offset 244 */ + uint16_t subsystem_vendor_id; + + uint16_t reserved_14; + + /* Subsystem device ID must be at offset 248 */ + uint16_t subsystem_device_id; + + uint16_t reserved_15[2]; + uint8_t reserved_16; + uint8_t checksum; +}nvram22_t; + +typedef struct +{ + /* + * NVRAM header for 2100 board. + */ + + uint8_t id[4]; + uint8_t nvram_version; + uint8_t reserved_0; + + /* + * NVRAM RISC parameter block + */ + + uint8_t parameter_block_version; + uint8_t reserved_1; + + struct + { + uint8_t enable_hard_loop_id :1; + uint8_t enable_fairness :1; + uint8_t enable_full_duplex :1; + uint8_t enable_fast_posting :1; + uint8_t enable_target_mode :1; + uint8_t disable_initiator_mode :1; + uint8_t enable_adisc :1; + uint8_t enable_lun_response :1; + uint8_t enable_port_update_event :1; + uint8_t disable_initial_lip :1; + uint8_t enable_decending_soft_assign :1; + uint8_t previous_assigned_addressing :1; + uint8_t enable_stop_q_on_full :1; + uint8_t enable_full_login_on_lip :1; + uint8_t enable_name_change :1; + uint8_t unused_15 :1; + }firmware_options; + + uint16_t frame_payload_size; + uint16_t max_iocb_allocation; + uint16_t execution_throttle; + uint8_t retry_count; + uint8_t retry_delay; + uint8_t node_name[8]; + uint16_t adapter_hard_loop_id; + uint8_t reserved_2; + uint8_t login_timeout; + uint16_t reserved_3[4]; + + /* Reserved for expanded RISC parameter block */ + uint16_t reserved_4[16]; + + /* + * NVRAM host parameter block + */ + + struct + { + uint8_t unused_0 :1; + uint8_t disable_bios :1; + uint8_t disable_luns :1; + uint8_t enable_selectable_boot :1; + uint8_t disable_risc_code_load :1; + uint8_t set_cache_line_size_1 :1; + uint8_t pci_parity_disable :1; + uint8_t enable_extended_logging :1; + uint8_t enable_64bit_addressing :1; + uint8_t enable_lip_reset :1; + uint8_t enable_lip_full_login :1; + uint8_t enable_target_reset :1; + uint8_t enable_database_storage :1; + uint8_t unused_13 :1; + uint8_t unused_14 :1; + uint8_t unused_15 :1; + }host_p; + + uint8_t boot_node_name[8]; + uint8_t boot_lun_number; + uint8_t reset_delay; + uint8_t port_down_retry_count; + uint8_t reserved_5; + + uint16_t maximum_luns_per_target; + + uint16_t reserved_6[7]; + + /* Offset 100 */ + uint16_t reserved_7[25]; + + /* Offset 150 */ + uint16_t reserved_8[25]; + + /* Offset 200 */ + uint16_t reserved_9[22]; + + /* Subsystem ID must be at offset 244 */ + uint16_t subsystem_vendor_id; + + uint16_t reserved_10; + + /* Subsystem device ID must be at offset 248 */ + uint16_t subsystem_device_id; + + uint16_t reserved_11[2]; + uint8_t reserved_12; + uint8_t checksum; +}nvram21_t; + +/* + * ISP queue - command entry structure definition. + */ +#define MAX_CMDSZ 16 /* SCSI maximum CDB size. */ +typedef struct +{ + uint8_t entry_type; /* Entry type. */ + #define COMMAND_TYPE 0x11 /* Command entry */ + uint8_t entry_count; /* Entry count. */ + uint8_t sys_define; /* System defined. */ + uint8_t entry_status; /* Entry Status. */ + uint32_t handle; /* System handle. */ + uint8_t reserved; + uint8_t target; /* SCSI ID */ + uint16_t lun; /* SCSI LUN */ + uint16_t control_flags; /* Control flags. */ +#define CF_HEAD_TAG BIT_1 +#define CF_ORDERED_TAG BIT_2 +#define CF_SIMPLE_TAG BIT_3 +#define CF_READ BIT_5 +#define CF_WRITE BIT_6 +#define CF_NO_FAST_POSTING BIT_7 + uint16_t reserved_1; + uint16_t timeout; /* Command timeout. */ + uint16_t dseg_count; /* Data segment count. */ + uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ + uint32_t byte_count; /* Total byte count. */ + uint32_t dseg_0_address; /* Data segment 0 address. */ + uint32_t dseg_0_length; /* Data segment 0 length. */ + uint32_t dseg_1_address; /* Data segment 1 address. */ + uint32_t dseg_1_length; /* Data segment 1 length. */ + uint32_t dseg_2_address; /* Data segment 2 address. */ + uint32_t dseg_2_length; /* Data segment 2 length. */ +}cmd_entry_t; + +/* + * ISP queue - 64-Bit addressing, command entry structure definition. + */ +typedef struct +{ + uint8_t entry_type; /* Entry type. */ + #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */ + uint8_t entry_count; /* Entry count. */ + uint8_t sys_define; /* System defined. */ + uint8_t entry_status; /* Entry Status. */ + uint32_t handle; /* System handle. */ + uint8_t reserved; + uint8_t target; /* SCSI ID */ + uint16_t lun; /* SCSI LUN */ + uint16_t control_flags; /* Control flags. */ + uint16_t reserved_1; + uint16_t timeout; /* Command timeout. */ + uint16_t dseg_count; /* Data segment count. */ + uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ + uint32_t byte_count; /* Total byte count. */ + uint32_t dseg_0_address[2]; /* Data segment 0 address. */ + uint32_t dseg_0_length; /* Data segment 0 length. */ + uint32_t dseg_1_address[2]; /* Data segment 1 address. */ + uint32_t dseg_1_length; /* Data segment 1 length. */ +}cmd_a64_entry_t, request_t; + +/* + * ISP queue - continuation entry structure definition. + */ +typedef struct +{ + uint8_t entry_type; /* Entry type. */ + #define CONTINUE_TYPE 0x02 /* Continuation entry. */ + uint8_t entry_count; /* Entry count. */ + uint8_t sys_define; /* System defined. */ + uint8_t entry_status; /* Entry Status. */ + uint32_t reserved; + uint32_t dseg_0_address; /* Data segment 0 address. */ + uint32_t dseg_0_length; /* Data segment 0 length. */ + uint32_t dseg_1_address; /* Data segment 1 address. */ + uint32_t dseg_1_length; /* Data segment 1 length. */ + uint32_t dseg_2_address; /* Data segment 2 address. */ + uint32_t dseg_2_length; /* Data segment 2 length. */ + uint32_t dseg_3_address; /* Data segment 3 address. */ + uint32_t dseg_3_length; /* Data segment 3 length. */ + uint32_t dseg_4_address; /* Data segment 4 address. */ + uint32_t dseg_4_length; /* Data segment 4 length. */ + uint32_t dseg_5_address; /* Data segment 5 address. */ + uint32_t dseg_5_length; /* Data segment 5 length. */ + uint32_t dseg_6_address; /* Data segment 6 address. */ + uint32_t dseg_6_length; /* Data segment 6 length. */ +}cont_entry_t; + +/* + * ISP queue - 64-Bit addressing, continuation entry structure definition. + */ +typedef struct +{ + uint8_t entry_type; /* Entry type. */ + #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */ + uint8_t entry_count; /* Entry count. */ + uint8_t sys_define; /* System defined. */ + uint8_t entry_status; /* Entry Status. */ + uint32_t dseg_0_address[2]; /* Data segment 0 address. */ + uint32_t dseg_0_length; /* Data segment 0 length. */ + uint32_t dseg_1_address[2]; /* Data segment 1 address. */ + uint32_t dseg_1_length; /* Data segment 1 length. */ + uint32_t dseg_2_address[2]; /* Data segment 2 address. */ + uint32_t dseg_2_length; /* Data segment 2 length. */ + uint32_t dseg_3_address[2]; /* Data segment 3 address. */ + uint32_t dseg_3_length; /* Data segment 3 length. */ + uint32_t dseg_4_address[2]; /* Data segment 4 address. */ + uint32_t dseg_4_length; /* Data segment 4 length. */ +}cont_a64_entry_t; + +/* + * ISP queue - status entry structure definition. + */ +typedef struct +{ + uint8_t entry_type; /* Entry type. */ + #define STATUS_TYPE 0x03 /* Status entry. */ + uint8_t entry_count; /* Entry count. */ + uint8_t sys_define; /* System defined. */ + uint8_t entry_status; /* Entry Status. */ + #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */ + #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */ + #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */ + #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */ + #define RF_BUSY BIT_1 /* Busy */ + uint32_t handle; /* System handle. */ + uint16_t scsi_status; /* SCSI status. */ + uint16_t comp_status; /* Completion status. */ + uint16_t state_flags; /* State flags. */ + uint16_t status_flags; /* Status flags. */ + #define IOCBSTAT_SF_LOGO 0x2000 /* logo after 2 abts w/ no response (2 sec) */ + uint16_t rsp_info_len; /* Response Info Length. */ + uint16_t req_sense_length; /* Request sense data length. */ + uint32_t residual_length; /* Residual transfer length. */ + uint8_t rsp_info[8]; /* FCP response information. */ + uint8_t req_sense_data[32]; /* Request sense data. */ +}sts_entry_t, response_t; + +/* + * ISP queue - marker entry structure definition. + */ +typedef struct +{ + uint8_t entry_type; /* Entry type. */ + #define MARKER_TYPE 0x04 /* Marker entry. */ + uint8_t entry_count; /* Entry count. */ + uint8_t sys_define; /* System defined. */ + uint8_t entry_status; /* Entry Status. */ + uint32_t sys_define_2; /* System defined. */ + uint8_t reserved; + uint8_t target; /* SCSI ID */ + uint8_t modifier; /* Modifier (7-0). */ + #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */ + #define MK_SYNC_ID 1 /* Synchronize ID */ + #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */ + #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */ + /* clear port changed, */ + /* use sequence number. */ + uint8_t reserved_1; + uint16_t sequence_number; /* Sequence number of event */ + uint16_t lun; /* SCSI LUN */ + uint8_t reserved_2[48]; +}mrk_entry_t; + +/* + * ISP queue - enable LUN entry structure definition. + */ +typedef struct +{ + uint8_t entry_type; /* Entry type. */ + #define ENABLE_LUN_TYPE 0x0B /* Enable LUN entry. */ + uint8_t entry_count; /* Entry count. */ + uint8_t sys_define; /* System defined. */ + uint8_t entry_status; /* Entry Status. */ + uint32_t sys_define_2; /* System defined. */ + uint8_t reserved_8; + uint8_t reserved_1; + uint16_t reserved_2; + uint32_t reserved_3; + uint8_t status; + uint8_t reserved_4; + uint8_t command_count; /* Number of ATIOs allocated. */ + uint8_t immed_notify_count; /* Number of Immediate Notify */ + /* entries allocated. */ + uint16_t reserved_5; + uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */ + uint16_t reserved_6[20]; +}elun_entry_t; + +/* + * ISP queue - modify LUN entry structure definition. + */ +typedef struct +{ + uint8_t entry_type; /* Entry type. */ + #define MODIFY_LUN_TYPE 0x0C /* Modify LUN entry. */ + uint8_t entry_count; /* Entry count. */ + uint8_t sys_define; /* System defined. */ + uint8_t entry_status; /* Entry Status. */ + uint32_t sys_define_2; /* System defined. */ + uint8_t reserved_8; + uint8_t reserved_1; + uint8_t operators; + uint8_t reserved_2; + uint32_t reserved_3; + uint8_t status; + uint8_t reserved_4; + uint8_t command_count; /* Number of ATIOs allocated. */ + uint8_t immed_notify_count; /* Number of Immediate Notify */ + /* entries allocated. */ + uint16_t reserved_5; + uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */ + uint16_t reserved_7[20]; +}modify_lun_entry_t; + +/* + * ISP queue - immediate notify entry structure definition. + */ +typedef struct +{ + uint8_t entry_type; /* Entry type. */ + #define IMMED_NOTIFY_TYPE 0x0D /* Immediate notify entry. */ + uint8_t entry_count; /* Entry count. */ + uint8_t sys_define; /* System defined. */ + uint8_t entry_status; /* Entry Status. */ + uint32_t sys_define_2; /* System defined. */ + uint8_t reserved_8; + uint8_t initiator_id; + uint8_t reserved_1; + uint8_t target_id; + uint32_t reserved_2; + uint16_t status; + uint16_t task_flags; + uint16_t seq_id; + uint16_t reserved_5[11]; + uint16_t scsi_status; + uint8_t sense_data[18]; +}notify_entry_t; + +/* + * ISP queue - notify acknowledge entry structure definition. + */ +typedef struct +{ + uint8_t entry_type; /* Entry type. */ + #define NOTIFY_ACK_TYPE 0x0E /* Notify acknowledge entry. */ + uint8_t entry_count; /* Entry count. */ + uint8_t sys_define; /* System defined. */ + uint8_t entry_status; /* Entry Status. */ + uint32_t sys_define_2; /* System defined. */ + uint8_t reserved_8; + uint8_t initiator_id; + uint8_t reserved_1; + uint8_t target_id; + uint16_t flags; + uint16_t reserved_2; + uint16_t status; + uint16_t task_flags; + uint16_t seq_id; + uint16_t reserved_3[21]; +}nack_entry_t; + +/* + * ISP queue - Accept Target I/O (ATIO) entry structure definition. + */ +typedef struct +{ + uint8_t entry_type; /* Entry type. */ + #define ACCEPT_TGT_IO_TYPE 0x16 /* Accept target I/O entry. */ + uint8_t entry_count; /* Entry count. */ + uint8_t sys_define; /* System defined. */ + uint8_t entry_status; /* Entry Status. */ + uint32_t sys_define_2; /* System defined. */ + uint8_t reserved_8; + uint8_t initiator_id; + uint16_t exchange_id; + uint16_t flags; + uint16_t status; + uint8_t reserved_1; + uint8_t task_codes; + uint8_t task_flags; + uint8_t execution_codes; + uint8_t cdb[MAX_CMDSZ]; + uint32_t data_length; + uint16_t lun; + uint16_t reserved_2A; + uint16_t scsi_status; + uint8_t sense_data[18]; +}atio_entry_t; + +/* + * ISP queue - Continue Target I/O (CTIO) entry for status mode 0 + * structure definition. + */ +typedef struct +{ + uint8_t entry_type; /* Entry type. */ + #define CONTINUE_TGT_IO_TYPE 0x17 /* CTIO entry */ + uint8_t entry_count; /* Entry count. */ + uint8_t sys_define; /* System defined. */ + uint8_t entry_status; /* Entry Status. */ + uint32_t sys_define_2; /* System defined. */ + uint8_t reserved_8; + uint8_t initiator_id; + uint16_t exchange_id; + uint16_t flags; + uint16_t status; + uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */ + uint16_t dseg_count; /* Data segment count. */ + uint32_t relative_offset; + uint32_t residual; + uint16_t reserved_1[3]; + uint16_t scsi_status; + uint32_t transfer_length; + uint32_t dseg_0_address; /* Data segment 0 address. */ + uint32_t dseg_0_length; /* Data segment 0 length. */ + uint32_t dseg_1_address; /* Data segment 1 address. */ + uint32_t dseg_1_length; /* Data segment 1 length. */ + uint32_t dseg_2_address; /* Data segment 2 address. */ + uint32_t dseg_2_length; /* Data segment 2 length. */ +}ctio_entry_t; + +/* + * ISP queue - CTIO returned entry structure definition. + */ +typedef struct +{ + uint8_t entry_type; /* Entry type. */ + #define CTIO_RET_TYPE 0x17 /* CTIO return entry */ + uint8_t entry_count; /* Entry count. */ + uint8_t sys_define; /* System defined. */ + uint8_t entry_status; /* Entry Status. */ + uint32_t sys_define_2; /* System defined. */ + uint8_t reserved_8; + uint8_t initiator_id; + uint16_t exchange_id; + uint16_t flags; + uint16_t status; + uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */ + uint16_t dseg_count; /* Data segment count. */ + uint32_t relative_offset; + uint32_t residual; + uint16_t reserved_1[8]; + uint16_t scsi_status; + uint8_t sense_data[18]; +}ctio_ret_entry_t; + +/* + * ISP queue - CTIO A64 entry structure definition. + */ +typedef struct +{ + uint8_t entry_type; /* Entry type. */ + #define CTIO_A64_TYPE 0x1F /* CTIO A64 entry */ + uint8_t entry_count; /* Entry count. */ + uint8_t sys_define; /* System defined. */ + uint8_t entry_status; /* Entry Status. */ + uint32_t sys_define_2; /* System defined. */ + uint8_t reserved_8; + uint8_t initiator_id; + uint16_t exchange_id; + uint16_t flags; + uint16_t status; + uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */ + uint16_t dseg_count; /* Data segment count. */ + uint32_t relative_offset; + uint32_t residual; + uint16_t reserved_1[3]; + uint16_t scsi_status; + uint32_t transfer_length; + uint32_t dseg_0_address[2]; /* Data segment 0 address. */ + uint32_t dseg_0_length; /* Data segment 0 length. */ + uint32_t dseg_1_address[2]; /* Data segment 1 address. */ + uint32_t dseg_1_length; /* Data segment 1 length. */ +}ctio_a64_entry_t; + +/* + * ISP queue - CTIO returned entry structure definition. + */ +typedef struct +{ + uint8_t entry_type; /* Entry type. */ + #define CTIO_A64_RET_TYPE 0x1F /* CTIO A64 returned entry */ + uint8_t entry_count; /* Entry count. */ + uint8_t sys_define; /* System defined. */ + uint8_t entry_status; /* Entry Status. */ + uint32_t sys_define_2; /* System defined. */ + uint8_t reserved_8; + uint8_t initiator_id; + uint16_t exchange_id; + uint16_t flags; + uint16_t status; + uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */ + uint16_t dseg_count; /* Data segment count. */ + uint32_t relative_offset; + uint32_t residual; + uint16_t reserved_1[8]; + uint16_t scsi_status; + uint8_t sense_data[18]; +}ctio_a64_ret_entry_t; + +/* + * ISP queue - Status Contination entry structure definition. + */ +typedef struct +{ + uint8_t entry_type; /* Entry type. */ + #define STATUS_CONT_TYPE 0x10 /* Status contination entry */ + uint8_t entry_count; /* Entry count. */ + uint8_t reserved; + uint8_t entry_status; /* Entry Status. */ + uint8_t sense_data[60]; +}status_cont_entry_t; + +/* + * ISP queue - Command Set entry structure definition. + */ +typedef struct +{ + uint8_t entry_type; /* Entry type. */ + #define CMD_SET_TYPE 0x18 /* Command set entry */ + uint8_t entry_count; /* Entry count. */ + uint8_t sys_define; /* System defined. */ + uint8_t entry_status; /* Entry Status. */ + uint32_t sys_define_2; /* System defined. */ + uint16_t reserved; + uint16_t status; + uint16_t control_flags; /* Control flags. */ + uint16_t count; + uint32_t iocb_0_address; + uint32_t iocb_1_address; + uint32_t iocb_2_address; + uint32_t iocb_3_address; + uint32_t iocb_4_address; + uint32_t iocb_5_address; + uint32_t iocb_6_address; + uint32_t iocb_7_address; + uint32_t iocb_8_address; + uint32_t iocb_9_address; + uint32_t iocb_10_address; + uint32_t iocb_11_address; +}cmd_set_entry_t; + +/* + * ISP queue - Command Set A64 entry structure definition. + */ +typedef struct +{ + uint8_t entry_type; /* Entry type. */ + #define CMD_SET_TYPE 0x18 /* Command set entry */ + uint8_t entry_count; /* Entry count. */ + uint8_t sys_define; /* System defined. */ + uint8_t entry_status; /* Entry Status. */ + uint32_t sys_define_2; /* System defined. */ + uint16_t reserved; + uint16_t status; + uint16_t control_flags; /* Control flags. */ + uint16_t count; + uint32_t iocb_0_address[2]; + uint32_t iocb_1_address[2]; + uint32_t iocb_2_address[2]; + uint32_t iocb_3_address[2]; + uint32_t iocb_4_address[2]; + uint32_t iocb_5_address[2]; +}cmd_set_a64_entry_t; + +/* 4.11 + * ISP queue - Command Set entry structure definition. + */ +typedef struct +{ + uint8_t entry_type; /* Entry type. */ + #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */ + uint8_t entry_count; /* Entry count. */ + uint8_t sys_define; /* System defined. */ + uint8_t entry_status; /* Entry Status. */ + uint32_t handle; /* System handle. */ + uint8_t reserved; + uint8_t loop_id; + uint16_t status; + uint16_t control_flags; /* Control flags. */ + uint16_t reserved2; + uint16_t timeout; + uint16_t DSDcount; + uint16_t RespDSDcount; + uint8_t reserved3[10]; + uint32_t Response_bytecount; + uint32_t Request_bytecount; + uint32_t dseg_req_address[2]; /* Data segment 0 address. */ + uint32_t dseg_req_length; /* Data segment 0 length. */ + uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */ + uint32_t dseg_rsp_length; /* Data segment 1 length. */ +}cmd_ms_iocb_entry_t; + + +/* + * ISP request and response queue entry sizes + */ +#define RESPONSE_ENTRY_SIZE (sizeof(response_t)) +#define REQUEST_ENTRY_SIZE (sizeof(request_t)) + +/* + * ISP status entry - completion status definitions. + */ +#define CS_COMPLETE 0x0 /* No errors */ +#define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */ +#define CS_DMA 0x2 /* A DMA direction error. */ +#define CS_TRANSPORT 0x3 /* Transport error. */ +#define CS_RESET 0x4 /* SCSI bus reset occurred */ +#define CS_ABORTED 0x5 /* System aborted command. */ +#define CS_TIMEOUT 0x6 /* Timeout error. */ +#define CS_DATA_OVERRUN 0x7 /* Data overrun. */ +#define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */ +#define CS_ABORT_MSG 0xE /* Target rejected abort msg. */ +#define CS_DEV_RESET_MSG 0x12 /* Target rejected dev rst msg. */ +#define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable (selection timeout) */ +#define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */ +#define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */ +#define CS_PORT_BUSY 0x2B /* Port Busy */ +#define CS_BAD_PAYLOAD 0x80 /* Driver defined */ +#define CS_UNKNOWN 0x81 /* Driver defined */ +#define CS_RETRY 0x82 /* Driver defined */ + +/* + * ISP status entry - SCSI status byte bit definitions. + */ +#define SS_RESIDUAL_UNDER BIT_11 +#define SS_RESIDUAL_OVER BIT_10 +#define SS_SENSE_LEN_VALID BIT_9 +#ifdef ISP2200 +#define SS_RESPONSE_INFO_LEN_VALID BIT_8 +#else +#define SS_RESIDUAL_LEN_VALID BIT_8 +#endif + +#define SS_RESERVE_CONFLICT (BIT_4 | BIT_3) +#define SS_BUSY_CONDITION BIT_3 +#define SS_CONDITION_MET BIT_2 +#define SS_CHECK_CONDITION BIT_1 + +/* + * ISP target entries - Flags bit definitions. + */ +#define OF_RESET BIT_5 /* Reset LIP flag */ +#define OF_DATA_IN BIT_6 /* Data in to initiator */ + /* (data from target to initiator) */ +#define OF_DATA_OUT BIT_7 /* Data out from initiator */ + /* (data from initiator to target) */ +#define OF_NO_DATA (BIT_7 | BIT_6) +#define OF_INC_RC BIT_8 /* Increment command resource count */ +#define OF_FAST_POST BIT_9 /* Enable mailbox fast posting. */ +#define OF_SSTS BIT_15 /* Send SCSI status */ + +/* + * Target Read/Write buffer structure. + */ +#define TARGET_DATA_OFFSET 4 +#define TARGET_DATA_SIZE 0x2000 /* 8K */ +#define TARGET_INQ_OFFSET (TARGET_DATA_OFFSET + TARGET_DATA_SIZE) +#define TARGET_SENSE_SIZE 18 +#define TARGET_BUF_SIZE 36 + +#if QL1280_TARGET_MODE_SUPPORT +typedef struct +{ + uint8_t hdr[4]; + uint8_t data[TARGET_DATA_SIZE]; +}tgt_buf_t; +#endif /* QL1280_TARGET_MODE_SUPPORT */ +typedef struct +{ + uint16_t loop_id; +#ifdef QL_MAPPED_TARGETS + uint16_t lun_offset; +#endif + uint32_t down_timer; + scsi_lu_t *luns[MAX_LUNS]; +}tgt_t; + +/* + * 24 bit port ID type definition. + */ +typedef union { + struct { + uint8_t port_id[3]; + uint8_t rsvd_1; + }r; +#if defined(_BIT_FIELDS_LTOH) + uint32_t b24 : 24, + rsvd : 8; + struct { + uint8_t al_pa; + uint8_t area; + uint8_t domain; + uint8_t rsvd_1; + }b; +#else + uint32_t rsvd : 8, + b24 : 24; + struct { + uint8_t domain; + uint8_t area; + uint8_t al_pa; + uint8_t rsvd_1; + }b; +#endif +} port_id_t; + + +typedef struct +{ + uint8_t name[8]; /* big endian node name */ + uint8_t wwn[8]; /* big endian port name */ + uint16_t loop_id; + uint8_t port_id[3]; /* 24-bit port ID */ + uint8_t rsvd_1; + /* + * This is used to retry login for devices specified for + * persistent binding or lost devices. + */ + uint8_t port_login_retry_count; + uint8_t port_timer; + uint16_t flag; + uint32_t mask[8]; /* LUN Mask for this Device */ + /* flags bits defined as follows */ +#define DEV_PUBLIC BIT_0 +#define DEV_OFFLINE BIT_1 +#define DEV_LUNMASK_SET BIT_2 /* some LUNs masked for this device */ +#define DEV_MP_DISABLED BIT_3 /* device disabled for qlmultipath */ +#define DEV_TAPE_DEVICE BIT_4 +#define DEV_CONFIGURED BIT_5 +#define DEV_MISSING BIT_6 +#define DEV_RETURN BIT_7 +#define DEV_HOST BIT_8 +#define DEV_RELOGIN BIT_9 +#define DEV_PORT_DOWN BIT_10 +}fcdev_t; + + +typedef struct +{ + uint8_t in_use; +}fabricid_t; + +/* + * Flash Database structures. + */ +#define FLASH_DATABASE_0 0x1c000 +#define FLASH_DATABASE_1 0x18000 +#define FLASH_DATABASE_VERSION 1 + +typedef struct +{ + uint32_t seq; + uint8_t version; + uint8_t checksum; + uint16_t size; + uint8_t spares[8]; +}flash_hdr_t; + +typedef struct +{ + uint32_t name[2]; + uint8_t spares[8]; +}flash_node_t; + +typedef struct +{ + flash_hdr_t hdr; + flash_node_t node[MAX_FIBRE_DEVICES]; +}flash_database_t; + +/* + * SNS structures. + */ +#define SNS_DATA_SIZE 608 + +typedef struct +{ + uint16_t buffer_length; + uint16_t reserved; + uint32_t buffer_address[2]; + uint16_t subcommand_length; + uint16_t reserved_1; +}sns_hdr_t; + +typedef struct +{ + union + { + struct + { + sns_hdr_t hdr; + uint16_t subcommand; + uint8_t param[SNS_DATA_SIZE - sizeof(sns_hdr_t) - 2]; + }req; + + uint8_t rsp[SNS_DATA_SIZE]; + }p; +}sns_data_t; + +/* + * SNS request/response structures for GP_IDNN. + */ +typedef struct +{ + uint8_t controlbyte; + uint8_t port_id[3]; + uint32_t reserved; + uint8_t nodename[8]; +}port_data_t; + +#ifdef ISP2200 +#define GP_IDNN_LENGTH (256 * sizeof(port_data_t)) + 16 +#else +#define GP_IDNN_LENGTH (126 * sizeof(port_data_t)) + 16 +#endif + +typedef union +{ + struct + { + uint16_t buffer_length; + uint16_t reserved; + uint32_t buffer_address[2]; + uint16_t subcommand_length; + uint16_t reserved_1; + uint16_t subcommand; + uint16_t length; + uint32_t reserved2; + uint32_t protocol; + uint8_t param[GP_IDNN_LENGTH - 28]; + }req; + + struct + { + uint8_t revision; + uint8_t inid[3]; + uint8_t fcstype; + uint8_t subtype; + uint8_t options; + uint8_t reserved; + uint16_t response; + uint16_t residual; + uint8_t reserved1; + uint8_t reason_code; + uint8_t explanation_code; + uint8_t vendor_unique; +#ifdef ISP2200 + port_data_t port_data[256]; +#else + port_data_t port_data[126]; +#endif + }rsp; + +}gp_idnn_t; + +#ifdef ISP2200 +#define GN_LIST_LENGTH 256 * sizeof(port_list_entry_t) +#else +#define GN_LIST_LENGTH 126 * sizeof(port_list_entry_t) +#endif +/* + * Structure used in Get Port List mailbox command (0x75). + */ +typedef struct +{ + uint8_t name[8]; + uint16_t loop_id; +}port_list_entry_t; + +/* + * Structure used for device info. + */ +typedef struct +{ + uint8_t name[8]; /* big endian node name */ + uint8_t wwn[8]; /* big endian port name */ + uint16_t loop_id; + uint8_t port_id[3]; +}device_data_t; + +/* + * Port Database structure definition + * Little endian except where noted. + */ +#define PORT_DATABASE_SIZE 128 /* bytes */ +typedef struct { + uint8_t options; + uint8_t control; + uint8_t master_state; + uint8_t slave_state; +#define PD_STATE_DISCOVERY 0 +#define PD_STATE_WAIT_DISCOVERY_ACK 1 +#define PD_STATE_PORT_LOGIN 2 +#define PD_STATE_WAIT_PORT_LOGIN_ACK 3 +#define PD_STATE_PROCESS_LOGIN 4 +#define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5 +#define PD_STATE_PORT_LOGGED_IN 6 +#define PD_STATE_PORT_UNAVAILABLE 7 +#define PD_STATE_PROCESS_LOGOUT 8 +#define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9 +#define PD_STATE_PORT_LOGOUT 10 +#define PD_STATE_WAIT_PORT_LOGOUT_ACK 11 + uint8_t reserved[2]; + uint8_t hard_address; + uint8_t reserved_1; + uint8_t port_id[4]; + uint8_t node_name[8]; /* Big endian. */ + uint8_t port_name[8]; /* Big endian. */ + uint16_t execution_throttle; + uint16_t execution_count; + uint8_t reset_count; + uint8_t reserved_2; + uint16_t resource_allocation; + uint16_t current_allocation; + uint16_t queue_head; + uint16_t queue_tail; + uint16_t transmit_execution_list_next; + uint16_t transmit_execution_list_previous; + uint16_t common_features; + uint16_t total_concurrent_sequences; + uint16_t RO_by_information_category; + uint8_t recipient; + uint8_t initiator; + uint16_t receive_data_size; + uint16_t concurrent_sequences; + uint16_t open_sequences_per_exchange; + uint16_t lun_abort_flags; + uint16_t lun_stop_flags; + uint16_t stop_queue_head; + uint16_t stop_queue_tail; + uint16_t port_retry_timer; + uint16_t next_sequence_id; + uint16_t frame_count; + uint16_t PRLI_payload_length; + uint8_t prli_svc_param_word_0[2]; /* Big endian */ + /* Bits 15-0 of word 0 */ + uint8_t prli_svc_param_word_3[2]; /* Big endian */ + /* Bits 15-0 of word 3 */ + uint16_t loop_id; + uint16_t extended_lun_info_list_pointer; + uint16_t extended_lun_stop_list_pointer; +} port_database_t; + + + +/* + * Registered State Change Notification structures. + */ +typedef struct { + port_id_t d_id; + uint8_t format; +} rscn_t; + + + +#ifdef FC_IP_SUPPORT +/* + * Definitions for IP support + */ +#define LOOP_ID_MASK 0x00FF +#define PLE_NOT_SCSI_DEVICE 0x8000 /* Upper bit of loop ID set if not SCSI */ + +/* Firmware IP initialization control block definitions */ +typedef struct _IPInitBlock +{ + uint8_t cVersion; + uint8_t cReserved1; + uint16_t wIpFirmwareOptions; + uint16_t wIpHeaderSize; + uint16_t wIpMTUSize; + uint16_t wIpBufferSize; + uint16_t wReserved2; + uint16_t wReserved3; + uint16_t wReserved4; + uint16_t wReserved5; + uint16_t wIpQueueSize; + uint16_t wIpLowWaterMark; + uint16_t wIpQueueAddr[4]; + uint16_t wIpQueueInPointer; + uint16_t wIpFastPostCount; + uint16_t wIpBufferContainerCount; + uint16_t wIpIocbResourceAllocation; +} IP_INIT_BLOCK, *PIP_INIT_BLOCK; + +#define IPIB_VERSION 0x01 +#define IPIB_LOW_WATER_MARK 0 +#define IPIB_FAST_POST_COUNT 4 +#define IPIB_BUFFER_CONTAINER_COUNT 64 +#define IPIB_IOCB_RESERVE_COUNT 250 + +/* IP firmware options */ +#define IPIB_OPTION_64BIT_ADDRESSING 0x0001 +#define IPIB_OPTION_NO_BROADCAST_FASTPOST 0x0002 +#define IPIB_OPTION_OUT_OF_BUFFERS_EVENT 0x0004 + +/* IP device data structure */ +typedef struct _IpDeviceBlock +{ + uint32_t lDeviceFlags; + uint16_t wLoopId; + uint16_t wUnused1; + uint8_t acWorldWideName[8]; + uint8_t acPortId[3]; + uint8_t cUnused2; + struct _IpDeviceBlock *pNextIpDevice; + struct _IpDeviceBlock *pLastIpDevice; + uint32_t lUnused3; +} IP_DEVICE_BLOCK, *PIP_DEVICE_BLOCK; + +#define IP_DEV_FLAG_PRESENT 0x00000001 +#define IP_DEV_FLAG_PUBLIC_DEVICE 0x00000002 + +#define PUBLIC_LOOP_DEVICE ((uint16_t)-1) + +/* Maximum number of IP connections */ +#define QLLAN_MAX_IP_DEVICES 64 + +/* IP IOCB types */ +#define ET_IP_COMMAND_32 0x13 +#define ET_IP_COMMAND_64 0x1B +#define ET_IP_RECEIVE 0x23 +#define ET_IP_RECEIVE_CONTINUATION 0x2B +#define ET_IP_FARP_REQUEST 0x30 + +/* Data segment descriptor structures */ +typedef struct +{ + uint32_t lBase; + uint32_t lCount; +} DATA_SEG; + +typedef struct +{ + uint32_t lBase[2]; + uint32_t lCount; +} DATA_SEG_A64; + +/* IP Command IOCB structure */ +typedef struct _IpCommandEntry +{ + uint32_t lHeader; + uint32_t lHandle; + uint8_t cReserved1; + uint8_t cLoopId; + uint16_t wCompletionStatus; + uint16_t wControlFlags; + uint16_t wReserved2; + uint16_t wTimeout; + uint16_t wSegmentCount; + uint16_t wServiceClass; + uint16_t wReserved3[7]; + uint32_t lTotalByteCount; + union + { + DATA_SEG asDataSeg[3]; + DATA_SEG_A64 asDataSeg64[2]; + } ds; +} IP_COMMAND_ENTRY, *PIP_COMMAND_ENTRY; + +/* IP Receive IOCB structure */ +#define IP_RECEIVE_ENTRY_MAX_HANDLES 24 +typedef struct _IpReceiveEntry +{ + uint8_t cEntryType; + uint8_t cEntryCount; + uint8_t cSegmentCount; + uint8_t cEntryStatus; + uint16_t wS_IDLow; + uint8_t cS_IDHigh; + uint8_t cReserved1; + uint8_t cReserved2; + uint8_t cLoopId; + uint16_t wCompletionStatus; + uint16_t wServiceClass; + uint16_t wSequenseLength; + uint16_t waBufferHandle[IP_RECEIVE_ENTRY_MAX_HANDLES]; +} IP_RECEIVE_ENTRY, *PIP_RECEIVE_ENTRY; + +/* IP Receive IOCB completion status bits */ +#define IP_REC_STATUS_SPLIT_BUFFER 0x0001 + +/* IP FARP Request IOCB structure */ +typedef struct _IpFarpRequestEntry +{ + uint8_t cEntryType; + uint8_t cEntryCount; + uint8_t cReserved1; + uint8_t cEntryStatus; + uint16_t wRequesterPortIdLow; + uint8_t cRequesterPortIdHigh; + uint8_t cReserved2; + uint8_t acRequesterPortName[8]; +} IP_FARP_REQUEST_ENTRY, *PIP_FARP_REQUEST_ENTRY; + +/* IP mailbox commands */ +#define MBC_INITIALIZE_IP 0x0077 +#define MBC_SEND_FARP_REQUEST 0x0078 + +/* Fabric login mailbox command option bits */ +#define MBC_NO_PLOGI_IF_LOGGED_IN 0x01 +#define MBC_NO_PROCESS_LOGIN 0x02 + +/* Mailbox command completion status */ +#define MBS_PORT_ID_IN_USE 0x4007 +#define MBS_LOOP_ID_IN_USE 0x4008 +#define MBS_ALL_LOOP_IDS_IN_USE 0x4009 +#define MBS_NAME_SERVER_NOT_LOGGED_IN 0x400A + +/* IP async events */ +#define MBA_IP_TRANSMIT_COMPLETE 0x8022 +#define MBA_IP_RECEIVE_COMPLETE 0x8023 +#define MBA_IP_BROADCAST_RECEIVED 0x8024 +#define MBA_IP_RECEIVE_BUFFERS_LOW 0x8025 +#define MBA_IP_OUT_OF_BUFFERS 0x8026 +#define MBA_IP_RECEIVE_COMPLETE_SPLIT 0x8027 + +/* FARP request payload structure */ +typedef struct _IpSendFarpPayload +{ + uint8_t cMatchAddressCode; + uint8_t acReserved1[3]; + uint8_t cResponderFlags; + uint8_t acReserved2[3]; + uint8_t acRequesterPortName[8]; + uint8_t acRequesterNodeName[8]; + uint8_t acResponderPortName[8]; + uint8_t acResponderNodeName[8]; +} IP_SEND_FARP_PAYLOAD, *PIP_SEND_FARP_PAYLOAD; + +#define IP_FARP_MATCH_PORTNAME 0x01 +#define IP_FARP_REQUEST_LOGIN 0x01 +#else +/* Fabric login mailbox command option bits */ +#define MBC_NO_PLOGI_IF_LOGGED_IN 0x01 +#define MBC_NO_PROCESS_LOGIN 0x02 + +/* Mailbox command completion status */ +#define MBS_PORT_ID_IN_USE 0x4007 +#define MBS_LOOP_ID_IN_USE 0x4008 +#define MBS_ALL_LOOP_IDS_IN_USE 0x4009 +#define MBS_NAME_SERVER_NOT_LOGGED_IN 0x400A + +#endif /* FC_IP_SUPPORT */ + +/* + * Linux Host Adapter structure + */ +typedef struct scsi_qla_host +{ + /* ISP ring lock, rings, and indexes */ + request_t req[REQUEST_ENTRY_CNT+1]; + response_t res[RESPONSE_ENTRY_CNT+1]; + + /* Linux adapter configuration data */ + struct Scsi_Host *host; /* pointer to host data */ + struct scsi_qla_host *next; + device_reg_t *iobase; /* Base Memory-mapped or I/O address */ + device2300_reg_t *iobase2300;/* Base Memory-mapped or I/O address */ + +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,1,95) + struct pci_dev *pdev; +#endif + uint8_t pci_bus; + uint8_t pci_device_fn; + uint8_t devnum; + volatile unsigned char *mmpbase; /* memory mapped address */ + u_long host_no; + u_long instance; + uint8_t revision; + uint8_t ports; + u_long actthreads; + u_long qthreads; + u_long isr_count; /* Interrupt count */ + u_long isp_aborts; + u_long lip_count; + u_long spurious_int; + uint32_t device_id; + + /* ISP connection configuration data */ + uint16_t max_public_loop_ids; + uint16_t min_external_loopid; /* First external loop Id */ + uint8_t current_topology; /* Current ISP configuration */ + uint8_t prev_topology; /* Previous ISP configuration */ +#define ISP_CFG_NL 1 +#define ISP_CFG_N 2 +#define ISP_CFG_FL 4 +#define ISP_CFG_F 8 + + uint8_t id; /* Host adapter SCSI id */ + uint16_t loop_id; /* Host adapter loop id */ + uint8_t port_id[3]; /* Host adapter port id */ + uint8_t operating_mode; /* current F/W operating connection mode */ + /* 0 - LOOP, 1 - P2P, 2 - LOOP_P2P, + * 3 - P2P_LOOP + */ + + /* NVRAM configuration data */ + uint16_t loop_reset_delay; /* Loop reset delay. */ + uint16_t hiwat; /* High water mark per device. */ + uint16_t execution_throttle; /* queue depth */ + uint16_t minimum_timeout; /* Minimum timeout. */ + uint8_t retry_count; + uint8_t login_timeout; + uint8_t port_down_retry_count; + uint8_t loop_down_timeout; + uint16_t max_luns; + uint16_t max_targets; + + /* Device TGT/LUN queues. */ + tgt_t *tgt[MAX_BUSES][MAX_FIBRE_DEVICES]; /* Logical unit queues */ + + /* Interrupt lock, and data */ + + /* Fibre Channel Device Database and LIP sequence. */ + fcdev_t fc_db[MAX_FIBRE_DEVICES]; /* Driver database. */ + uint32_t flash_db; /* Flash database address in use. */ + fabricid_t fabricid[MAX_FIBRE_DEVICES]; /* Fabric ids table . */ + uint32_t flash_seq; /* Flash database seq # in use. */ + volatile uint16_t lip_seq; /* LIP sequence number. */ + + /* Linux bottom half run queue */ + struct tq_struct run_qla_bh; + + /* Linux kernel thread */ + struct task_struct *dpc_handler; /* kernel thread */ + struct semaphore *dpc_wait; /* DPC waits on this semaphore */ + struct semaphore *dpc_notify; /* requester waits for DPC on this + * semaphore + */ + uint8_t dpc_active; /* DPC routine is active */ + + /* Received ISP mailbox data. */ + volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT]; + + /* Outstandings ISP commands. */ + srb_t *outstanding_cmds[MAX_OUTSTANDING_COMMANDS]; + +#if BITS_PER_LONG > 32 + uint64_t request_dma; /* Physical address. */ +#else + uint32_t request_dma; /* Physical address. */ +#endif + request_t *request_ring; /* Base virtual address */ + request_t *request_ring_ptr; /* Current address. */ + uint16_t req_ring_index; /* Current index. */ + uint16_t req_q_cnt; /* Number of available entries. */ + +#if BITS_PER_LONG > 32 + uint64_t response_dma; /* Physical address. */ +#else + uint32_t response_dma; /* Physical address. */ +#endif + response_t *response_ring; /* Base virtual address */ + response_t *response_ring_ptr; /* Current address. */ + uint16_t rsp_ring_index; /* Current index. */ + +#if QL2X00_TARGET_MODE_SUPPORT + /* Target buffer and sense data. */ + u_long tbuf_dma; /* Physical address. */ + tgt_buf_t *tbuf; + u_long tsense_dma; /* Physical address. */ + uint8_t *tsense; +#endif + +#ifdef FC_IP_SUPPORT + /* Data for IP support */ + uint8_t acPortName[8]; + IP_BUFFER_ENTRY asIpBuffers[IP_BUFFER_QUEUE_DEPTH]; + uint32_t ppIpBufferQueueLow; + uint32_t ppIpBufferQueueHigh; + IP_BUFFER_ENTRY *pIpBufferQueue; + uint16_t wIpBufferIn; + uint16_t wIpBufferOut; + uint32_t lMaximumTransferSize; + uint32_t lReceiveBufferSize; + uint16_t wReceiveBufferCount; + uint16_t wHeaderSize; + PSEND_COMPLETION_CALLBACK pSendCompletionRoutine; + PRECEIVE_PACKETS_CALLBACK pReturnReceivePacketsRoutine; + void *pReturnReceivePacketsContext; + PNOTIFY_CALLBACK pNotifyRoutine; + void *pNotifyContext; + BUFFER_CB *pReceiveBufferCBs; + IP_DEVICE_BLOCK asIpDeviceDatabase[QLLAN_MAX_IP_DEVICES]; + IP_DEVICE_BLOCK *pIpDeviceFree; + IP_DEVICE_BLOCK *pIpDeviceTop; + IP_DEVICE_BLOCK *pIpDeviceBottom; + uint32_t lCurrentTagIndex; + void *apActiveIpQueue[MAX_SEND_PACKETS]; +#endif + + /* Firmware Initialization Control Block data */ +#if BITS_PER_LONG > 32 + uint64_t init_cb_dma; /* Physical address. */ +#else + uint32_t init_cb_dma; /* Physical address. */ +#endif + init_cb_t *init_cb; + + /* Timeout timers. */ + uint8_t queue_restart_timer; + uint8_t loop_down_timer; /* loop down timer */ + uint8_t loop_down_abort_time; /* port down timer */ + uint32_t timer_active; + uint32_t forceLip; + struct timer_list timer; + + /* Watchdog queue, lock and total timer */ +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,1,0) + spinlock_t retry_lock; /* Watchdog Queue Lock */ +#endif + srb_t *retry_q_first; /* First job on watchdog queue */ + srb_t *retry_q_last; /* Last job on watchdog queue */ + + srb_t *done_q_first; /* First job on done queue */ + srb_t *done_q_last; /* Last job on done queue */ + + /* RSCN queue. */ + rscn_t rscn_queue[MAX_RSCN_COUNT]; + uint8_t rscn_in_ptr; + uint8_t rscn_out_ptr; + + /* Host Adapter database */ + fcdev_t *phost_db; + uint8_t host_db_ptr; + + volatile struct + { + uint32_t online :1; /* 0 */ + uint32_t enable_64bit_addressing :1; /* 1 */ + uint32_t mbox_int :1; /* 2 */ + uint32_t mbox_busy :1; /* 3 */ + uint32_t reset_marker :1; /* 4 */ + uint32_t loop_resync_needed :1; /* 5 */ + uint32_t watchdog_enabled :1; /* 6 */ + uint32_t isp_abort_needed :1; /* 7 */ + uint32_t disable_host_adapter :1; /* 8 */ + uint32_t loop_resync_active :1; /* 9 */ + uint32_t reset_active :1; /* 10 */ + uint32_t abort_isp_active :1; /* 11 */ + uint32_t disable_risc_code_load :1; /* 12 */ + uint32_t set_cache_line_size_1 :1; /* 13 */ + uint32_t enable_target_mode :1; /* 14 */ + uint32_t disable_luns :1; /* 15 */ + uint32_t enable_lip_reset :1; /* 16 */ + uint32_t enable_lip_full_login :1; /* 17 */ + uint32_t enable_target_reset :1; /* 18 */ + uint32_t updated_fc_db :1; /* 19 */ + uint32_t enable_flash_db_update :1; /* 20 */ + uint32_t abort_queue_needed :1; /* 21 */ + +#define QLA2100_IN_ISR_BIT 22 + uint32_t in_isr :1; /* 22 */ + uint32_t dpc_sched :1; /* 23 */ + uint32_t start_timer :1; /* 24 */ + uint32_t nvram_config_done :1; /* 25 */ + uint32_t update_config_needed :1; /* 26 */ + uint32_t done_requests_needed :1; /* 27 */ + uint32_t restart_queues_needed :1; /* 28 */ + uint32_t port_restart_needed :1; /* 29 */ +#ifdef FC_IP_SUPPORT + uint32_t enable_ip :1; /* 30 */ +#endif + /* 4.11 */ + uint32_t managment_server_logged_in:1; /* 31 */ + } flags; + + uint32_t device_flags; +#define DFLG_LOCAL_DEVICES BIT_0 +#define DFLG_RETRY_LOCAL_DEVICES BIT_1 +#define RSCN_UPDATE BIT_2 +#define LOGIN_RETRY_NEEDED BIT_3 +#define RSCN_QUEUE_OVERFLOW BIT_4 +#define DFLG_FABRIC_DEVICES BIT_5 +#define RELOGIN_NEEDED BIT_6 + + uint8_t marker_needed; + uint8_t missing_targets; + uint8_t sns_retry_cnt; + uint8_t cmd_wait_cnt; + uint32_t dpc_flags; +#define MAILBOX_RETRY BIT_0 +#define COMMAND_WAIT_NEEDED BIT_1 +#define COMMAND_WAIT_ACTIVE BIT_2 +#define ISP_RESET_NEEDED BIT_3 +#define LOGOUT_DONE BIT_4 +#define ISP_RESET_ONCE BIT_5 + + uint16_t interrupts_on; + + volatile uint16_t loop_state; +/* These values are NOT used as flags. */ +#define LOOP_TIMEOUT 0x1 +#define LOOP_DOWN 0x2 +#define LOOP_UP 0x4 +#define LOOP_UPDATE 0x8 +#define LOOP_READY 0x10 + + /* following are new and needed for IOCTL support */ + uint8_t node_name[8]; + uint8_t nvram_version; + uint8_t ioctl_timer; + uint8_t IoctlPassThru_InProgress; + uint8_t IoctlPassFCCT_InProgress; + void *ioctl_mem; +#if BITS_PER_LONG > 32 + uint64_t ioctl_mem_phys; +#else + uint32_t ioctl_mem_phys; +#endif + + /* HBA serial number */ + uint8_t serial0; + uint8_t serial1; + uint8_t serial2; + + /* oem related items */ + uint8_t oem_id; + uint8_t oem_spare0; + uint8_t oem_part[6]; + uint8_t oem_fru[8]; + uint8_t oem_ec[8]; + uint8_t oem_string[8]; + + uint32_t dump_done; + +} scsi_qla_host_t; + +/* + * Macros to help code, maintain, etc. + */ +#define TGT_Q(ha, b, t) (ha->tgt[b][t]) +#define GET_LU_Q(ha, b, t, l) ( (TGT_Q(ha,b,t) != NULL)? TGT_Q(ha, b, t)->luns[l] : NULL) +#define LU_Q(ha, b, t, l) (TGT_Q(ha, b, t)->luns[l]) +#define PORT_DOWN(ha, t) ((ha)->fc_db[(t)].port_timer) + +/* + * Locking Macro Definitions + * + * LOCK/UNLOCK definitions are lock/unlock primitives for multi-processor + * or spl/splx for uniprocessor. + */ +#define QLA2100_INTR_LOCK(ha) +#define QLA2100_INTR_UNLOCK(ha) + +#define QLA2100_RING_LOCK(ha) +#define QLA2100_RING_UNLOCK(ha) + +#if defined(__cplusplus) +} +#endif +#endif + +#if defined(__386__) +# define QLA2100_BIOSPARAM qla2100_biosparam +#else +# define QLA2100_BIOSPARAM NULL +#endif + +/* + * Linux - SCSI Driver Interface Function Prototypes. + */ +int qla2100_ioctl(Scsi_Device *, int , void *); +int qla2100_proc_info ( char *, char **, off_t, int, int, int); +const char * qla2100_info(struct Scsi_Host *host); +int qla2100_detect(Scsi_Host_Template *); +int qla2100_release(struct Scsi_Host *); +const char * qla2100_info(struct Scsi_Host *); +int qla2100_queuecommand(Scsi_Cmnd *, void (* done)(Scsi_Cmnd *)); +int qla2100_abort(Scsi_Cmnd *); +int qla2100_reset(Scsi_Cmnd *, unsigned int); +int qla2100_biosparam(Disk *, kdev_t, int[]); +void qla2100_intr_handler(int, void *, struct pt_regs *); +//void qla2100_device_queue_depth(scsi_qla_host_t *, Scsi_Device *); +void qla2100_setup(char *s, int *dummy); + +/* Number of segments 1 - 65535 */ +#define SG_SEGMENTS 32 /* Cmd entry + 6 continuations */ + +/* + * Scsi_Host_template (see hosts.h) + * Device driver Interfaces to mid-level SCSI driver. + */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95) +/* This interface is now obsolete !!! */ +#define QLA2100_LINUX_TEMPLATE { \ + next: NULL, \ + usage_count: NULL, \ + proc_dir: NULL, \ + proc_info: qla2100_proc_info, \ + name: "Qlogic Fibre Channel 2100", \ + detect: qla2100_detect, \ + release: qla2100_release, \ + info: qla2100_info, \ + command: NULL, \ + queuecommand: qla2100_queuecommand, \ + abort: qla2100_abort, \ + reset: qla2100_reset, \ + slave_attach: NULL, \ + bios_param: QLA2100_BIOSPARAM, \ + can_queue: 1, /* MAX_OUTSTANDING_COMMANDS */ \ + this_id: -1, /* scsi id of host adapter */ \ + sg_tablesize: SG_ALL, \ + cmd_per_lun: 1, /* max commands per lun */ \ + present: 0, /* number of ISP present */ \ + unchecked_isa_dma: 0, /* no memeory DMA restrictions */ \ + use_clustering: ENABLE_CLUSTERING \ +} +#else + +#define QLA2100_LINUX_TEMPLATE { \ + next: NULL, \ + module: NULL, \ + proc_dir: NULL, \ + proc_info: qla2100_proc_info, \ + name: "Qlogic Fibre Channel 2100", \ + detect: qla2100_detect, \ + release: qla2100_release, \ + info: qla2100_info, \ + ioctl: qla2100_ioctl, \ + command: NULL, \ + queuecommand: qla2100_queuecommand, \ + eh_strategy_handler: NULL, \ + eh_abort_handler: NULL, \ + eh_device_reset_handler: NULL, \ + eh_bus_reset_handler: NULL, \ + eh_host_reset_handler: NULL, \ + abort: qla2100_abort, \ + reset: qla2100_reset, \ + slave_attach: NULL, \ + bios_param: QLA2100_BIOSPARAM, \ + can_queue: 255, /* max simultaneous cmds */\ + this_id: -1, /* scsi id of host adapter */\ + sg_tablesize: SG_SEGMENTS, /* max scatter-gather cmds */\ + cmd_per_lun: 3, /* cmds per lun (linked cmds) */\ + present: 0, /* number of 7xxx's present */\ + unchecked_isa_dma: 0, /* no memory DMA restrictions */\ + use_clustering: ENABLE_CLUSTERING, \ + use_new_eh_code: 0, \ + emulated: 0 \ +} +#endif +#endif /* _IO_HBA_QLA2100_H */ diff -urN linux-2.4.10/drivers/scsi/qla2x00exioct.h linux-2.4.10-lia/drivers/scsi/qla2x00exioct.h --- linux-2.4.10/drivers/scsi/qla2x00exioct.h Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/scsi/qla2x00exioct.h Mon Jul 23 14:12:38 2001 @@ -0,0 +1,823 @@ +/* + * File Name: exioct.h + * + * San/Device Management Ioctl Header + * File is created to adhere to Solaris requirement using 8-space tabs. + * + * !!!!! PLEASE DO NOT REMOVE THE TABS !!!!! + * !!!!! PLEASE NO SINGLE LINE COMMENTS: // !!!!! + * !!!!! PLEASE NO MORE THAN 80 CHARS PER LINE !!!!! + * + * *********************************************************************** + * * ** + * * NOTICE ** + * * COPYRIGHT (C) 2000 QLOGIC CORPORATION ** + * * ALL RIGHTS RESERVED ** + * * ** + * *********************************************************************** + * + * Revision History: + * + * Rev. 0 March 1, 2000 + * YPL - Created. + * + * Rev. 1 March 2, 2000 + * RLU - Updated with latest definitions. Added more comments. + * + * Rev. 2 May 16, 2000 + * SP - Updated definitions and changed structures (March 27, 2000) + * SP - Addded structures + * + * Rev. 3 June 1, 2000 + * THL - Made major changes to include all changes talked in our meeting. + * + * Rev. 4 June 5, 2000 + * RLU - Added new definitions/structures for SDM_GET_AEN and SDM_REG_AEN + * functions. + * - Major definition/structure name changes as discussed in meetings. + * - Deleted duplicated command code and structure definitions. + * + * Rev. 4.1 June 14, 2000 + * WTR - Moved Solaris specific defines to exioctso.h. This makes it + * possible for application developers to include only exioct.h + * in their Solaris application development. + * + * Rev. 4.2 June 15, 2000 + * THL - Changed UINT16 and UINT32 back to WORD and DWORD for NT; otherwise, + * NT will get a compilation error for redefining UINT16 and UINT32. + * Added RISC_CODE/FLASH_RAM macros. + * + * Rev. 4.3 June 22, 2000 + * THL - Changed SDM_FC_ADDR according to External Ioctls document. + * Added SDM_DEF_TYPE macros. + * + * Rev. 4.4 June 22, 2000 + * THL - Moved NT specific defines to exioctnt.h. + * + * Rev. 4.5 August 15, 2000 + * SP - Rolled back some changes made by Todd R. + * Kept new status code SDM_STATUS_NO_MEMORY + * Port types fabric and tape device + * + * Rev. 4.7 Sep 6, 2000 + * YPL - Replace SDM_ with EXT_, _ISP with _CHIP. + * Add vendor specific statuses, device update, config defines. + * + * Rev. 5.0 Sep 13, 2000 + * YPL - Update version to 5, remove max defines, make port type bit. + * Change HBA_PORT_PROPERTY to have bus/target/lun defined as UINT16 + * + * Rev. 5.1 Sep 22, 2000 + * THL - Add destination address for specify scsi address or FC address. + * Remove "not support" comment and add more macros. + * + * Rev. 5.2 Sep 27, 2000 + * THL - Add new macros and structure for add and swap target device. + * Create new data structure for get port database. + * TLE - Merge changes needed for FailOver + * + * Rev. 5.3 Sep 29, 2000 + * THL - Add access mode for NVRAM. + * + * Rev. 5.4 Oct 03, 2000 + * THL - Add EXT_SC_GET_FC_STATISTICS. + * + * Rev. 5.5 Oct 18, 2000 + * THL - Remove duplicated EXT_DEF_ADDR_MODE_32 and EXT_DEF_ADDR_MODE_16. + * Reformat new data structures and defines. + * + * Rev. 5.6 Oct 19, 2000 + * RLU - Changed file name from ExIoct.h to exioct.h. + * - Added definition of EXT_RNID_DATA for API implementation. + * - Reformat some lines to conform to the format agreed + * upon in IOCTL meeting (and mentioned at beginning of + * this file). + * + * Rev. 5.7 Oct 25, 2000 + * BN - Added LUN bitmask structure and macros + * + * Rev. 5.8 Oct 25, 2000 + * BN - Added EXT_CC_DRIVER_PROP define + * + * Rev. 5.9 Oct 26, 2000 + * BN - Sync with UnixApi project + * + * Rev. 5.10 Oct 30, 2000 + * BN - Remove not needed #define for EXT_CC_DRIVER_PROP + * - Add EXT_ to IS_LUN_BIT_SET, SET_LUN_BIT, CLR_LUN_BIT + * + * Rev. 5.11 Nov 1, 2000 + * BN - Increased [1] of EXT_DEVICEDATA to [EXT_MAX_TARGET] + * TLE - Decreased [EXT_MAX_TARGET] of EXT_DEVICEDATA to [1] + * + * Rev. 5.12 Nov 7, 2000 + * RLU - Deleted EXT_DEF_MAX_LUNS define and changed all references + * to it to use EXT_MAX_LUN. + * - Changed the revision numbers for the last 2 revisions down + * to use 5.x. + * + * Rev. 5.13 Nov 28, 2000 + * RLU - Change value defines from EXT_... to EXT_DEF_... + * + * Rev. 5.14 Jan 08, 2001 + * BN - Added #define SDM_CC_LOOPBACK SDM_CC_LOOPBACK_OS + * + */ + +#ifndef _EXIOCT_H +#define _EXIOCT_H + +/* + * NOTE: the following version defines must be updated each time the + * changes made may affect the backward compatibility of the + * input/output relations of the SDM IOCTL functions. + */ +#define EXT_VERSION 5 + + +/* + * OS independent General definitions + */ +#define EXT_DEF_SIGNATURE_SIZE 8 +#define EXT_DEF_WWN_NAME_SIZE 8 +#define EXT_DEF_WWP_NAME_SIZE 8 +#define EXT_DEF_SERIAL_NUM_SIZE 4 +#define EXT_DEF_PORTID_SIZE 4 +#define EXT_DEF_PORTID_SIZE_ACTUAL 3 +#define EXT_DEF_MAX_STR_SIZE 128 +#define EXT_DEF_SCSI_PASSTHRU_CDB_LENGTH 12 + +#define EXT_DEF_ADDR_MODE_32 1 +#define EXT_DEF_ADDR_MODE_64 2 + +/* + * *********************************************************************** + * X OS type definitions + * *********************************************************************** + */ +#ifdef _MSC_VER /* NT */ + +#pragma pack(1) +#include "ExIoctNT.h" + +#elif defined(linux) /* Linux */ + +#include "qla2x00exioctln.h" + +#elif defined(sun) || defined(__sun) /* Solaris */ + +#include "exioctso.h" + +#endif + +/* + * *********************************************************************** + * OS dependent General configuration defines + * *********************************************************************** + */ +#define EXT_DEF_MAX_HBA EXT_DEF_MAX_HBA_OS +#define EXT_DEF_MAX_BUS EXT_DEF_MAX_BUS_OS +#define EXT_DEF_MAX_TARGET EXT_DEF_MAX_TARGET_OS +#define EXT_DEF_MAX_LUN EXT_DEF_MAX_LUN_OS + +/* + * *********************************************************************** + * Common header struct definitions for San/Device Mgmt + * *********************************************************************** + */ +typedef struct { + UINT64 Signature; /* 8 chars string */ + UINT16 AddrMode; /* 2 */ + UINT16 Version; /* 2 */ + UINT16 SubCode; /* 2 */ + UINT16 Instance; /* 2 */ + UINT32 Status; /* 4 */ + UINT32 DetailStatus; /* 4 */ + UINT32 Reserved1; /* 4 */ + UINT32 RequestLen; /* 4 */ + UINT32 ResponseLen; /* 4 */ + UINT64 RequestAdr; /* 8 */ + UINT64 ResponseAdr; /* 8 */ + UINT16 HbaSelect; /* 2 */ + UINT16 VendorSpecificStatus[11]; /* 22 */ + UINT64 VendorSpecificData; /* 8 chars string */ +} EXT_IOCTL, *PEXT_IOCTL; /* 84 / 0x54 */ + +/* + * Addressing mode used by the user application + */ +#define EXT_ADDR_MODE EXT_ADDR_MODE_OS + +/* + * Status. These macros are being used for setting Status field in + * EXT_IOCTL structure. + */ +#define EXT_STATUS_OK 0 +#define EXT_STATUS_ERR 1 +#define EXT_STATUS_BUSY 2 +#define EXT_STATUS_PENDING 3 +#define EXT_STATUS_SUSPENDED 4 +#define EXT_STATUS_RETRY_PENDING 5 +#define EXT_STATUS_INVALID_PARAM 6 +#define EXT_STATUS_DATA_OVERRUN 7 +#define EXT_STATUS_DATA_UNDERRUN 8 +#define EXT_STATUS_DEV_NOT_FOUND 9 +#define EXT_STATUS_COPY_ERR 10 +#define EXT_STATUS_MAILBOX 11 +#define EXT_STATUS_UNSUPPORTED_SUBCODE 12 +#define EXT_STATUS_UNSUPPORTED_VERSION 13 +#define EXT_STATUS_MS_NO_RESPONSE 14 +#define EXT_STATUS_SCSI_STATUS 15 +#define EXT_STATUS_BUFFER_TOO_SMALL 16 +#define EXT_STATUS_NO_MEMORY 17 +#define EXT_STATUS_UNKNOWN 18 +#define EXT_STATUS_UNKNOWN_DSTATUS 19 +#define EXT_STATUS_INVALID_REQUEST 20 + +/* + * Detail Status contains the SCSI bus status codes. + */ + +#define EXT_DSTATUS_GOOD 0x00 +#define EXT_DSTATUS_CHECK_CONDITION 0x02 +#define EXT_DSTATUS_CONDITION_MET 0x04 +#define EXT_DSTATUS_BUSY 0x08 +#define EXT_DSTATUS_INTERMEDIATE 0x10 +#define EXT_DSTATUS_INTERMEDIATE_COND_MET 0x14 +#define EXT_DSTATUS_RESERVATION_CONFLICT 0x18 +#define EXT_DSTATUS_COMMAND_TERMINATED 0x22 +#define EXT_DSTATUS_QUEUE_FULL 0x28 + +/* + * Detail Status contains the needed Response buffer space(bytes) + * when Status = EXT_STATUS_BUFFER_TOO_SMALL + */ + + +/* + * Detail Status contains one of the following codes + * when Status = EXT_STATUS_INVALID_PARAM or + * = EXT_STATUS_DEV_NOT_FOUND + */ +#define EXT_DSTATUS_NOADNL_INFO 0x00 +#define EXT_DSTATUS_HBA_INST 0x01 +#define EXT_DSTATUS_TARGET 0x02 +#define EXT_DSTATUS_LUN 0x03 +#define EXT_DSTATUS_REQUEST_LEN 0x04 +#define EXT_DSTATUS_PATH_INDEX 0x05 + +/* + * Currently supported DeviceControl / ioctl command codes + */ +#define EXT_CC_QUERY EXT_CC_QUERY_OS +#define EXT_CC_SEND_FCCT_PASSTHRU EXT_CC_SEND_FCCT_PASSTHRU_OS +#define EXT_CC_REG_AEN EXT_CC_REG_AEN_OS +#define EXT_CC_GET_AEN EXT_CC_GET_AEN_OS +#define EXT_CC_SEND_ELS_RNID EXT_CC_SEND_ELS_RNID_OS +#define EXT_CC_SEND_SCSI_PASSTHRU EXT_CC_SCSI_PASSTHRU_OS +#define EXT_CC_READ_HOST_PARAMS EXT_CC_READ_HOST_PARAMS_OS +#define EXT_CC_READ_RISC_PARAMS EXT_CC_READ_RISC_PARAMS_OS +#define EXT_CC_UPDATE_HOST_PARAMS EXT_CC_UPDATE_HOST_PARAMS_OS +#define EXT_CC_UPDATE_RISC_PARAMS EXT_CC_UPDATE_RISC_PARAMS_OS +#define EXT_CC_READ_NVRAM EXT_CC_READ_NVRAM_OS +#define EXT_CC_UPDATE_NVRAM EXT_CC_UPDATE_NVRAM_OS + +#define EXT_CC_LOOPBACK EXT_CC_LOOPBACK_OS +/* + * HBA port operations + */ +#define EXT_CC_GET_DATA EXT_CC_GET_DATA_OS +#define EXT_CC_SET_DATA EXT_CC_SET_DATA_OS + +/* + * The following DeviceControl / ioctl command codes currently are not + * supported. + */ +#define EXT_CC_SEND_ELS_RTIN EXT_CC_SEND_ELS_RTIN_OS + + +/* + * *********************************************************************** + * EXT_IOCTL SubCode definition. + * These macros are being used for setting SubCode field in EXT_IOCTL + * structure. + * *********************************************************************** + */ + +/* + * Query. + * Uses with EXT_QUERY as the ioctl code. + */ +#define EXT_SC_QUERY_HBA_NODE 1 +#define EXT_SC_QUERY_HBA_PORT 2 +#define EXT_SC_QUERY_DISC_PORT 3 +#define EXT_SC_QUERY_DISC_TGT 4 +#define EXT_SC_QUERY_DISC_LUN 5 /* Currently Not Supported */ +#define EXT_SC_QUERY_DRIVER 6 +#define EXT_SC_QUERY_FW 7 +#define EXT_SC_QUERY_CHIP 8 + +/* + * Get. + * Uses with EXT_GET_DATA as the ioctl code + */ +/* 1 - 99 Common */ +#define EXT_SC_GET_SCSI_ADDR 1 /* Currently Not Supported */ +#define EXT_SC_GET_ERR_DETECTIONS 2 /* Currently Not Supported */ +#define EXT_SC_GET_STATISTICS 3 +#define EXT_SC_GET_BUS_MODE 4 /* Currently Not Supported */ +#define EXT_SC_GET_DR_DUMP_BUF 5 /* Currently Not Supported */ +#define EXT_SC_GET_RISC_CODE 6 +#define EXT_SC_GET_FLASH_RAM 7 + +/* 100 - 199 FC_INTF_TYPE */ +#define EXT_SC_GET_LINK_STATUS 101 /* Currently Not Supported */ +#define EXT_SC_GET_LOOP_ID 102 /* Currently Not Supported */ +#define EXT_SC_GET_LUN_BITMASK 103 +#define EXT_SC_GET_PORT_DATABASE 104 /* Currently Not Supported */ +#define EXT_SC_GET_PORT_DATABASE_MEM 105 /* Currently Not Supported */ +#define EXT_SC_GET_PORT_SUMMARY 106 +#define EXT_SC_GET_POSITION_MAP 107 +#define EXT_SC_GET_RETRY_CNT 108 /* Currently Not Supported */ +#define EXT_SC_GET_RNID 109 +#define EXT_SC_GET_RTIN 110 /* Currently Not Supported */ +#define EXT_SC_GET_FC_LUN_BITMASK 111 +#define EXT_SC_GET_FC_STATISTICS 112 + +/* 200 - 299 SCSI_INTF_TYPE */ +#define EXT_SC_GET_SEL_TIMEOUT 201 /* Currently Not Supported */ + + +/* + * Set. + * Uses with EXT_SET_DATA as the ioctl code + */ +/* 1 - 99 Common */ +#define EXT_SC_RST_STATISTICS 3 /* Currently Not Supported */ +#define EXT_SC_SET_BUS_MODE 4 /* Currently Not Supported */ +#define EXT_SC_SET_DR_DUMP_BUF 5 /* Currently Not Supported */ +#define EXT_SC_SET_RISC_CODE 6 +#define EXT_SC_SET_FLASH_RAM 7 + +/* 100 - 199 FC_INTF_TYPE */ +#define EXT_SC_SET_LUN_BITMASK 103 +#define EXT_SC_SET_RETRY_CNT 108 /* Currently Not Supported */ +#define EXT_SC_SET_RNID 109 +#define EXT_SC_SET_RTIN 110 /* Currently Not Supported */ +#define EXT_SC_SET_FC_LUN_BITMASK 111 +#define EXT_SC_ADD_TARGET_DEVICE 112 +#define EXT_SC_SWAP_TARGET_DEVICE 113 + +/* 200 - 299 SCSI_INTF_TYPE */ +#define EXT_SC_SET_SEL_TIMEOUT 201 /* Currently Not Supported */ + +/* SCSI passthrough */ +#define EXT_SC_SEND_SCSI_PASSTHRU 0 +#define EXT_SC_SEND_FC_SCSI_PASSTHRU 1 + +/* NVRAM */ +#define EXT_SC_NVRAM_HARDWARE 0 /* Save */ +#define EXT_SC_NVRAM_DRIVER 1 /* Driver (Apply) */ +#define EXT_SC_NVRAM_ALL 2 /* NVRAM/Driver (Save+Apply) */ + +/* Read */ + +/* Write */ + +/* Reset */ + +/* Request struct */ + + +/* + * Response struct + */ +typedef struct _EXT_HBA_NODE { + UINT8 WWNN [EXT_DEF_WWN_NAME_SIZE]; /* 8 */ + UINT8 Manufacturer [EXT_DEF_MAX_STR_SIZE]; /* 128; "QLOGIC" */ + UINT8 Model [EXT_DEF_MAX_STR_SIZE]; /* 128; "QLA2200" */ + UINT8 SerialNum [EXT_DEF_SERIAL_NUM_SIZE];/* 4; 123 */ + UINT8 DriverVersion[EXT_DEF_MAX_STR_SIZE]; /* 128; "7.4.3" */ + UINT8 FWVersion [EXT_DEF_MAX_STR_SIZE]; /* 128; "2.1.6" */ + + /* The following field is currently not supported */ + UINT8 OptRomVersion[EXT_DEF_MAX_STR_SIZE]; /* 128; "1.44" */ + + UINT16 PortCount; /* 2; 1 */ + UINT16 InterfaceType; /* 2; FC/SCSI */ + + /* The following two fields are not yet supported */ + UINT32 DriverAttr; /* 4 */ + UINT32 FWAttr; /* 4 */ + + UINT32 Reserved[8]; /* 32 */ +} EXT_HBA_NODE, *PEXT_HBA_NODE; /* 696 */ + +/* HBA node query interface type */ +#define EXT_DEF_FC_INTF_TYPE 1 +#define EXT_DEF_SCSI_INTF_TYPE 2 + +typedef struct _EXT_HBA_PORT { + UINT8 WWPN[EXT_DEF_WWN_NAME_SIZE]; /* 8 */ + UINT8 Id [EXT_DEF_PORTID_SIZE]; /* 4; 3 bytes valid Port Id. */ + UINT16 Type; /* 2; Port Type */ + UINT16 State; /* 2; Port State */ + UINT16 Mode; /* 2 */ + UINT16 DiscPortCount; /* 2 */ + UINT16 DiscPortNameType; /* 2; USE_NODE_NAME or */ + /* USE_PORT_NAME */ + UINT16 DiscTargetCount; /* 2 */ + UINT16 Bus; /* 1 */ + UINT16 Target; /* 1 */ + UINT16 Lun; /* 1 */ + UINT16 Unused; /* 1 */ + UINT32 Reserved[6]; /* 28 */ +} EXT_HBA_PORT, *PEXT_HBA_PORT; /* 56 */ + +/* port type bit definitions */ +#define EXT_DEF_INITIATOR_DEV 0x1 +#define EXT_DEF_TARGET_DEV 0x2 +#define EXT_DEF_TAPE_DEV 0x4 +#define EXT_DEF_FABRIC_DEV 0x8 + + +/* HBA port state */ +#define EXT_DEF_HBA_OK 0 +#define EXT_DEF_HBA_SUSPENDED 1 +#define EXT_DEF_HBA_LOOP_DOWN 2 + +/* Connection mode */ +#define EXT_DEF_P2P_MODE 1 +#define EXT_DEF_LOOP_MODE 2 + +/* Valid name type for Disc. port/target */ +#define EXT_DEF_USE_NODE_NAME 1 +#define EXT_DEF_USE_PORT_NAME 2 + +typedef struct _EXT_DISC_PORT { + UINT8 WWNN[EXT_DEF_WWN_NAME_SIZE]; /* 8 */ + UINT8 WWPN[EXT_DEF_WWN_NAME_SIZE]; /* 8 */ + UINT8 Id [EXT_DEF_PORTID_SIZE]; /* 4; 3 bytes used. big endian*/ + + /* The following fields currently are not supported */ + UINT16 Type; /* 2; Port Type */ + UINT16 Status; /* 2; Port Status */ + UINT16 Bus; /* 2; n/a for Solaris */ + + UINT16 TargetId; /* 2 */ + UINT32 Reserved[8]; /* 32 */ +} EXT_DISC_PORT, *PEXT_DISC_PORT; /* 60 */ + +typedef struct _EXT_DISC_TARGET { + UINT8 WWNN[EXT_DEF_WWN_NAME_SIZE]; /* 8 */ + UINT8 WWPN[EXT_DEF_WWN_NAME_SIZE]; /* 8 */ + UINT8 Id [EXT_DEF_PORTID_SIZE]; /* 4; 3 bytes used. big endian*/ + + /* The following fields currently are not supported */ + UINT16 Type; /* 2; Target Type */ + UINT16 Status; /* 2; Target Status*/ + UINT16 Bus; /* 2; n/a for Solaris */ + + UINT16 TargetId; /* 2 */ + + /* The following field is currently not supported */ + UINT16 LunCount; /* 2; n/a for nt */ + + UINT16 Reserved[15]; /* 30 */ +} EXT_DISC_TARGET, *PEXT_DISC_TARGET; /* 60 */ + +/* The following command is not supported */ +typedef struct _EXT_DISC_LUN { /* n/a for nt */ + UINT16 Id; /* 2 */ + UINT16 State; /* 2 */ + UINT16 IoCount; /* 2 */ + UINT16 Reserved[15]; /* 30 */ +} EXT_DISC_LUN, *PEXT_DISC_LUN; /* 36 */ + + +/* SCSI address */ +typedef struct _EXT_SCSI_ADDR { + UINT16 Bus; /* 2 */ + UINT16 Target; /* 2 */ + UINT16 Lun; /* 2 */ + UINT16 Padding[5]; /* 10 */ +} EXT_SCSI_ADDR, *PEXT_SCSI_ADDR; /* 16 */ + + +/* Fibre Channel address */ +typedef struct _EXT_FC_ADDR { + union { + UINT8 WWNN[EXT_DEF_WWN_NAME_SIZE]; /* 8 */ + UINT8 WWPN[EXT_DEF_WWN_NAME_SIZE]; /* 8 */ + UINT8 Id[EXT_DEF_PORTID_SIZE]; /* 4 */ + } FcAddr; + UINT16 Type; /* 2 */ + UINT16 Padding[2]; /* 2 */ +} EXT_FC_ADDR, *PEXT_FC_ADDR; /* 24 */ + +#define EXT_DEF_TYPE_WWNN 1 +#define EXT_DEF_TYPE_WWPN 2 +#define EXT_DEF_TYPE_PORTID 3 +#define EXT_DEF_TYPE_FABRIC 4 + + +/* Destination address */ +typedef struct _EXT_DEST_ADDR { + union { + UINT8 WWNN[EXT_DEF_WWN_NAME_SIZE]; /* 8 */ + UINT8 WWPN[EXT_DEF_WWN_NAME_SIZE]; /* 8 */ + UINT8 Id[EXT_DEF_PORTID_SIZE]; /* 4 */ + struct { + UINT16 Bus; /* 2 */ + UINT16 Target; /* 2 */ + } ScsiAddr; + } DestAddr; + UINT16 DestType; /* 2 */ + UINT16 Lun; /* 2 */ + UINT16 Padding[2]; /* 4 */ +} EXT_DEST_ADDR, *PEXT_DEST_ADDR; /* 20 */ + + +#define EXT_DEF_DESTTYPE_WWNN 1 +#define EXT_DEF_DESTTYPE_WWPN 2 +#define EXT_DEF_DESTTYPE_PORTID 3 +#define EXT_DEF_DESTTYPE_FABRIC 4 +#define EXT_DEF_DESTTYPE_SCSI 5 + +/* Statistic */ +typedef struct _EXT_HBA_PORT_STAT { + UINT32 ControllerErrorCount; /* 4 */ + UINT32 DeviceErrorCount; /* 4 */ + UINT32 TotalIoCount; /* 4 */ + UINT32 TotalMBytes; /* 4; MB of data processed */ + UINT32 TotalLipResets; /* 4; Total no. of LIP Reset */ + UINT32 TotalInterrupts; /* 4; Total no. of Interrupts */ + UINT32 TotalLinkFailures; /* 4 */ + UINT32 TotalLossOfSync; /* 4 */ + UINT32 TotalLossOfSignals; /* 4 */ + UINT32 PrimitiveSeqProtocolErrorCount;/* 4 */ + UINT32 InvalidTransmissionWordCount; /* 4 */ + UINT32 InvalidCRCCount; /* 4 */ + UINT32 Reserved[16]; /* 64 */ +} EXT_HBA_PORT_STAT, *PEXT_HBA_PORT_STAT; /* 112 */ + + +/* Driver property */ +typedef struct _EXT_DRIVER { + UINT8 Version[EXT_DEF_MAX_STR_SIZE];/* 128 */ + UINT16 NumOfBus; /* 2; Port Type */ + UINT16 TargetsPerBus; /* 2; Port Status */ + UINT16 LunsPerTarget; /* 2 */ + UINT32 MaxTransferLen; /* 4 */ + UINT32 MaxDataSegments; /* 4 */ + UINT16 DmaBitAddresses; /* 2 */ + UINT16 IoMapType; /* 2 */ + UINT32 Attrib; /* 4 */ + UINT32 InternalFlags[4]; /* 16 */ + UINT32 Reserved[8]; /* 32 */ +} EXT_DRIVER, *PEXT_DRIVER; /* 198 */ + + +/* Firmware property */ +typedef struct _EXT_FW { + UINT8 Version[EXT_DEF_MAX_STR_SIZE];/* 128 */ + UINT32 Attrib; /* 4 */ + UINT16 Reserved[33]; /* 66 */ +} EXT_FW, *PEXT_FW; /* 198 */ + + +/* ISP/Chip property */ +typedef struct _EXT_CHIP { + UINT16 VendorId; /* 2 */ + UINT16 DeviceId; /* 2 */ + UINT16 SubVendorId; /* 2 */ + UINT16 SubSystemId; /* 2 */ + UINT16 PciBusNumber; /* 2 */ + UINT16 PciSlotNumber; /* 2 */ + UINT32 IoAddr; /* 4 */ + UINT32 IoAddrLen; /* 4 */ + UINT32 MemAddr; /* 4 */ + UINT32 MemAddrLen; /* 4 */ + UINT16 ChipType; /* 2 */ + UINT16 InterruptLevel; /* 2 */ + UINT16 OutMbx[8]; /* 16 */ + UINT32 Reserved[8]; /* 32 */ +} EXT_CHIP, *PEXT_CHIP; /* 80 */ + + +/* Request Buffer for RNID */ +typedef struct _EXT_RNID_REQ { + EXT_FC_ADDR Addr; + UINT8 DataFormat; + UINT32 Reserved[16]; +} EXT_RNID_REQ, *PEXT_RNID_REQ; + +/* Request Buffer for Set RNID */ +typedef struct _EXT_SET_RNID_REQ { + UINT8 IPVersion[2]; + UINT8 UDPPortNumber[2]; + UINT8 IPAddress[16]; + UINT32 Reserved[16]; +} EXT_SET_RNID_REQ, *PEXT_SET_RNID_REQ; + +/* RNID definition and data struct */ +#define SEND_RNID_RSP_SIZE 72 + +typedef struct _RNID_DATA +{ + UINT8 WWN[16]; /* 16 */ + UINT32 UnitType; /* 4 */ + UINT8 PortId[4]; /* 4 */ + UINT32 NumOfAttachedNodes; /* 4 */ + UINT8 IPVersion[2]; /* 2 */ + UINT8 UDPPortNumber[2]; /* 2 */ + UINT8 IPAddress[16]; /* 16 */ + UINT16 Reserved; /* 2 */ + UINT16 TopoDiscFlags; /* 2 */ +} EXT_RNID_DATA, *PEXT_RNID_DATA; /* 52 */ + + +/* SCSI pass-through */ +typedef struct _EXT_SCSI_PASSTHRU { + EXT_SCSI_ADDR TargetAddr; + UINT8 Direction; + UINT8 CdbLength; + UINT8 Cdb[EXT_DEF_SCSI_PASSTHRU_CDB_LENGTH]; + UINT32 Reserved[16]; + UINT8 SenseData[256]; +} EXT_SCSI_PASSTHRU, *PEXT_SCSI_PASSTHRU; + +/* FC SCSI pass-through */ +typedef struct _EXT_FC_SCSI_PASSTHRU { + EXT_DEST_ADDR FCScsiAddr; + UINT8 Direction; + UINT8 CdbLength; + UINT8 Cdb[EXT_DEF_SCSI_PASSTHRU_CDB_LENGTH]; + UINT32 Reserved[16]; + UINT8 SenseData[256]; +} EXT_FC_SCSI_PASSTHRU, *PEXT_FC_SCSI_PASSTHRU; + +/* SCSI pass-through direction */ +#define EXT_DEF_SCSI_PASSTHRU_DATA_IN 1 +#define EXT_DEF_SCSI_PASSTHRU_DATA_OUT 2 + + +/* EXT_REG_AEN Request struct */ +typedef struct _EXT_REG_AEN { + UINT32 Enable; /* 4; non-0 to enable, 0 to disable. */ + UINT32 Reserved; /* 4 */ +} EXT_REG_AEN, *PEXT_REG_AEN; /* 8 */ + +/* EXT_GET_AEN Response struct */ +typedef struct _EXT_ASYNC_EVENT { + UINT32 AsyncEventCode; /* 4 */ + union { + struct { + UINT8 RSCNInfo[EXT_DEF_PORTID_SIZE_ACTUAL];/* 3, BE */ + UINT8 AddrFormat; /* 1 */ + UINT32 Rsvd_1[2]; /* 8 */ + } RSCN; + + UINT32 Reserved[3]; /* 12 */ + } Payload; +} EXT_ASYNC_EVENT, *PEXT_ASYNC_EVENT; /* 16 */ + +/* Asynchronous Event Codes */ +#define EXT_DEF_LIP_OCCURRED 0x8010 +#define EXT_DEF_LINK_UP 0x8011 +#define EXT_DEF_LINK_DOWN 0x8012 +#define EXT_DEF_LIP_RESET 0x8013 +#define EXT_DEF_RSCN 0x8015 +#define EXT_DEF_DEVICE_UPDATE 0x8014 + +/* Required # of entries in the queue buffer allocated. */ +#define EXT_DEF_MAX_AEN_QUEUE EXT_DEF_MAX_AEN_QUEUE_OS + +/* LUN BitMask structure definition, array of 32bit words, + * 1 bit per lun. When bit == 1, the lun is masked. + * Most significant bit of mask[0] is lun 0, bit 24 is lun 7. + */ +typedef struct _EXT_LUN_BIT_MASK { +#if ((EXT_MAX_LUN & 0x7) == 0) + UINT8 mask[EXT_DEF_MAX_LUN >> 3]; +#else + UINT8 mask[(EXT_DEF_MAX_LUN + 8) >> 3 ]; +#endif +} EXT_LUN_BIT_MASK, *PEXT_LUN_BIT_MASK; + +/* Device type to get for EXT_SC_GET_PORT_SUMMARY */ +#define EXT_DEF_GET_KNOWN_DEVICE 0x1 +#define EXT_DEF_GET_VISIBLE_DEVICE 0x2 +#define EXT_DEF_GET_HIDDEN_DEVICE 0x4 +#define EXT_DEF_GET_FABRIC_DEVICE 0x8 +#define EXT_DEF_GET_LOOP_DEVICE 0x10 + +/* Each entry in device database */ +typedef struct _EXT_DEVICEDATAENTRY +{ + UINT8 NodeWWN[8]; /* Node World Wide Name for device */ + UINT8 PortWWN[8]; /* Port World Wide Name for device */ + UINT8 PortID[3]; /* Current PortId for device */ + UINT8 ControlFlags; /* Control flag */ + EXT_SCSI_ADDR TargetAddress; /* scsi address */ + UINT32 DeviceFlags; /* Flags for device */ + UINT16 LoopID; /* Loop ID */ + UINT16 BaseLunNumber; + UINT32 Reserved[32]; +} EXT_DEVICEDATAENTRY, *PEXT_DEVICEDATAENTRY; + +#define EXT_DEF_EXTERNAL_LUN_COUNT 2048 +#define EXT_DEF_EXTERNAL_LUN_BITMASK_BYTES (EXT_DEF_EXTERNAL_LUN_COUNT / 8) + +/* Structure as used in the IOCTL. */ + +typedef struct _EXT_EXTERNAL_LUN_BITMASK_ENTRY +{ + UINT8 NodeName[EXT_DEF_WWN_NAME_SIZE]; + UINT8 PortName[EXT_DEF_WWN_NAME_SIZE]; + + UINT32 Reserved2; + UINT32 Reserved3; + UINT32 Reserved4; + UINT32 Reserved5; /* Pad to 32-byte header.*/ + + UINT8 Bitmask[EXT_DEF_EXTERNAL_LUN_BITMASK_BYTES]; +} EXT_EXTERNAL_LUN_BITMASK_ENTRY, *PEXT_EXTERNAL_LUN_BITMASK_ENTRY; + + +/* Structure as it is stored in the NT registry.*/ + +typedef struct _LUN_BITMASK_LIST +{ + UINT16 Version; /* Should be LUN_BITMASK_REGISTRY_VERSION */ + UINT16 EntryCount; /* Count of variable entries following.*/ + UINT32 Reserved1; + UINT32 Reserved2; + UINT32 Reserved3; + UINT32 Reserved4; + UINT32 Reserved5; + UINT32 Reserved6; + UINT32 Reserved7; /* Pad to 32-byte header.*/ + + EXT_EXTERNAL_LUN_BITMASK_ENTRY BitmaskEntry[1]; + /* Variable-length data.*/ + +} EXT_LUN_BITMASK_LIST, *PEXT_LUN_BITMASK_LIST; + + +/* Device database information */ +typedef struct _EXT_DEVICEDATA +{ + UINT32 TotalDevices; /* Set to total number of device. */ + UINT32 ReturnListEntryCount; /* Set to number of device entries */ + /* returned in list. */ + + EXT_DEVICEDATAENTRY EntryList[1]; /* Variable length */ +} EXT_DEVICEDATA, *PEXT_DEVICEDATA; + + +/* Swap Target Device Data structure */ +typedef struct _EXT_SWAPTARGETDEVICE +{ + EXT_DEVICEDATAENTRY CurrentExistDevice; + EXT_DEVICEDATAENTRY NewDevice; +} EXT_SWAPTARGETDEVICE, *PEXT_SWAPTARGETDEVICE; + +#define EXT_DEF_LUN_BITMASK_LIST_MIN_ENTRIES 1 +#define EXT_DEF_LUN_BITMASK_LIST_MAX_ENTRIES 256 + +#ifdef _WIN64 +#define EXT_DEF_LUN_BITMASK_LIST_HEADER_SIZE 32 +#else +#define EXT_DEF_LUN_BITMASK_LIST_HEADER_SIZE \ + offsetof(LUN_BITMASK_LIST_BUFFER, asBitmaskEntry) +#endif + +#define EXT_DEF_LUN_BITMASK_LIST_MIN_SIZE \ + (EXT_DEF_LUN_BITMASK_LIST_HEADER_SIZE + \ + (sizeof(EXT_EXTERNAL_LUN_BITMASK_ENTRY) * EXT_DEF_LUN_BITMASK_LIST_MIN_ENTRIES)) +#define EXT_LUN_BITMASK_LIST_MAX_SIZE \ + (EXT_LUN_BITMASK_LIST_HEADER_SIZE + \ + (sizeof(EXT_EXTERNAL_LUN_BITMASK_ENTRY) * EXT_DEF_LUN_BITMASK_LIST_MAX_ENTRIES)) +/* + * LUN mask bit manipulation macros + * + * P = Pointer to an EXT_LUN_BIT_MASK union. + * L = LUN number. + */ +#define EXT_IS_LUN_BIT_SET(P,L) \ + ((P->mask[L/8] & (0x80 >> (L%8)))?1:0) + +#define EXT_SET_LUN_BIT(P,L) \ + (P->mask[L/8] |= (0x80 >> (L%8))) + +#define EXT_CLR_LUN_BIT(P,L) \ + (P->mask[L/8] &= ~(0x80 >> (L%8))) + + + +#ifdef _MSC_VER +#pragma pack() +#endif + +#endif /* _EXIOCT_H */ diff -urN linux-2.4.10/drivers/scsi/qla2x00exioctln.h linux-2.4.10-lia/drivers/scsi/qla2x00exioctln.h --- linux-2.4.10/drivers/scsi/qla2x00exioctln.h Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/scsi/qla2x00exioctln.h Mon Jul 23 14:12:47 2001 @@ -0,0 +1,131 @@ +/***************************************************************************** +* QLOGIC LINUX SOFTWARE +* +* QLogic ISP2x00 device driver for Linux 2.2.x and 2.4.x +* Copyright (C) 2000 Qlogic Corporation +* (www.qlogic.com) +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of the GNU General Public License as published by the +* Free Software Foundation; either version 2, or (at your option) any +* later version. +* +* This program is distributed in the hope that it will be useful, but +* WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +* General Public License for more details. +****************************************************************************/ + +/* + Rev 8 Jan 08, 2001 BN + - Added LOOP_BACK ioctl define + + Rev 7 Nov 06, 2000 BN + - Added EXT_DEF_MAX_AEN_QUEUE_OS define + - Added define for handle_hba_t + + Rev 6 Oct 25, 2000 BN + - Added EXT_CC_DRIVER_PROP_OS define + + Rev 5 Oct 25, 2000 BN + - Redo the copyright header and add AEN details + + Rev 4 Oct 23, 2000 BN + - Added definition for BOOLEAN + + Rev 3 Oct 23, 2000 + BN + - Added definitions for EXT_ADDR_MODE_OS + and also include of + + Rev 2 Oct 18, 2000 + BN + - Enable API Exention support + + Rev 1 Original version Sep 7, 2000 + BN + + + +*/ + +#include + +#if BITS_PER_LONG <= 32 +#define EXT_ADDR_MODE_OS EXT_DEF_ADDR_MODE_32 +#else +#define EXT_ADDR_MODE_OS EXT_DEF_ADDR_MODE_64 +#endif + +#define UINT8 uint8_t +#define UINT16 uint16_t +#define UINT32 uint32_t +#define UINT64 void * +#define BOOLEAN uint8_t + +#define uint8_t unsigned char +#define uint16_t unsigned short +#define uint32_t unsigned int + +#if BITS_PER_LONG > 32 +#define uint64_t unsigned long +#else +#define uint64_t unsigned long long +#endif + +typedef struct track_instance +{ + + int handle; + +} track_instance_t; + + +#define EXT_DEF_MAX_HBA_OS 256 /* 0 - 0xFF */ +#define EXT_DEF_MAX_BUS_OS 1 +#define EXT_DEF_MAX_TARGET_OS 256 /* 0 - 0xFF */ +#define EXT_DEF_MAX_LUN_OS 256 /* 0 - 0xFF */ + +#define EXT_DEF_MAX_AEN_QUEUE_OS 64 + +#define QLMULTIPATH_MAGIC 'y' +#define _QLBUILD /* for exioct.h to enable include of qinsdmgt.h */ + +#define EXT_CC_STARTIOCTL _IOWR(QLMULTIPATH_MAGIC, 0 , sizeof(EXT_IOCTL)) +#define EXT_CC_SETINSTANCE _IOWR(QLMULTIPATH_MAGIC, 1 , sizeof(EXT_IOCTL)) + +#define EXT_CC_QUERY_OS _IOWR(QLMULTIPATH_MAGIC, 2 , sizeof(EXT_IOCTL)) +#define EXT_CC_SEND_FCCT_PASSTHRU_OS _IOWR(QLMULTIPATH_MAGIC, 3 , sizeof(EXT_IOCTL)) +#define EXT_CC_READ_NVRAM_OS _IOWR(QLMULTIPATH_MAGIC, 4 , sizeof(EXT_IOCTL)) +#define EXT_CC_SCSI_PASSTHRU_OS _IOWR(QLMULTIPATH_MAGIC, 5 , sizeof(EXT_IOCTL)) +#define EXT_CC_STOP_QCMD _IOWR(QLMULTIPATH_MAGIC, 6 , sizeof(EXT_IOCTL)) +#define EXT_CC_RESUME_QCMD _IOWR(QLMULTIPATH_MAGIC, 7 , sizeof(EXT_IOCTL)) +#define EXT_CC_GET_DATA_OS _IOWR(QLMULTIPATH_MAGIC, 8 , sizeof(EXT_IOCTL)) +#define EXT_CC_WWPN_TO_SCSIADDR _IOWR(QLMULTIPATH_MAGIC, 9 , sizeof(EXT_IOCTL)) +#define EXT_CC_REG_AEN_OS _IOWR(QLMULTIPATH_MAGIC, 10 , sizeof(EXT_IOCTL)) +#define EXT_CC_GET_AEN_OS _IOWR(QLMULTIPATH_MAGIC, 11 , sizeof(EXT_IOCTL)) + +#define EXT_CC_DRIVER_PROP_OS _IOWR(QLMULTIPATH_MAGIC, 12 , sizeof(EXT_IOCTL)) + +#define EXT_CC_LOOPBACK_OS _IOWR(QLMULTIPATH_MAGIC, 20 , sizeof(EXT_IOCTL)) + + + +/* + * Overrides for Emacs so that we almost follow Linus's tabbing style. + * Emacs will notice this stuff at the end of the file and automatically + * adjust the settings for this buffer only. This must remain at the end + * of the file. + * --------------------------------------------------------------------------- + * Local variables: + * c-indent-level: 2 + * c-brace-imaginary-offset: 0 + * c-brace-offset: -2 + * c-argdecl-indent: 2 + * c-label-offset: -2 + * c-continued-statement-offset: 2 + * c-continued-brace-offset: 0 + * indent-tabs-mode: nil + * tab-width: 8 + * End: + */ diff -urN linux-2.4.10/drivers/scsi/qla2x00ioctl.c linux-2.4.10-lia/drivers/scsi/qla2x00ioctl.c --- linux-2.4.10/drivers/scsi/qla2x00ioctl.c Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/scsi/qla2x00ioctl.c Mon Jul 23 14:12:54 2001 @@ -0,0 +1,1179 @@ +/******************************************************************************** +* QLOGIC LINUX SOFTWARE +* +* QLogic QLA2x00 device driver for Linux 2.2.x and 2.4.x +* Copyright (C) 2000 Qlogic Corporation +* (www.qlogic.com) +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of the GNU General Public License as published by the +* Free Software Foundation; either version 2, or (at your option) any +* later version. +* +* This program is distributed in the hope that it will be useful, but +* WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +* General Public License for more details. +** +******************************************************************************/ +/**************************************************************************** +Revision History: + Rev. 1.3 Beta February 20, 2001 BN QLogic + - Zero the sp used for IOCTL SCSI Passthru operations + Rev. 1.2 Beta January 31, 2001 BN QLogic + - Added setting of scsi completion to pext->DetailStatus + and set pext->Status to EXT_STATUS_SCSI_STATUS. + - Added details to Statistics IOCTL for ispaborts, + lip_count, isr_count. + + Rev. 1.2 Beta January 8, 2001 BN QLogic + - Added loop-back diagnostic IOCTL support. + + Rev. 1.1 Beta October 27, 2000 BN QLogic + - Updated return status from ioctl function. + + Rev. 1.0 Beta October 20, 2000 BN QLogic + - Initial version check in + + +*/ + +void copy_up_EXT( PEXT_IOCTL pext, void *arg) { +uint32_t i; +uint8_t *usr_temp, *kernel_tmp; + + /* copy up the EXT_IOCTL to application (api library) */ + for (i=0 ; i < sizeof(EXT_IOCTL) ; i++) { + usr_temp = (uint8_t *)arg + i; + kernel_tmp = (uint8_t *)pext + i; + __put_user(*kernel_tmp, usr_temp); + } + + return; +} + + +/************************************************************************* + * ioctl_scsi_pt_done + * + * Description: + * Sets completion flag. + * + * Returns: + *************************************************************************/ +void ioctl_scsi_pt_done(Scsi_Cmnd *pscsi_cmd) { + struct Scsi_Host *host; + scsi_qla_host_t *ha; + + host = pscsi_cmd->host; + ha = (scsi_qla_host_t *) host->hostdata; + + ha->IoctlPassThru_InProgress = 0; + return; +} + + +/************************************************************************* + * ioctl_fcct_done + * + * Description: + * Sets completion flag. + * + * Returns: + *************************************************************************/ +void ioctl_fcct_done(Scsi_Cmnd *pscsi_cmd) { + struct Scsi_Host *host; + scsi_qla_host_t *ha; + + host = pscsi_cmd->host; + ha = (scsi_qla_host_t *) host->hostdata; + /* printk("ioctl_fcct_done post function called OK\n"); */ + DEBUG(sprintf(debug_buff,"ioctl_fcct_done post function called OK\n")); + DEBUG(qla2100_print(debug_buff)); + ha->IoctlPassFCCT_InProgress = 0; + return; +} + + +/************************************************************************* + * qla2100_ioctl + * + * Description: + * Performs ioctl requests not satified by the upper levels. + * + * Returns: + * ret = 0 Success + * ret != 0 Failed; detailed status copied to EXT_IOCTL structure + * if applicable + *************************************************************************/ +int +qla2100_ioctl(Scsi_Device *dev, int cmd, void *arg){ + + static EXT_IOCTL ext; + PEXT_IOCTL pext = &ext; + struct Scsi_Host *host; + scsi_qla_host_t *ha, *search_ha; + scsi_lu_t *q; +#if BITS_PER_LONG <= 32 + uint32_t handle; +#else + uint64_t handle; +#endif + uint32_t cnt, i, b, t, l, port_cnt, status; + uint32_t tgt_cnt, tgt, transfer_size, inst; + uint8_t *extptr, *usrsrc, *usr_temp, *kernel_tmp, *kernel_tmp1; + static Scsi_Cmnd scsi_cmd; + Scsi_Cmnd *pscsi_cmd = &scsi_cmd; + static Scsi_Device scsi_device; + static srb_t ioctl_sp; + srb_t *sp = &ioctl_sp; + static EXT_SCSI_PASSTHRU scsi_pass; + EXT_SCSI_PASSTHRU *pscsi_pass = &scsi_pass; + static EXT_HBA_NODE tmp_hba_node; + static EXT_HBA_PORT tmp_hba_port; + static EXT_DISC_PORT tmp_disc_port; + static EXT_DISC_TARGET tmp_disc_target; + static EXT_CHIP tmp_isp; + static EXT_HBA_PORT_STAT tmp_stat; + uint16_t mb[MAILBOX_REGISTER_COUNT]; + unsigned long cpu_flags = 0; + uint16_t scratch; + uint16_t *wptr = &scratch; + qla_boards_t *bdp; + uint8_t *temp; + uint8_t tempbuf[8]; + cmd_ms_iocb_entry_t *pkt; + + int ret = EINVAL; + + BZERO((caddr_t)sp,sizeof(srb_t)); + + host = dev->host; + ha = (scsi_qla_host_t *) host->hostdata; /* midlayer chosen instance */ + + ret = verify_area(VERIFY_READ, (void *)arg, sizeof(EXT_IOCTL)); + if (ret) { + DEBUG2(printk("[qla2100_ioctl: ERROR in verify_area READ ha=%8x]\n",(uint32_t)ha);) + return(ret); + } + /* copy in application layer EXT_IOCTL */ + for (i=0 ; i < sizeof(EXT_IOCTL) ; i++) { + usrsrc = (uint8_t *)(arg + i); + extptr = (uint8_t *)pext + i; + __get_user(*extptr, usrsrc); + } + + /* printk("[GOT QLA2100 IOCTL sig=%s cmd=%x]\n", + (char *)&pext->Signature,cmd); */ + + /* check signature of this ioctl */ + temp = (uint8_t *) &pext->Signature; +#if BITS_PER_LONG <= 32 +for (i=0 ; i<4 ; i++,temp++) tempbuf[i] = *temp; + if( (tempbuf[0] == 'Q') && (tempbuf[1] == 'L') && + (tempbuf[2] == 'O') && (tempbuf[3] == 'G')) status = 0; + else status = 1; +#else + if( (tempbuf[0] == 'Q') && (tempbuf[1] == 'L') && + (tempbuf[2] == 'O') && (tempbuf[3] == 'G') && + (tempbuf[4] == 'I') && (tempbuf[5] == 'C')) status = 0; + else status = 1; +#endif + if ( status != 0) { + DEBUG2(printk("[GOT QLA2100 IOCTL but signature did not match ha=%8x]\n", + (uint32_t)ha);) + ret = EXT_STATUS_ERR; + return(ret); + } + /* check version of this ioctl */ + if (pext->Version != EXT_VERSION) { + pext->Status = EXT_STATUS_ERR; + pext->DetailStatus = EXT_STATUS_INVALID_PARAM; + copy_up_EXT(pext,arg); + printk(KERN_WARNING "qla2x00: GOT QLA2100 IOCTL but version did not match.\n"); + ret = EXT_STATUS_ERR; + return(ret); + } + /* check for API setting HBA Instance for subsequent operations */ + if (cmd == (int)EXT_CC_SETINSTANCE) { + /* since API opens devices once and uses handle for subsequent calls */ + /* we keep a parameter to designate the "active HBA" for ioctls */ + if (pext->HbaSelect < num_hosts) { + apiHBAInstance = pext->HbaSelect; + pext->Status = EXT_STATUS_OK; + pext->DetailStatus = EXT_STATUS_OK; + copy_up_EXT(pext,arg); + ret = EXT_STATUS_OK; + } else { + pext->Status = EXT_STATUS_ERR; + pext->DetailStatus = EXT_STATUS_INVALID_PARAM; + copy_up_EXT(pext,arg); + DEBUG2(printk("[qla2100_ioctl: ERROR in EXT_SETINSTANCE ha=%8x]\n",(uint32_t)ha);) + ret = EXT_STATUS_ERR; + } + return(ret); /* Instance for subsequent IOCTLs are not set */ + } + + /* check for valid apiHBAInstance (set previously by EXT_SETINSTANCE + or default 0) and set ha context for this IOCTL */ + for (search_ha=qla2100_hostlist; + (search_ha != NULL) && search_ha->instance != apiHBAInstance; + search_ha = search_ha->next) ; + if ( !search_ha ) { + pext->Status = EXT_STATUS_ERR; + pext->DetailStatus = EXT_STATUS_INVALID_PARAM; + copy_up_EXT(pext,arg); + DEBUG2(printk("[qla2100_ioctl: ERROR in matching apiHBAInstance to an HBA Instance]\n");) + ret = EXT_STATUS_ERR; + return(ret); + } + /* IOCTL ha context is ready to be set from apiHBAInstance */ + ha = search_ha; + /* set EXT_IOCTL.HbaSelect for reference by IOCTL caller */ + pext->HbaSelect = apiHBAInstance; + + switch (cmd) { /* switch on EXT IOCTL COMMAND CODE */ + case EXT_CC_STARTIOCTL: + pext->Instance = num_hosts; + pext->Status = EXT_STATUS_OK; + pext->DetailStatus = EXT_STATUS_OK; + copy_up_EXT(pext,arg); + /*printk("[QLA2100 EXT_STARTIOCTL did OK ]\n");*/ + ret = EXT_STATUS_OK; + break; + case EXT_CC_QUERY: + /* All Query type ioctls are done here */ + switch(pext->SubCode) { + case EXT_SC_QUERY_HBA_NODE: + /* fill all available HBA NODE Information */ + bdp = &QLBoardTbl_fc[ha->devnum]; + for (i=0; i < 8 ;i++) tmp_hba_node.WWNN[i] = ha->node_name[i]; + sprintf((char *)(tmp_hba_node.Manufacturer),"Qlogic Corp."); + sprintf((char *)(tmp_hba_node.Model),(char *)&bdp->bdName[0]); + tmp_hba_node.SerialNum[0] = ha->node_name[5]; + tmp_hba_node.SerialNum[1] = ha->node_name[6]; + tmp_hba_node.SerialNum[2] = ha->node_name[7]; + sprintf((char *)(tmp_hba_node.DriverVersion),QLA2100_VERSION); + sprintf((char *)(tmp_hba_node.FWVersion),"%2d.%02d.%02d", + bdp->fwver[0], bdp->fwver[1], bdp->fwver[2]); + /* tmp_hba_node.NvramVersion = ha->nvram_version; */ + sprintf((char *)(tmp_hba_node.OptRomVersion),"0"); + tmp_hba_node.InterfaceType = EXT_DEF_FC_INTF_TYPE; + tmp_hba_node.PortCount = 1; + + ret = verify_area(VERIFY_WRITE, (void *)pext->ResponseAdr, + sizeof(EXT_HBA_NODE)); + if (ret) { + pext->Status = EXT_STATUS_ERR; + pext->DetailStatus = EXT_STATUS_COPY_ERR; + copy_up_EXT(pext,arg); + DEBUG2(printk("[qla2100_ioctl: ERROR verify_area WRITE ha=%8x]\n",(uint32_t)ha);) + return(ret); + } + /* now copy up the HBA_NODE to user */ + if (pext->ResponseLen < sizeof(EXT_HBA_NODE)) transfer_size = pext->ResponseLen; + else transfer_size = sizeof(EXT_HBA_NODE); + for (i=0 ; i < transfer_size ; i++) { + usr_temp = (uint8_t *)pext->ResponseAdr + i; + kernel_tmp = (uint8_t *)&tmp_hba_node + i; + __put_user(*kernel_tmp, usr_temp); + } + /*printk("[finished QLA2100 IOCTL QUERY_HBA_NODE ]\n"); */ + pext->Status = EXT_STATUS_OK; + pext->DetailStatus = EXT_STATUS_OK; + copy_up_EXT(pext,arg); + ret = EXT_STATUS_OK; + break; + case EXT_SC_QUERY_HBA_PORT: + /* reflect all HBA PORT related info */ + tmp_hba_port.WWPN[7] = ha->init_cb->port_name[7]; + tmp_hba_port.WWPN[6] = ha->init_cb->port_name[6]; + tmp_hba_port.WWPN[5] = ha->init_cb->port_name[5]; + tmp_hba_port.WWPN[4] = ha->init_cb->port_name[4]; + tmp_hba_port.WWPN[3] = ha->init_cb->port_name[3]; + tmp_hba_port.WWPN[2] = ha->init_cb->port_name[2]; + tmp_hba_port.WWPN[1] = ha->init_cb->port_name[1]; + tmp_hba_port.WWPN[0] = ha->init_cb->port_name[0]; + tmp_hba_port.Id[1] = ha->port_id[0]; + tmp_hba_port.Id[2] = ha->port_id[1]; + tmp_hba_port.Id[3] = ha->port_id[2]; + tmp_hba_port.Type = EXT_DEF_INITIATOR_DEV; + + port_cnt = 0; + tgt_cnt = 0; + for (tgt = 0; tgt < MAX_FIBRE_DEVICES ; tgt++) { + if (ha->fc_db[tgt].loop_id > LAST_SNS_LOOP_ID) + continue; + port_cnt++; + + /* at this point the linux driver does not differentiate */ + /* Initiator devices (ie HBAs) from Targets; so the count */ + /* is same for both */ + /* if (ha->fc_db[tgt] & FC_INITIATOR_DEVICE) + continue; */ + tgt_cnt++; + } + tmp_hba_port.DiscPortCount = port_cnt; + tmp_hba_port.DiscTargetCount = tgt_cnt; + + if ( ha->loop_down_timer == 0 && ha->loop_state == LOOP_DOWN) { + tmp_hba_port.State = EXT_DEF_HBA_LOOP_DOWN; + } else tmp_hba_port.State = EXT_DEF_HBA_OK; + tmp_hba_port.DiscPortNameType = EXT_DEF_USE_PORT_NAME; + + ret = verify_area(VERIFY_WRITE, (void *)pext->ResponseAdr , + sizeof(EXT_HBA_PORT)); + if (ret) { + pext->Status = EXT_STATUS_ERR; + pext->DetailStatus = EXT_STATUS_COPY_ERR; + copy_up_EXT(pext,arg); + DEBUG2(printk("[qla2100_ioctl: ERROR verify_area WRITE ha=%8x]\n",(uint32_t)ha);) + return(ret); + } + /* now copy up the HBA_PORT to user */ + if (pext->ResponseLen < sizeof(EXT_HBA_PORT)) transfer_size = pext->ResponseLen; + else transfer_size = sizeof(EXT_HBA_PORT); + for (i=0 ; i < transfer_size ; i++) { + usr_temp = (uint8_t *)pext->ResponseAdr + i; + kernel_tmp = (uint8_t *)&tmp_hba_port + i; + __put_user(*kernel_tmp, usr_temp); + } + /*printk("[finished QLA2100 IOCTL QUERY_HBA_PORT ports=%x tgts=%x]\n",port_cnt,tgt_cnt); */ + pext->Status = EXT_STATUS_OK; + pext->DetailStatus = EXT_STATUS_OK; + copy_up_EXT(pext,arg); + ret = EXT_STATUS_OK; + break; + case EXT_SC_QUERY_DISC_PORT: + for (tgt=0, inst=0; tgt < MAX_FIBRE_DEVICES; tgt++) { + if (ha->fc_db[tgt].loop_id > LAST_SNS_LOOP_ID) + continue; + if( inst != pext->Instance ) { + inst++; + continue; + } + break; + } + if (tgt == MAX_FIBRE_DEVICES) { + pext->Status = ret = EXT_STATUS_ERR; + pext->DetailStatus = EXT_STATUS_DEV_NOT_FOUND; + copy_up_EXT(pext,arg); + return(ret); + } + + tmp_disc_port.WWNN[0] = ha->fc_db[tgt].name[0]; + tmp_disc_port.WWNN[1] = ha->fc_db[tgt].name[1]; + tmp_disc_port.WWNN[2] = ha->fc_db[tgt].name[2]; + tmp_disc_port.WWNN[3] = ha->fc_db[tgt].name[3]; + + tmp_disc_port.WWNN[4] = ha->fc_db[tgt].name[4]; + tmp_disc_port.WWNN[5] = ha->fc_db[tgt].name[5]; + tmp_disc_port.WWNN[6] = ha->fc_db[tgt].name[6]; + tmp_disc_port.WWNN[7] = ha->fc_db[tgt].name[7]; + + tmp_disc_port.WWPN[0] = ha->fc_db[tgt].wwn[0]; + tmp_disc_port.WWPN[1] = ha->fc_db[tgt].wwn[1]; + tmp_disc_port.WWPN[2] = ha->fc_db[tgt].wwn[2]; + tmp_disc_port.WWPN[3] = ha->fc_db[tgt].wwn[3]; + + tmp_disc_port.WWPN[4] = ha->fc_db[tgt].wwn[4]; + tmp_disc_port.WWPN[5] = ha->fc_db[tgt].wwn[5]; + tmp_disc_port.WWPN[6] = ha->fc_db[tgt].wwn[6]; + tmp_disc_port.WWPN[7] = ha->fc_db[tgt].wwn[7]; + + tmp_disc_port.Id[1] = ha->fc_db[tgt].port_id[0]; + tmp_disc_port.Id[2] = ha->fc_db[tgt].port_id[1]; + tmp_disc_port.Id[3] = ha->fc_db[tgt].port_id[2]; + tmp_disc_port.Type = EXT_DEF_TARGET_DEV; + + tmp_disc_port.Status = EXT_STATUS_OK; + tmp_disc_port.Bus = 0; + tmp_disc_port.TargetId = tgt; + + ret = verify_area(VERIFY_WRITE, (void *)pext->ResponseAdr , + sizeof(EXT_DISC_PORT)); + if (ret) { + pext->Status = EXT_STATUS_ERR; + pext->DetailStatus = EXT_STATUS_COPY_ERR; + copy_up_EXT(pext,arg); + DEBUG2(printk("[qla2100_ioctl: ERROR verify_area WRITE ha=%8x]\n",(uint32_t)ha);) + return(ret); + } + + /* now copy up the DISC_PORT to user */ + if (pext->ResponseLen < sizeof(EXT_DISC_PORT)) transfer_size = pext->ResponseLen; + else transfer_size = sizeof(EXT_DISC_PORT); + for (i=0 ; i < transfer_size ; i++) { + usr_temp = (uint8_t *)pext->ResponseAdr + i; + kernel_tmp = (uint8_t *)&tmp_disc_port + i; + __put_user(*kernel_tmp, usr_temp); + } + /*printk("[finished QLA2100 IOCTL QUERY_DISC_PORT ]\n"); */ + pext->Status = EXT_STATUS_OK; + pext->DetailStatus = EXT_STATUS_OK; + copy_up_EXT(pext,arg); + ret = EXT_STATUS_OK; + break; + case EXT_SC_QUERY_DISC_TGT: + /* (for multipath merge) to do: search the ha->tgt[][] data base + instead of ha->fc_db[] so that we give details on Targets that + are visible to the OS. */ + for (tgt=0, inst=0; tgt < MAX_FIBRE_DEVICES; tgt++) { + if (ha->fc_db[tgt].loop_id > LAST_SNS_LOOP_ID) + continue; + if( inst != pext->Instance ) { + inst++; + continue; + } + break; + } + if (tgt == MAX_FIBRE_DEVICES) { + pext->Status = ret = EXT_STATUS_ERR; + pext->DetailStatus = EXT_STATUS_DEV_NOT_FOUND; + copy_up_EXT(pext,arg); + return(ret); + } + tmp_disc_target.WWNN[0]= ha->fc_db[tgt].name[0]; + tmp_disc_target.WWNN[1]= ha->fc_db[tgt].name[1]; + tmp_disc_target.WWNN[2]= ha->fc_db[tgt].name[2]; + tmp_disc_target.WWNN[3]= ha->fc_db[tgt].name[3]; + + tmp_disc_target.WWNN[4]= ha->fc_db[tgt].name[4]; + tmp_disc_target.WWNN[5]= ha->fc_db[tgt].name[5]; + tmp_disc_target.WWNN[6]= ha->fc_db[tgt].name[6]; + tmp_disc_target.WWNN[7]= ha->fc_db[tgt].name[7]; + + + tmp_disc_target.WWPN[0]= ha->fc_db[tgt].wwn[0]; + tmp_disc_target.WWPN[1]= ha->fc_db[tgt].wwn[1]; + tmp_disc_target.WWPN[2]= ha->fc_db[tgt].wwn[2]; + tmp_disc_target.WWPN[3]= ha->fc_db[tgt].wwn[3]; + + tmp_disc_target.WWPN[4]= ha->fc_db[tgt].wwn[4]; + tmp_disc_target.WWPN[5]= ha->fc_db[tgt].wwn[5]; + tmp_disc_target.WWPN[6]= ha->fc_db[tgt].wwn[6]; + tmp_disc_target.WWPN[7]= ha->fc_db[tgt].wwn[7]; + tmp_disc_target.Id[1] = ha->fc_db[tgt].port_id[0]; + tmp_disc_target.Id[2] = ha->fc_db[tgt].port_id[1]; + tmp_disc_target.Id[3] = ha->fc_db[tgt].port_id[2]; + tmp_disc_target.Type = EXT_DEF_TARGET_DEV; + + tmp_disc_target.Status = EXT_STATUS_OK; + tmp_disc_target.Bus = 0; + tmp_disc_target.TargetId = tgt; + + cnt = 0; + for (i=0; i < MAX_LUNS ; i++) { + if ((ha->tgt[0][tgt])->luns[i] !=0) + cnt++; + } + tmp_disc_target.LunCount = cnt; + + ret = verify_area(VERIFY_WRITE, (void *)pext->ResponseAdr , + sizeof(EXT_DISC_TARGET)); + if (ret) { + pext->Status = EXT_STATUS_ERR; + pext->DetailStatus = EXT_STATUS_COPY_ERR; + copy_up_EXT(pext,arg); + DEBUG2(printk("[qla2100_ioctl: ERROR verify_area WRITE ha=%8x]\n",(uint32_t)ha);) + return(ret); + } + /* now copy up the DISC_TGT to user */ + if (pext->ResponseLen < sizeof(EXT_DISC_PORT)) transfer_size = pext->ResponseLen; + else transfer_size = sizeof(EXT_DISC_TARGET); + for (i=0 ; i < transfer_size ; i++) { + usr_temp = (uint8_t *)pext->ResponseAdr + i; + kernel_tmp = (uint8_t *)&tmp_disc_target + i; + __put_user(*kernel_tmp, usr_temp); + } + /* printk("[finished QLA2100 IOCTL QUERY_DISC_TGT Luns=%x pid0=%x pid1=%x pid2=%x]\n",cnt,ha->fc_db[tgt].port_id[0],ha->fc_db[tgt].port_id[1],ha->fc_db[tgt].port_id[2]);*/ + + pext->Status = EXT_STATUS_OK; + pext->DetailStatus = EXT_STATUS_OK; + copy_up_EXT(pext,arg); + ret = EXT_STATUS_OK; + break; + case EXT_SC_QUERY_CHIP: + host = ha->host; + tmp_isp.VendorId = QLA2100_VENDOR_ID; + tmp_isp.DeviceId = ha->device_id; + tmp_isp.SubVendorId = QLA2100_VENDOR_ID; + tmp_isp.SubSystemId = 0; + tmp_isp.PciBusNumber = ha->pci_bus; + tmp_isp.PciSlotNumber = (ha->pci_device_fn & 0xf8) >> 3; + tmp_isp.IoAddr = host->io_port; + tmp_isp.IoAddrLen = 512; + tmp_isp.MemAddr = 0; + tmp_isp.MemAddrLen = 0; + tmp_isp.ChipType = 0; + tmp_isp.InterruptLevel = host->irq; + for (i=0;i<8;i++) tmp_isp.OutMbx[i] = 0; + + ret = verify_area(VERIFY_WRITE, (void *)pext->ResponseAdr , + sizeof(EXT_CHIP)); + if (ret) { + pext->Status = EXT_STATUS_ERR; + pext->DetailStatus = EXT_STATUS_COPY_ERR; + copy_up_EXT(pext,arg); + DEBUG2(printk("[qla2100_ioctl: ERROR verify_area WRITE ha=%8x]\n",(uint32_t)ha);) + return(ret); + } + /* now copy up the ISP to user */ + if (pext->ResponseLen < sizeof(EXT_CHIP)) transfer_size = pext->ResponseLen; + else transfer_size = sizeof(EXT_CHIP); + for (i=0 ; i < transfer_size ; i++) { + usr_temp = (uint8_t *)pext->ResponseAdr + i; + kernel_tmp = (uint8_t *)&tmp_isp + i; + __put_user(*kernel_tmp, usr_temp); + } + /* printk("[finished QLA2100 IOCTL QUERY_CHIP]\n"); */ + pext->Status = EXT_STATUS_OK; + pext->DetailStatus = EXT_STATUS_OK; + copy_up_EXT(pext,arg); + ret = EXT_STATUS_OK; + break; + + case EXT_SC_QUERY_DISC_LUN: + pext->Status = EXT_STATUS_OK; + pext->DetailStatus = EXT_STATUS_OK; + copy_up_EXT(pext,arg); + ret = EXT_STATUS_OK; + break; + default: + ret = EXT_STATUS_ERR; + break; + } + break; + case EXT_CC_GET_DATA: + switch(pext->SubCode) { + case EXT_SC_GET_STATISTICS: + + tmp_stat.ControllerErrorCount = ha->isp_aborts; + tmp_stat.DeviceErrorCount = 0; + tmp_stat.TotalIoCount = ha->qthreads; + tmp_stat.TotalMBytes = 0; + tmp_stat.TotalLipResets = ha->lip_count; + tmp_stat.TotalInterrupts = ha->isr_count; + + ret = verify_area(VERIFY_WRITE, (void *)pext->ResponseAdr, + sizeof(EXT_HBA_PORT_STAT)); + if (ret) { + pext->Status = EXT_STATUS_ERR; + pext->DetailStatus = EXT_STATUS_COPY_ERR; + copy_up_EXT(pext,arg); + DEBUG2(printk("[qla2100_ioctl: ERROR verify_area WRITE ha=%8x]\n",(uint32_t)ha);) + return(ret); + } + /* now copy up the STATISTICS to user */ + if (pext->ResponseLen < sizeof(EXT_HBA_PORT_STAT)) transfer_size = pext->ResponseLen; + else transfer_size = sizeof(EXT_HBA_PORT_STAT); + for (i=0 ; i < transfer_size ; i++) { + usr_temp = (uint8_t *)pext->ResponseAdr + i; + kernel_tmp = (uint8_t *)&tmp_stat + i; + __put_user(*kernel_tmp, usr_temp); + } + /*printk("[finished QLA2100 IOCTL STATISTICS ]\n");*/ + pext->Status = EXT_STATUS_OK; + pext->DetailStatus = EXT_STATUS_OK; + copy_up_EXT(pext,arg); + ret = EXT_STATUS_OK; + break; + default: + break; + } + break; + case EXT_CC_SEND_FCCT_PASSTHRU: + DEBUG(sprintf(debug_buff,"qla2100_ioctl: start EXT_CC_SEND_FCCT_PASSTHRU\n")); + DEBUG(qla2100_print(debug_buff)); + /* Management Server type (fc switch) pass thru ioctl */ + /* same as EXT_FCSCSI_REQ but it is going to the FC switch */ + /* clear ioctl_sp and scsi_cmd to be used */ + kernel_tmp = (uint8_t *)sp; + for (i=0;iioctl_mem; + for (i=0;iResponseLen > PAGE_SIZE) pext->ResponseLen = PAGE_SIZE; + if (pext->RequestLen > PAGE_SIZE) { + pext->Status = EXT_STATUS_ERR; + pext->DetailStatus = EXT_STATUS_INVALID_PARAM; + copy_up_EXT(pext,arg); + /*printk("[EXT_CC_SEND_FCCT_PASSTHRU too big ResponseLen=%x ReqLen=%x]\n",pext->ResponseLen,pext->RequestLen); */ + DEBUG2(printk("[qla2100_ioctl: ERROR size of requested Resp_len in EXT_CC_SEND_FCCT_PASSTHRU]\n");) + return(ret); + } + ret = verify_area(VERIFY_READ, (void *)pext->RequestAdr, + pext->RequestLen); + if (ret){ + pext->Status = EXT_STATUS_ERR; + pext->DetailStatus = EXT_STATUS_COPY_ERR; + copy_up_EXT(pext,arg); + /*printk("[EXT_CC_SEND_FCCT_PASSTHRU verify read error]\n");*/ + DEBUG2(printk("[qla2100_ioctl: ERROR verify_area READ of EXT_CC_SEND_FCCT_PASSTHRU]\n");) + return(ret); + } + for (i=0 ; i < pext->RequestLen ; i++) { + /* copy in from user space the fcct command to be sent */ + usr_temp = (uint8_t *)pext->RequestAdr + i; + kernel_tmp = (uint8_t *)ha->ioctl_mem + i; + __get_user(*kernel_tmp, usr_temp); + /* printk("{%x}",*kernel_tmp); */ + } + /* check on current topology or loop down */ + if ((ha->current_topology != ISP_CFG_F) && + (ha->current_topology != ISP_CFG_FL ) ) { + pext->Status = EXT_STATUS_ERR; + pext->DetailStatus = EXT_STATUS_DEV_NOT_FOUND; + copy_up_EXT(pext,arg); + /*printk("[EXT_CC_SEND_FCCT_PASSTHRU wrong topology current=%x]\n", + ha->current_topology); */ + DEBUG2(printk("[qla2100_ioctl: ERROR EXT_CC_SEND_FCCT_PASSTHRU not in F-Port or FL-Port mode]\n");) + return(ret); + } + /* check on loop down */ + if ( ha->loop_down_timer == 0 && ha->loop_state == LOOP_DOWN) { + pext->Status = EXT_STATUS_ERR; + pext->DetailStatus = EXT_STATUS_DEV_NOT_FOUND; + copy_up_EXT(pext,arg); + /* printk("[EXT_CC_SEND_FCCT_PASSTHRU loop down]\n"); */ + DEBUG2(printk("[qla2100_ioctl: ERROR EXT_CC_SEND_FCCT_PASSTHRU not in F-Port mode]\n");) + return(ret); + } + /* login to management server device */ + if (ha->flags.managment_server_logged_in == 0) { + mb[0] = MBC_LOGIN_FABRIC_PORT; + mb[1] = MANAGEMENT_SERVER << 8; + mb[2] = 0xff; + mb[3] = 0xfffa; + + ret = qla2100_mailbox_command(ha, BIT_3|BIT_2|BIT_1|BIT_0, + &mb[0]); + if ( (ret != 0) || (mb[0] == 0x4006) || + (mb[0] == 0x4009) || (mb[0] != 0x4000) ) { + pext->Status = EXT_STATUS_ERR; + pext->DetailStatus = EXT_STATUS_DEV_NOT_FOUND; + copy_up_EXT(pext,arg); + /* printk("[EXT_CC_SEND_FCCT_PASSTHRU could not login to sns]\n"); */ + DEBUG2(printk("[qla2100_ioctl: ERROR could not login to Management Server]\n");) + DEBUG(sprintf(debug_buff,"FCCT ioctl: call qla2100_ms_req_pkt\n")); + DEBUG(qla2100_print(debug_buff)); + return(ret); + } + ha->flags.managment_server_logged_in = 1; + } + + /* setup sp for this FCCT pass thru */ + pscsi_cmd->host = ha->host; + sp->cmd = pscsi_cmd; + sp->flags = SRB_WATCHDOG; + + /* mark this as a special delivery and collection command */ + scsi_cmd.flags = 0; + scsi_cmd.scsi_done = ioctl_fcct_done; + + DEBUG(sprintf(debug_buff,"FCCT ioctl: FABRIC_LOGIN OK, call qla2100_ms_req_pkt\n")); + DEBUG(qla2100_print(debug_buff)); + + /* get spin lock for this operation */ + spin_lock_irqsave(&io_request_lock, cpu_flags); + + /* Get MS request packet. */ + if( (pkt = (cmd_ms_iocb_entry_t *)qla2100_ms_req_pkt(ha, sp) ) ) { + pkt->entry_type = MS_IOCB_TYPE; + pkt->entry_count = 1; + pkt->loop_id = MANAGEMENT_SERVER; + pkt->timeout = 4; + pkt->DSDcount = 1; + pkt->RespDSDcount = 2; + pkt->Response_bytecount = pext->ResponseLen; + pkt->Request_bytecount = pext->RequestLen; + + /* loading command payload address */ + pkt->dseg_req_address[0] = LS_64BITS(ha->ioctl_mem_phys); + pkt->dseg_req_address[1] = MS_64BITS(ha->ioctl_mem_phys); + pkt->dseg_req_length = pext->RequestLen; + + /* loading command response address */ + pkt->dseg_rsp_address[0] = LS_64BITS(ha->ioctl_mem_phys); + pkt->dseg_rsp_address[1] = MS_64BITS(ha->ioctl_mem_phys); + pkt->dseg_rsp_length = pext->ResponseLen; + + /* set flag to indicate IOCTL FCCT PassThru in progress */ + ha->IoctlPassFCCT_InProgress = 1; + + ha->ioctl_timer = 6; /* 6 ticks of 1 second timer max wait */ + + /* Issue command to ISP */ + qla2100_isp_cmd(ha); + } + /* release spin lock since command is issued */ + spin_unlock_irqrestore(&io_request_lock, cpu_flags); + + DEBUG(sprintf(debug_buff, + "FCCT ioctl: Command issued and released spin lock\n")); + DEBUG(qla2100_print(debug_buff)); + + if (!pkt) { + pext->Status = EXT_STATUS_ERR; + pext->DetailStatus = EXT_STATUS_DEV_NOT_FOUND; + copy_up_EXT(pext,arg); + /* printk("[EXT_CC_SEND_FCCT_PASSTHRU could not get Request Packet]\n"); */ + DEBUG2(printk("[qla2100_ioctl:EXT_CC_SEND_FCCT_PASSTHRU could not get Request Packet]\n");) + return(ret); + } + + /* wait for post function or timer to zero the InProgress flag */ + while (ha->IoctlPassFCCT_InProgress == 1) { + udelay(35); + } + + DEBUG(sprintf(debug_buff, + "FCCT ioctl: finished while(InProgress) wait loop \n")); + DEBUG(qla2100_print(debug_buff)); + /* printk("[FCCT IOCTL finished while(InProgress) wait loop ]\n");*/ + + if (ha->IoctlPassFCCT_InProgress == 1) { + /* We waited and post function did not get called */ + DEBUG(printk("[FCCT IOCTL post function not called]\n");) + DEBUG(sprintf(debug_buff, + "FCCT ioctl: post function not called \n")); + DEBUG(qla2100_print(debug_buff)); + pext->Status = EXT_STATUS_ERR; + pext->DetailStatus = EXT_STATUS_DEV_NOT_FOUND; + copy_up_EXT(pext,arg); + ret = EXT_STATUS_ERR; + } else { + /* getting device data and putting in pext->ResponseAdr */ + /* printk("[post function called; start FCCT IOCTL returning up data ]\n");*/ + ret = verify_area(VERIFY_WRITE, (void *)pext->ResponseAdr , + pext->ResponseLen); + if (ret) { + pext->Status = EXT_STATUS_ERR; + pext->DetailStatus = EXT_STATUS_COPY_ERR; + copy_up_EXT(pext,arg); + DEBUG2(printk("[qla2100_ioctl: ERROR verify_area WRITE for IOCTL PT ha=%8x]\n", + (uint32_t)ha);) + return(ret); + } + /* sending back data returned from Management Server */ + for (i=0 ; i < pext->ResponseLen ; i++) { + usr_temp = (uint8_t *)pext->ResponseAdr + i; + kernel_tmp = (uint8_t *)ha->ioctl_mem + i; + /*printk("[%x]",*kernel_tmp);*/ + __put_user(*kernel_tmp, usr_temp); + } + /*printk("[finished QLA2100 IOCTL EXT_CC_SEND_FCCT_PASSTHRU]\n");*/ + pext->Status = EXT_STATUS_SCSI_STATUS; + pext->DetailStatus = sp->scode; + copy_up_EXT(pext,arg); + ret = EXT_STATUS_OK; + } + break; + + case EXT_CC_SEND_SCSI_PASSTHRU: + /* printk("[start EXT_CC_SEND_SCSI_PASSTHRU]\n"); */ + ret = verify_area(VERIFY_READ, (void *)pext->RequestAdr, + sizeof(EXT_SCSI_PASSTHRU)); + if (ret) { + pext->Status = EXT_STATUS_ERR; + pext->DetailStatus = EXT_STATUS_COPY_ERR; + copy_up_EXT(pext,arg); + DEBUG2(printk("[qla2100_ioctl: ERROR verify_area READ of EXT_SCSI_PASSTHRU]\n");) + return(ret); + } + for (i=0 ; i < sizeof(EXT_SCSI_PASSTHRU) ; i++) { + usr_temp = (uint8_t *)pext->RequestAdr + i; + kernel_tmp = (uint8_t *)pscsi_pass + i; + __get_user(*kernel_tmp, usr_temp); + } + if (pext->ResponseLen > PAGE_SIZE) { + pext->Status = EXT_STATUS_ERR; + pext->DetailStatus = EXT_STATUS_INVALID_PARAM; + copy_up_EXT(pext,arg); + DEBUG2(printk("[qla2100_ioctl: ERROR size of requested EXT_SCSI_PASSTHRU]\n");) + return(ret); + } + /* clear ioctl_sp and scsi_cmd and scsi_device to be used */ + kernel_tmp = (uint8_t *)sp; + for (i=0;iioctl_mem; + for (i=0;ihost = ha->host; + sp->cmd = pscsi_cmd; + sp->flags = SRB_WATCHDOG; + + /* mark this as a special delivery and collection command */ + scsi_cmd.flags = 0; + scsi_cmd.scsi_done = ioctl_scsi_pt_done; + + scsi_cmd.device = &scsi_device; + scsi_cmd.device->tagged_queue = 0; + scsi_cmd.use_sg = 0; /* no ScatterGather */ + scsi_cmd.target = pscsi_pass->TargetAddr.Target; + scsi_cmd.lun = pscsi_pass->TargetAddr.Lun; + scsi_cmd.request_bufflen = pext->ResponseLen; + scsi_cmd.request_buffer = ha->ioctl_mem; + scsi_cmd.timeout_per_command = 0x300; + + // printk("[start FCSCSI IOCTL look at direction t=%x l=%x]\n", + // scsi_cmd.target,scsi_cmd.lun); + if (pscsi_pass->Direction == EXT_DEF_SCSI_PASSTHRU_DATA_OUT) { + /* sending user data from pext->ResponseAdr to device */ + ret = verify_area(VERIFY_READ, (void *)pext->ResponseAdr, + pext->ResponseLen); + if (ret) { + pext->Status = EXT_STATUS_ERR; + pext->DetailStatus = EXT_STATUS_COPY_ERR; + copy_up_EXT(pext,arg); + DEBUG2(printk("[qla2100_ioctl: ERROR verify_area READ EXT_SCSI_PASSTHRU]\n");) + return(ret); + } + for (i=0 ; i < pext->ResponseLen ; i++) { + usr_temp = (uint8_t *)pext->ResponseAdr + i; + kernel_tmp = (uint8_t *)ha->ioctl_mem + i; + __get_user(*kernel_tmp, usr_temp); + } + } + if (pscsi_pass->CdbLength == 6) { + scsi_cmd.cmd_len = 6; + scsi_cmd.data_cmnd[0] = scsi_cmd.cmnd[0] = pscsi_pass->Cdb[0]; + scsi_cmd.data_cmnd[1] = scsi_cmd.cmnd[1] = pscsi_pass->Cdb[1]; + scsi_cmd.data_cmnd[2] = scsi_cmd.cmnd[2] = pscsi_pass->Cdb[2]; + scsi_cmd.data_cmnd[3] = scsi_cmd.cmnd[3] = pscsi_pass->Cdb[3]; + scsi_cmd.data_cmnd[4] = scsi_cmd.cmnd[4] = pscsi_pass->Cdb[4]; + scsi_cmd.data_cmnd[5] = scsi_cmd.cmnd[5] = pscsi_pass->Cdb[5]; + scsi_cmd.data_cmnd[6] = scsi_cmd.cmnd[6] = 0; + scsi_cmd.data_cmnd[7] = scsi_cmd.cmnd[7] = 0; + scsi_cmd.data_cmnd[8] = scsi_cmd.cmnd[8] = 0; + scsi_cmd.data_cmnd[9] = scsi_cmd.cmnd[9] = 0; + } else if (pscsi_pass->CdbLength == 10) { + scsi_cmd.cmd_len = 0x0A; + scsi_cmd.data_cmnd[0] = scsi_cmd.cmnd[0] = pscsi_pass->Cdb[0]; + scsi_cmd.data_cmnd[1] = scsi_cmd.cmnd[1] = pscsi_pass->Cdb[1]; + scsi_cmd.data_cmnd[2] = scsi_cmd.cmnd[2] = pscsi_pass->Cdb[2]; + scsi_cmd.data_cmnd[3] = scsi_cmd.cmnd[3] = pscsi_pass->Cdb[3]; + scsi_cmd.data_cmnd[4] = scsi_cmd.cmnd[4] = pscsi_pass->Cdb[4]; + scsi_cmd.data_cmnd[5] = scsi_cmd.cmnd[5] = pscsi_pass->Cdb[5]; + scsi_cmd.data_cmnd[6] = scsi_cmd.cmnd[6] = pscsi_pass->Cdb[6]; + scsi_cmd.data_cmnd[7] = scsi_cmd.cmnd[7] = pscsi_pass->Cdb[7]; + scsi_cmd.data_cmnd[8] = scsi_cmd.cmnd[8] = pscsi_pass->Cdb[8]; + scsi_cmd.data_cmnd[9] = scsi_cmd.cmnd[9] = pscsi_pass->Cdb[9]; + } else if (pscsi_pass->CdbLength == 12) { + scsi_cmd.cmd_len = 0x0C; + scsi_cmd.data_cmnd[0] = scsi_cmd.cmnd[0] = pscsi_pass->Cdb[0]; + scsi_cmd.data_cmnd[1] = scsi_cmd.cmnd[1] = pscsi_pass->Cdb[1]; + scsi_cmd.data_cmnd[2] = scsi_cmd.cmnd[2] = pscsi_pass->Cdb[2]; + scsi_cmd.data_cmnd[3] = scsi_cmd.cmnd[3] = pscsi_pass->Cdb[3]; + scsi_cmd.data_cmnd[4] = scsi_cmd.cmnd[4] = pscsi_pass->Cdb[4]; + scsi_cmd.data_cmnd[5] = scsi_cmd.cmnd[5] = pscsi_pass->Cdb[5]; + scsi_cmd.data_cmnd[6] = scsi_cmd.cmnd[6] = pscsi_pass->Cdb[6]; + scsi_cmd.data_cmnd[7] = scsi_cmd.cmnd[7] = pscsi_pass->Cdb[7]; + scsi_cmd.data_cmnd[8] = scsi_cmd.cmnd[8] = pscsi_pass->Cdb[8]; + scsi_cmd.data_cmnd[9] = scsi_cmd.cmnd[9] = pscsi_pass->Cdb[9]; + scsi_cmd.data_cmnd[10] = scsi_cmd.cmnd[10] = pscsi_pass->Cdb[10]; + scsi_cmd.data_cmnd[11] = scsi_cmd.cmnd[10] = pscsi_pass->Cdb[11]; + } + /* Generate LU queue on bus, target, LUN */ + b = SCSI_BUS_32(pscsi_cmd); + t = SCSI_TCN_32(pscsi_cmd); + l = SCSI_LUN_32(pscsi_cmd); + + /* set sp->target for 32bit/64bit delivery */ + sp->wdg_time = 0; + + /* check presense of requested target and other conditions */ + if( TGT_Q(ha,b,t) == NULL || + ( TGT_Q(ha,b,t) && TGT_Q(ha,b,t)->loop_id > LAST_SNS_LOOP_ID) || + ( ha->loop_down_timer == 0 && ha->loop_state == LOOP_DOWN)) { + printk(KERN_WARNING "qla2x00: FCSCSI IOCTL Target MISSING.\n"); + DEBUG2(printk("scsi(%2d:%2d:%2d:%2d): SCSI PT port unavailable\n", + (int)ha->host_no,b,t,l);) + pext->Status = EXT_STATUS_ERR; + pext->DetailStatus = EXT_STATUS_DEV_NOT_FOUND; + copy_up_EXT(pext,arg); + return(ret); + } + /* get spin lock for this operation */ + spin_lock_irqsave(&io_request_lock, cpu_flags); + + /* Allocate a LUN/DEVICE queue from this request */ + if( (q = GET_LU_Q(ha, b, t,l)) == NULL ) { + DRIVER_LOCK + if( (q = qla2100_lun_alloc()) == NULL ) { + pext->Status = EXT_STATUS_ERR; + pext->DetailStatus = EXT_STATUS_DEV_NOT_FOUND; + copy_up_EXT(pext,arg); + DEBUG2(printk("[qla2100_ioctl: ERROR in GET_LU_Q for SCSI_PASSTHRU ha=%8x]\n", + (uint32_t)ha);) + ret = EXT_STATUS_ERR; + return(ret); + } + LU_Q(ha, b, t, l) = q; + DEBUG(sprintf(debug_buff,"Allocate new device queue 0x%x\n",q)); + DEBUG(qla2100_print(debug_buff)); + DRIVER_UNLOCK + } + /* Set an invalid handle until we issue the command to ISP */ + /* then we will set the real handle value. */ + handle = INVALID_HANDLE; + CMD_HANDLE(pscsi_cmd) = (unsigned char *)handle; + + if( sp->flags ) { + sp->port_down_retry_count = ha->port_down_retry_count - 1; + sp->retry_count = ha->retry_count; + DEBUG3(sprintf(debug_buff,"qla2100: PT Set retry counts =0x%x,0x%x\n\r", + sp->port_down_retry_count,sp->retry_count)); + DEBUG3(qla2100_print(debug_buff)); + } + qla2100_putq_t(q,sp); + + /* set flag to indicate IOCTL SCSI PassThru in progress */ + ha->IoctlPassThru_InProgress = 1; + + //printk("[start FCSCSI IOCTL restart queues]\n"); + /* send command to adapter */ + qla2100_restart_queues(ha,FALSE); + + /* release spin lock since command is queued */ + spin_unlock_irqrestore(&io_request_lock, cpu_flags); + + ha->ioctl_timer = 6; /* 6 ticks of 1 second timer max wait */ + + /* wait for post function or timer to zero the InProgress flag */ + while (ha->IoctlPassThru_InProgress == 1) { + udelay(35); + } + + //printk("[start FCSCSI IOCTL finished while]\n"); + if (ha->IoctlPassThru_InProgress == 1) { + /* We waited and post function did not get called */ + DEBUG(printk("[FCSCSI IOCTL post function not called]\n");) + pext->Status = EXT_STATUS_ERR; + pext->DetailStatus = EXT_STATUS_DEV_NOT_FOUND; + copy_up_EXT(pext,arg); + ret = EXT_STATUS_ERR; + } else { + if (pscsi_pass->Direction == EXT_DEF_SCSI_PASSTHRU_DATA_IN) { + /* getting device data and putting in pext->ResponseAdr */ + ret = verify_area(VERIFY_WRITE, (void *)pext->ResponseAdr , + pext->ResponseLen); + if (ret) { + pext->Status = EXT_STATUS_ERR; + pext->DetailStatus = EXT_STATUS_COPY_ERR; + copy_up_EXT(pext,arg); + DEBUG2(printk("[qla2100_ioctl: ERROR verify_area WRITE for IOCTL PT ha=%8x]\n", + (uint32_t)ha);) + return(ret); + } + /* now copy up the READ data to user */ + for (i=0 ; i < pext->ResponseLen ; i++) { + usr_temp = (uint8_t *)pext->ResponseAdr + i; + kernel_tmp = (uint8_t *)ha->ioctl_mem + i; + /*printk("[%x]",*kernel_tmp);*/ + __put_user(*kernel_tmp, usr_temp); + } + } + //printk("[[sense0=%x sense2=%x]]\n", + //pscsi_cmd->sense_buffer[0], + //pscsi_cmd->sense_buffer[2]); + /* copy up structure to make sense data available to user */ + for (i=0;i<16;i++) + pscsi_pass->SenseData[i] = pscsi_cmd->sense_buffer[i]; + ret = verify_area(VERIFY_WRITE, (void *)pext->RequestAdr, + sizeof(EXT_SCSI_PASSTHRU)); + if (ret) { + pext->Status = EXT_STATUS_ERR; + pext->DetailStatus = EXT_STATUS_COPY_ERR; + copy_up_EXT(pext,arg); + DEBUG2(printk("[qla2100_ioctl: ERROR verify_area WRITE of EXT_SCSI_PASSTHRU]\n");) + return(ret); + } + for (i=0 ; i < sizeof(EXT_SCSI_PASSTHRU) ; i++) { + usr_temp = (uint8_t *)pext->RequestAdr + i; + kernel_tmp = (uint8_t *)pscsi_pass + i; + __put_user(*kernel_tmp, usr_temp); + } + /* printk("[finished QLA2100 IOCTL EXT_FCSCSI_REQ]\n"); */ + pext->Status = EXT_STATUS_SCSI_STATUS; + pext->DetailStatus = sp->scode; + copy_up_EXT(pext,arg); + ret = EXT_STATUS_OK; + } + break; + + case EXT_CC_READ_NVRAM: + if (pext->ResponseLen < sizeof(nvram21_t)) transfer_size = pext->ResponseLen; + else transfer_size = sizeof(nvram21_t)/2; + for( i = 0, cnt = 0; cnt < transfer_size ; cnt++ , i++ ) { + *wptr = qla2100_get_nvram_word(ha, cnt); + + usr_temp = (uint8_t *)pext->ResponseAdr; + kernel_tmp = (uint8_t *)wptr; + + usr_temp += i; /* even byte */ + __put_user(*kernel_tmp, usr_temp); + + i++; + usr_temp = (uint8_t *)pext->ResponseAdr; + kernel_tmp1 = (uint8_t *)wptr + 1; + usr_temp += i; /* odd byte */ + __put_user(*kernel_tmp1, usr_temp); + } + + /* printk("[finished QLA2100 IOCTL EXT_NVR_RD]\n"); */ + pext->Status = EXT_STATUS_OK; + pext->DetailStatus = EXT_STATUS_OK; + copy_up_EXT(pext,arg); + ret = EXT_STATUS_OK; + break; + + case EXT_CC_LOOPBACK: + DEBUG(sprintf(debug_buff,"qla2100_ioctl: start EXT_CC_LOOPBACK\n")); + DEBUG(qla2100_print(debug_buff)); + + /* printk("[start EXT_CC_LOOPBACK]\n"); */ + + if (ha->device_id == QLA2100_DEVICE_ID) { + pext->Status = EXT_STATUS_ERR; + pext->DetailStatus = EXT_STATUS_DEV_NOT_FOUND; + copy_up_EXT(pext,arg); + DEBUG2(printk("[EXT_CC_SEND_LOOP_BACK not supported on QLA2100]\n");) + return(ret); + } + + if (pext->ResponseLen > PAGE_SIZE) pext->ResponseLen = PAGE_SIZE; + if (pext->RequestLen > PAGE_SIZE) { + pext->Status = EXT_STATUS_ERR; + pext->DetailStatus = EXT_STATUS_INVALID_PARAM; + copy_up_EXT(pext,arg); + /*printk("[EXT_CC_LOOPBACK too big ResponseLen=%x ReqLen=%x]\n",pext->ResponseLen,pext->RequestLen); */ + DEBUG2(printk("[qla2100_ioctl: ERROR size of requested Resp_len in EXT_CC_SEND_LOOP_BACK]\n");) + return(ret); + } + ret = verify_area(VERIFY_READ, (void *)pext->RequestAdr, + pext->RequestLen); + if (ret){ + pext->Status = EXT_STATUS_ERR; + pext->DetailStatus = EXT_STATUS_COPY_ERR; + copy_up_EXT(pext,arg); + /*printk("[EXT_CC_LOOPBACK verify read error]\n");*/ + DEBUG2(printk("[qla2100_ioctl: ERROR verify_area READ of EXT_CC_LOOPBACK]\n");) + return(ret); + } + for (i=0 ; i < pext->ResponseLen ; i++) { + /* copy in from user space the user data pattern to be sent */ + usr_temp = (uint8_t *)pext->ResponseAdr + i; + kernel_tmp = (uint8_t *)ha->ioctl_mem + i; + __get_user(*kernel_tmp, usr_temp); + /* printk("{%x}",*kernel_tmp); */ + } + /* check on loop down */ + if ( ha->loop_down_timer == 0 && ha->loop_state == LOOP_DOWN) { + pext->Status = EXT_STATUS_ERR; + pext->DetailStatus = EXT_STATUS_DEV_NOT_FOUND; + copy_up_EXT(pext,arg); + /* printk("[EXT_CC_LOOPBACK loop down]\n"); */ + return(ret); + } + + /* get spin lock for this operation */ + spin_lock_irqsave(&io_request_lock, cpu_flags); + + mb[0] = MBC_DIAGNOSTIC_LOOP_BACK; + mb[1] = 0x72; /* options: 64 bit, use buffer for snd/rcv on ext. loop */ + mb[2] = mb[3] = mb[4] = mb[5] = mb[6] = mb[7] = mb[8] = mb[9] = 0; + mb[10] = LSW(pext->ResponseLen); + mb[11] = MSW(pext->ResponseLen); + mb[12] = 0; /* transfer segment count */ + mb[13] = 0; /* receive segment count */ + mb[14] = LSW(ha->ioctl_mem_phys); /* send data address */ + mb[15] = MSW(ha->ioctl_mem_phys); + mb[20] = QL21_64BITS_3RDWD(ha->ioctl_mem_phys); + mb[21] = QL21_64BITS_4THWD(ha->ioctl_mem_phys); + mb[16] = LSW(ha->ioctl_mem_phys); /* recv data address */ + mb[17] = MSW(ha->ioctl_mem_phys); + mb[6] = QL21_64BITS_3RDWD(ha->ioctl_mem_phys); + mb[7] = QL21_64BITS_4THWD(ha->ioctl_mem_phys); + mb[18] = 1; /* iteration count lsb */ + mb[19] = 0; /* iteration count msb */ + + DEBUG(sprintf(debug_buff, + "LoopBack ioctl: issue loop back mailbox command\n")); + DEBUG(qla2100_print(debug_buff)); + + // wait for 64 bit loopback ready firmware + status = qla2100_mailbox_command(ha,BIT_21|BIT_20|BIT_19|BIT_18| + BIT_17|BIT_16|BIT_15|BIT_14| + BIT_13|BIT_12|BIT_11| + BIT_10|BIT_7|BIT_6|BIT_1|BIT_0, + &mb[0]); + + /* release spin lock since command is issued */ + spin_unlock_irqrestore(&io_request_lock, cpu_flags); + + if (status) { + DEBUG(sprintf(debug_buff, + "LoopBack ioctl: issue loop back mailbox command FAILED\n")); + DEBUG(qla2100_print(debug_buff)); + pext->Status = EXT_STATUS_ERR; + pext->DetailStatus = EXT_STATUS_ERR; + copy_up_EXT(pext,arg); + ret = EXT_STATUS_ERR; + } else { + /* put looped back data in pext->ResponseAdr */ + /* printk("[LoopBack ioctl: LoopBack was OK ]\n");*/ + ret = verify_area(VERIFY_WRITE, (void *)pext->ResponseAdr , + pext->ResponseLen); + if (ret) { + pext->Status = EXT_STATUS_ERR; + pext->DetailStatus = EXT_STATUS_COPY_ERR; + copy_up_EXT(pext,arg); + DEBUG2(printk("[LoopBack ioctl: ERROR verify_area WRITE ha=%x]\n", + (uint32_t)ha);) + return(ret); + } + /* sending back looped back data */ + for (i=0 ; i < pext->ResponseLen ; i++) { + usr_temp = (uint8_t *)pext->ResponseAdr + i; + kernel_tmp = (uint8_t *)ha->ioctl_mem + i; + /*printk("[%x]",*kernel_tmp);*/ + __put_user(*kernel_tmp, usr_temp); + } + /*printk("[finished QLA2100 IOCTL EXT_CC_LOOPBACK]\n");*/ + pext->Status = EXT_STATUS_OK; + pext->DetailStatus = EXT_STATUS_OK; + copy_up_EXT(pext,arg); + ret = EXT_STATUS_OK; + } + break; + +/* case EXT_CC_RSCN_REG: + break; + case EXT_CC_RSCN_GET: + break; + case EXT_CC_ELS_RNID_SEND: + break; + case EXT_CC_ELS_RTIN_SEND: + break; + case EXT_CC_PLATFORM_REG: + break; + +all others go here */ + + default: + break; + } + + return(ret); +} + diff -urN linux-2.4.10/drivers/scsi/qlavendor.c linux-2.4.10-lia/drivers/scsi/qlavendor.c --- linux-2.4.10/drivers/scsi/qlavendor.c Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/scsi/qlavendor.c Mon Jul 23 14:13:02 2001 @@ -0,0 +1,325 @@ +/******************************************************************************** +* QLOGIC LINUX SOFTWARE +* +* QLogic ISP2x00 device driver for Linux 2.2.x (redhat 6.X). +* +* COPYRIGHT (C) 2000 QLOGIC CORPORATION +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the Qlogic's Linux Software License. See below. +* +* This program is WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* 1. Redistribution's or source code must retain the above copyright +* notice, this list of conditions, and the following disclaimer, +* without modification, immediately at the beginning of the file. +* 2. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +********************************************************************************/ + +/***************************************************************************************** + QLOGIC CORPORATION SOFTWARE + "GNU" GENERAL PUBLIC LICENSE + TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION + AND MODIFICATION + +This GNU General Public License ("License") applies solely to QLogic Linux +Software ("Software") and may be distributed under the terms of this License. + +1. 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If you cannot +distribute so as to satisfy simultaneously your obligations under this License +and any other pertinent obligations, then as a consequence you may not distribute the +Software at all. + +If any portion of this section is held invalid or unenforceable under any particular +circumstance, the balance of the section is intended to apply and the section as a whole +is intended to apply in other circumstances. +NO WARRANTY + +11. THE SOFTWARE IS PROVIDEDWITHOUT A WARRANTY OF ANY KIND. THERE IS NO +WARRANTY FOR THE SOFTWARE, TO THE EXTENT PERMITTED BY APPLICABLE LAW. +EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR +OTHER PARTIES PROVIDE THE SOFTWARE "AS IS" WITHOUT WARRANTY OF ANY KIND, +EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE +ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE SOFTWARE IS WITH YOU. +SHOULD THE SOFTWARE PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL +NECESSARY SERVICING, REPAIR OR CORRECTION. + +12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING +WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR +REDISTRIBUTE THE SOFTWARE AS PERMITTED ABOVE, BE LIABLE TO YOU FOR +DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL +DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE SOFTWARE (INCLUDING +BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR +LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE SOFTWARE TO +OPERATE WITH ANY OTHER SOFTWARES), EVEN IF SUCH HOLDER OR OTHER PARTY HAS +BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +END OF TERMS AND CONDITIONS + +******************************************************************************/ +/* + * vendor specific op codes. +*/ + +#define UCSCSI_DCMD 0x20 /* DAC960 direct command */ +#define UCSCSI_DCMD_PASSTHRU 0x21 /* DAC960 pass-through command */ +#define UC_SCSI_DCMD 0x22 /* DAC960 FSI direct command */ +#define DAC_CDB_LEN 12 +#define DAC_SENSE_LEN 64 + +#define SCSI_WRITE10 0x2A /* Required for direct disk writes */ +#define SCSI_WRITE6 0x0A /* Required for direct disk writes */ +#define SCSI_WRITEBUFFER 0x3B /* Required for flashing disk FW */ +#define DACMD_WRITE_CONF_ONDISK 0x4B +#define DACMD_WRITE_CONFIG 0x06 +#define DACMD_WRITE_CONF2 0x3C +#define DACMD_WRITE_CONFLABEL 0x49 /* Write configuration label */ +#define DACMD_WRITE_CONFIG_V3x 0x4F +#define DACMD_ADD_CONFIG_V2x 0x18 +#define DACMD_ADD_CONFIG_V3x 0x4C +#define DACMD_STORE_IMAGE 0x21 +#define DACMD_ADD_CAPACITY 0x2A /* add physical drives to existing array */ +#define DACMD_WRITE_IOPORT 0x3A /* write port B */ +#define DACMD_S2S_WRITEFULLCONF 0x60 /* write full configuration */ +#define DACMD_S2S_ADDFULLCONF 0x62 /* add full configuration */ +#define DACMD_S2S_WRITELUNMAP_OLD 0x58 /* write LUN map information */ +#define DACMD_S2S_WRITELUNMAP 0xD2 /* Write LUN MAP Information */ +#define DACMD_S2S_WRITE_IOPORT 0x66 /* write expanded IO port */ +#define DACMD_WRITE_V3x 0x34 /* write data from plain memory */ +#define DACMD_S2S_WRITESIG 0x4D /* write signature information */ + +#define MDACIOCTL_STOREIMAGE 0x2C /* Store the softeware image on controller */ +#define MDACIOCTL_WRITESIGNATURE 0xA6 /* Write Controller Signature */ +#define MDACIOCTL_SETREALTIMECLOCK 0xAC /* Set real time clock value */ +#define MDACIOCTL_PASS_THRU_CDB 0xAD /* Set up a pass-through command */ +#define MDACIOCTL_PASS_THRU_INITIATE 0xAE /* Initiates a pass-through read/write command (bi-directional) */ +#define MDACIOCTL_CREATENEWCONF 0xC0 /* Create new configruation */ +#define MDACIOCTL_ADDNEWCONF 0xC4 /* Add new logical/physical device to configruation */ +#define MDACIOCTL_MORE 0xC6 /* Do MORE operation */ +#define MDACIOCTL_SETPHYSDEVPARAMETER 0xC8 /* Set physical device parameters */ +#define MDACIOCTL_SETLOGDEVPARAMETER 0xCF /* Set logical device parameters */ +#define MDACIOCTL_SETCONTROLLERPARAMTER 0xD1 /* Set controller parameter */ +#define MDACIOCTL_WRITESANMAP 0xD4 /* Set logical device LUN map */ +#define MDACIOCTL_SETMACADDRESS 0xD5 /* Set controller MAC address */ + + /* + * qla2100_set_scsi_direction + * This routine will set the proper direction for vendor specific + * commands. + * + * Note: Vendors should modify this routine to set the proper + * direction of the transfer if they used vendor specific commands. + * + * Input: + * ha = adapter block pointer. + * sp = SCSI Request Block structure pointer. + * + * Returns: + * 0 = success, was able to issue command. + */ + + void qla2100_set_vend_direction(scsi_qla_host_t *ha, + Scsi_Cmnd *cmd, cmd_entry_t *pkt) { + /* This section added 10-JAN-2001 by Lethe. Required to facilitate SCSI + pass-through for flashing disk firmware, and direct disk writes under + Mylex 6.x and 5.x Firmware */ + if( cmd->data_cmnd[0] == UCSCSI_DCMD_PASSTHRU) { + pkt->control_flags = 0; + switch (cmd->data_cmnd[2]) { + case SCSI_WRITE6: + case SCSI_WRITE10: + case SCSI_WRITEBUFFER: + pkt->control_flags |= BIT_6; + break; + default: + pkt->control_flags |= BIT_5; + } + } + else if( cmd->data_cmnd[0] == UCSCSI_DCMD ) + { + pkt->control_flags = 0; + switch( cmd->data_cmnd[2] ) + { + case DACMD_WRITE_CONF_ONDISK: + case DACMD_WRITE_CONFIG: + case DACMD_WRITE_CONF2: + case DACMD_WRITE_CONFLABEL: + case DACMD_WRITE_CONFIG_V3x: + case DACMD_ADD_CONFIG_V2x: + case DACMD_ADD_CONFIG_V3x: + case DACMD_STORE_IMAGE: + case DACMD_ADD_CAPACITY: + case DACMD_WRITE_IOPORT: + case DACMD_S2S_WRITEFULLCONF: + case DACMD_S2S_ADDFULLCONF: + case DACMD_S2S_WRITELUNMAP_OLD: + case DACMD_S2S_WRITELUNMAP: + case DACMD_S2S_WRITE_IOPORT: + case DACMD_WRITE_V3x: + case DACMD_S2S_WRITESIG: + pkt->control_flags |= BIT_6; + break; + default: + pkt->control_flags |= BIT_5; + } + } + +/******************************************************************************************* +* The below logic is required to operate correctly with Mylex (IBM's) DAC960 family of * +* external RAID controllers. * +* * +* In addition to defining whether below CDBs are Reads or Writes, Mylex, in their infinite * +* wisdom, defined a vendor-specific CDB which can act as a Read OR a write, depending on * +* the parameters sent in a previous MDACIOCTL_PASS_THRU_CDB. Instead of adding a lot of * +* logic to define and maintain a MDACIOCTL_PASS_THRU_CDB queue, and parse each one of them * +* to determine direction, I took easy way out (also the low-overhead method). * +* * +* If the high-order bit of the 32-bit UniqueID, defined in byte 3 of data_cmnd[3] is set * +* then I will mark that as a CDB which is going to be a write, otherwise the pass thru * +* operation will be a read. If somebody wishes to rewrite the driver to maintain a 30-sec * +* command queue, and parse the contents of each data buffer passed in to determine R or W * +* then they are free to do so, and it will not impact future versions of the Distributed * +* Array Manager, which required this fix in the first place. * +* * +* This configurator and patch was written by David A. Lethe of Xyratex david@santools.com. * +* In addition, the logic to check cmd->data_cmnd[0] == UC_SCSI_DCMD, was written by * +* Sammy Wilborn of Silicon Graphics, Inc, and David Lethe * +* They define CDBs used by the DAC960FF family, when running FW 7.x and above. * +* * +*******************************************************************************************/ + + else if ( cmd->data_cmnd[0] == UC_SCSI_DCMD ) /* Mylex DAC960 FW 7.x */ + { + pkt->control_flags = 0; + switch( cmd->data_cmnd[2] ) + { + case MDACIOCTL_STOREIMAGE: + case MDACIOCTL_SETREALTIMECLOCK: + case MDACIOCTL_WRITESIGNATURE: + case MDACIOCTL_CREATENEWCONF: + case MDACIOCTL_ADDNEWCONF: + case MDACIOCTL_MORE: + case MDACIOCTL_SETPHYSDEVPARAMETER: + case MDACIOCTL_SETLOGDEVPARAMETER: + case MDACIOCTL_SETCONTROLLERPARAMTER: + case MDACIOCTL_WRITESANMAP: + case MDACIOCTL_SETMACADDRESS: + case MDACIOCTL_PASS_THRU_CDB: + pkt->control_flags |= BIT_6; + break; + default: + if (cmd->data_cmnd[2] == MDACIOCTL_PASS_THRU_INITIATE) { + /* If the high bit of the UniqueID field of the vendor- + specific field is TRUE, then it is marked as a write. */ + if (cmd->data_cmnd[3] & 0x80) + pkt->control_flags |= BIT_6; + else + pkt->control_flags |= BIT_5; + } + else + pkt->control_flags |= BIT_5; + break; + } + } + else + { + pkt->control_flags |= BIT_5; + } + + } diff -urN linux-2.4.10/drivers/scsi/scsi_ioctl.c linux-2.4.10-lia/drivers/scsi/scsi_ioctl.c --- linux-2.4.10/drivers/scsi/scsi_ioctl.c Mon Aug 20 10:19:06 2001 +++ linux-2.4.10-lia/drivers/scsi/scsi_ioctl.c Mon Aug 20 12:20:58 2001 @@ -198,6 +198,9 @@ unsigned int needed, buf_needed; int timeout, retries, result; int data_direction; +#if __GNUC__ < 3 + int foo; +#endif if (!sic) return -EINVAL; @@ -207,12 +210,21 @@ if (verify_area(VERIFY_READ, sic, sizeof(Scsi_Ioctl_Command))) return -EFAULT; - if(__get_user(inlen, &sic->inlen)) +#if __GNUC__ < 3 + foo = __get_user(inlen, &sic->inlen); + if(foo) return -EFAULT; - if(__get_user(outlen, &sic->outlen)) + foo = __get_user(outlen, &sic->outlen); + if(foo) + return -EFAULT; +#else + if(__get_user(inlen, &sic->inlen)) return -EFAULT; + if(__get_user(outlen, &sic->outlen)) + return -EFAULT; +#endif /* * We do not transfer more than MAX_BUF with this interface. * If the user needs to transfer more data than this, they diff -urN linux-2.4.10/drivers/scsi/simscsi.c linux-2.4.10-lia/drivers/scsi/simscsi.c --- linux-2.4.10/drivers/scsi/simscsi.c Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/scsi/simscsi.c Wed Feb 21 16:30:57 2001 @@ -0,0 +1,382 @@ +/* + * Simulated SCSI driver. + * + * Copyright (C) 1999, 2001 Hewlett-Packard Co + * Copyright (C) 1999, 2001 David Mosberger-Tang + * Copyright (C) 1999 Stephane Eranian + * + * 99/12/18 David Mosberger Added support for READ10/WRITE10 needed by linux v2.3.33 + */ +#include +#include +#include +#include +#include +#include + +#include + +#include + +#include "scsi.h" +#include "sd.h" +#include "hosts.h" +#include "simscsi.h" + +#define DEBUG_SIMSCSI 1 + +/* Simulator system calls: */ + +#define SSC_OPEN 50 +#define SSC_CLOSE 51 +#define SSC_READ 52 +#define SSC_WRITE 53 +#define SSC_GET_COMPLETION 54 +#define SSC_WAIT_COMPLETION 55 + +#define SSC_WRITE_ACCESS 2 +#define SSC_READ_ACCESS 1 + +#ifdef DEBUG_SIMSCSI + int simscsi_debug; +# define DBG simscsi_debug +#else +# define DBG 0 +#endif + +#if 0 +struct timer_list disk_timer; +#else +static void simscsi_interrupt (unsigned long val); +DECLARE_TASKLET(simscsi_tasklet, simscsi_interrupt, 0); +#endif + +struct disk_req { + unsigned long addr; + unsigned len; +}; + +struct disk_stat { + int fd; + unsigned count; +}; + +extern long ia64_ssc (long arg0, long arg1, long arg2, long arg3, int nr); + +static int desc[8] = { -1, -1, -1, -1, -1, -1, -1, -1 }; + +static struct queue_entry { + Scsi_Cmnd *sc; +} queue[SIMSCSI_REQ_QUEUE_LEN]; + +static int rd, wr; +static atomic_t num_reqs = ATOMIC_INIT(0); + +/* base name for default disks */ +static char *simscsi_root = DEFAULT_SIMSCSI_ROOT; + +#define MAX_ROOT_LEN 128 + +/* + * used to setup a new base for disk images + * to use /foo/bar/disk[a-z] as disk images + * you have to specify simscsi=/foo/bar/disk on the command line + */ +static int __init +simscsi_setup (char *s) +{ + /* XXX Fix me we may need to strcpy() ? */ + if (strlen(s) > MAX_ROOT_LEN) { + printk("simscsi_setup: prefix too long---using default %s\n", simscsi_root); + } + simscsi_root = s; + return 1; +} + +__setup("simscsi=", simscsi_setup); + +static void +simscsi_interrupt (unsigned long val) +{ + unsigned long flags; + Scsi_Cmnd *sc; + + spin_lock_irqsave(&io_request_lock, flags); + { + while ((sc = queue[rd].sc) != 0) { + atomic_dec(&num_reqs); + queue[rd].sc = 0; + if (DBG) + printk("simscsi_interrupt: done with %ld\n", sc->serial_number); + (*sc->scsi_done)(sc); + rd = (rd + 1) % SIMSCSI_REQ_QUEUE_LEN; + } + } + spin_unlock_irqrestore(&io_request_lock, flags); +} + +int +simscsi_detect (Scsi_Host_Template *templ) +{ + templ->proc_name = "simscsi"; +#if 0 + init_timer(&disk_timer); + disk_timer.function = simscsi_interrupt; +#endif + return 1; /* fake one SCSI host adapter */ +} + +int +simscsi_release (struct Scsi_Host *host) +{ + return 0; /* this is easy... */ +} + +const char * +simscsi_info (struct Scsi_Host *host) +{ + return "simulated SCSI host adapter"; +} + +int +simscsi_abort (Scsi_Cmnd *cmd) +{ + printk ("simscsi_abort: unimplemented\n"); + return SCSI_ABORT_SUCCESS; +} + +int +simscsi_reset (Scsi_Cmnd *cmd, unsigned int reset_flags) +{ + printk ("simscsi_reset: unimplemented\n"); + return SCSI_RESET_SUCCESS; +} + +int +simscsi_biosparam (Disk *disk, kdev_t n, int ip[]) +{ + int size = disk->capacity; + + ip[0] = 64; + ip[1] = 32; + ip[2] = size >> 11; + return 0; +} + +static void +simscsi_readwrite (Scsi_Cmnd *sc, int mode, unsigned long offset, unsigned long len) +{ + struct disk_stat stat; + struct disk_req req; + + req.addr = __pa(sc->request_buffer); + req.len = len; /* # of bytes to transfer */ + + if (sc->request_bufflen < req.len) + return; + + stat.fd = desc[sc->target]; + if (DBG) + printk("simscsi_%s @ %lx (off %lx)\n", + mode == SSC_READ ? "read":"write", req.addr, offset); + ia64_ssc(stat.fd, 1, __pa(&req), offset, mode); + ia64_ssc(__pa(&stat), 0, 0, 0, SSC_WAIT_COMPLETION); + + if (stat.count == req.len) { + sc->result = GOOD; + } else { + sc->result = DID_ERROR << 16; + } +} + +static void +simscsi_sg_readwrite (Scsi_Cmnd *sc, int mode, unsigned long offset) +{ + int list_len = sc->use_sg; + struct scatterlist *sl = (struct scatterlist *)sc->buffer; + struct disk_stat stat; + struct disk_req req; + + stat.fd = desc[sc->target]; + + while (list_len) { + req.addr = __pa(sl->address); + req.len = sl->length; + if (DBG) + printk("simscsi_sg_%s @ %lx (off %lx) use_sg=%d len=%d\n", + mode == SSC_READ ? "read":"write", req.addr, offset, + list_len, sl->length); + ia64_ssc(stat.fd, 1, __pa(&req), offset, mode); + ia64_ssc(__pa(&stat), 0, 0, 0, SSC_WAIT_COMPLETION); + + /* should not happen in our case */ + if (stat.count != req.len) { + sc->result = DID_ERROR << 16; + return; + } + offset += sl->length; + sl++; + list_len--; + } + sc->result = GOOD; +} + +/* + * function handling both READ_6/WRITE_6 (non-scatter/gather mode) + * commands. + * Added 02/26/99 S.Eranian + */ +static void +simscsi_readwrite6 (Scsi_Cmnd *sc, int mode) +{ + unsigned long offset; + + offset = (((sc->cmnd[1] & 0x1f) << 16) | (sc->cmnd[2] << 8) | sc->cmnd[3])*512; + if (sc->use_sg > 0) + simscsi_sg_readwrite(sc, mode, offset); + else + simscsi_readwrite(sc, mode, offset, sc->cmnd[4]*512); +} + + +static void +simscsi_readwrite10 (Scsi_Cmnd *sc, int mode) +{ + unsigned long offset; + + offset = ( (sc->cmnd[2] << 24) | (sc->cmnd[3] << 16) + | (sc->cmnd[4] << 8) | (sc->cmnd[5] << 0))*512; + if (sc->use_sg > 0) + simscsi_sg_readwrite(sc, mode, offset); + else + simscsi_readwrite(sc, mode, offset, ((sc->cmnd[7] << 8) | sc->cmnd[8])*512); +} + +int +simscsi_queuecommand (Scsi_Cmnd *sc, void (*done)(Scsi_Cmnd *)) +{ + char fname[MAX_ROOT_LEN+16]; + char *buf; +#if DEBUG_SIMSCSI + register long sp asm ("sp"); + + if (DBG) + printk("simscsi_queuecommand: target=%d,cmnd=%u,sc=%lu,sp=%lx,done=%p\n", + sc->target, sc->cmnd[0], sc->serial_number, sp, done); +#endif + + sc->result = DID_BAD_TARGET << 16; + sc->scsi_done = done; + if (sc->target <= 7 && sc->lun == 0) { + switch (sc->cmnd[0]) { + case INQUIRY: + if (sc->request_bufflen < 35) { + break; + } + sprintf (fname, "%s%c", simscsi_root, 'a' + sc->target); + desc[sc->target] = ia64_ssc (__pa(fname), SSC_READ_ACCESS|SSC_WRITE_ACCESS, + 0, 0, SSC_OPEN); + if (desc[sc->target] < 0) { + /* disk doesn't exist... */ + break; + } + buf = sc->request_buffer; + buf[0] = 0; /* magnetic disk */ + buf[1] = 0; /* not a removable medium */ + buf[2] = 2; /* SCSI-2 compliant device */ + buf[3] = 2; /* SCSI-2 response data format */ + buf[4] = 31; /* additional length (bytes) */ + buf[5] = 0; /* reserved */ + buf[6] = 0; /* reserved */ + buf[7] = 0; /* various flags */ + memcpy(buf + 8, "HP SIMULATED DISK 0.00", 28); + sc->result = GOOD; + break; + + case TEST_UNIT_READY: + sc->result = GOOD; + break; + + case READ_6: + if (desc[sc->target] < 0 ) + break; + simscsi_readwrite6(sc, SSC_READ); + break; + + case READ_10: + if (desc[sc->target] < 0 ) + break; + simscsi_readwrite10(sc, SSC_READ); + break; + + case WRITE_6: + if (desc[sc->target] < 0) + break; + simscsi_readwrite6(sc, SSC_WRITE); + break; + + case WRITE_10: + if (desc[sc->target] < 0) + break; + simscsi_readwrite10(sc, SSC_WRITE); + break; + + + case READ_CAPACITY: + if (desc[sc->target] < 0 || sc->request_bufflen < 8) { + break; + } + buf = sc->request_buffer; + + /* pretend to be a 1GB disk (partition table contains real stuff): */ + buf[0] = 0x00; + buf[1] = 0x1f; + buf[2] = 0xff; + buf[3] = 0xff; + /* set block size of 512 bytes: */ + buf[4] = 0; + buf[5] = 0; + buf[6] = 2; + buf[7] = 0; + sc->result = GOOD; + break; + + case MODE_SENSE: + printk("MODE_SENSE\n"); + break; + + case START_STOP: + printk("START_STOP\n"); + break; + + default: + panic("simscsi: unknown SCSI command %u\n", sc->cmnd[0]); + } + } + if (sc->result == DID_BAD_TARGET) { + sc->result |= DRIVER_SENSE << 24; + sc->sense_buffer[0] = 0x70; + sc->sense_buffer[2] = 0x00; + } + if (atomic_read(&num_reqs) >= SIMSCSI_REQ_QUEUE_LEN) { + panic("Attempt to queue command while command is pending!!"); + } + atomic_inc(&num_reqs); + queue[wr].sc = sc; + wr = (wr + 1) % SIMSCSI_REQ_QUEUE_LEN; + +#if 0 + if (!timer_pending(&disk_timer)) { + disk_timer.expires = jiffies; + add_timer(&disk_timer); + } +#else + tasklet_schedule(&simscsi_tasklet); +#endif + return 0; +} + + +static Scsi_Host_Template driver_template = SIMSCSI; + +#include "scsi_module.c" diff -urN linux-2.4.10/drivers/scsi/simscsi.h linux-2.4.10-lia/drivers/scsi/simscsi.h --- linux-2.4.10/drivers/scsi/simscsi.h Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/drivers/scsi/simscsi.h Wed Feb 21 16:31:25 2001 @@ -0,0 +1,39 @@ +/* + * Simulated SCSI driver. + * + * Copyright (C) 1999 Hewlett-Packard Co + * Copyright (C) 1999 David Mosberger-Tang + */ +#ifndef SIMSCSI_H +#define SIMSCSI_H + +#define SIMSCSI_REQ_QUEUE_LEN 64 + +#define DEFAULT_SIMSCSI_ROOT "/var/ski-disks/sd" + +extern int simscsi_detect (Scsi_Host_Template *); +extern int simscsi_release (struct Scsi_Host *); +extern const char *simscsi_info (struct Scsi_Host *); +extern int simscsi_queuecommand (Scsi_Cmnd *, void (*done)(Scsi_Cmnd *)); +extern int simscsi_abort (Scsi_Cmnd *); +extern int simscsi_reset (Scsi_Cmnd *, unsigned int); +extern int simscsi_biosparam (Disk *, kdev_t, int[]); + +#define SIMSCSI { \ + detect: simscsi_detect, \ + release: simscsi_release, \ + info: simscsi_info, \ + queuecommand: simscsi_queuecommand, \ + abort: simscsi_abort, \ + reset: simscsi_reset, \ + bios_param: simscsi_biosparam, \ + can_queue: SIMSCSI_REQ_QUEUE_LEN, \ + this_id: -1, \ + sg_tablesize: SG_ALL, \ + cmd_per_lun: SIMSCSI_REQ_QUEUE_LEN, \ + present: 0, \ + unchecked_isa_dma: 0, \ + use_clustering: DISABLE_CLUSTERING \ +} + +#endif /* SIMSCSI_H */ diff -urN linux-2.4.10/drivers/sound/cs4281/cs4281m.c linux-2.4.10-lia/drivers/sound/cs4281/cs4281m.c --- linux-2.4.10/drivers/sound/cs4281/cs4281m.c Mon Aug 20 10:19:08 2001 +++ linux-2.4.10-lia/drivers/sound/cs4281/cs4281m.c Mon Aug 20 12:20:58 2001 @@ -1942,8 +1942,8 @@ len -= x; } CS_DBGOUT(CS_WAVE_WRITE, 4, printk(KERN_INFO - "cs4281: clear_advance(): memset %d at 0x%.8x for %d size \n", - (unsigned)c, (unsigned)((char *) buf) + bptr, len)); + "cs4281: clear_advance(): memset %d at %p for %d size \n", + (unsigned)c, ((char *) buf) + bptr, len)); memset(((char *) buf) + bptr, c, len); } @@ -1978,9 +1978,8 @@ wake_up(&s->dma_adc.wait); } CS_DBGOUT(CS_PARMS, 8, printk(KERN_INFO - "cs4281: cs4281_update_ptr(): s=0x%.8x hwptr=%d total_bytes=%d count=%d \n", - (unsigned)s, s->dma_adc.hwptr, - s->dma_adc.total_bytes, s->dma_adc.count)); + "cs4281: cs4281_update_ptr(): s=%p hwptr=%d total_bytes=%d count=%d \n", + s, s->dma_adc.hwptr, s->dma_adc.total_bytes, s->dma_adc.count)); } // update DAC pointer // @@ -2012,11 +2011,10 @@ // Continue to play silence until the _release. // CS_DBGOUT(CS_WAVE_WRITE, 6, printk(KERN_INFO - "cs4281: cs4281_update_ptr(): memset %d at 0x%.8x for %d size \n", + "cs4281: cs4281_update_ptr(): memset %d at %p for %d size \n", (unsigned)(s->prop_dac.fmt & (AFMT_U8 | AFMT_U16_LE)) ? 0x80 : 0, - (unsigned)s->dma_dac.rawbuf, - s->dma_dac.dmasize)); + s->dma_dac.rawbuf, s->dma_dac.dmasize)); memset(s->dma_dac.rawbuf, (s->prop_dac. fmt & (AFMT_U8 | AFMT_U16_LE)) ? @@ -2047,9 +2045,8 @@ } } CS_DBGOUT(CS_PARMS, 8, printk(KERN_INFO - "cs4281: cs4281_update_ptr(): s=0x%.8x hwptr=%d total_bytes=%d count=%d \n", - (unsigned) s, s->dma_dac.hwptr, - s->dma_dac.total_bytes, s->dma_dac.count)); + "cs4281: cs4281_update_ptr(): s=%p hwptr=%d total_bytes=%d count=%d \n", + s, s->dma_dac.hwptr, s->dma_dac.total_bytes, s->dma_dac.count)); } } @@ -2180,8 +2177,7 @@ VALIDATE_STATE(s); CS_DBGOUT(CS_FUNCTION, 4, printk(KERN_INFO - "cs4281: mixer_ioctl(): s=0x%.8x cmd=0x%.8x\n", - (unsigned) s, cmd)); + "cs4281: mixer_ioctl(): s=%p cmd=0x%.8x\n", s, cmd)); #if CSDEBUG cs_printioctl(cmd); #endif @@ -2746,9 +2742,8 @@ CS_DBGOUT(CS_FUNCTION, 2, printk(KERN_INFO "cs4281: CopySamples()+ ")); CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO - " dst=0x%x src=0x%x count=%d iChannels=%d fmt=0x%x\n", - (unsigned) dst, (unsigned) src, (unsigned) count, - (unsigned) iChannels, (unsigned) fmt)); + " dst=%p src=%p count=%d iChannels=%d fmt=0x%x\n", + dst, src, (unsigned) count, (unsigned) iChannels, (unsigned) fmt)); // Gershwin does format conversion in hardware so normally // we don't do any host based coversion. The data formatter @@ -2828,9 +2823,9 @@ void *src = hwsrc; //default to the standard destination buffer addr CS_DBGOUT(CS_FUNCTION, 6, printk(KERN_INFO - "cs_copy_to_user()+ fmt=0x%x fmt_o=0x%x cnt=%d dest=0x%.8x\n", + "cs_copy_to_user()+ fmt=0x%x fmt_o=0x%x cnt=%d dest=%p\n", s->prop_adc.fmt, s->prop_adc.fmt_original, - (unsigned) cnt, (unsigned) dest)); + (unsigned) cnt, dest)); if (cnt > s->dma_adc.dmasize) { cnt = s->dma_adc.dmasize; @@ -2875,7 +2870,7 @@ unsigned copied = 0; CS_DBGOUT(CS_FUNCTION | CS_WAVE_READ, 2, - printk(KERN_INFO "cs4281: cs4281_read()+ %d \n", count)); + printk(KERN_INFO "cs4281: cs4281_read()+ %Zu \n", count)); VALIDATE_STATE(s); if (ppos != &file->f_pos) @@ -2898,7 +2893,7 @@ // while (count > 0) { CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO - "_read() count>0 count=%d .count=%d .swptr=%d .hwptr=%d \n", + "_read() count>0 count=%Zu .count=%d .swptr=%d .hwptr=%d \n", count, s->dma_adc.count, s->dma_adc.swptr, s->dma_adc.hwptr)); spin_lock_irqsave(&s->lock, flags); @@ -2955,11 +2950,10 @@ // the "cnt" is the number of bytes to read. CS_DBGOUT(CS_WAVE_READ, 2, printk(KERN_INFO - "_read() copy_to cnt=%d count=%d ", cnt, count)); + "_read() copy_to cnt=%d count=%Zu ", cnt, count)); CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO - " .dmasize=%d .count=%d buffer=0x%.8x ret=%d\n", - s->dma_adc.dmasize, s->dma_adc.count, - (unsigned) buffer, ret)); + " .dmasize=%d .count=%d buffer=%p ret=%Zd\n", + s->dma_adc.dmasize, s->dma_adc.count, buffer, ret)); if (cs_copy_to_user (s, buffer, s->dma_adc.rawbuf + swptr, cnt, &copied)) @@ -2975,7 +2969,7 @@ start_adc(s); } CS_DBGOUT(CS_FUNCTION | CS_WAVE_READ, 2, - printk(KERN_INFO "cs4281: cs4281_read()- %d\n", ret)); + printk(KERN_INFO "cs4281: cs4281_read()- %Zd\n", ret)); return ret; } @@ -2991,7 +2985,7 @@ int cnt; CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE, 2, - printk(KERN_INFO "cs4281: cs4281_write()+ count=%d\n", + printk(KERN_INFO "cs4281: cs4281_write()+ count=%Zu\n", count)); VALIDATE_STATE(s); @@ -3047,7 +3041,7 @@ start_dac(s); } CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE, 2, - printk(KERN_INFO "cs4281: cs4281_write()- %d\n", ret)); + printk(KERN_INFO "cs4281: cs4281_write()- %Zd\n", ret)); return ret; } @@ -3168,8 +3162,7 @@ int val, mapped, ret; CS_DBGOUT(CS_FUNCTION, 4, printk(KERN_INFO - "cs4281: cs4281_ioctl(): file=0x%.8x cmd=0x%.8x\n", - (unsigned) file, cmd)); + "cs4281: cs4281_ioctl(): file=%p cmd=0x%.8x\n", file, cmd)); #if CSDEBUG cs_printioctl(cmd); #endif @@ -3595,8 +3588,8 @@ (struct cs4281_state *) file->private_data; CS_DBGOUT(CS_FUNCTION | CS_RELEASE, 2, printk(KERN_INFO - "cs4281: cs4281_release(): inode=0x%.8x file=0x%.8x f_mode=%d\n", - (unsigned) inode, (unsigned) file, file->f_mode)); + "cs4281: cs4281_release(): inode=%p file=%p f_mode=%d\n", + inode, file, file->f_mode)); VALIDATE_STATE(s); @@ -3630,8 +3623,8 @@ struct list_head *entry; CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO - "cs4281: cs4281_open(): inode=0x%.8x file=0x%.8x f_mode=0x%x\n", - (unsigned) inode, (unsigned) file, file->f_mode)); + "cs4281: cs4281_open(): inode=%p file=%p f_mode=0x%x\n", + inode, file, file->f_mode)); list_for_each(entry, &cs4281_devs) { @@ -4340,10 +4333,8 @@ CS_DBGOUT(CS_INIT, 2, printk(KERN_INFO - "cs4281: probe() BA0=0x%.8x BA1=0x%.8x pBA0=0x%.8x pBA1=0x%.8x \n", - (unsigned) temp1, (unsigned) temp2, - (unsigned) s->pBA0, (unsigned) s->pBA1)); - + "cs4281: probe() BA0=0x%.8x BA1=0x%.8x pBA0=%p pBA1=%p \n", + (unsigned) temp1, (unsigned) temp2, s->pBA0, s->pBA1)); CS_DBGOUT(CS_INIT, 2, printk(KERN_INFO "cs4281: probe() pBA0phys=0x%.8x pBA1phys=0x%.8x\n", @@ -4390,15 +4381,13 @@ if (pmdev) { CS_DBGOUT(CS_INIT | CS_PM, 4, printk(KERN_INFO - "cs4281: probe() pm_register() succeeded (0x%x).\n", - (unsigned)pmdev)); + "cs4281: probe() pm_register() succeeded (%p).\n", pmdev)); pmdev->data = s; } else { CS_DBGOUT(CS_INIT | CS_PM | CS_ERROR, 0, printk(KERN_INFO - "cs4281: probe() pm_register() failed (0x%x).\n", - (unsigned)pmdev)); + "cs4281: probe() pm_register() failed (%p).\n", pmdev)); s->pm.flags |= CS4281_PM_NOT_REGISTERED; } #endif diff -urN linux-2.4.10/drivers/sound/cs4281/cs4281pm-24.c linux-2.4.10-lia/drivers/sound/cs4281/cs4281pm-24.c --- linux-2.4.10/drivers/sound/cs4281/cs4281pm-24.c Sun Feb 4 10:05:29 2001 +++ linux-2.4.10-lia/drivers/sound/cs4281/cs4281pm-24.c Mon Aug 20 18:49:47 2001 @@ -38,16 +38,16 @@ #define CS4281_SUSPEND_TBL cs4281_suspend_tbl #define CS4281_RESUME_TBL cs4281_resume_tbl */ -#define CS4281_SUSPEND_TBL cs4281_null -#define CS4281_RESUME_TBL cs4281_null +#define CS4281_SUSPEND_TBL (int (*) (struct pci_dev *, u32)) cs4281_null +#define CS4281_RESUME_TBL (int (*) (struct pci_dev *)) cs4281_null int cs4281_pm_callback(struct pm_dev *dev, pm_request_t rqst, void *data) { struct cs4281_state *state; CS_DBGOUT(CS_PM, 2, printk(KERN_INFO - "cs4281: cs4281_pm_callback dev=0x%x rqst=0x%x state=%d\n", - (unsigned)dev,(unsigned)rqst,(unsigned)data)); + "cs4281: cs4281_pm_callback dev=%p rqst=0x%x state=%p\n", + dev,(unsigned)rqst,data)); state = (struct cs4281_state *) dev->data; if (state) { switch(rqst) { @@ -78,7 +78,7 @@ } #else /* CS4281_PM */ -#define CS4281_SUSPEND_TBL cs4281_null -#define CS4281_RESUME_TBL cs4281_null +#define CS4281_SUSPEND_TBL (int (*) (struct pci_dev *, u32)) cs4281_null +#define CS4281_RESUME_TBL (int (*) (struct pci_dev *)) cs4281_null #endif /* CS4281_PM */ diff -urN linux-2.4.10/drivers/sound/sound_firmware.c linux-2.4.10-lia/drivers/sound/sound_firmware.c --- linux-2.4.10/drivers/sound/sound_firmware.c Fri Feb 9 11:30:23 2001 +++ linux-2.4.10-lia/drivers/sound/sound_firmware.c Wed Feb 28 13:06:57 2001 @@ -7,7 +7,6 @@ #include #include -static int errno; static int do_mod_firmware_load(const char *fn, char **fp) { int fd; diff -urN linux-2.4.10/drivers/usb/usb-ohci.c linux-2.4.10-lia/drivers/usb/usb-ohci.c --- linux-2.4.10/drivers/usb/usb-ohci.c Mon Sep 24 15:08:03 2001 +++ linux-2.4.10-lia/drivers/usb/usb-ohci.c Mon Sep 24 15:23:36 2001 @@ -2351,21 +2351,22 @@ { ohci_t * ohci; struct usb_bus * bus; + dma_addr_t bus_addr; ohci = (ohci_t *) kmalloc (sizeof *ohci, GFP_KERNEL); if (!ohci) return NULL; - + memset (ohci, 0, sizeof (ohci_t)); - ohci->hcca = pci_alloc_consistent (dev, sizeof *ohci->hcca, - &ohci->hcca_dma); + ohci->hcca = pci_alloc_consistent (dev, sizeof *ohci->hcca, &bus_addr); if (!ohci->hcca) { kfree (ohci); return NULL; } memset (ohci->hcca, 0, sizeof (struct ohci_hcca)); + ohci->hcca_dma = bus_addr; ohci->disabled = 1; ohci->sleeping = 0; ohci->irq = -1; diff -urN linux-2.4.10/drivers/video/vgacon.c linux-2.4.10-lia/drivers/video/vgacon.c --- linux-2.4.10/drivers/video/vgacon.c Mon Sep 24 15:08:10 2001 +++ linux-2.4.10-lia/drivers/video/vgacon.c Mon Sep 24 15:23:43 2001 @@ -109,14 +109,7 @@ static unsigned int vga_default_font_height; /* Height of default screen font */ static unsigned char vga_video_type; /* Card type */ static unsigned char vga_hardscroll_enabled; -#ifdef CONFIG_IA64_SOFTSDV_HACKS -/* - * SoftSDV doesn't have hardware assist VGA scrolling - */ -static unsigned char vga_hardscroll_user_enable = 0; -#else static unsigned char vga_hardscroll_user_enable = 1; -#endif static unsigned char vga_font_is_default = 1; static int vga_vesa_blanked; static int vga_palette_blanked; diff -urN linux-2.4.10/fs/devfs/base.c linux-2.4.10-lia/fs/devfs/base.c --- linux-2.4.10/fs/devfs/base.c Mon Sep 24 15:08:12 2001 +++ linux-2.4.10-lia/fs/devfs/base.c Mon Sep 24 15:23:45 2001 @@ -1941,6 +1941,27 @@ return master->slave; } /* End Function devfs_get_unregister_slave */ +#ifdef CONFIG_DEVFS_GUID +/** + * devfs_unregister_slave - remove the slave that is unregistered when @master is unregistered. + * Destroys the connection established by devfs_auto_unregister. + * + * @master: The master devfs entry. + */ + +void devfs_unregister_slave (devfs_handle_t master) +{ + devfs_handle_t slave; + + if (master == NULL) return; + + slave = master->slave; + if (slave) { + master->slave = NULL; + unregister (slave); + }; +} +#endif /* CONFIG_DEVFS_GUID */ /** * devfs_get_name - Get the name for a device entry in its parent directory. @@ -2118,6 +2139,9 @@ EXPORT_SYMBOL(devfs_register_blkdev); EXPORT_SYMBOL(devfs_unregister_chrdev); EXPORT_SYMBOL(devfs_unregister_blkdev); +#ifdef CONFIG_DEVFS_GUID +EXPORT_SYMBOL(devfs_unregister_slave); +#endif /** diff -urN linux-2.4.10/fs/exec.c linux-2.4.10-lia/fs/exec.c --- linux-2.4.10/fs/exec.c Mon Sep 24 15:08:12 2001 +++ linux-2.4.10-lia/fs/exec.c Mon Sep 24 22:04:08 2001 @@ -153,7 +153,7 @@ } /* - * count() counts the number of arguments/envelopes + * count() counts the number of strings in array ARGV. */ static int count(char ** argv, int max) { @@ -176,7 +176,7 @@ } /* - * 'copy_strings()' copies argument/envelope strings from user + * 'copy_strings()' copies argument/environment strings from user * memory to free pages in kernel mem. These are in a format ready * to be put directly into the top of new user memory. */ diff -urN linux-2.4.10/fs/fcntl.c linux-2.4.10-lia/fs/fcntl.c --- linux-2.4.10/fs/fcntl.c Mon Sep 24 15:08:13 2001 +++ linux-2.4.10-lia/fs/fcntl.c Mon Sep 24 15:23:46 2001 @@ -289,6 +289,7 @@ * to fix this will be in libc. */ err = filp->f_owner.pid; + force_successful_syscall_return(); break; case F_SETOWN: lock_kernel(); diff -urN linux-2.4.10/fs/inode.c linux-2.4.10-lia/fs/inode.c --- linux-2.4.10/fs/inode.c Mon Sep 24 15:08:13 2001 +++ linux-2.4.10-lia/fs/inode.c Mon Sep 24 21:29:26 2001 @@ -16,7 +16,6 @@ #include #include #include -#include /* * New inode.c implementation. @@ -836,6 +835,8 @@ { struct inode * inode; + spin_lock_prefetch(&inode_lock); + inode = alloc_inode(); if (inode) { struct inode * old; diff -urN linux-2.4.10/fs/namei.c linux-2.4.10-lia/fs/namei.c --- linux-2.4.10/fs/namei.c Mon Sep 24 15:08:16 2001 +++ linux-2.4.10-lia/fs/namei.c Mon Sep 24 22:04:25 2001 @@ -629,10 +629,14 @@ static int __emul_lookup_dentry(const char *name, struct nameidata *nd) { if (path_walk(name, nd)) - return 0; + return 0; /* something went wrong... */ - if (!nd->dentry->d_inode) { + if (!nd->dentry->d_inode || S_ISDIR(nd->dentry->d_inode->i_mode)) { struct nameidata nd_root; + /* + * NAME was not found in alternate root or it's a directory. Try to find + * it in the normal root: + */ nd_root.last_type = LAST_ROOT; nd_root.flags = nd->flags; read_lock(¤t->fs->lock); @@ -642,12 +646,14 @@ if (path_walk(name, &nd_root)) return 1; if (nd_root.dentry->d_inode) { + /* file exists in normal root filesystem: */ path_release(nd); nd->dentry = nd_root.dentry; nd->mnt = nd_root.mnt; nd->last = nd_root.last; return 1; } + /* file doesn't exist */ path_release(&nd_root); } return 1; diff -urN linux-2.4.10/fs/partitions/Config.in linux-2.4.10-lia/fs/partitions/Config.in --- linux-2.4.10/fs/partitions/Config.in Mon Aug 20 10:19:20 2001 +++ linux-2.4.10-lia/fs/partitions/Config.in Mon Aug 20 12:21:01 2001 @@ -24,6 +24,8 @@ bool ' Minix subpartition support' CONFIG_MINIX_SUBPARTITION bool ' Solaris (x86) partition table support' CONFIG_SOLARIS_X86_PARTITION bool ' Unixware slices support' CONFIG_UNIXWARE_DISKLABEL + bool ' EFI GUID Partition support' CONFIG_EFI_PARTITION + dep_bool ' /dev/guid support (EXPERIMENTAL)' CONFIG_DEVFS_GUID $CONFIG_DEVFS_FS $CONFIG_EFI_PARTITION fi dep_bool ' Windows Logical Disk Manager (Dynamic Disk) support' CONFIG_LDM_PARTITION $CONFIG_EXPERIMENTAL if [ "$CONFIG_LDM_PARTITION" = "y" ]; then diff -urN linux-2.4.10/fs/partitions/Makefile linux-2.4.10-lia/fs/partitions/Makefile --- linux-2.4.10/fs/partitions/Makefile Thu Jul 26 16:30:04 2001 +++ linux-2.4.10-lia/fs/partitions/Makefile Mon Aug 13 23:46:06 2001 @@ -24,6 +24,7 @@ obj-$(CONFIG_SUN_PARTITION) += sun.o obj-$(CONFIG_ULTRIX_PARTITION) += ultrix.o obj-$(CONFIG_IBM_PARTITION) += ibm.o +obj-$(CONFIG_EFI_PARTITION) += efi.o include $(TOPDIR)/Rules.make diff -urN linux-2.4.10/fs/partitions/check.c linux-2.4.10-lia/fs/partitions/check.c --- linux-2.4.10/fs/partitions/check.c Mon Sep 24 15:08:18 2001 +++ linux-2.4.10-lia/fs/partitions/check.c Mon Sep 24 15:23:51 2001 @@ -34,6 +34,10 @@ #include "ibm.h" #include "ultrix.h" +#ifdef CONFIG_EFI_PARTITION +# include "efi.h" +#endif + extern int *blk_size[]; int warn_no_part = 1; /*This is ugly: should make genhd removable media aware*/ @@ -42,6 +46,9 @@ #ifdef CONFIG_ACORN_PARTITION acorn_partition, #endif +#ifdef CONFIG_EFI_PARTITION + efi_partition, +#endif #ifdef CONFIG_LDM_PARTITION ldm_partition, /* this must come before msdos */ #endif @@ -75,6 +82,20 @@ NULL }; +#ifdef CONFIG_DEVFS_GUID +static devfs_handle_t guid_top_handle; + +#define GUID_UNPARSED_LEN 36 +static void +uuid_unparse_1(efi_guid_t *guid, char *out) +{ + sprintf(out, "%08x-%04x-%04x-%02x%02x-%02x%02x%02x%02x%02x%02x", + guid->data1, guid->data2, guid->data3, + guid->data4[0], guid->data4[1], guid->data4[2], guid->data4[3], + guid->data4[4], guid->data4[5], guid->data4[6], guid->data4[7]); +} +#endif + /* * This is ucking fugly but its probably the best thing for 2.4.x * Take it as a clear reminder than we should put the device name @@ -288,6 +309,101 @@ devfs_register_partitions (hd, i, hd->sizes ? 0 : 1); } +#ifdef CONFIG_DEVFS_GUID +/* + devfs_register_guid: create a /dev/guid entry for a disk or partition + if it has a GUID. + + The /dev/guid entry will be a symlink to the "real" devfs device. + It is marked as "slave" of the real device, + to be automatically unregistered by devfs if that device is unregistered. + + If the partition already had a /dev/guid entry, delete (unregister) it. + (If the disk was repartitioned, it's likely the old GUID entry will be wrong). + + dev, minor: Device for which an entry is to be created. + + Prerequisites: dev->part[minor].guid must be either NULL or point + to a valid kmalloc'ed GUID. +*/ + +static void devfs_register_guid (struct gendisk *dev, int minor) +{ + efi_guid_t *guid = dev->part[minor].guid; + devfs_handle_t guid_handle, slave, + real_master = dev->part[minor].de; + devfs_handle_t master = real_master; + char guid_link[GUID_UNPARSED_LEN + 1]; + char dirname[128]; + int pos, st; + + if (!guid_top_handle) + guid_top_handle = devfs_mk_dir (NULL, "guid", NULL); + + if (!guid || !master) return; + + do { + slave = devfs_get_unregister_slave (master); + if (slave) { + if (slave == master || slave == real_master) { + printk (KERN_WARNING + "devfs_register_guid: infinite slave loop!\n"); + return; + } else if (devfs_get_parent (slave) == guid_top_handle) { + printk (KERN_INFO + "devfs_register_guid: unregistering %s\n", + devfs_get_name (slave, NULL)); + devfs_unregister_slave (master); + slave = NULL; + } else + master = slave; + }; + } while (slave); + + uuid_unparse_1 (guid, guid_link); + pos = devfs_generate_path (real_master, dirname + 3, + sizeof (dirname) - 3); + if (pos < 0) { + printk (KERN_WARNING + "devfs_register_guid: error generating path: %d\n", + pos); + return; + }; + + strncpy (dirname + pos, "../", 3); + + st = devfs_mk_symlink (guid_top_handle, guid_link, + DEVFS_FL_DEFAULT, + dirname + pos, &guid_handle, NULL); + + if (st < 0) { + printk ("Error %d creating symlink\n", st); + } else { + devfs_auto_unregister (master, guid_handle); + }; +}; + +/* + free_disk_guids: kfree all guid data structures alloced for + the disk device specified by (dev, minor) and all its partitions. + + This function does not remove symlinks in /dev/guid. +*/ +static void free_disk_guids (struct gendisk *dev, int minor) +{ + int i; + efi_guid_t *guid; + + for (i = 0; i < dev->max_p; i++) { + guid = dev->part[minor + i].guid; + if (!guid) continue; + kfree (guid); + dev->part[minor + i].guid = NULL; + }; +} + +#endif /* CONFIG_DEVFS_GUID */ + #ifdef CONFIG_DEVFS_FS static void devfs_register_partition (struct gendisk *dev, int minor, int part) { @@ -296,7 +412,11 @@ unsigned int devfs_flags = DEVFS_FL_DEFAULT; char devname[16]; - if (dev->part[minor + part].de) return; + /* Even if the devfs handle is still up-to-date, + the GUID entry probably isn't */ + if (dev->part[minor + part].de) + goto do_guid; + dir = devfs_get_parent (dev->part[minor].de); if (!dir) return; if ( dev->flags && (dev->flags[devnum] & GENHD_FL_REMOVABLE) ) @@ -307,6 +427,11 @@ dev->major, minor + part, S_IFBLK | S_IRUSR | S_IWUSR, dev->fops, NULL); + do_guid: +#ifdef CONFIG_DEVFS_GUID + devfs_register_guid (dev, minor + part); +#endif + return; } static struct unique_numspace disc_numspace = UNIQUE_NUMBERSPACE_INITIALISER; @@ -320,7 +445,9 @@ char dirname[64], symlink[16]; static devfs_handle_t devfs_handle; - if (dev->part[minor].de) return; + if (dev->part[minor].de) + goto do_guid; + if ( dev->flags && (dev->flags[devnum] & GENHD_FL_REMOVABLE) ) devfs_flags |= DEVFS_FL_REMOVABLE; if (dev->de_arr) { @@ -348,6 +475,12 @@ devfs_auto_unregister (dev->part[minor].de, slave); if (!dev->de_arr) devfs_auto_unregister (slave, dir); + + do_guid: +#ifdef CONFIG_DEVFS_GUID + devfs_register_guid (dev, minor); +#endif + return; } #endif /* CONFIG_DEVFS_FS */ @@ -371,6 +504,9 @@ dev->part[minor].de = NULL; devfs_dealloc_unique_number (&disc_numspace, dev->part[minor].number); +# ifdef CONFIG_DEVFS_GUID + free_disk_guids (dev, minor); +# endif } #endif /* CONFIG_DEVFS_FS */ } @@ -388,8 +524,21 @@ void register_disk(struct gendisk *gdev, kdev_t dev, unsigned minors, struct block_device_operations *ops, long size) { + int i; + if (!gdev) return; + +#ifdef CONFIG_DEVFS_GUID + /* Initialize all guid fields to NULL (=^ not kmalloc'ed). + It is assumed that drivers call register_disk after + allocating the gen_hd structure, and call grok_partitions + directly for a revalidate event, as those drives I've inspected + (among which hd and sd) do. */ + for (i = 0; i < gdev->max_p; i++) + gdev->part[MINOR(dev) + i].guid = NULL; +#endif + grok_partitions(gdev, MINOR(dev)>>gdev->minor_shift, minors, size); } @@ -407,6 +556,13 @@ if (!size || minors == 1) return; +#ifdef CONFIG_DEVFS_GUID + /* In case this is a revalidation, free GUID memory. + On the first call for this device, + register_disk has set all entries to NULL, + and nothing will happen. */ + free_disk_guids (dev, first_minor); +#endif check_partition(dev, MKDEV(dev->major, first_minor), 1 + first_minor); /* diff -urN linux-2.4.10/fs/partitions/efi.c linux-2.4.10-lia/fs/partitions/efi.c --- linux-2.4.10/fs/partitions/efi.c Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/fs/partitions/efi.c Tue Jun 26 22:33:56 2001 @@ -0,0 +1,633 @@ +/************************************************************ + * EFI GUID Partition Table handling + * Per Intel EFI Specification v0.99 + * http://developer.intel.com/technology/efi/efi.htm + * efi.[ch] by Matt Domsch + * Copyright 2000 Dell Computer Corporation + * + * Note, the EFI Specification, v0.99, has a reference to + * Dr. Dobbs Journal, May 1994 (actually it's in May 1992) + * but that isn't the CRC function being used by EFI. Intel's + * EFI Sample Implementation shows that they use the same function + * as was COPYRIGHT (C) 1986 Gary S. Brown. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * + * TODO: + * + * Changelog: + * Tue Dec 5 2000 Matt Domsch + * - Moved crc32() to linux/lib, added efi_crc32(). + * + * Thu Nov 30 2000 Matt Domsch + * - Replaced Intel's CRC32 function with an equivalent + * non-license-restricted version. + * + * Wed Oct 25 2000 Matt Domsch + * - Fixed the LastLBA() call to return the proper last block + * + * Thu Oct 12 2000 Matt Domsch + * - Thanks to Andries Brouwer for his debugging assistance. + * - Code works, detects all the partitions. + * + ************************************************************/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "check.h" +#include "efi.h" + +#if CONFIG_BLK_DEV_MD +extern void md_autodetect_dev(kdev_t dev); +#endif + + +#undef EFI_DEBUG +#ifdef EFI_DEBUG +static char *efi_printk_level = KERN_DEBUG; +#define debug_printk printk +#else +#define debug_printk(...) +#endif + +/************************************************************ + * efi_crc32() + * Requires: + * - a buffer of length len + * Modifies: nothing + * Returns: + * EFI-style CRC32 value for buf + * + * This function uses the crc32 function by Gary S. Brown, + * but seeds the function with ~0, and xor's with ~0 at the end. + ************************************************************/ + +u32 static inline +efi_crc32(const void *buf, unsigned long len) +{ + return (crc32(buf, len, ~0L) ^ ~0L); +} + + + + +/************************************************************ + * IsLegacyMBRValid() + * Requires: + * - mbr is a pointer to a legacy mbr structure + * Modifies: nothing + * Returns: + * 1 on true + * 0 on false + ************************************************************/ +static inline int +IsLegacyMBRValid(LegacyMBR_t *mbr) +{ + return (mbr ? (mbr->Signature == MSDOS_MBR_SIGNATURE) : 0); +} + + + +/************************************************************ + * LastLBA() + * Requires: + * - struct gendisk hd + * - kdev_t dev + * Modifies: nothing + * Returns: + * Last LBA value on success. This is stored (by sd and + * ide-geometry) in + * the part[0] entry for this disk, and is the number of + * physical sectors available on the disk. + * 0 on error + ************************************************************/ +u64 +LastLBA(struct gendisk *hd, kdev_t dev) +{ + if (!hd || !hd->part) return 0; + return hd->part[MINOR(dev)].nr_sects - 1; +} + + +/************************************************************ + * ReadLBA() + * Requires: + * - hd is our disk device. + * - dev is our device major number + * - lba is the logical block address desired (disk hardsector number) + * - buffer is a buffer of size size into which data copied + * - size_t count is size of the read (in bytes) + * Modifies: + * - buffer + * Returns: + * - count of bytes read + * - 0 on error + * Bugs: + * - bread() takes second argument as a signed int, not a u64. + * This is because getblk() takes the block number as a signed int. + * This overflow is known on l-k. We overflow at about 1TB. + * + ************************************************************/ + +static size_t +ReadLBA(struct gendisk *hd, kdev_t dev, u64 _lba, u8 *buffer, size_t count) +{ + struct buffer_head *bh; + size_t totalreadcount = 0, bytesread; + int lba = (_lba & 0x7FFFFFFF), i, blockstoread, blocksize; + debug_printk(efi_printk_level "ReadLBA(%p,%s,%x,%p,%x)\n", + hd, kdevname(dev), lba, buffer, count); + + if (!hd || !buffer || !count) return 0; + + + blocksize = get_hardsect_size(dev); + blockstoread = count / blocksize; + if (count % blocksize) blockstoread += 1; + debug_printk(efi_printk_level "about to read %d blocks\n", + blockstoread); + + + for (i=0; i bh->b_size ? bh->b_size : count); + memcpy(buffer, bh->b_data, bytesread); + + buffer += bytesread; /* Advance the buffer pointer */ + totalreadcount += bytesread; /* Advance the total read count */ + count -= bytesread; /* Subtract bytesread from count */ + + brelse(bh); + } + + return totalreadcount; +} + +void +PrintGuidPartitionTableHeader(GuidPartitionTableHeader_t *gpt) +{ + debug_printk(efi_printk_level "GUID Partition Table Header\n"); + if (!gpt) return; + debug_printk(efi_printk_level "Signature : %lx\n", + gpt->Signature); + debug_printk(efi_printk_level "Revision : %x\n", + gpt->Revision); + debug_printk(efi_printk_level "HeaderSize : %x\n", + gpt->HeaderSize); + debug_printk(efi_printk_level "HeaderCRC32 : %x\n", + gpt->HeaderCRC32); + debug_printk(efi_printk_level "MyLBA : %lx\n", + gpt->MyLBA); + debug_printk(efi_printk_level "AlternateLBA : %lx\n", + gpt->AlternateLBA); + debug_printk(efi_printk_level "FirstUsableLBA : %lx\n", + gpt->FirstUsableLBA); + debug_printk(efi_printk_level "LastUsableLBA : %lx\n", + gpt->LastUsableLBA); + + debug_printk(efi_printk_level "PartitionEntryLBA : %lx\n", + gpt->PartitionEntryLBA); + debug_printk(efi_printk_level "NumberOfPartitionEntries : %x\n", + gpt->NumberOfPartitionEntries); + debug_printk(efi_printk_level "SizeOfPartitionEntry : %x\n", + gpt->SizeOfPartitionEntry); + debug_printk(efi_printk_level "PartitionEntryArrayCRC32 : %x\n", + gpt->PartitionEntryArrayCRC32); + + return; +} + + + +/************************************************************ + * ReadGuidPartitionEntries() + * Requires: + * - filedes is an open file descriptor, suitable for reading + * - lba is the Logical Block Address of the partition table + * - gpt is a buffer into which the GPT will be put + * Modifies: + * - filedes file and pointer + * - gpt + * Returns: + * pte on success + * NULL on error + * Notes: remember to free pte when you're done! + ************************************************************/ +GuidPartitionEntry_t * +ReadGuidPartitionEntries(struct gendisk *hd, kdev_t dev, + GuidPartitionTableHeader_t *gpt) +{ + size_t count; + GuidPartitionEntry_t *pte; + if (!hd || !gpt) return NULL; + + count = gpt->NumberOfPartitionEntries * gpt->SizeOfPartitionEntry; + debug_printk(efi_printk_level "ReadGPTEs() kmallocing %x bytes\n", + count); + if (!count) return NULL; + pte = kmalloc(count, GFP_KERNEL); + if (!pte) return NULL; + memset(pte, 0, count); + + if (ReadLBA(hd, dev, gpt->PartitionEntryLBA, (u8 *)pte, + count) < count) { + kfree(pte); + return NULL; + } + return pte; +} + + + +/************************************************************ + * ReadGuidPartitionTableHeader() + * Requires: + * - hd is our struct gendisk + * - dev is our device major number + * - lba is the Logical Block Address of the partition table + * - gpt is a buffer into which the GPT will be put + * - pte is a buffer into which the PTEs will be put + * Modifies: + * - gpt and pte + * Returns: + * 1 on success + * 0 on error + ************************************************************/ + +GuidPartitionTableHeader_t * +ReadGuidPartitionTableHeader(struct gendisk *hd, kdev_t dev, u64 lba) + +{ + GuidPartitionTableHeader_t *gpt; + if (!hd) return NULL; + + gpt = kmalloc(sizeof(GuidPartitionTableHeader_t), GFP_KERNEL); + if (!gpt) return NULL; + memset(gpt, 0, sizeof(GuidPartitionTableHeader_t)); + + debug_printk(efi_printk_level "GPTH() calling ReadLBA().\n"); + if (ReadLBA(hd, dev, lba, (u8 *)gpt, + sizeof(GuidPartitionTableHeader_t)) < + sizeof(GuidPartitionTableHeader_t)) { + debug_printk(efi_printk_level "ReadGPTH(%lx) read failed.\n", + lba); + kfree(gpt); + return NULL; + } + PrintGuidPartitionTableHeader(gpt); + + return gpt; +} + + + +/************************************************************ + * IsGuidPartitionTableValid() + * Requires: + * - gd points to our struct gendisk + * - dev is our device major number + * - lba is the logical block address of the GPTH to test + * - gpt is a GPTH if it's valid + * - ptes is a PTEs if it's valid + * Modifies: + * - gpt and ptes + * Returns: + * 1 if valid + * 0 on error + ************************************************************/ +static int +IsGuidPartitionTableValid(struct gendisk *hd, kdev_t dev, u64 lba, + GuidPartitionTableHeader_t **gpt, + GuidPartitionEntry_t **ptes) +{ + u32 crc, origcrc; + + if (!hd || !gpt || !ptes) return 0; + if (!(*gpt = ReadGuidPartitionTableHeader(hd, dev, lba))) return 0; + + /* Check the GUID Partition Table Signature */ + if ((*gpt)->Signature != GUID_PT_HEADER_SIGNATURE) { + debug_printk(efi_printk_level "GUID Partition Table Header Signature is wrong: %x != %x\n", (*gpt)->Signature, GUID_PT_HEADER_SIGNATURE); + kfree(*gpt); + *gpt = NULL; + return 0; + } + + /* Check the GUID Partition Table CRC */ + origcrc = (*gpt)->HeaderCRC32; + (*gpt)->HeaderCRC32 = 0; + crc = efi_crc32((const unsigned char *)(*gpt), (*gpt)->HeaderSize); + + + if (crc != origcrc) { + debug_printk(efi_printk_level "GUID Partition Table Header CRC is wrong: %x != %x\n", (*gpt)->HeaderCRC32, origcrc); + kfree(*gpt); + *gpt = NULL; + return 0; + } + (*gpt)->HeaderCRC32 = origcrc; + + /* Check that the MyLBA entry points to the LBA that contains + * the GUID Partition Table */ + if ((*gpt)->MyLBA != lba) { + debug_printk(efi_printk_level "GPT MyLBA incorrect: %lx != %lx\n", (*gpt)->MyLBA, lba); + kfree(*gpt); + *gpt = NULL; + return 0; + } + + if (!(*ptes = ReadGuidPartitionEntries(hd, dev, *gpt))) { + debug_printk(efi_printk_level "read PTEs failed.\n"); + kfree(*gpt); + *gpt = NULL; + return 0; + } + + /* Check the GUID Partition Entry Array CRC */ + crc = efi_crc32((const unsigned char *)(*ptes), + (*gpt)->NumberOfPartitionEntries * + (*gpt)->SizeOfPartitionEntry); + + if (crc != (*gpt)->PartitionEntryArrayCRC32) { + debug_printk(efi_printk_level "GUID Partitition Entry Array CRC check failed.\n"); + kfree(*gpt); + *gpt = NULL; + kfree(*ptes); + *ptes = NULL; + return 0; + } + + + /* We're done, all's well */ + return 1; +} + + + +/************************************************************ + * FindValidGPT() + * Requires: + * - gd points to our struct gendisk + * - dev is our device major number + * - gpt is a GPTH if it's valid + * - ptes is a PTE + * Modifies: + * - gpt & ptes + * Returns: + * 1 if valid + * 0 on error + ************************************************************/ +static int +FindValidGPT(struct gendisk *hd, kdev_t dev, + GuidPartitionTableHeader_t **gpt, + GuidPartitionEntry_t **ptes) +{ + int rc = 0; + GuidPartitionTableHeader_t *pgpt = NULL, *agpt = NULL; + GuidPartitionEntry_t *pptes = NULL, *aptes = NULL; + u64 lastlba; + if (!hd || !gpt || !ptes) return 0; + + lastlba = LastLBA(hd, dev); + /* Check the Primary GPT */ + rc = IsGuidPartitionTableValid(hd, dev, 1, &pgpt, &pptes); + if (rc) { + /* Primary GPT is OK, check the alternate and warn if bad */ + rc = IsGuidPartitionTableValid(hd, dev, pgpt->AlternateLBA, + &agpt, &aptes); + if (!rc){ + printk(KERN_WARNING "Alternate GPT is invalid, using primary GPT.\n"); + } + + *gpt = pgpt; + *ptes = pptes; + if (agpt) kfree(agpt); + if (aptes) kfree(aptes); + return 1; + } /* if primary is valid */ + else { + /* Primary GPT is bad, check the Alternate GPT */ + rc = IsGuidPartitionTableValid(hd, dev, lastlba, + &agpt, &aptes); + if (rc) { + /* Primary is bad, alternate is good. + Return values from the alternate and warn. + */ + printk(KERN_WARNING "Primary GPT is invalid, using alternate GPT.\n"); + *gpt = agpt; + *ptes = aptes; + return 1; + } + else { + /* Primary is bad, alternate is bad, try "other" + * alternate. This is necessary because if we + * have an odd-sized disk, user-space might + * have put the alternate in block lastlba-1. + */ + if (!(lastlba & 1)) { + lastlba--; + rc = IsGuidPartitionTableValid(hd, dev, + lastlba, + &agpt, &aptes); + if (rc) { + /* Primary is bad, alternate is good. + * Return values from the alternate + * and warn. + */ + printk("Primary GPT is invalid, using alternate GPT.\n"); + *gpt = agpt; + *ptes = aptes; + return 1; + } + } + } + } + /* Both primary and alternate GPTs are bad. + * This isn't our disk, return 0. + */ + return 0; +} + +#ifdef CONFIG_DEVFS_GUID +/* set_partition_guid */ +/* Fill in the GUID field of the partition. + It is set to NULL by register_disk before. */ +static void set_partition_guid (struct gendisk *hd, + const int minor, + const efi_guid_t *guid) +{ + efi_guid_t *part_guid = hd->part[minor].guid; + + if (!guid || !hd) return; + + part_guid = kmalloc (sizeof (efi_guid_t), GFP_KERNEL); + + if (part_guid) { + memcpy (part_guid, guid, sizeof (efi_guid_t)); + } else { + printk (KERN_WARNING + "add_gpt_partitions: cannot allocate GUID memory!\n"); + }; + + hd->part[minor].guid = part_guid; +} +#endif /* CONFIG_DEVFS_GUID */ + +/* + * Create devices for each entry in the GUID Partition Table Entries. + * The first block of each partition is a Legacy MBR. + * + * We do not create a Linux partition for GPT, but + * only for the actual data partitions. + * Returns: + * -1 if unable to read the partition table + * 0 if this isn't our partition table + * 1 if successful + * + */ + +static int +add_gpt_partitions(struct gendisk *hd, kdev_t dev, int nextminor) +{ + GuidPartitionTableHeader_t *gpt = NULL; + GuidPartitionEntry_t *ptes = NULL; + u32 i, nummade=0; + + efi_guid_t unusedGuid = UNUSED_ENTRY_GUID; +#if CONFIG_BLK_DEV_MD + efi_guid_t raidGuid = PARTITION_LINUX_RAID_GUID; +#endif + + if (!hd) return -1; + + if (!FindValidGPT(hd, dev, &gpt, &ptes) || + !gpt || !ptes) { + if (gpt) kfree(gpt); + if (ptes) kfree(ptes); + return 0; + } + + debug_printk(efi_printk_level "GUID Partition Table is valid! Yea!\n"); + +#ifdef CONFIG_DEVFS_GUID + set_partition_guid (hd, nextminor - 1, &(gpt->DiskGUID)); +#endif + + for (i = 0; i < gpt->NumberOfPartitionEntries && + nummade < (hd->max_p - 1); i++) { + if (!efi_guidcmp(unusedGuid, ptes[i].PartitionTypeGuid)) + continue; + + add_gd_partition(hd, nextminor, ptes[i].StartingLBA, + (ptes[i].EndingLBA-ptes[i].StartingLBA + 1)); + +#ifdef CONFIG_DEVFS_GUID + set_partition_guid (hd, nextminor, &(ptes[i].UniquePartitionGuid)); +#endif + + /* If there's this is a RAID volume, tell md */ +#if CONFIG_BLK_DEV_MD + if (!efi_guidcmp(raidGuid, ptes[i].PartitionTypeGuid)) { + md_autodetect_dev(MKDEV(MAJOR(dev),nextminor)); + } +#endif + nummade++; + nextminor++; + + } + kfree(ptes); + kfree(gpt); + printk("\n"); + return 1; + +} + + +/* + * efi_partition() + * + * If the first block on the disk is a legacy MBR, + * it got handled already by msdos_partition(). + * If it's a Protective MBR, we'll handle it here. + * + * Returns: + * -1 if unable to read the partition table + * 0 if this isn't our partitoin table + * 1 if successful + * + */ + +int +efi_partition(struct gendisk *hd, kdev_t dev, + unsigned long first_sector, int first_part_minor) { + int hardblocksize = get_hardsect_size(dev); + int orig_blksize_size = BLOCK_SIZE; + int rc = 0; + + /* Need to change the block size that the block layer uses */ + if (blksize_size[MAJOR(dev)]){ + orig_blksize_size = blksize_size[MAJOR(dev)][MINOR(dev)]; + } + + if (orig_blksize_size != hardblocksize) + set_blocksize(dev, hardblocksize); + + rc = add_gpt_partitions(hd, dev, first_part_minor); + + /* change back */ + if (orig_blksize_size != hardblocksize) + set_blocksize(dev, orig_blksize_size); + + return rc; +} + + +/* + * Overrides for Emacs so that we follow Linus's tabbing style. + * Emacs will notice this stuff at the end of the file and automatically + * adjust the settings for this buffer only. This must remain at the end + * of the file. + * --------------------------------------------------------------------------- + * Local variables: + * c-indent-level: 4 + * c-brace-imaginary-offset: 0 + * c-brace-offset: -4 + * c-argdecl-indent: 4 + * c-label-offset: -4 + * c-continued-statement-offset: 4 + * c-continued-brace-offset: 0 + * indent-tabs-mode: nil + * tab-width: 8 + * End: + */ diff -urN linux-2.4.10/fs/partitions/efi.h linux-2.4.10-lia/fs/partitions/efi.h --- linux-2.4.10/fs/partitions/efi.h Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/fs/partitions/efi.h Mon Sep 24 23:00:15 2001 @@ -0,0 +1,154 @@ +/************************************************************ + * EFI GUID Partition Table + * Per Intel EFI Specification v0.99 + * http://developer.intel.com/technology/efi/efi.htm + * + * By Matt Domsch Fri Sep 22 22:15:56 CDT 2000 + * Copyright 2000 Dell Computer Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + ************************************************************/ + +#ifndef FS_PART_EFI_H_INCLUDED +#define FS_PART_EFI_H_INCLUDED + +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#define MSDOS_MBR_SIGNATURE 0xaa55 +#define EFI_PMBR_OSTYPE_EFI 0xEF +#define EFI_PMBR_OSTYPE_EFI_GPT 0xEE + +#define GUID_PT_BLOCK_SIZE 512 + +#define GUID_PT_HEADER_SIGNATURE 0x5452415020494645L +#define GUID_PT_HEADER_REVISION_V1 0x00010000 +#define GUID_PT_HEADER_REVISION_V0_99 0x00000099 +#define UNUSED_ENTRY_GUID \ + ((efi_guid_t) { 0x00000000, 0x0000, 0x0000, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }}) +#define PARTITION_SYSTEM_GUID \ +((efi_guid_t) { 0xC12A7328, 0xF81F, 0x11d2, { 0xBA, 0x4B, 0x00, 0xA0, 0xC9, 0x3E, 0xC9, 0x3B }}) +#define LEGACY_MBR_PARTITION_GUID \ + ((efi_guid_t) { 0x024DEE41, 0x33E7, 0x11d3, { 0x9D, 0x69, 0x00, 0x08, 0xC7, 0x81, 0xF3, 0x9F }}) +#define PARTITION_MSFT_RESERVED_GUID \ + ((efi_guid_t) { 0xE3C9E316, 0x0B5C, 0x4DB8, { 0x81, 0x7D, 0xF9, 0x2D, 0xF0, 0x02, 0x15, 0xAE }}) +#define PARTITION_BASIC_DATA_GUID \ + ((efi_guid_t) { 0xEBD0A0A2, 0xB9E5, 0x4433, { 0x87, 0xC0, 0x68, 0xB6, 0xB7, 0x26, 0x99, 0xC7 }}) +#define PARTITION_LINUX_RAID_GUID \ + ((efi_guid_t) { 0xa19d880f, 0x05fc, 0x4d3b, { 0xa0, 0x06, 0x74, 0x3f, 0x0f, 0x84, 0x91, 0x1e }}) +#define PARTITION_LINUX_SWAP_GUID \ + ((efi_guid_t) { 0x0657fd6d, 0xa4ab, 0x43c4, { 0x84, 0xe5, 0x09, 0x33, 0xc8, 0x4b, 0x4f, 0x4f }}) + +typedef struct _GuidPartitionTableHeader_t { + u64 Signature; + u32 Revision; + u32 HeaderSize; + u32 HeaderCRC32; + u32 Reserved1; + u64 MyLBA; + u64 AlternateLBA; + u64 FirstUsableLBA; + u64 LastUsableLBA; + efi_guid_t DiskGUID; + u64 PartitionEntryLBA; + u32 NumberOfPartitionEntries; + u32 SizeOfPartitionEntry; + u32 PartitionEntryArrayCRC32; + u8 Reserved2[GUID_PT_BLOCK_SIZE - 92]; +} GuidPartitionTableHeader_t; + +typedef struct _GuidPartitionEntryAttributes_t { + __u64 RequiredToFunction:1; + __u64 Reserved:63; +} GuidPartitionEntryAttributes_t; + +typedef struct _GuidPartitionEntry_t { + efi_guid_t PartitionTypeGuid; + efi_guid_t UniquePartitionGuid; + u64 StartingLBA; + u64 EndingLBA; + GuidPartitionEntryAttributes_t Attributes; + efi_char16_t PartitionName[72/sizeof(efi_char16_t)]; +} GuidPartitionEntry_t; + + + +typedef struct _PartitionRecord_t { + u8 BootIndicator; /* Not used by EFI firmware. Set to 0x80 to indicate that this + is the bootable legacy partition. */ + u8 StartHead; /* Start of partition in CHS address, not used by EFI firmware. */ + u8 StartSector; /* Start of partition in CHS address, not used by EFI firmware. */ + u8 StartTrack; /* Start of partition in CHS address, not used by EFI firmware. */ + u8 OSType; /* OS type. A value of 0xEF defines an EFI system partition. + Other values are reserved for legacy operating systems, and + allocated independently of the EFI specification. */ + u8 EndHead; /* End of partition in CHS address, not used by EFI firmware. */ + u8 EndSector; /* End of partition in CHS address, not used by EFI firmware. */ + u8 EndTrack; /* End of partition in CHS address, not used by EFI firmware. */ + u32 StartingLBA; /* Starting LBA address of the partition on the disk. Used by + EFI firmware to define the start of the partition. */ + u32 SizeInLBA; /* Size of partition in LBA. Used by EFI firmware to determine + the size of the partition. */ +} PartitionRecord_t; + +typedef struct _LegacyMBR_t { + u8 BootCode[440]; + u32 UniqueMBRSignature; + u16 Unknown; + PartitionRecord_t PartitionRecord[4]; + u16 Signature; +} __attribute__ ((packed)) LegacyMBR_t; + + + +#define EFI_GPT_PRIMARY_PARTITION_TABLE_LBA 1 + +/* Functions */ +extern int +efi_partition(struct gendisk *hd, kdev_t dev, + unsigned long first_sector, int first_part_minor); + + + + +#endif + +/* + * Overrides for Emacs so that we follow Linus's tabbing style. + * Emacs will notice this stuff at the end of the file and automatically + * adjust the settings for this buffer only. This must remain at the end + * of the file. + * -------------------------------------------------------------------------- + * Local variables: + * c-indent-level: 4 + * c-brace-imaginary-offset: 0 + * c-brace-offset: -4 + * c-argdecl-indent: 4 + * c-label-offset: -4 + * c-continued-statement-offset: 4 + * c-continued-brace-offset: 0 + * indent-tabs-mode: nil + * tab-width: 8 + * End: + */ diff -urN linux-2.4.10/fs/partitions/msdos.c linux-2.4.10-lia/fs/partitions/msdos.c --- linux-2.4.10/fs/partitions/msdos.c Sat Jul 28 12:50:13 2001 +++ linux-2.4.10-lia/fs/partitions/msdos.c Mon Aug 13 23:46:45 2001 @@ -36,6 +36,10 @@ #include "check.h" #include "msdos.h" +#ifdef CONFIG_EFI_PARTITION +#include "efi.h" +#endif + #if CONFIG_BLK_DEV_MD extern void md_autodetect_dev(kdev_t dev); #endif @@ -454,6 +458,16 @@ return 0; } p = (struct partition *) (data + 0x1be); +#ifdef CONFIG_EFI_PARTITION + for (i=1 ; i<=4 ; i++,p++) { + /* If this is an EFI GPT disk, msdos should ignore it. */ + if (SYS_IND(p) == EFI_PMBR_OSTYPE_EFI_GPT) { + bforget(bh); + return 0; + } + } + p = (struct partition *) (data + 0x1be); +#endif #ifdef CONFIG_BLK_DEV_IDE if (!tested_for_xlate++) { /* Do this only once per disk */ diff -urN linux-2.4.10/fs/proc/base.c linux-2.4.10-lia/fs/proc/base.c --- linux-2.4.10/fs/proc/base.c Fri Jul 20 12:39:56 2001 +++ linux-2.4.10-lia/fs/proc/base.c Mon Jul 23 13:51:12 2001 @@ -419,7 +419,24 @@ } #endif +static loff_t mem_lseek(struct file * file, loff_t offset, int orig) +{ + switch (orig) { + case 0: + file->f_pos = offset; + break; + case 1: + file->f_pos += offset; + break; + default: + return -EINVAL; + } + force_successful_syscall_return(); + return file->f_pos; +} + static struct file_operations proc_mem_operations = { + llseek: mem_lseek, read: mem_read, write: mem_write, open: mem_open, diff -urN linux-2.4.10/include/asm-alpha/processor.h linux-2.4.10-lia/include/asm-alpha/processor.h --- linux-2.4.10/include/asm-alpha/processor.h Mon Sep 24 15:08:23 2001 +++ linux-2.4.10-lia/include/asm-alpha/processor.h Mon Sep 24 15:23:56 2001 @@ -169,4 +169,25 @@ +#define ARCH_HAS_PREFETCH +#define ARCH_HAS_PREFETCHW +#define ARCH_HAS_SPINLOCK_PREFETCH + +extern inline void prefetch(const void *ptr) +{ + __asm__ ("ldl $31,%0" : : "m"(*(char *)ptr)); +} + +extern inline void prefetchw(const void *ptr) +{ + __asm__ ("ldl $31,%0" : : "m"(*(char *)ptr)); +} + +extern inline void prefetch_spin_lock(const void *ptr) +{ + __asm__ ("ldl $31,%0" : : "m"(*(char *)ptr)); +} + + + #endif /* __ASM_ALPHA_PROCESSOR_H */ diff -urN linux-2.4.10/include/asm-i386/processor.h linux-2.4.10-lia/include/asm-i386/processor.h --- linux-2.4.10/include/asm-i386/processor.h Mon Sep 24 15:08:23 2001 +++ linux-2.4.10-lia/include/asm-i386/processor.h Mon Sep 24 15:23:57 2001 @@ -504,4 +504,32 @@ #endif +/* Prefetch instructions for Pentium III and AMD Athlon */ +#ifdef CONFIG_MPENTIUMIII + +#define ARCH_HAS_PREFETCH +extern inline void prefetch(const void *x) +{ + __asm__ __volatile__ ("prefetchnta (%0)" : : "r"(x)); +} + +#elif CONFIG_X86_USE_3DNOW + +#define ARCH_HAS_PREFETCH +#define ARCH_HAS_PREFETCHW +#define ARCH_HAS_SPINLOCK_PREFETCH + +extern inline void prefetch(const void *x) +{ + __asm__ __volatile__ ("prefetch (%0)" : : "r"(x)); +} + +extern inline void prefetchw(const void *x) +{ + __asm__ __volatile__ ("prefetch (%0)" : : "r"(x)); +} +#define prefetch_spin_lock(x) prefetchw(x) + +#endif + #endif /* __ASM_I386_PROCESSOR_H */ diff -urN linux-2.4.10/include/asm-ia64/acpi-ext.h linux-2.4.10-lia/include/asm-ia64/acpi-ext.h --- linux-2.4.10/include/asm-ia64/acpi-ext.h Tue Jul 31 10:30:09 2001 +++ linux-2.4.10-lia/include/asm-ia64/acpi-ext.h Tue Aug 14 00:01:46 2001 @@ -9,7 +9,7 @@ * Copyright (C) 1999 VA Linux Systems * Copyright (C) 1999 Walt Drummond * Copyright (C) 2000 Intel Corp. - * Copyright (C) 2000 J.I. Lee + * Copyright (C) 2000,2001 J.I. Lee * ACPI 2.0 specification */ @@ -189,9 +189,16 @@ u32 global_vector; } acpi20_entry_platform_src_t; +/* constants for interrupt routing API for device drivers */ +#define ACPI20_ENTRY_PIS_PMI 1 +#define ACPI20_ENTRY_PIS_INIT 2 +#define ACPI20_ENTRY_PIS_CPEI 3 +#define ACPI_MAX_PLATFORM_IRQS 4 + extern int acpi20_parse(acpi20_rsdp_t *); extern int acpi_parse(acpi_rsdp_t *); extern const char *acpi_get_sysname (void); +extern int acpi_request_vector(u32 int_type); extern void (*acpi_idle) (void); /* power-management idle function, if any */ #pragma pack() diff -urN linux-2.4.10/include/asm-ia64/ia32.h linux-2.4.10-lia/include/asm-ia64/ia32.h --- linux-2.4.10/include/asm-ia64/ia32.h Tue Jul 31 10:30:09 2001 +++ linux-2.4.10-lia/include/asm-ia64/ia32.h Mon Sep 24 22:56:58 2001 @@ -33,7 +33,9 @@ typedef __kernel_fsid_t __kernel_fsid_t32; #define IA32_PAGE_SHIFT 12 /* 4KB pages */ -#define IA32_PAGE_SIZE (1ULL << IA32_PAGE_SHIFT) +#define IA32_PAGE_SIZE (1UL << IA32_PAGE_SHIFT) +#define IA32_PAGE_MASK (~(IA32_PAGE_SIZE - 1)) +#define IA32_PAGE_ALIGN(addr) (((addr) + IA32_PAGE_SIZE - 1) & IA32_PAGE_MASK) #define IA32_CLOCKS_PER_SEC 100 /* Cast in stone for IA32 Linux */ #define IA32_TICK(tick) ((unsigned long long)(tick) * IA32_CLOCKS_PER_SEC / CLOCKS_PER_SEC) @@ -46,6 +48,9 @@ __kernel_pid_t32 l_pid; }; +#define F_GETLK64 12 +#define F_SETLK64 13 +#define F_SETLKW64 14 /* sigcontext.h */ /* @@ -103,13 +108,19 @@ #define _IA32_NSIG_BPW 32 #define _IA32_NSIG_WORDS (_IA32_NSIG / _IA32_NSIG_BPW) +#define IA32_SET_SA_HANDLER(ka,handler,restorer) \ + ((ka)->sa.sa_handler = (__sighandler_t) \ + (((unsigned long)(restorer) << 32) \ + | ((handler) & 0xffffffff))) +#define IA32_SA_HANDLER(ka) ((unsigned long) (ka)->sa.sa_handler & 0xffffffff) +#define IA32_SA_RESTORER(ka) ((unsigned long) (ka)->sa.sa_handler >> 32) + typedef struct { unsigned int sig[_IA32_NSIG_WORDS]; } sigset32_t; struct sigaction32 { - unsigned int sa_handler; /* Really a pointer, but need to deal - with 32 bits */ + unsigned int sa_handler; /* Really a pointer, but need to deal with 32 bits */ unsigned int sa_flags; unsigned int sa_restorer; /* Another 32 bit pointer */ sigset32_t sa_mask; /* A 32 bit mask */ @@ -162,6 +173,31 @@ unsigned int __unused5; }; +struct stat64 { + unsigned short st_dev; + unsigned char __pad0[10]; + unsigned int __st_ino; + unsigned int st_mode; + unsigned int st_nlink; + unsigned int st_uid; + unsigned int st_gid; + unsigned short st_rdev; + unsigned char __pad3[10]; + unsigned int st_size_lo; + unsigned int st_size_hi; + unsigned int st_blksize; + unsigned int st_blocks; /* Number 512-byte blocks allocated. */ + unsigned int __pad4; /* future possible st_blocks high bits */ + unsigned int st_atime; + unsigned int __pad5; + unsigned int st_mtime; + unsigned int __pad6; + unsigned int st_ctime; + unsigned int __pad7; /* will be high 32 bits of ctime someday */ + unsigned int st_ino_lo; + unsigned int st_ino_hi; +}; + struct statfs32 { int f_type; int f_bsize; @@ -252,7 +288,7 @@ #define ELF_ARCH EM_386 #define IA32_PAGE_OFFSET 0xc0000000 -#define IA32_STACK_TOP ((IA32_PAGE_OFFSET/3) * 2) +#define IA32_STACK_TOP IA32_PAGE_OFFSET /* * The system segments (GDT, TSS, LDT) have to be mapped below 4GB so the IA-32 engine can @@ -377,7 +413,7 @@ */ #define IA32_FSR_DEFAULT 0x55550000 /* set all tag bits */ -#define IA32_FCR_DEFAULT 0x17800000037fULL /* extended precision, all masks */ +#define IA32_FCR_DEFAULT 0x17800000037fUL /* extended precision, all masks */ #define IA32_PTRACE_GETREGS 12 #define IA32_PTRACE_SETREGS 13 @@ -421,6 +457,7 @@ extern void ia32_init_addr_space (struct pt_regs *regs); extern int ia32_setup_arg_pages (struct linux_binprm *bprm); extern int ia32_exception (struct pt_regs *regs, unsigned long isr); +extern unsigned long ia32_do_mmap (struct file *, unsigned long, unsigned long, int, int, loff_t); #endif /* !CONFIG_IA32_SUPPORT */ diff -urN linux-2.4.10/include/asm-ia64/io.h linux-2.4.10-lia/include/asm-ia64/io.h --- linux-2.4.10/include/asm-ia64/io.h Tue Jul 31 10:30:09 2001 +++ linux-2.4.10-lia/include/asm-ia64/io.h Mon Sep 24 22:26:47 2001 @@ -43,7 +43,7 @@ } static inline void* -phys_to_virt(unsigned long address) +phys_to_virt (unsigned long address) { return (void *) (address + PAGE_OFFSET); } @@ -54,6 +54,7 @@ */ #define bus_to_virt phys_to_virt #define virt_to_bus virt_to_phys +#define page_to_bus page_to_phys # endif /* KERNEL */ diff -urN linux-2.4.10/include/asm-ia64/iosapic.h linux-2.4.10-lia/include/asm-ia64/iosapic.h --- linux-2.4.10/include/asm-ia64/iosapic.h Tue Jul 31 10:30:09 2001 +++ linux-2.4.10-lia/include/asm-ia64/iosapic.h Mon Sep 24 22:05:11 2001 @@ -53,8 +53,17 @@ extern void __init iosapic_init (unsigned long address, unsigned int base_irq, int pcat_compat); +extern int iosapic_register_irq (u32 global_vector, unsigned long polarity, + unsigned long edge_triggered, u32 base_irq, + char *iosapic_address); extern void iosapic_register_legacy_irq (unsigned long irq, unsigned long pin, unsigned long polarity, unsigned long trigger); +extern int iosapic_register_platform_irq (u32 int_type, u32 global_vector, u32 iosapic_vector, + u16 eid, u16 id, unsigned long polarity, + unsigned long edge_triggered, u32 base_irq, + char *iosapic_address); +extern unsigned int iosapic_version (char *addr); + extern void iosapic_pci_fixup (int); # endif /* !__ASSEMBLY__ */ diff -urN linux-2.4.10/include/asm-ia64/ipc.h linux-2.4.10-lia/include/asm-ia64/ipc.h --- linux-2.4.10/include/asm-ia64/ipc.h Sun Feb 6 18:42:40 2000 +++ linux-2.4.10-lia/include/asm-ia64/ipc.h Wed Dec 31 16:00:00 1969 @@ -1,31 +0,0 @@ -#ifndef __i386_IPC_H__ -#define __i386_IPC_H__ - -/* - * These are used to wrap system calls on x86. - * - * See arch/i386/kernel/sys_i386.c for ugly details.. - */ -struct ipc_kludge { - struct msgbuf *msgp; - long msgtyp; -}; - -#define SEMOP 1 -#define SEMGET 2 -#define SEMCTL 3 -#define MSGSND 11 -#define MSGRCV 12 -#define MSGGET 13 -#define MSGCTL 14 -#define SHMAT 21 -#define SHMDT 22 -#define SHMGET 23 -#define SHMCTL 24 - -/* Used by the DIPC package, try and avoid reusing it */ -#define DIPC 25 - -#define IPCCALL(version,op) ((version)<<16 | (op)) - -#endif diff -urN linux-2.4.10/include/asm-ia64/keyboard.h linux-2.4.10-lia/include/asm-ia64/keyboard.h --- linux-2.4.10/include/asm-ia64/keyboard.h Fri Apr 21 16:38:40 2000 +++ linux-2.4.10-lia/include/asm-ia64/keyboard.h Mon Sep 24 23:00:16 2001 @@ -2,16 +2,16 @@ #define _ASM_IA64_KEYBOARD_H /* - * This file contains the ia-64 architecture specific keyboard - * definitions. + * This file contains the ia64 architecture specific keyboard definitions. * - * Copyright (C) 1998, 1999 Hewlett-Packard Co - * Copyright (C) 1998, 1999 David Mosberger-Tang + * Copyright (C) 1998, 1999, 2001 Hewlett-Packard Co + * Copyright (C) 1998, 1999, 2001 David Mosberger-Tang */ # ifdef __KERNEL__ #include +#include #define KEYBOARD_IRQ isa_irq_to_vector(1) #define DISABLE_KBD_DURING_INTERRUPTS 0 @@ -38,6 +38,7 @@ #define INIT_KBD #define SYSRQ_KEY 0x54 +#define E1_PAUSE 119 /* PAUSE key */ /* resource allocation */ #define kbd_request_region() diff -urN linux-2.4.10/include/asm-ia64/machvec.h linux-2.4.10-lia/include/asm-ia64/machvec.h --- linux-2.4.10/include/asm-ia64/machvec.h Thu Apr 5 12:51:47 2001 +++ linux-2.4.10-lia/include/asm-ia64/machvec.h Mon Sep 24 22:20:43 2001 @@ -1,11 +1,11 @@ /* * Machine vector for IA-64. - * + * * Copyright (C) 1999 Silicon Graphics, Inc. * Copyright (C) Srinivasa Thirumalachar * Copyright (C) Vijay Chander * Copyright (C) 1999-2001 Hewlett-Packard Co. - * Copyright (C) 1999-2001 David Mosberger-Tang + * David Mosberger-Tang */ #ifndef _ASM_IA64_MACHVEC_H #define _ASM_IA64_MACHVEC_H @@ -28,6 +28,7 @@ typedef void ia64_mv_cmci_handler_t (int, void *, struct pt_regs *); typedef void ia64_mv_log_print_t (void); typedef void ia64_mv_send_ipi_t (int, int, int, int); +typedef void ia64_mv_global_tlb_purge_t (unsigned long, unsigned long, unsigned long); typedef struct irq_desc *ia64_mv_irq_desc (unsigned int); typedef u8 ia64_mv_irq_to_vector (u8); typedef unsigned int ia64_mv_local_vector_to_irq (u8 vector); @@ -67,6 +68,8 @@ # include # elif defined (CONFIG_IA64_SGI_SN1) # include +# elif defined (CONFIG_IA64_SGI_SN2) +# include # elif defined (CONFIG_IA64_GENERIC) # ifdef MACHVEC_PLATFORM_HEADER @@ -82,6 +85,7 @@ # define platform_log_print ia64_mv.log_print # define platform_pci_fixup ia64_mv.pci_fixup # define platform_send_ipi ia64_mv.send_ipi +# define platform_global_tlb_purge ia64_mv.global_tlb_purge # define platform_pci_dma_init ia64_mv.dma_init # define platform_pci_alloc_consistent ia64_mv.alloc_consistent # define platform_pci_free_consistent ia64_mv.free_consistent @@ -147,6 +151,7 @@ platform_cmci_handler, \ platform_log_print, \ platform_send_ipi, \ + platform_global_tlb_purge, \ platform_pci_dma_init, \ platform_pci_alloc_consistent, \ platform_pci_free_consistent, \ @@ -216,6 +221,9 @@ #endif #ifndef platform_send_ipi # define platform_send_ipi ia64_send_ipi /* default to architected version */ +#endif +#ifndef platform_global_tlb_purge +# define platform_global_tlb_purge ia64_global_tlb_purge /* default to architected version */ #endif #ifndef platform_pci_dma_init # define platform_pci_dma_init swiotlb_init diff -urN linux-2.4.10/include/asm-ia64/machvec_sn1.h linux-2.4.10-lia/include/asm-ia64/machvec_sn1.h --- linux-2.4.10/include/asm-ia64/machvec_sn1.h Thu Apr 5 12:51:47 2001 +++ linux-2.4.10-lia/include/asm-ia64/machvec_sn1.h Mon Sep 24 22:06:06 2001 @@ -5,6 +5,7 @@ extern ia64_mv_irq_init_t sn1_irq_init; extern ia64_mv_map_nr_t sn1_map_nr; extern ia64_mv_send_ipi_t sn1_send_IPI; +extern ia64_mv_global_tlb_purge_t sn1_global_tlb_purge; extern ia64_mv_pci_fixup_t sn1_pci_fixup; extern ia64_mv_inb_t sn1_inb; extern ia64_mv_inw_t sn1_inw; @@ -34,6 +35,7 @@ #define platform_irq_init sn1_irq_init #define platform_map_nr sn1_map_nr #define platform_send_ipi sn1_send_IPI +#define platform_global_tlb_purge sn1_global_tlb_purge #define platform_pci_fixup sn1_pci_fixup #define platform_inb sn1_inb #define platform_inw sn1_inw diff -urN linux-2.4.10/include/asm-ia64/mca.h linux-2.4.10-lia/include/asm-ia64/mca.h --- linux-2.4.10/include/asm-ia64/mca.h Thu Apr 5 12:51:47 2001 +++ linux-2.4.10-lia/include/asm-ia64/mca.h Mon Sep 24 22:58:05 2001 @@ -8,7 +8,7 @@ */ /* XXX use this temporary define for MP systems trying to INIT */ -#define SAL_MPINIT_WORKAROUND +#undef SAL_MPINIT_WORKAROUND #ifndef _ASM_IA64_MCA_H #define _ASM_IA64_MCA_H @@ -61,8 +61,6 @@ IA64_MCA_RENDEZ_CHECKIN_DONE = 0x1 }; -#define IA64_MAXCPUS 64 /* Need to do something about this */ - /* Information maintained by the MC infrastructure */ typedef struct ia64_mc_info_s { u64 imi_mca_handler; @@ -71,7 +69,7 @@ size_t imi_monarch_init_handler_size; u64 imi_slave_init_handler; size_t imi_slave_init_handler_size; - u8 imi_rendez_checkin[IA64_MAXCPUS]; + u8 imi_rendez_checkin[NR_CPUS]; } ia64_mc_info_t; @@ -128,7 +126,11 @@ extern void ia64_mca_rendez_int_handler(int,void *,struct pt_regs *); extern void ia64_mca_wakeup_int_handler(int,void *,struct pt_regs *); extern void ia64_mca_cmc_int_handler(int,void *,struct pt_regs *); -extern void ia64_log_print(int,int,prfunc_t); +extern void ia64_mca_cpe_int_handler(int,void *,struct pt_regs *); +extern void ia64_log_print(int,prfunc_t); +extern void ia64_mca_cmc_vector_setup(void); +extern void ia64_mca_check_errors( void ); +extern u64 ia64_log_get(int, prfunc_t); #define PLATFORM_CALL(fn, args) printk("Platform call TBD\n") diff -urN linux-2.4.10/include/asm-ia64/mca_asm.h linux-2.4.10-lia/include/asm-ia64/mca_asm.h --- linux-2.4.10/include/asm-ia64/mca_asm.h Tue Jul 31 10:30:09 2001 +++ linux-2.4.10-lia/include/asm-ia64/mca_asm.h Tue Aug 14 00:02:22 2001 @@ -41,7 +41,7 @@ */ #define DATA_PA_TO_VA(addr,temp) \ mov temp = 0x7 ;; \ - dep addr = temp, addr, 61, 3; + dep addr = temp, addr, 61, 3;; /* * This macro jumps to the instruction at the given virtual address @@ -74,6 +74,7 @@ \ mov ar.rsc = 0 ; \ ;; \ + srlz.d; \ mov temp2 = ar.bspstore; \ ;; \ DATA_VA_TO_PA(temp2); \ @@ -102,6 +103,8 @@ ;; \ dep temp1 = 0, temp1, PSR_I, 1; \ ;; \ + dep temp1 = 0, temp1, PSR_IC, 1; \ + ;; \ movl temp2 = start_addr; \ mov cr.ipsr = temp1; \ ;; \ @@ -145,6 +148,8 @@ #define VIRTUAL_MODE_ENTER(temp1, temp2, start_addr, old_psr) \ mov temp2 = psr; \ ;; \ + mov old_psr = temp2; \ + ;; \ dep temp2 = 0, temp2, PSR_IC, 2; \ ;; \ mov psr.l = temp2; \ @@ -163,7 +168,7 @@ ;; \ mov temp1 = old_psr; \ ;; \ - mov temp2 = 1 \ + mov temp2 = 1; \ ;; \ dep temp1 = temp2, temp1, PSR_I, 1; \ ;; \ @@ -182,8 +187,10 @@ movl temp2 = start_addr; \ ;; \ mov cr.iip = temp2; \ + ;; \ DATA_PA_TO_VA(sp, temp1); \ DATA_PA_TO_VA(gp, temp2); \ + srlz.i; \ ;; \ nop 1; \ nop 2; \ @@ -246,7 +253,7 @@ mov ar.bspstore=p_bspstore;; \ mov temp=ar.bsp;; \ sub temp=temp,p_bspstore;; \ - st8 [p_stackframe]=temp,8 + st8 [p_stackframe]=temp,8;; /* * rse_return_context @@ -278,28 +285,20 @@ mov ar.rnat=temp;; \ add p_stackframe=-rse_rnat_offset+rse_pfs_offset,p_stackframe;; \ ld8 temp=[p_stackframe];; \ - mov ar.pfs=temp; \ + mov ar.pfs=temp;; \ add p_stackframe=-rse_pfs_offset+rse_ifs_offset,p_stackframe;; \ ld8 temp=[p_stackframe];; \ - mov cr.ifs=temp; \ + mov cr.ifs=temp;; \ add p_stackframe=-rse_ifs_offset+rse_rsc_offset,p_stackframe;; \ ld8 temp=[p_stackframe];; \ mov ar.rsc=temp ; \ - add p_stackframe=-rse_rsc_offset,p_stackframe; \ - mov temp=cr.ipsr;; \ - st8 [p_stackframe]=temp,8; \ - mov temp=cr.iip;; \ - st8 [p_stackframe]=temp,-8; \ mov temp=psr;; \ or temp=temp,psr_mask_reg;; \ mov cr.ipsr=temp;; \ mov temp=ip;; \ add temp=0x30,temp;; \ mov cr.iip=temp;; \ - rfi;; \ - ld8 temp=[p_stackframe],8;; \ - mov cr.ipsr=temp;; \ - ld8 temp=[p_stackframe];; \ - mov cr.iip=temp + srlz.i;; \ + rfi;; #endif /* _ASM_IA64_MCA_ASM_H */ diff -urN linux-2.4.10/include/asm-ia64/mmu_context.h linux-2.4.10-lia/include/asm-ia64/mmu_context.h --- linux-2.4.10/include/asm-ia64/mmu_context.h Thu Apr 5 12:51:47 2001 +++ linux-2.4.10-lia/include/asm-ia64/mmu_context.h Mon Sep 24 23:02:56 2001 @@ -60,7 +60,6 @@ static inline void get_mmu_context (struct mm_struct *mm) { - /* check if our ASN is of an older generation and thus invalid: */ if (mm->context == 0) get_new_mmu_context(mm); } diff -urN linux-2.4.10/include/asm-ia64/module.h linux-2.4.10-lia/include/asm-ia64/module.h --- linux-2.4.10/include/asm-ia64/module.h Mon Sep 24 15:08:24 2001 +++ linux-2.4.10-lia/include/asm-ia64/module.h Mon Sep 24 22:57:00 2001 @@ -14,7 +14,6 @@ #define module_map(x) vmalloc(x) #define module_unmap(x) ia64_module_unmap(x) #define module_arch_init(x) ia64_module_init(x) -#define arch_init_modules(x) do { } while (0) /* * This must match in size and layout the data created by @@ -28,12 +27,23 @@ const char *gp; }; +static inline void +arch_init_modules (struct module *kmod) +{ + static struct archdata archdata; + register char *kernel_gp asm ("gp"); + + archdata.gp = kernel_gp; + kmod->archdata_start = (const char *) &archdata; + kmod->archdata_end = (const char *) (&archdata + 1); +} + /* * functions to add/remove a modules unwind info when * it is loaded or unloaded. */ static inline int -ia64_module_init(struct module *mod) +ia64_module_init (struct module *mod) { struct archdata *archdata; @@ -45,28 +55,23 @@ * Make sure the unwind pointers are sane. */ - if (archdata->unw_table) - { + if (archdata->unw_table) { printk(KERN_ERR "module_arch_init: archdata->unw_table must be zero.\n"); return 1; } - if (!mod_bound(archdata->gp, 0, mod)) - { + if (!mod_bound(archdata->gp, 0, mod)) { printk(KERN_ERR "module_arch_init: archdata->gp out of bounds.\n"); return 1; } - if (!mod_bound(archdata->unw_start, 0, mod)) - { + if (!mod_bound(archdata->unw_start, 0, mod)) { printk(KERN_ERR "module_arch_init: archdata->unw_start out of bounds.\n"); return 1; } - if (!mod_bound(archdata->unw_end, 0, mod)) - { + if (!mod_bound(archdata->unw_end, 0, mod)) { printk(KERN_ERR "module_arch_init: archdata->unw_end out of bounds.\n"); return 1; } - if (!mod_bound(archdata->segment_base, 0, mod)) - { + if (!mod_bound(archdata->segment_base, 0, mod)) { printk(KERN_ERR "module_arch_init: archdata->unw_table out of bounds.\n"); return 1; } @@ -82,7 +87,7 @@ } static inline void -ia64_module_unmap(void * addr) +ia64_module_unmap (void * addr) { struct module *mod = (struct module *) addr; struct archdata *archdata; @@ -90,8 +95,7 @@ /* * Before freeing the module memory remove the unwind table entry */ - if (mod_member_present(mod, archdata_start) && mod->archdata_start) - { + if (mod_member_present(mod, archdata_start) && mod->archdata_start) { archdata = (struct archdata *)(mod->archdata_start); if (archdata->unw_table != NULL) diff -urN linux-2.4.10/include/asm-ia64/msgbuf.h linux-2.4.10-lia/include/asm-ia64/msgbuf.h --- linux-2.4.10/include/asm-ia64/msgbuf.h Sun Feb 6 18:42:40 2000 +++ linux-2.4.10-lia/include/asm-ia64/msgbuf.h Mon Sep 24 22:06:49 2001 @@ -1,7 +1,7 @@ #ifndef _ASM_IA64_MSGBUF_H #define _ASM_IA64_MSGBUF_H -/* +/* * The msqid64_ds structure for IA-64 architecture. * Note extra padding because this structure is passed back and forth * between kernel and user space. diff -urN linux-2.4.10/include/asm-ia64/namei.h linux-2.4.10-lia/include/asm-ia64/namei.h --- linux-2.4.10/include/asm-ia64/namei.h Sun Apr 2 15:49:07 2000 +++ linux-2.4.10-lia/include/asm-ia64/namei.h Mon Sep 24 23:01:39 2001 @@ -2,15 +2,24 @@ #define _ASM_IA64_NAMEI_H /* - * Copyright (C) 1998, 1999 Hewlett-Packard Co - * Copyright (C) 1998, 1999 David Mosberger-Tang + * Copyright (C) 1998, 1999, 2001 Hewlett-Packard Co + * David Mosberger-Tang */ -/* - * This dummy routine maybe changed to something useful - * for /usr/gnemul/ emulation stuff. - * Look at asm-sparc/namei.h for details. - */ -#define __emul_prefix() NULL +#include +#include + +#define EMUL_PREFIX_LINUX_IA32 "emul/ia32-linux/" + +static inline char * +__emul_prefix (void) +{ + switch (current->personality) { + case PER_LINUX32: + return EMUL_PREFIX_LINUX_IA32; + default: + return NULL; + } +} #endif /* _ASM_IA64_NAMEI_H */ diff -urN linux-2.4.10/include/asm-ia64/offsets.h linux-2.4.10-lia/include/asm-ia64/offsets.h --- linux-2.4.10/include/asm-ia64/offsets.h Tue Jul 31 10:30:09 2001 +++ linux-2.4.10-lia/include/asm-ia64/offsets.h Mon Sep 24 22:07:13 2001 @@ -8,23 +8,23 @@ */ #define PT_PTRACED_BIT 0 #define PT_TRACESYS_BIT 1 -#define IA64_TASK_SIZE 3904 /* 0xf40 */ +#define IA64_TASK_SIZE 3920 /* 0xf50 */ #define IA64_PT_REGS_SIZE 400 /* 0x190 */ #define IA64_SWITCH_STACK_SIZE 560 /* 0x230 */ #define IA64_SIGINFO_SIZE 128 /* 0x80 */ #define IA64_CPU_SIZE 16384 /* 0x4000 */ -#define SIGFRAME_SIZE 2832 /* 0xb10 */ +#define SIGFRAME_SIZE 2816 /* 0xb00 */ #define UNW_FRAME_INFO_SIZE 448 /* 0x1c0 */ #define IA64_TASK_PTRACE_OFFSET 48 /* 0x30 */ #define IA64_TASK_SIGPENDING_OFFSET 16 /* 0x10 */ #define IA64_TASK_NEED_RESCHED_OFFSET 40 /* 0x28 */ #define IA64_TASK_PROCESSOR_OFFSET 100 /* 0x64 */ -#define IA64_TASK_THREAD_OFFSET 1456 /* 0x5b0 */ -#define IA64_TASK_THREAD_KSP_OFFSET 1456 /* 0x5b0 */ -#define IA64_TASK_THREAD_SIGMASK_OFFSET 1568 /* 0x620 */ -#define IA64_TASK_PFM_NOTIFY_OFFSET 2088 /* 0x828 */ -#define IA64_TASK_PID_OFFSET 196 /* 0xc4 */ +#define IA64_TASK_THREAD_OFFSET 1472 /* 0x5c0 */ +#define IA64_TASK_THREAD_KSP_OFFSET 1472 /* 0x5c0 */ +#define IA64_TASK_THREAD_SIGMASK_OFFSET 1584 /* 0x630 */ +#define IA64_TASK_PFM_MUST_BLOCK_OFFSET 2104 /* 0x838 */ +#define IA64_TASK_PID_OFFSET 220 /* 0xdc */ #define IA64_TASK_MM_OFFSET 88 /* 0x58 */ #define IA64_PT_REGS_CR_IPSR_OFFSET 0 /* 0x0 */ #define IA64_PT_REGS_CR_IIP_OFFSET 8 /* 0x8 */ @@ -126,12 +126,13 @@ #define IA64_SIGCONTEXT_FR6_OFFSET 560 /* 0x230 */ #define IA64_SIGCONTEXT_PR_OFFSET 128 /* 0x80 */ #define IA64_SIGCONTEXT_R12_OFFSET 296 /* 0x128 */ +#define IA64_SIGCONTEXT_RBS_BASE_OFFSET 2512 /* 0x9d0 */ +#define IA64_SIGCONTEXT_LOADRS_OFFSET 2520 /* 0x9d8 */ #define IA64_SIGFRAME_ARG0_OFFSET 0 /* 0x0 */ #define IA64_SIGFRAME_ARG1_OFFSET 8 /* 0x8 */ #define IA64_SIGFRAME_ARG2_OFFSET 16 /* 0x10 */ -#define IA64_SIGFRAME_RBS_BASE_OFFSET 24 /* 0x18 */ -#define IA64_SIGFRAME_HANDLER_OFFSET 32 /* 0x20 */ -#define IA64_SIGFRAME_SIGCONTEXT_OFFSET 176 /* 0xb0 */ +#define IA64_SIGFRAME_HANDLER_OFFSET 24 /* 0x18 */ +#define IA64_SIGFRAME_SIGCONTEXT_OFFSET 160 /* 0xa0 */ #define IA64_CLONE_VFORK 16384 /* 0x4000 */ #define IA64_CLONE_VM 256 /* 0x100 */ #define IA64_CPU_IRQ_COUNT_OFFSET 0 /* 0x0 */ diff -urN linux-2.4.10/include/asm-ia64/page.h linux-2.4.10-lia/include/asm-ia64/page.h --- linux-2.4.10/include/asm-ia64/page.h Thu Apr 5 12:51:47 2001 +++ linux-2.4.10-lia/include/asm-ia64/page.h Mon Sep 24 22:23:22 2001 @@ -55,12 +55,15 @@ #ifdef CONFIG_IA64_GENERIC # include # define virt_to_page(kaddr) (mem_map + platform_map_nr(kaddr)) +# define page_to_phys(page) XXX fix me #elif defined (CONFIG_IA64_SGI_SN1) # ifndef CONFIG_DISCONTIGMEM # define virt_to_page(kaddr) (mem_map + MAP_NR_DENSE(kaddr)) +# define page_to_phys(page) XXX fix me # endif #else # define virt_to_page(kaddr) (mem_map + MAP_NR_DENSE(kaddr)) +# define page_to_phys(page) ((page - mem_map) << PAGE_SHIFT) #endif #define VALID_PAGE(page) ((page - mem_map) < max_mapnr) diff -urN linux-2.4.10/include/asm-ia64/pal.h linux-2.4.10-lia/include/asm-ia64/pal.h --- linux-2.4.10/include/asm-ia64/pal.h Thu Apr 5 12:51:47 2001 +++ linux-2.4.10-lia/include/asm-ia64/pal.h Mon Sep 24 22:07:25 2001 @@ -7,9 +7,9 @@ * This is based on Intel IA-64 Architecture Software Developer's Manual rev 1.0 * chapter 11 IA-64 Processor Abstraction Layer * - * Copyright (C) 1998-2000 Hewlett-Packard Co - * Copyright (C) 1998-2000 David Mosberger-Tang - * Copyright (C) 2000 Stephane Eranian + * Copyright (C) 1998-2001 Hewlett-Packard Co + * David Mosberger-Tang + * Stephane Eranian * Copyright (C) 1999 VA Linux Systems * Copyright (C) 1999 Walt Drummond * Copyright (C) 1999 Srinivasa Prasad Thirumalachar @@ -17,7 +17,7 @@ * 99/10/01 davidm Make sure we pass zero for reserved parameters. * 00/03/07 davidm Updated pal_cache_flush() to be in sync with PAL v2.6. * 00/03/23 cfleck Modified processor min-state save area to match updated PAL & SAL info - * 00/05/24 eranian Updated to latest PAL spec, fix structures bugs, added + * 00/05/24 eranian Updated to latest PAL spec, fix structures bugs, added * 00/05/25 eranian Support for stack calls, and static physical calls * 00/06/18 eranian Support for stacked physical calls */ @@ -91,9 +91,9 @@ #define PAL_STATUS_UNIMPLEMENTED -1 /* Unimplemented procedure */ #define PAL_STATUS_EINVAL -2 /* Invalid argument */ #define PAL_STATUS_ERROR -3 /* Error */ -#define PAL_STATUS_CACHE_INIT_FAIL -4 /* Could not initialize the +#define PAL_STATUS_CACHE_INIT_FAIL -4 /* Could not initialize the * specified level and type of - * cache without sideeffects + * cache without sideeffects * and "restrict" was 1 */ @@ -189,8 +189,8 @@ #define PAL_CACHE_ATTR_WT 0 /* Write through cache */ #define PAL_CACHE_ATTR_WB 1 /* Write back cache */ -#define PAL_CACHE_ATTR_WT_OR_WB 2 /* Either write thru or write - * back depending on TLB +#define PAL_CACHE_ATTR_WT_OR_WB 2 /* Either write thru or write + * back depending on TLB * memory attributes */ @@ -211,13 +211,13 @@ tagprot_lsb : 6, /* Least -do- */ tagprot_msb : 6, /* Most Sig. tag address - * bit that this + * bit that this * protection covers. */ prot_bits : 6, /* # of protection bits */ method : 4, /* Protection method */ - t_d : 2; /* Indicates which part - * of the cache this + t_d : 2; /* Indicates which part + * of the cache this * protection encoding * applies. */ @@ -239,7 +239,7 @@ */ #define PAL_CACHE_PROT_PART_DATA_TAG 3 /* Data+tag protection (data is * more significant ) - */ + */ #define PAL_CACHE_PROT_PART_MAX 6 @@ -247,7 +247,7 @@ pal_status_t pcpi_status; pal_cache_protection_element_t pcp_info[PAL_CACHE_PROT_PART_MAX]; } pal_cache_protection_info_t; - + /* Processor cache protection method encodings */ #define PAL_CACHE_PROT_METHOD_NONE 0 /* No protection */ @@ -262,41 +262,41 @@ struct { u64 cache_type : 8, /* 7-0 cache type */ level : 8, /* 15-8 level of the - * cache in the + * cache in the * heirarchy. */ way : 8, /* 23-16 way in the set */ part : 8, /* 31-24 part of the - * cache + * cache */ reserved : 32; /* 63-32 is reserved*/ } pclid_info_read; struct { u64 cache_type : 8, /* 7-0 cache type */ level : 8, /* 15-8 level of the - * cache in the + * cache in the * heirarchy. */ way : 8, /* 23-16 way in the set */ part : 8, /* 31-24 part of the - * cache + * cache */ - mesi : 8, /* 39-32 cache line + mesi : 8, /* 39-32 cache line * state */ start : 8, /* 47-40 lsb of data to * invert */ length : 8, /* 55-48 #bits to - * invert + * invert */ trigger : 8; /* 63-56 Trigger error - * by doing a load - * after the write - */ - + * by doing a load + * after the write + */ + } pclid_info_write; } pal_cache_line_id_u_t; @@ -319,11 +319,11 @@ #define PAL_CACHE_LINE_ID_PART_TAG 1 /* Tag */ #define PAL_CACHE_LINE_ID_PART_DATA_PROT 2 /* Data protection */ #define PAL_CACHE_LINE_ID_PART_TAG_PROT 3 /* Tag protection */ -#define PAL_CACHE_LINE_ID_PART_DATA_TAG_PROT 4 /* Data+tag +#define PAL_CACHE_LINE_ID_PART_DATA_TAG_PROT 4 /* Data+tag * protection */ typedef struct pal_cache_line_info_s { - pal_status_t pcli_status; /* Return status of the read cache line + pal_status_t pcli_status; /* Return status of the read cache line * info call. */ u64 pcli_data; /* 64-bit data, tag, protection bits .. */ @@ -351,15 +351,15 @@ #define PAL_MC_INFO_REQ_ADDR 4 /* Requestor address */ #define PAL_MC_INFO_RESP_ADDR 5 /* Responder address */ #define PAL_MC_INFO_TARGET_ADDR 6 /* Target address */ -#define PAL_MC_INFO_IMPL_DEP 7 /* Implementation - * dependent +#define PAL_MC_INFO_IMPL_DEP 7 /* Implementation + * dependent */ typedef struct pal_process_state_info_s { u64 reserved1 : 2, rz : 1, /* PAL_CHECK processor - * rendezvous + * rendezvous * successful. */ @@ -370,13 +370,13 @@ * errors occurred */ - mn : 1, /* Min. state save - * area has been + mn : 1, /* Min. state save + * area has been * registered with PAL */ sy : 1, /* Storage integrity - * synched + * synched */ @@ -389,8 +389,8 @@ hd : 1, /* Non-essential hw * lost (no loss of - * functionality) - * causing the + * functionality) + * causing the * processor to run in * degraded mode. */ @@ -398,9 +398,9 @@ tl : 1, /* 1 => MC occurred * after an instr was * executed but before - * the trap that + * the trap that * resulted from instr - * execution was + * execution was * generated. * (Trap Lost ) */ @@ -410,7 +410,7 @@ */ dy : 1, /* Processor dynamic - * state valid + * state valid */ @@ -441,10 +441,10 @@ * are valid */ gr : 1, /* General registers - * are valid + * are valid * (excl. banked regs) */ - dsize : 16, /* size of dynamic + dsize : 16, /* size of dynamic * state returned * by the processor */ @@ -459,8 +459,8 @@ typedef struct pal_cache_check_info_s { u64 reserved1 : 16, - way : 5, /* Way in which the - * error occurred + way : 5, /* Way in which the + * error occurred */ reserved2 : 1, mc : 1, /* Machine check corrected */ @@ -469,8 +469,8 @@ */ wv : 1, /* Way field valid */ - op : 3, /* Type of cache - * operation that + op : 3, /* Type of cache + * operation that * caused the machine * check. */ @@ -493,7 +493,7 @@ typedef struct pal_tlb_check_info_s { u64 tr_slot : 8, /* Slot# of TR where - * error occurred + * error occurred */ reserved2 : 8, dtr : 1, /* Fail in data TR */ @@ -509,7 +509,7 @@ u64 size : 5, /* Xaction size*/ ib : 1, /* Internal bus error */ eb : 1, /* External bus error */ - cc : 1, /* Error occurred + cc : 1, /* Error occurred * during cache-cache * transfer. */ @@ -518,7 +518,7 @@ tv : 1, /* Targ addr valid */ rp : 1, /* Resp addr valid */ rq : 1, /* Req addr valid */ - bsi : 8, /* Bus error status + bsi : 8, /* Bus error status * info */ mc : 1, /* Machine check corrected */ @@ -601,8 +601,8 @@ #define pmci_bus_external_error pme_bus.eb #define pmci_bus_mc pme_bus.mc -/* - * NOTE: this min_state_save area struct only includes the 1KB +/* + * NOTE: this min_state_save area struct only includes the 1KB * architectural state save area. The other 3 KB is scratch space * for PAL. */ @@ -703,12 +703,12 @@ u64 pbf_disable_bus_addr_err_signal : 1; u64 pbf_disable_bus_data_err_check : 1; } pal_bus_features_s; -} pal_bus_features_u_t; +} pal_bus_features_u_t; extern void pal_bus_features_print (u64); /* Provide information about configurable processor bus features */ -static inline s64 +static inline s64 ia64_pal_bus_get_features (pal_bus_features_u_t *features_avail, pal_bus_features_u_t *features_status, pal_bus_features_u_t *features_control) @@ -721,13 +721,13 @@ features_status->pal_bus_features_val = iprv.v1; if (features_control) features_control->pal_bus_features_val = iprv.v2; - return iprv.status; + return iprv.status; } /* Enables/disables specific processor bus features */ -static inline s64 -ia64_pal_bus_set_features (pal_bus_features_u_t feature_select) -{ +static inline s64 +ia64_pal_bus_set_features (pal_bus_features_u_t feature_select) +{ struct ia64_pal_retval iprv; PAL_CALL_PHYS(iprv, PAL_BUS_SET_FEATURES, feature_select.pal_bus_features_val, 0, 0); return iprv.status; @@ -739,7 +739,7 @@ { struct ia64_pal_retval iprv; - PAL_CALL(iprv, PAL_CACHE_INFO, cache_level, cache_type, 0); + PAL_CALL(iprv, PAL_CACHE_INFO, cache_level, cache_type, 0); if (iprv.status == 0) { conf->pcci_status = iprv.status; @@ -747,7 +747,7 @@ conf->pcci_info_2.pcci2_data = iprv.v1; conf->pcci_reserved = iprv.v2; } - return iprv.status; + return iprv.status; } @@ -757,7 +757,7 @@ { struct ia64_pal_retval iprv; - PAL_CALL(iprv, PAL_CACHE_PROT_INFO, cache_level, cache_type, 0); + PAL_CALL(iprv, PAL_CACHE_PROT_INFO, cache_level, cache_type, 0); if (iprv.status == 0) { prot->pcpi_status = iprv.status; @@ -768,106 +768,106 @@ prot->pcp_info[4].pcpi_data = iprv.v2 & 0xffffffff; prot->pcp_info[5].pcpi_data = iprv.v2 >> 32; } - return iprv.status; + return iprv.status; } - + /* * Flush the processor instruction or data caches. *PROGRESS must be * initialized to zero before calling this for the first time.. */ -static inline s64 -ia64_pal_cache_flush (u64 cache_type, u64 invalidate, u64 *progress) -{ +static inline s64 +ia64_pal_cache_flush (u64 cache_type, u64 invalidate, u64 *progress) +{ struct ia64_pal_retval iprv; - PAL_CALL_IC_OFF(iprv, PAL_CACHE_FLUSH, cache_type, invalidate, *progress); + PAL_CALL_IC_OFF(iprv, PAL_CACHE_FLUSH, cache_type, invalidate, *progress); *progress = iprv.v1; - return iprv.status; + return iprv.status; } /* Initialize the processor controlled caches */ -static inline s64 -ia64_pal_cache_init (u64 level, u64 cache_type, u64 restrict) -{ +static inline s64 +ia64_pal_cache_init (u64 level, u64 cache_type, u64 restrict) +{ struct ia64_pal_retval iprv; - PAL_CALL(iprv, PAL_CACHE_INIT, level, cache_type, restrict); - return iprv.status; + PAL_CALL(iprv, PAL_CACHE_INIT, level, cache_type, restrict); + return iprv.status; } -/* Initialize the tags and data of a data or unified cache line of - * processor controlled cache to known values without the availability +/* Initialize the tags and data of a data or unified cache line of + * processor controlled cache to known values without the availability * of backing memory. */ -static inline s64 -ia64_pal_cache_line_init (u64 physical_addr, u64 data_value) -{ +static inline s64 +ia64_pal_cache_line_init (u64 physical_addr, u64 data_value) +{ struct ia64_pal_retval iprv; PAL_CALL(iprv, PAL_CACHE_LINE_INIT, physical_addr, data_value, 0); - return iprv.status; + return iprv.status; } /* Read the data and tag of a processor controlled cache line for diags */ -static inline s64 -ia64_pal_cache_read (pal_cache_line_id_u_t line_id, u64 physical_addr) -{ +static inline s64 +ia64_pal_cache_read (pal_cache_line_id_u_t line_id, u64 physical_addr) +{ struct ia64_pal_retval iprv; PAL_CALL(iprv, PAL_CACHE_READ, line_id.pclid_data, physical_addr, 0); - return iprv.status; + return iprv.status; } /* Return summary information about the heirarchy of caches controlled by the processor */ -static inline s64 -ia64_pal_cache_summary (u64 *cache_levels, u64 *unique_caches) -{ +static inline s64 +ia64_pal_cache_summary (u64 *cache_levels, u64 *unique_caches) +{ struct ia64_pal_retval iprv; PAL_CALL(iprv, PAL_CACHE_SUMMARY, 0, 0, 0); if (cache_levels) *cache_levels = iprv.v0; if (unique_caches) *unique_caches = iprv.v1; - return iprv.status; + return iprv.status; } /* Write the data and tag of a processor-controlled cache line for diags */ -static inline s64 -ia64_pal_cache_write (pal_cache_line_id_u_t line_id, u64 physical_addr, u64 data) -{ - struct ia64_pal_retval iprv; +static inline s64 +ia64_pal_cache_write (pal_cache_line_id_u_t line_id, u64 physical_addr, u64 data) +{ + struct ia64_pal_retval iprv; PAL_CALL(iprv, PAL_CACHE_WRITE, line_id.pclid_data, physical_addr, data); - return iprv.status; + return iprv.status; } /* Return the parameters needed to copy relocatable PAL procedures from ROM to memory */ -static inline s64 +static inline s64 ia64_pal_copy_info (u64 copy_type, u64 num_procs, u64 num_iopics, - u64 *buffer_size, u64 *buffer_align) -{ + u64 *buffer_size, u64 *buffer_align) +{ struct ia64_pal_retval iprv; - PAL_CALL(iprv, PAL_COPY_INFO, copy_type, num_procs, num_iopics); + PAL_CALL(iprv, PAL_COPY_INFO, copy_type, num_procs, num_iopics); if (buffer_size) *buffer_size = iprv.v0; if (buffer_align) *buffer_align = iprv.v1; - return iprv.status; + return iprv.status; } /* Copy relocatable PAL procedures from ROM to memory */ -static inline s64 -ia64_pal_copy_pal (u64 target_addr, u64 alloc_size, u64 processor, u64 *pal_proc_offset) -{ +static inline s64 +ia64_pal_copy_pal (u64 target_addr, u64 alloc_size, u64 processor, u64 *pal_proc_offset) +{ struct ia64_pal_retval iprv; PAL_CALL(iprv, PAL_COPY_PAL, target_addr, alloc_size, processor); if (pal_proc_offset) *pal_proc_offset = iprv.v0; - return iprv.status; + return iprv.status; } /* Return the number of instruction and data debug register pairs */ -static inline s64 -ia64_pal_debug_info (u64 *inst_regs, u64 *data_regs) -{ +static inline s64 +ia64_pal_debug_info (u64 *inst_regs, u64 *data_regs) +{ struct ia64_pal_retval iprv; PAL_CALL(iprv, PAL_DEBUG_INFO, 0, 0, 0); if (inst_regs) @@ -875,50 +875,50 @@ if (data_regs) *data_regs = iprv.v1; - return iprv.status; + return iprv.status; } #ifdef TBD /* Switch from IA64-system environment to IA-32 system environment */ -static inline s64 -ia64_pal_enter_ia32_env (ia32_env1, ia32_env2, ia32_env3) -{ +static inline s64 +ia64_pal_enter_ia32_env (ia32_env1, ia32_env2, ia32_env3) +{ struct ia64_pal_retval iprv; - PAL_CALL(iprv, PAL_ENTER_IA_32_ENV, ia32_env1, ia32_env2, ia32_env3); - return iprv.status; + PAL_CALL(iprv, PAL_ENTER_IA_32_ENV, ia32_env1, ia32_env2, ia32_env3); + return iprv.status; } #endif /* Get unique geographical address of this processor on its bus */ -static inline s64 -ia64_pal_fixed_addr (u64 *global_unique_addr) -{ +static inline s64 +ia64_pal_fixed_addr (u64 *global_unique_addr) +{ struct ia64_pal_retval iprv; PAL_CALL(iprv, PAL_FIXED_ADDR, 0, 0, 0); if (global_unique_addr) *global_unique_addr = iprv.v0; - return iprv.status; + return iprv.status; } /* Get base frequency of the platform if generated by the processor */ -static inline s64 -ia64_pal_freq_base (u64 *platform_base_freq) -{ +static inline s64 +ia64_pal_freq_base (u64 *platform_base_freq) +{ struct ia64_pal_retval iprv; PAL_CALL(iprv, PAL_FREQ_BASE, 0, 0, 0); if (platform_base_freq) *platform_base_freq = iprv.v0; - return iprv.status; + return iprv.status; } /* * Get the ratios for processor frequency, bus frequency and interval timer to - * to base frequency of the platform + * to base frequency of the platform */ -static inline s64 +static inline s64 ia64_pal_freq_ratios (struct pal_freq_ratio *proc_ratio, struct pal_freq_ratio *bus_ratio, - struct pal_freq_ratio *itc_ratio) -{ + struct pal_freq_ratio *itc_ratio) +{ struct ia64_pal_retval iprv; PAL_CALL(iprv, PAL_FREQ_RATIOS, 0, 0, 0); if (proc_ratio) @@ -927,20 +927,21 @@ *(u64 *)bus_ratio = iprv.v1; if (itc_ratio) *(u64 *)itc_ratio = iprv.v2; - return iprv.status; + return iprv.status; } -/* Make the processor enter HALT or one of the implementation dependent low +/* Make the processor enter HALT or one of the implementation dependent low * power states where prefetching and execution are suspended and cache and * TLB coherency is not maintained. */ -static inline s64 -ia64_pal_halt (u64 halt_state) -{ +static inline s64 +ia64_pal_halt (u64 halt_state) +{ struct ia64_pal_retval iprv; PAL_CALL(iprv, PAL_HALT, halt_state, 0, 0); - return iprv.status; + return iprv.status; } + typedef union pal_power_mgmt_info_u { u64 ppmi_data; struct { @@ -954,87 +955,87 @@ } pal_power_mgmt_info_u_t; /* Return information about processor's optional power management capabilities. */ -static inline s64 -ia64_pal_halt_info (pal_power_mgmt_info_u_t *power_buf) -{ +static inline s64 +ia64_pal_halt_info (pal_power_mgmt_info_u_t *power_buf) +{ struct ia64_pal_retval iprv; PAL_CALL_STK(iprv, PAL_HALT_INFO, (unsigned long) power_buf, 0, 0); - return iprv.status; + return iprv.status; } /* Cause the processor to enter LIGHT HALT state, where prefetching and execution are * suspended, but cache and TLB coherency is maintained. */ -static inline s64 -ia64_pal_halt_light (void) -{ +static inline s64 +ia64_pal_halt_light (void) +{ struct ia64_pal_retval iprv; PAL_CALL(iprv, PAL_HALT_LIGHT, 0, 0, 0); - return iprv.status; + return iprv.status; } /* Clear all the processor error logging registers and reset the indicator that allows * the error logging registers to be written. This procedure also checks the pending * machine check bit and pending INIT bit and reports their states. */ -static inline s64 -ia64_pal_mc_clear_log (u64 *pending_vector) -{ +static inline s64 +ia64_pal_mc_clear_log (u64 *pending_vector) +{ struct ia64_pal_retval iprv; PAL_CALL(iprv, PAL_MC_CLEAR_LOG, 0, 0, 0); if (pending_vector) *pending_vector = iprv.v0; - return iprv.status; + return iprv.status; } -/* Ensure that all outstanding transactions in a processor are completed or that any +/* Ensure that all outstanding transactions in a processor are completed or that any * MCA due to thes outstanding transaction is taken. */ -static inline s64 -ia64_pal_mc_drain (void) -{ +static inline s64 +ia64_pal_mc_drain (void) +{ struct ia64_pal_retval iprv; PAL_CALL(iprv, PAL_MC_DRAIN, 0, 0, 0); - return iprv.status; + return iprv.status; } /* Return the machine check dynamic processor state */ -static inline s64 -ia64_pal_mc_dynamic_state (u64 offset, u64 *size, u64 *pds) -{ +static inline s64 +ia64_pal_mc_dynamic_state (u64 offset, u64 *size, u64 *pds) +{ struct ia64_pal_retval iprv; PAL_CALL(iprv, PAL_MC_DYNAMIC_STATE, offset, 0, 0); if (size) *size = iprv.v0; if (pds) *pds = iprv.v1; - return iprv.status; + return iprv.status; } /* Return processor machine check information */ -static inline s64 -ia64_pal_mc_error_info (u64 info_index, u64 type_index, u64 *size, u64 *error_info) -{ +static inline s64 +ia64_pal_mc_error_info (u64 info_index, u64 type_index, u64 *size, u64 *error_info) +{ struct ia64_pal_retval iprv; PAL_CALL(iprv, PAL_MC_ERROR_INFO, info_index, type_index, 0); if (size) *size = iprv.v0; if (error_info) - *error_info = iprv.v1; - return iprv.status; + *error_info = iprv.v1; + return iprv.status; } /* Inform PALE_CHECK whether a machine check is expected so that PALE_CHECK willnot * attempt to correct any expected machine checks. */ -static inline s64 -ia64_pal_mc_expected (u64 expected, u64 *previous) -{ +static inline s64 +ia64_pal_mc_expected (u64 expected, u64 *previous) +{ struct ia64_pal_retval iprv; PAL_CALL(iprv, PAL_MC_EXPECTED, expected, 0, 0); if (previous) *previous = iprv.v0; - return iprv.status; + return iprv.status; } /* Register a platform dependent location with PAL to which it can save @@ -1042,39 +1043,39 @@ * event. */ static inline s64 -ia64_pal_mc_register_mem (u64 physical_addr) -{ +ia64_pal_mc_register_mem (u64 physical_addr) +{ struct ia64_pal_retval iprv; PAL_CALL(iprv, PAL_MC_REGISTER_MEM, physical_addr, 0, 0); - return iprv.status; + return iprv.status; } /* Restore minimal architectural processor state, set CMC interrupt if necessary * and resume execution */ -static inline s64 -ia64_pal_mc_resume (u64 set_cmci, u64 save_ptr) -{ +static inline s64 +ia64_pal_mc_resume (u64 set_cmci, u64 save_ptr) +{ struct ia64_pal_retval iprv; PAL_CALL(iprv, PAL_MC_RESUME, set_cmci, save_ptr, 0); - return iprv.status; + return iprv.status; } /* Return the memory attributes implemented by the processor */ -static inline s64 -ia64_pal_mem_attrib (u64 *mem_attrib) -{ +static inline s64 +ia64_pal_mem_attrib (u64 *mem_attrib) +{ struct ia64_pal_retval iprv; PAL_CALL(iprv, PAL_MEM_ATTRIB, 0, 0, 0); if (mem_attrib) *mem_attrib = iprv.v0 & 0xff; - return iprv.status; + return iprv.status; } /* Return the amount of memory needed for second phase of processor * self-test and the required alignment of memory. */ -static inline s64 +static inline s64 ia64_pal_mem_for_test (u64 *bytes_needed, u64 *alignment) { struct ia64_pal_retval iprv; @@ -1083,60 +1084,60 @@ *bytes_needed = iprv.v0; if (alignment) *alignment = iprv.v1; - return iprv.status; + return iprv.status; } typedef union pal_perf_mon_info_u { u64 ppmi_data; struct { u64 generic : 8, - width : 8, - cycles : 8, + width : 8, + cycles : 8, retired : 8, reserved : 32; } pal_perf_mon_info_s; } pal_perf_mon_info_u_t; - + /* Return the performance monitor information about what can be counted * and how to configure the monitors to count the desired events. */ -static inline s64 -ia64_pal_perf_mon_info (u64 *pm_buffer, pal_perf_mon_info_u_t *pm_info) -{ +static inline s64 +ia64_pal_perf_mon_info (u64 *pm_buffer, pal_perf_mon_info_u_t *pm_info) +{ struct ia64_pal_retval iprv; PAL_CALL(iprv, PAL_PERF_MON_INFO, (unsigned long) pm_buffer, 0, 0); if (pm_info) pm_info->ppmi_data = iprv.v0; - return iprv.status; + return iprv.status; } /* Specifies the physical address of the processor interrupt block * and I/O port space. */ -static inline s64 -ia64_pal_platform_addr (u64 type, u64 physical_addr) -{ +static inline s64 +ia64_pal_platform_addr (u64 type, u64 physical_addr) +{ struct ia64_pal_retval iprv; PAL_CALL(iprv, PAL_PLATFORM_ADDR, type, physical_addr, 0); - return iprv.status; + return iprv.status; } /* Set the SAL PMI entrypoint in memory */ -static inline s64 -ia64_pal_pmi_entrypoint (u64 sal_pmi_entry_addr) -{ +static inline s64 +ia64_pal_pmi_entrypoint (u64 sal_pmi_entry_addr) +{ struct ia64_pal_retval iprv; PAL_CALL(iprv, PAL_PMI_ENTRYPOINT, sal_pmi_entry_addr, 0, 0); - return iprv.status; + return iprv.status; } struct pal_features_s; /* Provide information about configurable processor features */ -static inline s64 -ia64_pal_proc_get_features (u64 *features_avail, - u64 *features_status, +static inline s64 +ia64_pal_proc_get_features (u64 *features_avail, + u64 *features_status, u64 *features_control) -{ +{ struct ia64_pal_retval iprv; PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, 0, 0); if (iprv.status == 0) { @@ -1144,16 +1145,16 @@ *features_status = iprv.v1; *features_control = iprv.v2; } - return iprv.status; + return iprv.status; } /* Enable/disable processor dependent features */ -static inline s64 -ia64_pal_proc_set_features (u64 feature_select) -{ +static inline s64 +ia64_pal_proc_set_features (u64 feature_select) +{ struct ia64_pal_retval iprv; PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, feature_select, 0, 0); - return iprv.status; + return iprv.status; } /* @@ -1162,7 +1163,7 @@ */ typedef struct ia64_ptce_info_s { u64 base; - u32 count[2]; + u32 count[2]; u32 stride[2]; } ia64_ptce_info_t; @@ -1189,9 +1190,9 @@ } /* Return info about implemented application and control registers. */ -static inline s64 -ia64_pal_register_info (u64 info_request, u64 *reg_info_1, u64 *reg_info_2) -{ +static inline s64 +ia64_pal_register_info (u64 info_request, u64 *reg_info_1, u64 *reg_info_2) +{ struct ia64_pal_retval iprv; PAL_CALL(iprv, PAL_REGISTER_INFO, info_request, 0, 0); if (reg_info_1) @@ -1199,7 +1200,7 @@ if (reg_info_2) *reg_info_2 = iprv.v1; return iprv.status; -} +} typedef union pal_hints_u { u64 ph_data; @@ -1210,62 +1211,62 @@ } pal_hints_s; } pal_hints_u_t; -/* Return information about the register stack and RSE for this processor +/* Return information about the register stack and RSE for this processor * implementation. */ -static inline s64 +static inline s64 ia64_pal_rse_info (u64 *num_phys_stacked, pal_hints_u_t *hints) -{ +{ struct ia64_pal_retval iprv; PAL_CALL(iprv, PAL_RSE_INFO, 0, 0, 0); if (num_phys_stacked) *num_phys_stacked = iprv.v0; if (hints) hints->ph_data = iprv.v1; - return iprv.status; + return iprv.status; } -/* Cause the processor to enter SHUTDOWN state, where prefetching and execution are +/* Cause the processor to enter SHUTDOWN state, where prefetching and execution are * suspended, but cause cache and TLB coherency to be maintained. * This is usually called in IA-32 mode. */ -static inline s64 -ia64_pal_shutdown (void) -{ +static inline s64 +ia64_pal_shutdown (void) +{ struct ia64_pal_retval iprv; PAL_CALL(iprv, PAL_SHUTDOWN, 0, 0, 0); - return iprv.status; + return iprv.status; } /* Perform the second phase of processor self-test. */ -static inline s64 +static inline s64 ia64_pal_test_proc (u64 test_addr, u64 test_size, u64 attributes, u64 *self_test_state) { struct ia64_pal_retval iprv; PAL_CALL(iprv, PAL_TEST_PROC, test_addr, test_size, attributes); if (self_test_state) *self_test_state = iprv.v0; - return iprv.status; + return iprv.status; } typedef union pal_version_u { u64 pal_version_val; struct { - u64 pv_pal_b_rev : 8; + u64 pv_pal_b_rev : 8; u64 pv_pal_b_model : 8; u64 pv_reserved1 : 8; u64 pv_pal_vendor : 8; u64 pv_pal_a_rev : 8; u64 pv_pal_a_model : 8; - u64 pv_reserved2 : 16; + u64 pv_reserved2 : 16; } pal_version_s; } pal_version_u_t; /* Return PAL version information */ -static inline s64 -ia64_pal_version (pal_version_u_t *pal_min_version, pal_version_u_t *pal_cur_version) -{ +static inline s64 +ia64_pal_version (pal_version_u_t *pal_min_version, pal_version_u_t *pal_cur_version) +{ struct ia64_pal_retval iprv; PAL_CALL_PHYS(iprv, PAL_VERSION, 0, 0, 0); if (pal_min_version) @@ -1274,7 +1275,7 @@ if (pal_cur_version) pal_cur_version->pal_version_val = iprv.v1; - return iprv.status; + return iprv.status; } typedef union pal_tc_info_u { @@ -1288,8 +1289,8 @@ reduce_tr : 1, reserved : 29; } pal_tc_info_s; -} pal_tc_info_u_t; - +} pal_tc_info_u_t; + #define tc_reduce_tr pal_tc_info_s.reduce_tr #define tc_unified pal_tc_info_s.unified #define tc_pf pal_tc_info_s.pf @@ -1298,10 +1299,10 @@ #define tc_num_sets pal_tc_info_s.num_sets -/* Return information about the virtual memory characteristics of the processor +/* Return information about the virtual memory characteristics of the processor * implementation. */ -static inline s64 +static inline s64 ia64_pal_vm_info (u64 tc_level, u64 tc_type, pal_tc_info_u_t *tc_info, u64 *tc_pages) { struct ia64_pal_retval iprv; @@ -1309,14 +1310,14 @@ if (tc_info) tc_info->pti_val = iprv.v0; if (tc_pages) - *tc_pages = iprv.v1; - return iprv.status; + *tc_pages = iprv.v1; + return iprv.status; } -/* Get page size information about the virtual memory characteristics of the processor +/* Get page size information about the virtual memory characteristics of the processor * implementation. */ -static inline s64 +static inline s64 ia64_pal_vm_page_size (u64 *tr_pages, u64 *vw_pages) { struct ia64_pal_retval iprv; @@ -1324,8 +1325,8 @@ if (tr_pages) *tr_pages = iprv.v0; if (vw_pages) - *vw_pages = iprv.v1; - return iprv.status; + *vw_pages = iprv.v1; + return iprv.status; } typedef union pal_vm_info_1_u { @@ -1348,23 +1349,23 @@ struct { u64 impl_va_msb : 8, rid_size : 8, - reserved : 48; + reserved : 48; } pal_vm_info_2_s; } pal_vm_info_2_u_t; - -/* Get summary information about the virtual memory characteristics of the processor + +/* Get summary information about the virtual memory characteristics of the processor * implementation. */ -static inline s64 -ia64_pal_vm_summary (pal_vm_info_1_u_t *vm_info_1, pal_vm_info_2_u_t *vm_info_2) -{ +static inline s64 +ia64_pal_vm_summary (pal_vm_info_1_u_t *vm_info_1, pal_vm_info_2_u_t *vm_info_2) +{ struct ia64_pal_retval iprv; PAL_CALL(iprv, PAL_VM_SUMMARY, 0, 0, 0); if (vm_info_1) vm_info_1->pvi1_val = iprv.v0; if (vm_info_2) vm_info_2->pvi2_val = iprv.v1; - return iprv.status; + return iprv.status; } typedef union pal_itr_valid_u { @@ -1379,14 +1380,14 @@ } pal_tr_valid_u_t; /* Read a translation register */ -static inline s64 +static inline s64 ia64_pal_tr_read (u64 reg_num, u64 tr_type, u64 *tr_buffer, pal_tr_valid_u_t *tr_valid) { struct ia64_pal_retval iprv; PAL_CALL_PHYS_STK(iprv, PAL_VM_TR_READ, reg_num, tr_type,(u64)__pa(tr_buffer)); if (tr_valid) tr_valid->piv_val = iprv.v0; - return iprv.status; + return iprv.status; } static inline s64 diff -urN linux-2.4.10/include/asm-ia64/pci.h linux-2.4.10-lia/include/asm-ia64/pci.h --- linux-2.4.10/include/asm-ia64/pci.h Wed May 16 10:31:27 2001 +++ linux-2.4.10-lia/include/asm-ia64/pci.h Mon Sep 24 23:02:56 2001 @@ -62,4 +62,8 @@ #define sg_dma_len(sg) ((sg)->length) +#define HAVE_PCI_MMAP +extern int pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma, + enum pci_mmap_state mmap_state, int write_combine); + #endif /* _ASM_IA64_PCI_H */ diff -urN linux-2.4.10/include/asm-ia64/perfmon.h linux-2.4.10-lia/include/asm-ia64/perfmon.h --- linux-2.4.10/include/asm-ia64/perfmon.h Thu Apr 5 12:51:47 2001 +++ linux-2.4.10-lia/include/asm-ia64/perfmon.h Mon Sep 24 22:07:39 2001 @@ -9,7 +9,7 @@ #include /* - * Structure used to define a context + * Request structure used to define a context */ typedef struct { unsigned long smpl_entries; /* how many entries in sampling buffer */ @@ -23,7 +23,7 @@ } pfreq_context_t; /* - * Structure used to configure a PMC or PMD + * Request structure used to write/read a PMC or PMD */ typedef struct { unsigned long reg_num; /* which register */ @@ -41,11 +41,16 @@ pfreq_reg_t pfr_reg; /* request to configure a PMD/PMC */ } perfmon_req_t; +#ifdef __KERNEL__ + extern void pfm_save_regs (struct task_struct *); extern void pfm_load_regs (struct task_struct *); -extern int pfm_inherit (struct task_struct *); +extern int pfm_inherit (struct task_struct *, struct pt_regs *); extern void pfm_context_exit (struct task_struct *); extern void pfm_flush_regs (struct task_struct *); +extern void pfm_cleanup_notifiers (struct task_struct *); + +#endif /* __KERNEL__ */ #endif /* _ASM_IA64_PERFMON_H */ diff -urN linux-2.4.10/include/asm-ia64/pgalloc.h linux-2.4.10-lia/include/asm-ia64/pgalloc.h --- linux-2.4.10/include/asm-ia64/pgalloc.h Tue Jul 31 10:30:09 2001 +++ linux-2.4.10-lia/include/asm-ia64/pgalloc.h Mon Sep 24 23:02:56 2001 @@ -9,7 +9,7 @@ * in (currently 8192). * * Copyright (C) 1998-2001 Hewlett-Packard Co - * Copyright (C) 1998-2001 David Mosberger-Tang + * David Mosberger-Tang * Copyright (C) 2000, Goutham Rao */ @@ -164,11 +164,6 @@ #else # define flush_tlb_all() __flush_tlb_all() #endif - -/* - * Serialize usage of ptc.g: - */ -extern spinlock_t ptcg_lock; /* * Flush a specified user mapping diff -urN linux-2.4.10/include/asm-ia64/processor.h linux-2.4.10-lia/include/asm-ia64/processor.h --- linux-2.4.10/include/asm-ia64/processor.h Mon Sep 24 15:08:24 2001 +++ linux-2.4.10-lia/include/asm-ia64/processor.h Mon Sep 24 22:26:48 2001 @@ -190,6 +190,7 @@ #include #include #include +#include /* like above but expressed as bitfields for more efficient access: */ struct ia64_psr { @@ -332,6 +333,9 @@ __u64 map_base; /* base address for get_unmapped_area() */ __u64 task_size; /* limit for task size */ struct siginfo *siginfo; /* current siginfo struct for ptrace() */ +#if JITTER_BUG + __u64 mem; +#endif #ifdef CONFIG_IA32_SUPPORT __u64 eflag; /* IA32 EFLAGS reg */ @@ -353,9 +357,10 @@ #ifdef CONFIG_PERFMON __u64 pmc[IA64_NUM_PMC_REGS]; __u64 pmd[IA64_NUM_PMD_REGS]; - unsigned long pfm_pend_notify; /* non-zero if we need to notify and block */ + unsigned long pfm_must_block; /* non-zero if we need to block on overflow */ void *pfm_context; /* pointer to detailed PMU context */ -# define INIT_THREAD_PM {0, }, {0, }, 0, 0, + atomic_t pfm_notifiers_check; /* indicate if release_thread much check tasklist */ +# define INIT_THREAD_PM {0, }, {0, }, 0, 0, {0}, #else # define INIT_THREAD_PM #endif @@ -628,10 +633,11 @@ } /* - * Save the processor status flags in FLAGS and then clear the - * interrupt collection and interrupt enable bits. + * Save the processor status flags in FLAGS and then clear the interrupt collection and + * interrupt enable bits. Don't trigger any mandatory RSE references while this bit is + * off! */ -#define ia64_clear_ic(flags) \ +#define ia64_clear_ic(flags) \ asm volatile ("mov %0=psr;; rsm psr.i | psr.ic;; srlz.i;;" \ : "=r"(flags) :: "memory"); @@ -814,9 +820,22 @@ #define THREAD_SIZE IA64_STK_OFFSET /* NOTE: The task struct and the stacks are allocated together. */ -#define alloc_task_struct() \ +#if JITTER_BUG +# define alloc_task_struct() \ +({ \ + unsigned long color, mem = __get_free_pages(GFP_KERNEL, IA64_TASK_STRUCT_LOG_NUM_PAGES); \ + struct task_struct *p; \ + color = ia64_fetch_and_add(1, &task_color) % NUM_TASK_COLORS; \ + p = (struct task_struct *) (mem + color*MAX_JITTER_SIZE/(NUM_TASK_COLORS - 1)); \ + p->thread.mem = mem; \ + p; \ +}) +# define free_task_struct(p) free_pages((p)->thread.mem, IA64_TASK_STRUCT_LOG_NUM_PAGES) +#else +# define alloc_task_struct() \ ((struct task_struct *) __get_free_pages(GFP_KERNEL, IA64_TASK_STRUCT_LOG_NUM_PAGES)) -#define free_task_struct(p) free_pages((unsigned long)(p), IA64_TASK_STRUCT_LOG_NUM_PAGES) +# define free_task_struct(p) free_pages((unsigned long)(p), IA64_TASK_STRUCT_LOG_NUM_PAGES) +#endif #define get_task_struct(tsk) atomic_inc(&virt_to_page(tsk)->count) #define init_task (init_task_union.task) @@ -969,25 +988,33 @@ return result; } +static inline __u64 +ia64_tpa (__u64 addr) +{ + __u64 result; + asm ("tpa %0=%1" : "=r"(result) : "r"(addr)); + return result; +} #define ARCH_HAS_PREFETCH #define ARCH_HAS_PREFETCHW #define ARCH_HAS_SPINLOCK_PREFETCH #define PREFETCH_STRIDE 256 -extern inline void prefetch(const void *x) +extern inline void +prefetch (const void *x) { __asm__ __volatile__ ("lfetch [%0]" : : "r"(x)); } - -extern inline void prefetchw(const void *x) + +extern inline void +prefetchw (const void *x) { __asm__ __volatile__ ("lfetch.excl [%0]" : : "r"(x)); } -#define spin_lock_prefetch(x) prefetchw(x) +#define spin_lock_prefetch(x) prefetchw(x) - #endif /* !__ASSEMBLY__ */ #endif /* _ASM_IA64_PROCESSOR_H */ diff -urN linux-2.4.10/include/asm-ia64/sal.h linux-2.4.10-lia/include/asm-ia64/sal.h --- linux-2.4.10/include/asm-ia64/sal.h Tue Jul 31 10:30:09 2001 +++ linux-2.4.10-lia/include/asm-ia64/sal.h Mon Sep 24 22:57:49 2001 @@ -7,10 +7,14 @@ * This is based on version 2.5 of the manual "IA-64 System * Abstraction Layer". * + * Copyright (C) 2001 Intel + * Copyright (C) 2001 Fred Lewis * Copyright (C) 1998, 1999, 2001 Hewlett-Packard Co * Copyright (C) 1998, 1999, 2001 David Mosberger-Tang * Copyright (C) 1999 Srinivasa Prasad Thirumalachar * + * 01/01/03 fvlewis Updated Error Record Structures to conform with Nov. 2000 + * revision of the SAL spec. * 99/09/29 davidm Updated for SAL 2.6. * 00/03/29 cfleck Updated SAL Error Logging info for processor (SAL 2.6) * (plus examples of platform error info structures from smariset @ Intel) @@ -19,7 +23,9 @@ #include #include +#include #include +#include extern spinlock_t sal_lock; @@ -173,10 +179,8 @@ } ia64_sal_ptc_domain_info_t; typedef struct ia64_sal_ptc_domain_proc_entry { - u64 reserved : 16; - u64 eid : 8; /* eid of processor */ u64 id : 8; /* id of processor */ - u64 ignored : 32; + u64 eid : 8; /* eid of processor */ } ia64_sal_ptc_domain_proc_entry_t; @@ -199,19 +203,15 @@ enum { SAL_INFO_TYPE_MCA = 0, /* Machine check abort information */ SAL_INFO_TYPE_INIT = 1, /* Init information */ - SAL_INFO_TYPE_CMC = 2 /* Corrected machine check information */ -}; - -/* Sub information type encodings */ -enum { - SAL_SUB_INFO_TYPE_PROCESSOR = 0, /* Processor information */ - SAL_SUB_INFO_TYPE_PLATFORM = 1 /* Platform information */ + SAL_INFO_TYPE_CMC = 2, /* Corrected machine check information */ + SAL_INFO_TYPE_CPE = 3 /* Corrected platform error information */ }; /* Encodings for machine check parameter types */ enum { SAL_MC_PARAM_RENDEZ_INT = 1, /* Rendezevous interrupt */ - SAL_MC_PARAM_RENDEZ_WAKEUP = 2 /* Wakeup */ + SAL_MC_PARAM_RENDEZ_WAKEUP = 2, /* Wakeup */ + SAL_MC_PARAM_CPE_INT = 3 /* Corrected Platform Error Int */ }; /* Encodings for rendezvous mechanisms */ @@ -227,174 +227,389 @@ SAL_VECTOR_OS_BOOT_RENDEZ = 2 }; -/* Definition of the SAL Error Log from the SAL spec */ +/* +** Definition of the SAL Error Log from the SAL spec +*/ + +/* SAL Error Record Section GUID Definitions */ +#define SAL_PROC_DEV_ERR_SECT_GUID \ + ((efi_guid_t) { 0xe429faf1, 0x3cb7, 0x11d4, { 0xbc, 0xa7, 0x0, 0x80, \ + 0xc7, 0x3c, 0x88, 0x81 }} ) +#define SAL_PLAT_MEM_DEV_ERR_SECT_GUID \ + ((efi_guid_t) { 0xe429faf2, 0x3cb7, 0x11d4, { 0xbc, 0xa7, 0x0, 0x80, \ + 0xc7, 0x3c, 0x88, 0x81 }} ) +#define SAL_PLAT_SEL_DEV_ERR_SECT_GUID \ + ((efi_guid_t) { 0xe429faf3, 0x3cb7, 0x11d4, { 0xbc, 0xa7, 0x0, 0x80, \ + 0xc7, 0x3c, 0x88, 0x81 }} ) +#define SAL_PLAT_PCI_BUS_ERR_SECT_GUID \ + ((efi_guid_t) { 0xe429faf4, 0x3cb7, 0x11d4, { 0xbc, 0xa7, 0x0, 0x80, \ + 0xc7, 0x3c, 0x88, 0x81 }} ) +#define SAL_PLAT_SMBIOS_DEV_ERR_SECT_GUID \ + ((efi_guid_t) { 0xe429faf5, 0x3cb7, 0x11d4, { 0xbc, 0xa7, 0x0, 0x80, \ + 0xc7, 0x3c, 0x88, 0x81 }} ) +#define SAL_PLAT_PCI_COMP_ERR_SECT_GUID \ + ((efi_guid_t) { 0xe429faf6, 0x3cb7, 0x11d4, { 0xbc, 0xa7, 0x0, 0x80, \ + 0xc7, 0x3c, 0x88, 0x81 }} ) +#define SAL_PLAT_SPECIFIC_ERR_SECT_GUID \ + ((efi_guid_t) { 0xe429faf7, 0x3cb7, 0x11d4, { 0xbc, 0xa7, 0x0, 0x80, \ + 0xc7, 0x3c, 0x88, 0x81 }} ) +#define SAL_PLAT_HOST_CTLR_ERR_SECT_GUID \ + ((efi_guid_t) { 0xe429faf8, 0x3cb7, 0x11d4, { 0xbc, 0xa7, 0x0, 0x80, \ + 0xc7, 0x3c, 0x88, 0x81 }} ) +#define SAL_PLAT_BUS_ERR_SECT_GUID \ + ((efi_guid_t) { 0xe429faf9, 0x3cb7, 0x11d4, { 0xbc, 0xa7, 0x0, 0x80, \ + 0xc7, 0x3c, 0x88, 0x81 }} ) -/* Definition of timestamp according to SAL spec for logging purposes */ +#define MAX_CACHE_ERRORS 6 +#define MAX_TLB_ERRORS 6 +#define MAX_BUS_ERRORS 1 -typedef struct sal_log_timestamp { - u8 slh_century; /* Century (19, 20, 21, ...) */ - u8 slh_year; /* Year (00..99) */ - u8 slh_month; /* Month (1..12) */ - u8 slh_day; /* Day (1..31) */ - u8 slh_reserved; - u8 slh_hour; /* Hour (0..23) */ - u8 slh_minute; /* Minute (0..59) */ +/* Definition of version according to SAL spec for logging purposes */ +typedef struct sal_log_revision +{ + u8 minor; /* BCD (0..99) */ + u8 major; /* BCD (0..99) */ +} sal_log_revision_t; + +/* Definition of timestamp according to SAL spec for logging purposes */ +typedef struct sal_log_timestamp +{ u8 slh_second; /* Second (0..59) */ + u8 slh_minute; /* Minute (0..59) */ + u8 slh_hour; /* Hour (0..23) */ + u8 slh_reserved; + u8 slh_day; /* Day (1..31) */ + u8 slh_month; /* Month (1..12) */ + u8 slh_year; /* Year (00..99) */ + u8 slh_century; /* Century (19, 20, 21, ...) */ } sal_log_timestamp_t; +/* Definition of log record header structures */ +typedef struct sal_log_record_header +{ + u64 id; /* Unique monotonically increasing ID */ + sal_log_revision_t revision; /* Major and Minor revision of header */ + u16 severity; /* Error Severity */ + u32 len; /* Length of this error log in bytes */ + sal_log_timestamp_t timestamp; /* Timestamp */ + efi_guid_t platform_guid; /* Unique OEM Platform ID */ +} sal_log_record_header_t; -#define MAX_CACHE_ERRORS 6 -#define MAX_TLB_ERRORS 6 -#define MAX_BUS_ERRORS 1 +/* Definition of log section header structures */ +typedef struct sal_log_sec_header +{ + efi_guid_t guid; /* Unique Section ID */ + sal_log_revision_t revision; /* Major and Minor revision of Section */ + u16 reserved; + u32 len; /* Section length */ +} sal_log_section_hdr_t; + +typedef struct sal_log_mod_error_info +{ + struct + { + u64 check_info : 1, + requestor_identifier : 1, + responder_identifier : 1, + target_identifier : 1, + precise_ip : 1, + reserved : 59; + } valid; + u64 check_info; + u64 requestor_identifier; + u64 responder_identifier; + u64 target_identifier; + u64 precise_ip; +} sal_log_mod_error_info_t; + +typedef struct sal_processor_static_info +{ + struct + { + u64 minstate : 1, + br : 1, + cr : 1, + ar : 1, + rr : 1, + fr : 1, + reserved : 58; + } valid; + pal_min_state_area_t min_state_area; + u64 br[8]; + u64 cr[128]; + u64 ar[128]; + u64 rr[8]; + struct ia64_fpreg fr[128]; +} sal_processor_static_info_t; -typedef struct sal_log_processor_info { - struct { - u64 slpi_psi : 1, - slpi_cache_check: MAX_CACHE_ERRORS, - slpi_tlb_check : MAX_TLB_ERRORS, - slpi_bus_check : MAX_BUS_ERRORS, - slpi_reserved2 : (31 - (MAX_TLB_ERRORS + MAX_CACHE_ERRORS - + MAX_BUS_ERRORS)), - slpi_minstate : 1, - slpi_bank1_gr : 1, - slpi_br : 1, - slpi_cr : 1, - slpi_ar : 1, - slpi_rr : 1, - slpi_fr : 1, - slpi_reserved1 : 25; - } slpi_valid; - - pal_processor_state_info_t slpi_processor_state_info; - - struct { - pal_cache_check_info_t slpi_cache_check; - u64 slpi_target_address; - } slpi_cache_check_info[MAX_CACHE_ERRORS]; - - pal_tlb_check_info_t slpi_tlb_check_info[MAX_TLB_ERRORS]; - - struct { - pal_bus_check_info_t slpi_bus_check; - u64 slpi_requestor_addr; - u64 slpi_responder_addr; - u64 slpi_target_addr; - } slpi_bus_check_info[MAX_BUS_ERRORS]; - - pal_min_state_area_t slpi_min_state_area; - u64 slpi_br[8]; - u64 slpi_cr[128]; - u64 slpi_ar[128]; - u64 slpi_rr[8]; - u64 slpi_fr[128]; +typedef struct sal_log_processor_info +{ + sal_log_section_hdr_t header; + struct + { + u64 proc_error_map : 1, + proc_state_param : 1, + proc_cr_lid : 1, + psi_static_struct : 1, + num_cache_check : 4, + num_tlb_check : 4, + num_bus_check : 4, + num_reg_file_check : 4, + num_ms_check : 4, + cpuid_info : 1, + reserved1 : 39; + } valid; + u64 proc_error_map; + u64 proc_state_parameter; + u64 proc_cr_lid; + sal_log_mod_error_info_t cache_check_info[16]; + sal_log_mod_error_info_t tlb_check_info[16]; + sal_log_mod_error_info_t bus_check_info[16]; + sal_log_mod_error_info_t reg_file_check_info[16]; + sal_log_mod_error_info_t ms_check_info[16]; + struct + { + u64 regs[5]; + u64 reserved; + } cpuid_info; + sal_processor_static_info_t processor_static_info; } sal_log_processor_info_t; /* platform error log structures */ -typedef struct platerr_logheader { - u64 nextlog; /* next log offset if present */ - u64 loglength; /* log length */ - u64 logsubtype; /* log subtype memory/bus/component */ - u64 eseverity; /* error severity */ -} ehdr_t; - -typedef struct sysmem_errlog { - ehdr_t lhdr; /* header */ - u64 vflag; /* valid bits for each field in the log */ - u64 addr; /* memory address */ - u64 data; /* memory data */ - u64 cmd; /* command bus value if any */ - u64 ctrl; /* control bus value if any */ - u64 addrsyndrome; /* memory address ecc/parity syndrome bits */ - u64 datasyndrome; /* data ecc/parity syndrome */ - u64 cacheinfo; /* platform cache info as defined in pal spec. table 7-34 */ -} merrlog_t; - -typedef struct sysbus_errlog { - ehdr_t lhdr; /* linkded list header */ - u64 vflag; /* valid bits for each field in the log */ - u64 busnum; /* bus number in error */ - u64 reqaddr; /* requestor address */ - u64 resaddr; /* responder address */ - u64 taraddr; /* target address */ - u64 data; /* requester r/w data */ - u64 cmd; /* bus commands */ - u64 ctrl; /* bus controls (be# &-0) */ - u64 addrsyndrome; /* addr bus ecc/parity bits */ - u64 datasyndrome; /* data bus ecc/parity bits */ - u64 cmdsyndrome; /* command bus ecc/parity bits */ - u64 ctrlsyndrome; /* control bus ecc/parity bits */ -} berrlog_t; -/* platform error log structures */ -typedef struct syserr_chdr { /* one header per component */ - u64 busnum; /* bus number on which the component resides */ - u64 devnum; /* same as device select */ - u64 funcid; /* function id of the device */ - u64 devid; /* pci device id */ - u64 classcode; /* pci class code for the device */ - u64 cmdreg; /* pci command reg value */ - u64 statreg; /* pci status reg value */ -} chdr_t; - -typedef struct cfginfo { - u64 cfgaddr; - u64 cfgval; -} cfginfo_t; - -typedef struct sys_comperr { /* per component */ - ehdr_t lhdr; /* linked list header */ - u64 vflag; /* valid bits for each field in the log */ - chdr_t scomphdr; - u64 numregpair; /* number of reg addr/value pairs */ - cfginfo_t cfginfo; -} cerrlog_t; - -typedef struct sel_records { - ehdr_t lhdr; - u64 seldata; -} isel_t; - -typedef struct plat_errlog { - u64 mbcsvalid; /* valid bits for each type of log */ - merrlog_t smemerrlog; /* platform memory error logs */ - berrlog_t sbuserrlog; /* platform bus error logs */ - cerrlog_t scomperrlog; /* platform chipset error logs */ - isel_t selrecord; /* ipmi sel record */ -} platforminfo_t; - -/* over all log structure (processor+platform) */ - -typedef union udev_specific_log { - sal_log_processor_info_t proclog; - platforminfo_t platlog; -} devicelog_t; - - -#define sal_log_processor_info_psi_valid slpi_valid.spli_psi -#define sal_log_processor_info_cache_check_valid slpi_valid.spli_cache_check -#define sal_log_processor_info_tlb_check_valid slpi_valid.spli_tlb_check -#define sal_log_processor_info_bus_check_valid slpi_valid.spli_bus_check -#define sal_log_processor_info_minstate_valid slpi_valid.spli_minstate -#define sal_log_processor_info_bank1_gr_valid slpi_valid.slpi_bank1_gr -#define sal_log_processor_info_br_valid slpi_valid.slpi_br -#define sal_log_processor_info_cr_valid slpi_valid.slpi_cr -#define sal_log_processor_info_ar_valid slpi_valid.slpi_ar -#define sal_log_processor_info_rr_valid slpi_valid.slpi_rr -#define sal_log_processor_info_fr_valid slpi_valid.slpi_fr - -typedef struct sal_log_header { - u64 slh_next_log; /* Offset of the next log from the beginning of this structure */ - u32 slh_log_len; /* Length of this error log in bytes */ - u16 slh_log_type; /* Type of log (0 - cpu ,1 - platform) */ - u16 slh_log_sub_type; /* SGI specific sub type */ - sal_log_timestamp_t slh_log_timestamp; /* Timestamp */ -} sal_log_header_t; - -/* SAL PSI log structure */ -typedef struct psilog { - sal_log_header_t sal_elog_header; - devicelog_t devlog; -} ia64_psilog_t; +typedef struct sal_log_mem_dev_err_info +{ + sal_log_section_hdr_t header; + struct + { + u64 error_status : 1, + physical_addr : 1, + addr_mask : 1, + node : 1, + card : 1, + module : 1, + bank : 1, + device : 1, + row : 1, + column : 1, + bit_position : 1, + requestor_id : 1, + responder_id : 1, + target_id : 1, + bus_spec_data : 1, + oem_id : 1, + oem_data : 1, + reserved : 47; + } valid; + u64 error_status; + u64 physical_addr; + u64 addr_mask; + u16 node; + u16 card; + u16 module; + u16 bank; + u16 device; + u16 row; + u16 column; + u16 bit_position; + u64 requestor_id; + u64 responder_id; + u64 target_id; + u64 bus_spec_data; + u8 oem_id[16]; + u8 oem_data[1]; /* Variable length data */ +} sal_log_mem_dev_err_info_t; + +typedef struct sal_log_sel_dev_err_info +{ + sal_log_section_hdr_t header; + struct + { + u64 record_id : 1, + record_type : 1, + generator_id : 1, + evm_rev : 1, + sensor_type : 1, + sensor_num : 1, + event_dir : 1, + event_data1 : 1, + event_data2 : 1, + event_data3 : 1, + reserved : 54; + } valid; + u16 record_id; + u8 record_type; + u8 timestamp[4]; + u16 generator_id; + u8 evm_rev; + u8 sensor_type; + u8 sensor_num; + u8 event_dir; + u8 event_data1; + u8 event_data2; + u8 event_data3; +} sal_log_sel_dev_err_info_t; + +typedef struct sal_log_pci_bus_err_info +{ + sal_log_section_hdr_t header; + struct + { + u64 err_status : 1, + err_type : 1, + bus_id : 1, + bus_address : 1, + bus_data : 1, + bus_cmd : 1, + requestor_id : 1, + responder_id : 1, + target_id : 1, + oem_data : 1, + reserved : 54; + } valid; + u64 err_status; + u16 err_type; + u16 bus_id; + u32 reserved; + u64 bus_address; + u64 bus_data; + u64 bus_cmd; + u64 requestor_id; + u64 responder_id; + u64 target_id; + u8 oem_data[1]; /* Variable length data */ +} sal_log_pci_bus_err_info_t; + +typedef struct sal_log_smbios_dev_err_info +{ + sal_log_section_hdr_t header; + struct + { + u64 event_type : 1, + length : 1, + time_stamp : 1, + data : 1, + reserved1 : 60; + } valid; + u8 event_type; + u8 length; + u8 time_stamp[6]; + u8 data[1]; // data of variable length, length == slsmb_length +} sal_log_smbios_dev_err_info_t; + +typedef struct sal_log_pci_comp_err_info +{ + sal_log_section_hdr_t header; + struct + { + u64 err_status : 1, + comp_info : 1, + num_mem_regs : 1, + num_io_regs : 1, + reg_data_pairs : 1, + oem_data : 1, + reserved : 58; + } valid; + u64 err_status; + struct + { + u16 vendor_id; + u16 device_id; + u16 class_code; + u8 func_num; + u8 dev_num; + u8 bus_num; + u8 seg_num; + u8 reserved[6]; + } comp_info; + u32 num_mem_regs; + u32 num_io_regs; + u64 reg_data_pairs[1]; + /* array of address/data register pairs is num_mem_regs + num_io_regs + elements long. Each array element consists of a u64 address followed + by a u64 data value. The oem_data array immediately follows the the + reg_data_pairs array */ + u8 oem_data[1]; /* Variable length data */ +} sal_log_pci_comp_err_info_t; + +typedef struct sal_log_plat_specific_err_info +{ + sal_log_section_hdr_t header; + struct + { + u64 err_status : 1, + guid : 1, + oem_data : 1, + reserved : 61; + } valid; + u64 err_status; + efi_guid_t guid; + u8 oem_data[1]; /* platform specific variable length data */ +} sal_log_plat_specific_err_info_t; + +typedef struct sal_log_host_ctlr_err_info +{ + sal_log_section_hdr_t header; + struct + { + u64 err_status : 1, + requestor_id : 1, + responder_id : 1, + target_id : 1, + bus_spec_data : 1, + oem_data : 1, + reserved : 58; + } valid; + u64 err_status; + u64 requestor_id; + u64 responder_id; + u64 target_id; + u64 bus_spec_data; + u8 oem_data[1]; /* Variable length OEM data */ +} sal_log_host_ctlr_err_info_t; + +typedef struct sal_log_plat_bus_err_info +{ + sal_log_section_hdr_t header; + struct + { + u64 err_status : 1, + requestor_id : 1, + responder_id : 1, + target_id : 1, + bus_spec_data : 1, + oem_data : 1, + reserved : 58; + } valid; + u64 err_status; + u64 requestor_id; + u64 responder_id; + u64 target_id; + u64 bus_spec_data; + u8 oem_data[1]; /* Variable length OEM data */ +} sal_log_plat_bus_err_info_t; + +/* Overall platform error section structure */ +typedef union sal_log_platform_err_info +{ + sal_log_mem_dev_err_info_t mem_dev_err; + sal_log_sel_dev_err_info_t sel_dev_err; + sal_log_pci_bus_err_info_t pci_bus_err; + sal_log_smbios_dev_err_info_t smbios_dev_err; + sal_log_pci_comp_err_info_t pci_comp_err; + sal_log_plat_specific_err_info_t plat_specific_err; + sal_log_host_ctlr_err_info_t host_ctlr_err; + sal_log_plat_bus_err_info_t plat_bus_err; +} sal_log_platform_err_info_t; + +/* SAL log over-all, multi-section error record structure (processor+platform) */ +typedef struct err_rec +{ + sal_log_record_header_t sal_elog_header; + sal_log_processor_info_t proc_err; + sal_log_platform_err_info_t plat_err; + u8 oem_data_pad[1024]; +} ia64_err_rec_t; /* * Now define a couple of inline functions for improved type checking @@ -433,19 +648,20 @@ } /* Clear the processor and platform information logged by SAL with respect to the - * machine state at the time of MCA's, INITs or CMCs + * machine state at the time of MCA's, INITs, CMCs, or CPEs. */ static inline s64 ia64_sal_clear_state_info (u64 sal_info_type) { struct ia64_sal_retval isrv; - SAL_CALL(isrv, SAL_CLEAR_STATE_INFO, sal_info_type, 0, 0, 0, 0, 0, 0); + SAL_CALL(isrv, SAL_CLEAR_STATE_INFO, sal_info_type, 0, + 0, 0, 0, 0, 0); return isrv.status; } /* Get the processor and platform information logged by SAL with respect to the machine - * state at the time of the MCAs, INITs or CMCs. + * state at the time of the MCAs, INITs, CMCs, or CPEs. */ static inline u64 ia64_sal_get_state_info (u64 sal_info_type, u64 *sal_info) @@ -455,16 +671,18 @@ sal_info, 0, 0, 0, 0); if (isrv.status) return 0; + return isrv.v0; } /* Get the maximum size of the information logged by SAL with respect to the machine - * state at the time of MCAs, INITs or CMCs + * state at the time of MCAs, INITs, CMCs, or CPEs. */ static inline u64 ia64_sal_get_state_info_size (u64 sal_info_type) { struct ia64_sal_retval isrv; - SAL_CALL(isrv, SAL_GET_STATE_INFO_SIZE, sal_info_type, 0, 0, 0, 0, 0, 0); + SAL_CALL(isrv, SAL_GET_STATE_INFO_SIZE, sal_info_type, 0, + 0, 0, 0, 0, 0); if (isrv.status) return 0; return isrv.v0; diff -urN linux-2.4.10/include/asm-ia64/semaphore.h linux-2.4.10-lia/include/asm-ia64/semaphore.h --- linux-2.4.10/include/asm-ia64/semaphore.h Tue Apr 17 17:19:31 2001 +++ linux-2.4.10-lia/include/asm-ia64/semaphore.h Mon Sep 24 23:02:56 2001 @@ -63,8 +63,6 @@ extern int __down_trylock (struct semaphore * sem); extern void __up (struct semaphore * sem); -extern spinlock_t semaphore_wake_lock; - /* * Atomically decrement the semaphore's count. If it goes negative, * block the calling thread in the TASK_UNINTERRUPTIBLE state. diff -urN linux-2.4.10/include/asm-ia64/sembuf.h linux-2.4.10-lia/include/asm-ia64/sembuf.h --- linux-2.4.10/include/asm-ia64/sembuf.h Sun Feb 6 18:42:40 2000 +++ linux-2.4.10-lia/include/asm-ia64/sembuf.h Mon Sep 24 22:10:28 2001 @@ -1,7 +1,7 @@ #ifndef _ASM_IA64_SEMBUF_H #define _ASM_IA64_SEMBUF_H -/* +/* * The semid64_ds structure for IA-64 architecture. * Note extra padding because this structure is passed back and forth * between kernel and user space. diff -urN linux-2.4.10/include/asm-ia64/shmbuf.h linux-2.4.10-lia/include/asm-ia64/shmbuf.h --- linux-2.4.10/include/asm-ia64/shmbuf.h Sun Feb 6 18:42:40 2000 +++ linux-2.4.10-lia/include/asm-ia64/shmbuf.h Mon Sep 24 22:10:36 2001 @@ -1,7 +1,7 @@ #ifndef _ASM_IA64_SHMBUF_H #define _ASM_IA64_SHMBUF_H -/* +/* * The shmid64_ds structure for IA-64 architecture. * Note extra padding because this structure is passed back and forth * between kernel and user space. diff -urN linux-2.4.10/include/asm-ia64/sigcontext.h linux-2.4.10-lia/include/asm-ia64/sigcontext.h --- linux-2.4.10/include/asm-ia64/sigcontext.h Tue Jul 31 10:30:09 2001 +++ linux-2.4.10-lia/include/asm-ia64/sigcontext.h Mon Sep 24 22:10:45 2001 @@ -2,13 +2,13 @@ #define _ASM_IA64_SIGCONTEXT_H /* - * Copyright (C) 1998, 1999 Hewlett-Packard Co - * Copyright (C) 1998, 1999 David Mosberger-Tang + * Copyright (C) 1998, 1999, 2001 Hewlett-Packard Co + * Copyright (C) 1998, 1999, 2001 David Mosberger-Tang */ #include -#define IA64_SC_FLAG_ONSTACK_BIT 1 /* is handler running on signal stack? */ +#define IA64_SC_FLAG_ONSTACK_BIT 0 /* is handler running on signal stack? */ #define IA64_SC_FLAG_IN_SYSCALL_BIT 1 /* did signal interrupt a syscall? */ #define IA64_SC_FLAG_FPH_VALID_BIT 2 /* is state in f[32]-f[127] valid? */ @@ -18,6 +18,19 @@ # ifndef __ASSEMBLY__ +/* + * Note on handling of register backing store: sc_ar_bsp contains the address that would + * be found in ar.bsp after executing a "cover" instruction the context in which the + * signal was raised. If signal delivery required switching to an alternate signal stack + * (sc_rbs_base is not NULL), the "dirty" partition (as it would exist after executing the + * imaginary "cover" instruction) is backed by the *alternate* signal stack, not the + * original one. In this case, sc_rbs_base contains the base address of the new register + * backing store. The number of registers in the dirty partition can be calculated as: + * + * ndirty = ia64_rse_num_regs(sc_rbs_base, sc_rbs_base + (sc_loadrs >> 16)) + * + */ + struct sigcontext { unsigned long sc_flags; /* see manifest constants above */ unsigned long sc_nat; /* bit i == 1 iff scratch reg gr[i] is a NaT */ @@ -40,8 +53,10 @@ unsigned long sc_gr[32]; /* general registers (static partition) */ struct ia64_fpreg sc_fr[128]; /* floating-point registers */ - unsigned long sc_rsvd[16]; /* reserved for future use */ + unsigned long sc_rbs_base; /* NULL or new base of sighandler's rbs */ + unsigned long sc_loadrs; /* see description above */ + unsigned long sc_rsvd[14]; /* reserved for future use */ /* * The mask must come last so we can increase _NSIG_WORDS * without breaking binary compatibility. diff -urN linux-2.4.10/include/asm-ia64/signal.h linux-2.4.10-lia/include/asm-ia64/signal.h --- linux-2.4.10/include/asm-ia64/signal.h Tue Jul 31 10:30:09 2001 +++ linux-2.4.10-lia/include/asm-ia64/signal.h Mon Sep 24 22:10:57 2001 @@ -2,8 +2,8 @@ #define _ASM_IA64_SIGNAL_H /* - * Copyright (C) 1998-2000 Hewlett-Packard Co - * Copyright (C) 1998-2000 David Mosberger-Tang + * Copyright (C) 1998-2001 Hewlett-Packard Co + * David Mosberger-Tang * * Unfortunately, this file is being included by bits/signal.h in * glibc-2.x. Hence the #ifdef __KERNEL__ ugliness. @@ -80,14 +80,24 @@ #define SA_RESTORER 0x04000000 -/* +/* * sigaltstack controls */ #define SS_ONSTACK 1 #define SS_DISABLE 2 -#define MINSIGSTKSZ 2048 -#define SIGSTKSZ 8192 +/* + * The minimum stack size needs to be fairly large because we want to + * be sure that an app compiled for today's CPUs will continue to run + * on all future CPU models. The CPU model matters because the signal + * frame needs to have space for the complete machine state, including + * all physical stacked registers. The number of physical stacked + * registers is CPU model dependent, but given that the width of + * ar.rsc.loadrs is 14 bits, we can assume that they'll never take up + * more than 16KB of space. + */ +#define MINSIGSTKSZ 131027 /* min. stack size for sigaltstack() */ +#define SIGSTKSZ 262144 /* default stack size for sigaltstack() */ #ifdef __KERNEL__ diff -urN linux-2.4.10/include/asm-ia64/smp.h linux-2.4.10-lia/include/asm-ia64/smp.h --- linux-2.4.10/include/asm-ia64/smp.h Tue Jul 31 10:30:09 2001 +++ linux-2.4.10-lia/include/asm-ia64/smp.h Mon Sep 24 22:26:48 2001 @@ -4,7 +4,7 @@ * Copyright (C) 1999 VA Linux Systems * Copyright (C) 1999 Walt Drummond * Copyright (C) 2001 Hewlett-Packard Co - * Copyright (C) 2001 David Mosberger-Tang + * David Mosberger-Tang */ #ifndef _ASM_IA64_SMP_H #define _ASM_IA64_SMP_H @@ -18,6 +18,7 @@ #include #include +#include #include #include @@ -107,7 +108,12 @@ return lid.f.id << 8 | lid.f.eid; } -#define NO_PROC_ID (-1) +#define NO_PROC_ID 0xffffffff /* no processor magic marker */ + +/* + * Extra overhead to move a task from one cpu to another (due to TLB and cache misses). + * Expressed in "negative nice value" units (larger number means higher priority/penalty). + */ #define PROC_CHANGE_PENALTY 20 extern void __init init_smp_config (void); diff -urN linux-2.4.10/include/asm-ia64/smplock.h linux-2.4.10-lia/include/asm-ia64/smplock.h --- linux-2.4.10/include/asm-ia64/smplock.h Thu Apr 5 12:51:47 2001 +++ linux-2.4.10-lia/include/asm-ia64/smplock.h Mon Sep 24 23:02:56 2001 @@ -17,7 +17,7 @@ /* * Release global kernel lock and global interrupt lock */ -static __inline__ void +static __inline__ void release_kernel_lock(struct task_struct *task, int cpu) { if (task->lock_depth >= 0) @@ -29,7 +29,7 @@ /* * Re-acquire the kernel lock */ -static __inline__ void +static __inline__ void reacquire_kernel_lock(struct task_struct *task) { if (task->lock_depth >= 0) @@ -43,14 +43,14 @@ * so we only need to worry about other * CPU's. */ -static __inline__ void +static __inline__ void lock_kernel(void) { if (!++current->lock_depth) spin_lock(&kernel_flag); } -static __inline__ void +static __inline__ void unlock_kernel(void) { if (--current->lock_depth < 0) diff -urN linux-2.4.10/include/asm-ia64/spinlock.h linux-2.4.10-lia/include/asm-ia64/spinlock.h --- linux-2.4.10/include/asm-ia64/spinlock.h Tue Jul 31 10:30:09 2001 +++ linux-2.4.10-lia/include/asm-ia64/spinlock.h Mon Sep 24 22:56:20 2001 @@ -2,8 +2,8 @@ #define _ASM_IA64_SPINLOCK_H /* - * Copyright (C) 1998-2000 Hewlett-Packard Co - * Copyright (C) 1998-2000 David Mosberger-Tang + * Copyright (C) 1998-2001 Hewlett-Packard Co + * Copyright (C) 1998-2001 David Mosberger-Tang * Copyright (C) 1999 Walt Drummond * * This file is used for SMP configurations only. @@ -39,7 +39,7 @@ "mov r30=1\n" \ "mov ar.ccv=r0\n" \ ";;\n" \ - IA64_SEMFIX"cmpxchg4.acq r30=[%0],r30,ar.ccv\n" \ + "cmpxchg4.acq r30=[%0],r30,ar.ccv\n" \ ";;\n" \ "cmp.ne p15,p0=r30,r0\n" \ "(p15) br.call.spnt.few b7=ia64_spinlock_contention\n" \ @@ -56,7 +56,7 @@ __asm__ __volatile__ ( \ "mov ar.ccv=r0\n" \ ";;\n" \ - IA64_SEMFIX"cmpxchg4.acq %0=[%2],%1,ar.ccv\n" \ + "cmpxchg4.acq %0=[%2],%1,ar.ccv\n" \ : "=r"(result) : "r"(1), "r"(&(x)->lock) : "ar.ccv", "memory"); \ (result == 0); \ }) @@ -84,11 +84,11 @@ "mov r29 = 1\n" \ ";;\n" \ "1:\n" \ - "ld4 r2 = [%0]\n" \ + "ld4.bias r2 = [%0]\n" \ ";;\n" \ "cmp4.eq p0,p7 = r0,r2\n" \ "(p7) br.cond.spnt.few 1b \n" \ - IA64_SEMFIX"cmpxchg4.acq r2 = [%0], r29, ar.ccv\n" \ + "cmpxchg4.acq r2 = [%0], r29, ar.ccv\n" \ ";;\n" \ "cmp4.eq p0,p7 = r0, r2\n" \ "(p7) br.cond.spnt.few 1b\n" \ @@ -108,15 +108,17 @@ } rwlock_t; #define RW_LOCK_UNLOCKED (rwlock_t) { 0, 0 } +#define rwlock_init(x) do { *(x) = RW_LOCK_UNLOCKED; } while(0) + #define read_lock(rw) \ do { \ int tmp = 0; \ - __asm__ __volatile__ ("1:\t"IA64_SEMFIX"fetchadd4.acq %0 = [%1], 1\n" \ + __asm__ __volatile__ ("1:\tfetchadd4.acq %0 = [%1], 1\n" \ ";;\n" \ "tbit.nz p6,p0 = %0, 31\n" \ "(p6) br.cond.sptk.few 2f\n" \ ".section .text.lock,\"ax\"\n" \ - "2:\t"IA64_SEMFIX"fetchadd4.rel %0 = [%1], -1\n" \ + "2:\tfetchadd4.rel %0 = [%1], -1\n" \ ";;\n" \ "3:\tld4.acq %0 = [%1]\n" \ ";;\n" \ @@ -132,7 +134,7 @@ #define read_unlock(rw) \ do { \ int tmp = 0; \ - __asm__ __volatile__ (IA64_SEMFIX"fetchadd4.rel %0 = [%1], -1\n" \ + __asm__ __volatile__ ("fetchadd4.rel %0 = [%1], -1\n" \ : "=r" (tmp) \ : "r" (rw) \ : "memory"); \ @@ -142,14 +144,14 @@ do { \ __asm__ __volatile__ ( \ "mov ar.ccv = r0\n" \ - "movl r29 = 0x80000000\n" \ + "dep r29 = -1, r0, 31, 1\n" \ ";;\n" \ "1:\n" \ "ld4 r2 = [%0]\n" \ ";;\n" \ "cmp4.eq p0,p7 = r0,r2\n" \ "(p7) br.cond.spnt.few 1b \n" \ - IA64_SEMFIX"cmpxchg4.acq r2 = [%0], r29, ar.ccv\n" \ + "cmpxchg4.acq r2 = [%0], r29, ar.ccv\n" \ ";;\n" \ "cmp4.eq p0,p7 = r0, r2\n" \ "(p7) br.cond.spnt.few 1b\n" \ diff -urN linux-2.4.10/include/asm-ia64/system.h linux-2.4.10-lia/include/asm-ia64/system.h --- linux-2.4.10/include/asm-ia64/system.h Tue Jul 31 10:30:09 2001 +++ linux-2.4.10-lia/include/asm-ia64/system.h Mon Sep 24 22:26:37 2001 @@ -29,15 +29,6 @@ #define GATE_ADDR (0xa000000000000000 + PAGE_SIZE) #define PERCPU_ADDR (0xa000000000000000 + 2*PAGE_SIZE) -#if defined(CONFIG_ITANIUM_B0_SPECIFIC) || defined(CONFIG_ITANIUM_B1_SPECIFIC) - /* Workaround for Errata 97. */ -# define IA64_SEMFIX_INSN mf; -# define IA64_SEMFIX "mf;" -#else -# define IA64_SEMFIX_INSN -# define IA64_SEMFIX "" -#endif - #ifndef __ASSEMBLY__ #include @@ -210,12 +201,12 @@ ({ \ switch (sz) { \ case 4: \ - __asm__ __volatile__ (IA64_SEMFIX"fetchadd4.rel %0=[%1],%2" \ + __asm__ __volatile__ ("fetchadd4.rel %0=[%1],%2" \ : "=r"(tmp) : "r"(v), "i"(n) : "memory"); \ break; \ \ case 8: \ - __asm__ __volatile__ (IA64_SEMFIX"fetchadd8.rel %0=[%1],%2" \ + __asm__ __volatile__ ("fetchadd8.rel %0=[%1],%2" \ : "=r"(tmp) : "r"(v), "i"(n) : "memory"); \ break; \ \ @@ -257,22 +248,22 @@ switch (size) { case 1: - __asm__ __volatile (IA64_SEMFIX"xchg1 %0=[%1],%2" : "=r" (result) + __asm__ __volatile ("xchg1 %0=[%1],%2" : "=r" (result) : "r" (ptr), "r" (x) : "memory"); return result; case 2: - __asm__ __volatile (IA64_SEMFIX"xchg2 %0=[%1],%2" : "=r" (result) + __asm__ __volatile ("xchg2 %0=[%1],%2" : "=r" (result) : "r" (ptr), "r" (x) : "memory"); return result; case 4: - __asm__ __volatile (IA64_SEMFIX"xchg4 %0=[%1],%2" : "=r" (result) + __asm__ __volatile ("xchg4 %0=[%1],%2" : "=r" (result) : "r" (ptr), "r" (x) : "memory"); return result; case 8: - __asm__ __volatile (IA64_SEMFIX"xchg8 %0=[%1],%2" : "=r" (result) + __asm__ __volatile ("xchg8 %0=[%1],%2" : "=r" (result) : "r" (ptr), "r" (x) : "memory"); return result; } @@ -313,22 +304,22 @@ __asm__ __volatile__ ("mov ar.ccv=%0;;" :: "rO"(_o_)); \ switch (size) { \ case 1: \ - __asm__ __volatile__ (IA64_SEMFIX"cmpxchg1."sem" %0=[%1],%2,ar.ccv" \ + __asm__ __volatile__ ("cmpxchg1."sem" %0=[%1],%2,ar.ccv" \ : "=r"(_r_) : "r"(_p_), "r"(_n_) : "memory"); \ break; \ \ case 2: \ - __asm__ __volatile__ (IA64_SEMFIX"cmpxchg2."sem" %0=[%1],%2,ar.ccv" \ + __asm__ __volatile__ ("cmpxchg2."sem" %0=[%1],%2,ar.ccv" \ : "=r"(_r_) : "r"(_p_), "r"(_n_) : "memory"); \ break; \ \ case 4: \ - __asm__ __volatile__ (IA64_SEMFIX"cmpxchg4."sem" %0=[%1],%2,ar.ccv" \ + __asm__ __volatile__ ("cmpxchg4."sem" %0=[%1],%2,ar.ccv" \ : "=r"(_r_) : "r"(_p_), "r"(_n_) : "memory"); \ break; \ \ case 8: \ - __asm__ __volatile__ (IA64_SEMFIX"cmpxchg8."sem" %0=[%1],%2,ar.ccv" \ + __asm__ __volatile__ ("cmpxchg8."sem" %0=[%1],%2,ar.ccv" \ : "=r"(_r_) : "r"(_p_), "r"(_n_) : "memory"); \ break; \ \ diff -urN linux-2.4.10/include/asm-ia64/user.h linux-2.4.10-lia/include/asm-ia64/user.h --- linux-2.4.10/include/asm-ia64/user.h Sun Feb 6 18:42:40 2000 +++ linux-2.4.10-lia/include/asm-ia64/user.h Mon Sep 24 22:56:58 2001 @@ -24,11 +24,12 @@ * current->start_stack, so we round each of these in order to be able * to write an integer number of pages. * - * Copyright (C) 1998, 1999 Hewlett-Packard Co - * Copyright (C) 1998, 1999 David Mosberger-Tang + * Copyright (C) 1998, 1999, 2001 Hewlett-Packard Co + * Copyright (C) 1998, 1999, 2001 David Mosberger-Tang */ #include +#include #include diff -urN linux-2.4.10/include/linux/agp_backend.h linux-2.4.10-lia/include/linux/agp_backend.h --- linux-2.4.10/include/linux/agp_backend.h Mon Sep 24 15:08:31 2001 +++ linux-2.4.10-lia/include/linux/agp_backend.h Mon Sep 24 21:30:16 2001 @@ -27,6 +27,8 @@ #ifndef _AGP_BACKEND_H #define _AGP_BACKEND_H 1 +#include + #ifndef TRUE #define TRUE 1 #endif @@ -48,6 +50,7 @@ INTEL_I815, INTEL_I840, INTEL_I850, + INTEL_460GX, VIA_GENERIC, VIA_VP3, VIA_MVP3, @@ -111,6 +114,7 @@ size_t page_count; int num_scratch_pages; unsigned long *memory; + void *vmptr; off_t pg_start; u32 type; u32 physical; diff -urN linux-2.4.10/include/linux/crc32.h linux-2.4.10-lia/include/linux/crc32.h --- linux-2.4.10/include/linux/crc32.h Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/include/linux/crc32.h Wed Dec 6 22:40:05 2000 @@ -0,0 +1,17 @@ +/* + * crc32.h + * See linux/lib/crc32.c for license and changes + */ +#ifndef _LINUX_CRC32_H +#define _LINUX_CRC32_H + +#include + +/* + * This computes a 32 bit CRC of the data in the buffer, and returns the CRC. + * The polynomial used is 0xedb88320. + */ + +extern u32 crc32 (const void *buf, unsigned long len, u32 seed); + +#endif /* _LINUX_CRC32_H */ diff -urN linux-2.4.10/include/linux/devfs_fs_kernel.h linux-2.4.10-lia/include/linux/devfs_fs_kernel.h --- linux-2.4.10/include/linux/devfs_fs_kernel.h Mon Sep 24 15:08:33 2001 +++ linux-2.4.10-lia/include/linux/devfs_fs_kernel.h Mon Sep 24 23:02:56 2001 @@ -97,6 +97,9 @@ extern devfs_handle_t devfs_get_next_sibling (devfs_handle_t de); extern void devfs_auto_unregister (devfs_handle_t master,devfs_handle_t slave); extern devfs_handle_t devfs_get_unregister_slave (devfs_handle_t master); +#ifdef CONFIG_DEVFS_GUID +extern void devfs_unregister_slave (devfs_handle_t master); +#endif extern const char *devfs_get_name (devfs_handle_t de, unsigned int *namelen); extern int devfs_register_chrdev (unsigned int major, const char *name, struct file_operations *fops); diff -urN linux-2.4.10/include/linux/genhd.h linux-2.4.10-lia/include/linux/genhd.h --- linux-2.4.10/include/linux/genhd.h Mon Sep 24 15:08:33 2001 +++ linux-2.4.10-lia/include/linux/genhd.h Mon Sep 24 23:02:56 2001 @@ -13,6 +13,10 @@ #include #include +#ifdef CONFIG_DEVFS_GUID +#include +#endif + /* These three have identical behaviour; use the second one if DOS fdisk gets confused about extended/logical partitions starting past cylinder 1023. */ #define DOS_EXTENDED_PARTITION 5 @@ -52,6 +56,9 @@ long nr_sects; devfs_handle_t de; /* primary (master) devfs entry */ int number; /* stupid old code wastes space */ +#ifdef CONFIG_DEVFS_GUID + efi_guid_t *guid; +#endif }; #define GENHD_FL_REMOVABLE 1 diff -urN linux-2.4.10/include/linux/highmem.h linux-2.4.10-lia/include/linux/highmem.h --- linux-2.4.10/include/linux/highmem.h Mon Sep 24 15:08:33 2001 +++ linux-2.4.10-lia/include/linux/highmem.h Mon Sep 24 23:02:56 2001 @@ -46,7 +46,7 @@ static inline void clear_user_highpage(struct page *page, unsigned long vaddr) { void *addr = kmap_atomic(page, KM_USER0); - clear_user_page(addr, vaddr); + clear_user_page(addr, vaddr, page); kunmap_atomic(addr, KM_USER0); } @@ -88,7 +88,7 @@ vfrom = kmap_atomic(from, KM_USER0); vto = kmap_atomic(to, KM_USER1); - copy_user_page(vto, vfrom, vaddr); + copy_user_page(vto, vfrom, vaddr, to); kunmap_atomic(vfrom, KM_USER0); kunmap_atomic(vto, KM_USER1); } diff -urN linux-2.4.10/include/linux/irq.h linux-2.4.10-lia/include/linux/irq.h --- linux-2.4.10/include/linux/irq.h Mon Sep 24 15:08:33 2001 +++ linux-2.4.10-lia/include/linux/irq.h Mon Sep 24 23:02:56 2001 @@ -56,15 +56,13 @@ * * Pad this out to 32 bytes for cache and indexing reasons. */ -typedef struct { +typedef struct irq_desc { unsigned int status; /* IRQ status */ hw_irq_controller *handler; struct irqaction *action; /* IRQ action list */ unsigned int depth; /* nested irq disables */ spinlock_t lock; } ____cacheline_aligned irq_desc_t; - -extern irq_desc_t irq_desc [NR_IRQS]; #include /* the arch dependent stuff */ diff -urN linux-2.4.10/include/linux/irq_cpustat.h linux-2.4.10-lia/include/linux/irq_cpustat.h --- linux-2.4.10/include/linux/irq_cpustat.h Fri Aug 10 18:13:47 2001 +++ linux-2.4.10-lia/include/linux/irq_cpustat.h Mon Jul 23 14:21:12 2001 @@ -23,12 +23,12 @@ #define __IRQ_STAT(cpu, member) (irq_stat[cpu].member) #else #define __IRQ_STAT(cpu, member) ((void)(cpu), irq_stat[0].member) -#endif +#endif /* arch independent irq_stat fields */ #define softirq_pending(cpu) __IRQ_STAT((cpu), __softirq_pending) -#define local_irq_count(cpu) __IRQ_STAT((cpu), __local_irq_count) -#define local_bh_count(cpu) __IRQ_STAT((cpu), __local_bh_count) +#define irq_count(cpu) __IRQ_STAT((cpu), __irq_count) +#define bh_count(cpu) __IRQ_STAT((cpu), __bh_count) #define syscall_count(cpu) __IRQ_STAT((cpu), __syscall_count) #define ksoftirqd_task(cpu) __IRQ_STAT((cpu), __ksoftirqd_task) /* arch dependent irq_stat fields */ diff -urN linux-2.4.10/include/linux/mm.h linux-2.4.10-lia/include/linux/mm.h --- linux-2.4.10/include/linux/mm.h Mon Sep 24 15:08:34 2001 +++ linux-2.4.10-lia/include/linux/mm.h Mon Sep 24 23:02:56 2001 @@ -101,6 +101,8 @@ #define VM_DONTCOPY 0x00020000 /* Do not copy this vma on fork */ #define VM_DONTEXPAND 0x00040000 /* Cannot expand with mremap() */ #define VM_RESERVED 0x00080000 /* Don't unmap it from swap_out */ +#define VM_WRITECOMBINED 0x00100000 /* Write-combined */ +#define VM_NONCACHED 0x00200000 /* Noncached access */ #define VM_STACK_FLAGS 0x00000177 diff -urN linux-2.4.10/include/linux/smp.h linux-2.4.10-lia/include/linux/smp.h --- linux-2.4.10/include/linux/smp.h Fri Aug 10 18:13:47 2001 +++ linux-2.4.10-lia/include/linux/smp.h Mon Sep 24 22:26:48 2001 @@ -35,11 +35,6 @@ extern void smp_boot_cpus(void); /* - * Processor call in. Must hold processors until .. - */ -extern void smp_callin(void); - -/* * Multiprocessors may now schedule */ extern void smp_commence(void); @@ -53,13 +48,9 @@ /* * True once the per process idle is forked */ -extern int smp_threads_ready; +extern volatile int smp_threads_ready; extern int smp_num_cpus; - -extern volatile unsigned long smp_msg_data; -extern volatile int smp_src_cpu; -extern volatile int smp_msg_id; #define MSG_ALL_BUT_SELF 0x8000 /* Assume <32768 CPU's */ #define MSG_ALL 0x8001 diff -urN linux-2.4.10/include/linux/string.h linux-2.4.10-lia/include/linux/string.h --- linux-2.4.10/include/linux/string.h Fri Aug 10 18:13:47 2001 +++ linux-2.4.10-lia/include/linux/string.h Mon Jul 23 14:21:49 2001 @@ -79,6 +79,7 @@ #ifndef __HAVE_ARCH_MEMCHR extern void * memchr(const void *,int,__kernel_size_t); #endif +extern char * kstrdup(const char *,int); #ifdef __cplusplus } diff -urN linux-2.4.10/include/linux/time.h linux-2.4.10-lia/include/linux/time.h --- linux-2.4.10/include/linux/time.h Fri Aug 10 18:13:46 2001 +++ linux-2.4.10-lia/include/linux/time.h Mon Sep 24 22:20:43 2001 @@ -101,7 +101,10 @@ extern void do_gettimeofday(struct timeval *tv); extern void do_settimeofday(struct timeval *tv); extern void get_fast_time(struct timeval *tv); -extern void (*do_get_fast_time)(struct timeval *); +# ifdef __ia64__ + /* XXX clean this up: this should be platform-specific... */ + extern void (*do_get_fast_time)(struct timeval *); +# endif #endif #define FD_SETSIZE __FD_SETSIZE diff -urN linux-2.4.10/include/net/inetpeer.h linux-2.4.10-lia/include/net/inetpeer.h --- linux-2.4.10/include/net/inetpeer.h Fri Aug 10 18:13:48 2001 +++ linux-2.4.10-lia/include/net/inetpeer.h Mon Sep 24 23:02:57 2001 @@ -38,7 +38,7 @@ extern struct inet_peer *inet_peer_unused_head; extern struct inet_peer **inet_peer_unused_tailp; /* can be called from BH context or outside */ -extern inline void inet_putpeer(struct inet_peer *p) +static inline void inet_putpeer(struct inet_peer *p) { spin_lock_bh(&inet_peer_unused_lock); if (atomic_dec_and_test(&p->refcnt)) { @@ -53,7 +53,7 @@ extern spinlock_t inet_peer_idlock; /* can be called with or without local BH being disabled */ -extern inline __u16 inet_getid(struct inet_peer *p) +static inline __u16 inet_getid(struct inet_peer *p) { __u16 id; diff -urN linux-2.4.10/init/main.c linux-2.4.10-lia/init/main.c --- linux-2.4.10/init/main.c Mon Sep 24 15:08:36 2001 +++ linux-2.4.10-lia/init/main.c Mon Sep 24 15:24:11 2001 @@ -107,6 +107,9 @@ #if defined(CONFIG_SYSVIPC) extern void ipc_init(void); #endif +#ifdef CONFIG_PERFMON +extern void perfmon_init(void); +#endif /* * Boot command-line arguments @@ -572,6 +575,9 @@ #endif mem_init(); kmem_cache_sizes_init(); +#ifdef CONFIG_PERFMON + perfmon_init(); +#endif mempages = num_physpages; fork_init(mempages); diff -urN linux-2.4.10/kernel/ksyms.c linux-2.4.10-lia/kernel/ksyms.c --- linux-2.4.10/kernel/ksyms.c Mon Sep 24 15:08:37 2001 +++ linux-2.4.10-lia/kernel/ksyms.c Mon Sep 24 15:24:11 2001 @@ -349,7 +349,7 @@ EXPORT_SYMBOL(del_timer); EXPORT_SYMBOL(request_irq); EXPORT_SYMBOL(free_irq); -#if !defined(CONFIG_ARCH_S390) +#if !defined(CONFIG_ARCH_S390) && !defined(CONFIG_IA64) EXPORT_SYMBOL(irq_stat); /* No separate irq_stat for s390, it is part of PSA */ #endif diff -urN linux-2.4.10/kernel/module.c linux-2.4.10-lia/kernel/module.c --- linux-2.4.10/kernel/module.c Mon Sep 24 15:08:37 2001 +++ linux-2.4.10-lia/kernel/module.c Mon Sep 24 21:29:34 2001 @@ -245,7 +245,6 @@ void __init init_modules(void) { kernel_module.nsyms = __stop___ksymtab - __start___ksymtab; - arch_init_modules(&kernel_module); } diff -urN linux-2.4.10/kernel/pm.c linux-2.4.10-lia/kernel/pm.c --- linux-2.4.10/kernel/pm.c Fri Apr 6 10:51:19 2001 +++ linux-2.4.10-lia/kernel/pm.c Mon Jul 23 14:22:24 2001 @@ -162,7 +162,7 @@ case PM_SUSPEND: case PM_RESUME: prev_state = dev->state; - next_state = (int) data; + next_state = (long) data; if (prev_state != next_state) { if (dev->callback) status = (*dev->callback)(dev, rqst, data); @@ -197,7 +197,7 @@ */ pm_request_t undo = (dev->prev_state ? PM_SUSPEND:PM_RESUME); - pm_send(dev, undo, (void*) dev->prev_state); + pm_send(dev, undo, (void*) (long) dev->prev_state); } entry = entry->prev; } diff -urN linux-2.4.10/kernel/printk.c linux-2.4.10-lia/kernel/printk.c --- linux-2.4.10/kernel/printk.c Mon Sep 24 15:08:37 2001 +++ linux-2.4.10-lia/kernel/printk.c Mon Sep 24 21:29:44 2001 @@ -310,6 +310,12 @@ __call_console_drivers(start, end); } } +#ifdef CONFIG_IA64_EARLY_PRINTK + if (!console_drivers) { + static void early_printk (const char *str, size_t len); + early_printk(&LOG_BUF(start), end - start); + } +#endif } /* @@ -648,3 +654,50 @@ tty->driver.write(tty, 0, msg, strlen(msg)); return; } + +#ifdef CONFIG_IA64_EARLY_PRINTK + +#include + +#define VGABASE ((char *)0xc0000000000b8000) +#define VGALINES 24 +#define VGACOLS 80 + +static int current_ypos = VGALINES, current_xpos = 0; + +void +early_printk (const char *str, size_t len) +{ + char c; + int i, k, j; + + while (len-- > 0) { + c = *str++; + if (current_ypos >= VGALINES) { + /* scroll 1 line up */ + for (k = 1, j = 0; k < VGALINES; k++, j++) { + for (i = 0; i < VGACOLS; i++) { + writew(readw(VGABASE + 2*(VGACOLS*k + i)), + VGABASE + 2*(VGACOLS*j + i)); + } + } + for (i = 0; i < VGACOLS; i++) { + writew(0x720, VGABASE + 2*(VGACOLS*j + i)); + } + current_ypos = VGALINES-1; + } + if (c == '\n') { + current_xpos = 0; + current_ypos++; + } else if (c != '\r') { + writew(((0x7 << 8) | (unsigned short) c), + VGABASE + 2*(VGACOLS*current_ypos + current_xpos++)); + if (current_xpos >= VGACOLS) { + current_xpos = 0; + current_ypos++; + } + } + } +} + +#endif /* CONFIG_IA64_EARLY_PRINTK */ diff -urN linux-2.4.10/kernel/ptrace.c linux-2.4.10-lia/kernel/ptrace.c --- linux-2.4.10/kernel/ptrace.c Mon Sep 24 15:08:37 2001 +++ linux-2.4.10-lia/kernel/ptrace.c Mon Sep 24 15:24:12 2001 @@ -126,14 +126,14 @@ flush_cache_page(vma, addr); if (write) { - maddr = kmap(page); - memcpy(maddr + (addr & ~PAGE_MASK), buf, len); + maddr = kmap(page) + (addr & ~PAGE_MASK); + memcpy(maddr, buf, len); flush_page_to_ram(page); - flush_icache_page(vma, page); + flush_icache_range((unsigned long) maddr, (unsigned long)maddr + len); kunmap(page); } else { - maddr = kmap(page); - memcpy(buf, maddr + (addr & ~PAGE_MASK), len); + maddr = kmap(page) + (addr & ~PAGE_MASK); + memcpy(buf, maddr, len); flush_page_to_ram(page); kunmap(page); } @@ -143,7 +143,7 @@ fault_in_page: spin_unlock(&mm->page_table_lock); /* -1: out of memory. 0 - unmapped page */ - if (handle_mm_fault(mm, vma, addr, write) > 0) + if (handle_mm_fault(mm, vma, addr, write ? VM_WRITE : VM_READ) > 0) goto repeat; return 0; diff -urN linux-2.4.10/kernel/sched.c linux-2.4.10-lia/kernel/sched.c --- linux-2.4.10/kernel/sched.c Mon Sep 24 15:08:37 2001 +++ linux-2.4.10-lia/kernel/sched.c Mon Sep 24 21:29:47 2001 @@ -266,7 +266,7 @@ target_tsk = tsk; } } else { - if (oldest_idle == -1ULL) { + if (oldest_idle == (cycles_t) -1) { int prio = preemption_goodness(tsk, p, cpu); if (prio > max_prio) { @@ -278,7 +278,7 @@ } tsk = target_tsk; if (tsk) { - if (oldest_idle != -1ULL) { + if (oldest_idle != (cycles_t) -1) { best_cpu = tsk->processor; goto send_now_idle; } diff -urN linux-2.4.10/kernel/signal.c linux-2.4.10-lia/kernel/signal.c --- linux-2.4.10/kernel/signal.c Mon Sep 24 15:08:37 2001 +++ linux-2.4.10-lia/kernel/signal.c Mon Sep 24 22:13:29 2001 @@ -1104,8 +1104,19 @@ ss_sp = NULL; } else { error = -ENOMEM; +#ifdef __ia64__ + /* + * XXX fix me: due to an oversight, MINSIGSTKSZ used to be defined + * as 2KB, which is far too small. This was after Linux kernel + * 2.4.9 but since there are a fair number of ia64 apps out there, + * we continue to allow "too" small sigaltstacks for a while. + */ + if (ss_size < 2048) + goto out; +#else if (ss_size < MINSIGSTKSZ) goto out; +#endif } current->sas_ss_sp = (unsigned long) ss_sp; diff -urN linux-2.4.10/kernel/softirq.c linux-2.4.10-lia/kernel/softirq.c --- linux-2.4.10/kernel/softirq.c Mon Sep 24 15:08:38 2001 +++ linux-2.4.10-lia/kernel/softirq.c Mon Sep 24 15:24:13 2001 @@ -40,7 +40,10 @@ - Bottom halves: globally serialized, grr... */ +/* No separate irq_stat for ia64, it is part of PSA */ +#if !defined(CONFIG_IA64) irq_cpustat_t irq_stat[NR_CPUS]; +#endif /* CONFIG_IA64 */ static struct softirq_action softirq_vec[32] __cacheline_aligned; @@ -60,7 +63,6 @@ asmlinkage void do_softirq() { - int cpu = smp_processor_id(); __u32 pending; long flags; __u32 mask; @@ -70,7 +72,7 @@ local_irq_save(flags); - pending = softirq_pending(cpu); + pending = local_softirq_pending(); if (pending) { struct softirq_action *h; @@ -79,7 +81,7 @@ local_bh_disable(); restart: /* Reset the pending bitmask before enabling irqs */ - softirq_pending(cpu) = 0; + local_softirq_pending() = 0; local_irq_enable(); @@ -94,7 +96,7 @@ local_irq_disable(); - pending = softirq_pending(cpu); + pending = local_softirq_pending(); if (pending & mask) { mask &= ~pending; goto restart; @@ -102,7 +104,7 @@ __local_bh_enable(); if (pending) - wakeup_softirqd(cpu); + wakeup_softirqd(smp_processor_id()); } local_irq_restore(flags); @@ -124,7 +126,7 @@ * Otherwise we wake up ksoftirqd to make sure we * schedule the softirq soon. */ - if (!(local_irq_count(cpu) | local_bh_count(cpu))) + if (!(irq_count(cpu) | bh_count(cpu))) wakeup_softirqd(cpu); } @@ -288,18 +290,16 @@ static void bh_action(unsigned long nr) { - int cpu = smp_processor_id(); - if (!spin_trylock(&global_bh_lock)) goto resched; - if (!hardirq_trylock(cpu)) + if (!local_hardirq_trylock()) goto resched_unlock; if (bh_base[nr]) bh_base[nr](); - hardirq_endlock(cpu); + local_hardirq_endlock(); spin_unlock(&global_bh_lock); return; @@ -378,15 +378,15 @@ __set_current_state(TASK_INTERRUPTIBLE); mb(); - ksoftirqd_task(cpu) = current; + local_ksoftirqd_task() = current; for (;;) { - if (!softirq_pending(cpu)) + if (!local_softirq_pending()) schedule(); __set_current_state(TASK_RUNNING); - while (softirq_pending(cpu)) { + while (local_softirq_pending()) { do_softirq(); if (current->need_resched) schedule(); diff -urN linux-2.4.10/kernel/time.c linux-2.4.10-lia/kernel/time.c --- linux-2.4.10/kernel/time.c Mon Oct 16 12:58:51 2000 +++ linux-2.4.10-lia/kernel/time.c Tue Aug 14 00:08:58 2001 @@ -36,11 +36,16 @@ */ struct timezone sys_tz; +#ifndef __ia64__ + static void do_normal_gettime(struct timeval * tm) { *tm=xtime; } +/* This indirection is needed only for x86 and other architectures + which do not have uniform support for cycle counters... */ + void (*do_get_fast_time)(struct timeval *) = do_normal_gettime; /* @@ -54,9 +59,12 @@ do_get_fast_time(t); } +#endif /* !__ia64__ */ + /* The xtime_lock is not only serializing the xtime read/writes but it's also serializing all accesses to the global NTP variables now. */ extern rwlock_t xtime_lock; +extern unsigned long last_time_offset; #if !defined(__alpha__) && !defined(__ia64__) @@ -100,6 +108,7 @@ write_lock_irq(&xtime_lock); xtime.tv_sec = value; xtime.tv_usec = 0; + last_time_offset = 0; time_adjust = 0; /* stop active adjtime() */ time_status |= STA_UNSYNC; time_maxerror = NTP_PHASE_LIMIT; @@ -145,6 +154,7 @@ { write_lock_irq(&xtime_lock); xtime.tv_sec += sys_tz.tz_minuteswest * 60; + last_time_offset = 0; write_unlock_irq(&xtime_lock); } @@ -231,13 +241,13 @@ /* In order to modify anything, you gotta be super-user! */ if (txc->modes && !capable(CAP_SYS_TIME)) return -EPERM; - + /* Now we validate the data before disabling interrupts */ if (txc->modes != ADJ_OFFSET_SINGLESHOT && (txc->modes & ADJ_OFFSET)) /* adjustment Offset limited to +- .512 seconds */ if (txc->offset <= - MAXPHASE || txc->offset >= MAXPHASE ) - return -EINVAL; + return -EINVAL; /* if the quartz is off by more than 10% something is VERY wrong ! */ if (txc->modes & ADJ_TICK) @@ -374,7 +384,7 @@ && (time_status & (STA_PPSWANDER|STA_PPSERROR)) != 0)) /* p. 24, (d) */ result = TIME_ERROR; - + if ((txc->modes & ADJ_OFFSET_SINGLESHOT) == ADJ_OFFSET_SINGLESHOT) txc->offset = save_adjust; else { @@ -399,6 +409,7 @@ txc->calcnt = pps_calcnt; txc->errcnt = pps_errcnt; txc->stbcnt = pps_stbcnt; + last_time_offset = 0; write_unlock_irq(&xtime_lock); do_gettimeofday(&txc->time); return(result); diff -urN linux-2.4.10/kernel/timer.c linux-2.4.10-lia/kernel/timer.c --- linux-2.4.10/kernel/timer.c Tue Jun 12 16:40:11 2001 +++ linux-2.4.10-lia/kernel/timer.c Mon Jul 23 13:50:45 2001 @@ -592,7 +592,7 @@ else kstat.per_cpu_user[cpu] += user_tick; kstat.per_cpu_system[cpu] += system; - } else if (local_bh_count(cpu) || local_irq_count(cpu) > 1) + } else if (local_bh_count() || local_irq_count() > 1) kstat.per_cpu_system[cpu] += system; } @@ -644,6 +644,7 @@ * This spinlock protect us from races in SMP while playing with xtime. -arca */ rwlock_t xtime_lock = RW_LOCK_UNLOCKED; +unsigned long last_time_offset; static inline void update_times(void) { @@ -661,6 +662,7 @@ wall_jiffies += ticks; update_wall_time(ticks); } + last_time_offset = 0; write_unlock_irq(&xtime_lock); calc_load(ticks); } @@ -673,7 +675,7 @@ void do_timer(struct pt_regs *regs) { - (*(unsigned long *)&jiffies)++; + (*(volatile unsigned long *)&jiffies)++; #ifndef CONFIG_SMP /* SMP process accounting uses the local APIC timer */ @@ -805,7 +807,7 @@ if (t.tv_nsec >= 1000000000L || t.tv_nsec < 0 || t.tv_sec < 0) return -EINVAL; - +#if !defined(__ia64__) if (t.tv_sec == 0 && t.tv_nsec <= 2000000L && current->policy != SCHED_OTHER) { @@ -818,6 +820,7 @@ udelay((t.tv_nsec + 999) / 1000); return 0; } +#endif expire = timespec_to_jiffies(&t) + (t.tv_sec || t.tv_nsec); diff -urN linux-2.4.10/lib/Makefile linux-2.4.10-lia/lib/Makefile --- linux-2.4.10/lib/Makefile Mon Sep 24 15:08:39 2001 +++ linux-2.4.10-lia/lib/Makefile Mon Sep 24 21:29:52 2001 @@ -10,7 +10,7 @@ export-objs := cmdline.o dec_and_lock.o rwsem-spinlock.o rwsem.o -obj-y := errno.o ctype.o string.o vsprintf.o brlock.o cmdline.o bust_spinlocks.o rbtree.o +obj-y := errno.o ctype.o string.o vsprintf.o brlock.o cmdline.o bust_spinlocks.o rbtree.o crc32.o obj-$(CONFIG_RWSEM_GENERIC_SPINLOCK) += rwsem-spinlock.o obj-$(CONFIG_RWSEM_XCHGADD_ALGORITHM) += rwsem.o diff -urN linux-2.4.10/lib/crc32.c linux-2.4.10-lia/lib/crc32.c --- linux-2.4.10/lib/crc32.c Wed Dec 31 16:00:00 1969 +++ linux-2.4.10-lia/lib/crc32.c Wed Dec 6 22:41:15 2000 @@ -0,0 +1,125 @@ +/* + * Dec 5, 2000 Matt Domsch + * - Copied crc32.c from the linux/drivers/net/cipe directory. + * - Now pass seed as an arg + * - changed unsigned long to u32, added #include + * - changed len to be an unsigned long + * - changed crc32val to be a register + * - License remains unchanged! It's still GPL-compatable! + */ + + /* ============================================================= */ + /* COPYRIGHT (C) 1986 Gary S. Brown. You may use this program, or */ + /* code or tables extracted from it, as desired without restriction. */ + /* */ + /* First, the polynomial itself and its table of feedback terms. The */ + /* polynomial is */ + /* X^32+X^26+X^23+X^22+X^16+X^12+X^11+X^10+X^8+X^7+X^5+X^4+X^2+X^1+X^0 */ + /* */ + /* Note that we take it "backwards" and put the highest-order term in */ + /* the lowest-order bit. The X^32 term is "implied"; the LSB is the */ + /* X^31 term, etc. The X^0 term (usually shown as "+1") results in */ + /* the MSB being 1. */ + /* */ + /* Note that the usual hardware shift register implementation, which */ + /* is what we're using (we're merely optimizing it by doing eight-bit */ + /* chunks at a time) shifts bits into the lowest-order term. In our */ + /* implementation, that means shifting towards the right. Why do we */ + /* do it this way? Because the calculated CRC must be transmitted in */ + /* order from highest-order term to lowest-order term. UARTs transmit */ + /* characters in order from LSB to MSB. By storing the CRC this way, */ + /* we hand it to the UART in the order low-byte to high-byte; the UART */ + /* sends each low-bit to hight-bit; and the result is transmission bit */ + /* by bit from highest- to lowest-order term without requiring any bit */ + /* shuffling on our part. Reception works similarly. */ + /* */ + /* The feedback terms table consists of 256, 32-bit entries. Notes: */ + /* */ + /* The table can be generated at runtime if desired; code to do so */ + /* is shown later. It might not be obvious, but the feedback */ + /* terms simply represent the results of eight shift/xor opera- */ + /* tions for all combinations of data and CRC register values. */ + /* */ + /* The values must be right-shifted by eight bits by the "updcrc" */ + /* logic; the shift must be unsigned (bring in zeroes). On some */ + /* hardware you could probably optimize the shift in assembler by */ + /* using byte-swap instructions. */ + /* polynomial $edb88320 */ + /* */ + /* -------------------------------------------------------------------- */ + +#include + +static u32 crc32_tab[] = { + 0x00000000L, 0x77073096L, 0xee0e612cL, 0x990951baL, 0x076dc419L, + 0x706af48fL, 0xe963a535L, 0x9e6495a3L, 0x0edb8832L, 0x79dcb8a4L, + 0xe0d5e91eL, 0x97d2d988L, 0x09b64c2bL, 0x7eb17cbdL, 0xe7b82d07L, + 0x90bf1d91L, 0x1db71064L, 0x6ab020f2L, 0xf3b97148L, 0x84be41deL, + 0x1adad47dL, 0x6ddde4ebL, 0xf4d4b551L, 0x83d385c7L, 0x136c9856L, + 0x646ba8c0L, 0xfd62f97aL, 0x8a65c9ecL, 0x14015c4fL, 0x63066cd9L, + 0xfa0f3d63L, 0x8d080df5L, 0x3b6e20c8L, 0x4c69105eL, 0xd56041e4L, + 0xa2677172L, 0x3c03e4d1L, 0x4b04d447L, 0xd20d85fdL, 0xa50ab56bL, + 0x35b5a8faL, 0x42b2986cL, 0xdbbbc9d6L, 0xacbcf940L, 0x32d86ce3L, + 0x45df5c75L, 0xdcd60dcfL, 0xabd13d59L, 0x26d930acL, 0x51de003aL, + 0xc8d75180L, 0xbfd06116L, 0x21b4f4b5L, 0x56b3c423L, 0xcfba9599L, + 0xb8bda50fL, 0x2802b89eL, 0x5f058808L, 0xc60cd9b2L, 0xb10be924L, + 0x2f6f7c87L, 0x58684c11L, 0xc1611dabL, 0xb6662d3dL, 0x76dc4190L, + 0x01db7106L, 0x98d220bcL, 0xefd5102aL, 0x71b18589L, 0x06b6b51fL, + 0x9fbfe4a5L, 0xe8b8d433L, 0x7807c9a2L, 0x0f00f934L, 0x9609a88eL, + 0xe10e9818L, 0x7f6a0dbbL, 0x086d3d2dL, 0x91646c97L, 0xe6635c01L, + 0x6b6b51f4L, 0x1c6c6162L, 0x856530d8L, 0xf262004eL, 0x6c0695edL, + 0x1b01a57bL, 0x8208f4c1L, 0xf50fc457L, 0x65b0d9c6L, 0x12b7e950L, + 0x8bbeb8eaL, 0xfcb9887cL, 0x62dd1ddfL, 0x15da2d49L, 0x8cd37cf3L, + 0xfbd44c65L, 0x4db26158L, 0x3ab551ceL, 0xa3bc0074L, 0xd4bb30e2L, + 0x4adfa541L, 0x3dd895d7L, 0xa4d1c46dL, 0xd3d6f4fbL, 0x4369e96aL, + 0x346ed9fcL, 0xad678846L, 0xda60b8d0L, 0x44042d73L, 0x33031de5L, + 0xaa0a4c5fL, 0xdd0d7cc9L, 0x5005713cL, 0x270241aaL, 0xbe0b1010L, + 0xc90c2086L, 0x5768b525L, 0x206f85b3L, 0xb966d409L, 0xce61e49fL, + 0x5edef90eL, 0x29d9c998L, 0xb0d09822L, 0xc7d7a8b4L, 0x59b33d17L, + 0x2eb40d81L, 0xb7bd5c3bL, 0xc0ba6cadL, 0xedb88320L, 0x9abfb3b6L, + 0x03b6e20cL, 0x74b1d29aL, 0xead54739L, 0x9dd277afL, 0x04db2615L, + 0x73dc1683L, 0xe3630b12L, 0x94643b84L, 0x0d6d6a3eL, 0x7a6a5aa8L, + 0xe40ecf0bL, 0x9309ff9dL, 0x0a00ae27L, 0x7d079eb1L, 0xf00f9344L, + 0x8708a3d2L, 0x1e01f268L, 0x6906c2feL, 0xf762575dL, 0x806567cbL, + 0x196c3671L, 0x6e6b06e7L, 0xfed41b76L, 0x89d32be0L, 0x10da7a5aL, + 0x67dd4accL, 0xf9b9df6fL, 0x8ebeeff9L, 0x17b7be43L, 0x60b08ed5L, + 0xd6d6a3e8L, 0xa1d1937eL, 0x38d8c2c4L, 0x4fdff252L, 0xd1bb67f1L, + 0xa6bc5767L, 0x3fb506ddL, 0x48b2364bL, 0xd80d2bdaL, 0xaf0a1b4cL, + 0x36034af6L, 0x41047a60L, 0xdf60efc3L, 0xa867df55L, 0x316e8eefL, + 0x4669be79L, 0xcb61b38cL, 0xbc66831aL, 0x256fd2a0L, 0x5268e236L, + 0xcc0c7795L, 0xbb0b4703L, 0x220216b9L, 0x5505262fL, 0xc5ba3bbeL, + 0xb2bd0b28L, 0x2bb45a92L, 0x5cb36a04L, 0xc2d7ffa7L, 0xb5d0cf31L, + 0x2cd99e8bL, 0x5bdeae1dL, 0x9b64c2b0L, 0xec63f226L, 0x756aa39cL, + 0x026d930aL, 0x9c0906a9L, 0xeb0e363fL, 0x72076785L, 0x05005713L, + 0x95bf4a82L, 0xe2b87a14L, 0x7bb12baeL, 0x0cb61b38L, 0x92d28e9bL, + 0xe5d5be0dL, 0x7cdcefb7L, 0x0bdbdf21L, 0x86d3d2d4L, 0xf1d4e242L, + 0x68ddb3f8L, 0x1fda836eL, 0x81be16cdL, 0xf6b9265bL, 0x6fb077e1L, + 0x18b74777L, 0x88085ae6L, 0xff0f6a70L, 0x66063bcaL, 0x11010b5cL, + 0x8f659effL, 0xf862ae69L, 0x616bffd3L, 0x166ccf45L, 0xa00ae278L, + 0xd70dd2eeL, 0x4e048354L, 0x3903b3c2L, 0xa7672661L, 0xd06016f7L, + 0x4969474dL, 0x3e6e77dbL, 0xaed16a4aL, 0xd9d65adcL, 0x40df0b66L, + 0x37d83bf0L, 0xa9bcae53L, 0xdebb9ec5L, 0x47b2cf7fL, 0x30b5ffe9L, + 0xbdbdf21cL, 0xcabac28aL, 0x53b39330L, 0x24b4a3a6L, 0xbad03605L, + 0xcdd70693L, 0x54de5729L, 0x23d967bfL, 0xb3667a2eL, 0xc4614ab8L, + 0x5d681b02L, 0x2a6f2b94L, 0xb40bbe37L, 0xc30c8ea1L, 0x5a05df1bL, + 0x2d02ef8dL + }; + +/* Return a 32-bit CRC of the contents of the buffer. */ + +u32 +crc32(const void *buf, unsigned long len, u32 seed) +{ + unsigned long i; + register u32 crc32val; + const unsigned char *s = buf; + + crc32val = seed; + for (i = 0; i < len; i ++) + { + crc32val = + crc32_tab[(crc32val ^ s[i]) & 0xff] ^ + (crc32val >> 8); + } + return crc32val; +} diff -urN linux-2.4.10/lib/dec_and_lock.c linux-2.4.10-lia/lib/dec_and_lock.c --- linux-2.4.10/lib/dec_and_lock.c Mon Sep 24 15:08:39 2001 +++ linux-2.4.10-lia/lib/dec_and_lock.c Mon Sep 24 22:13:39 2001 @@ -26,7 +26,6 @@ * store-conditional approach, for example. */ -#ifndef atomic_dec_and_lock int atomic_dec_and_lock(atomic_t *atomic, spinlock_t *lock) { spin_lock(lock); @@ -37,4 +36,3 @@ } EXPORT_SYMBOL(atomic_dec_and_lock); -#endif diff -urN linux-2.4.10/mm/memory.c linux-2.4.10-lia/mm/memory.c --- linux-2.4.10/mm/memory.c Mon Sep 24 15:08:39 2001 +++ linux-2.4.10-lia/mm/memory.c Mon Sep 24 21:30:00 2001 @@ -44,6 +44,7 @@ #include #include #include +#include #include #include @@ -126,7 +127,7 @@ pmd = pmd_offset(dir, 0); pgd_clear(dir); for (j = 0; j < PTRS_PER_PMD ; j++) { - prefetchw(pmd+j+(PREFETCH_STRIDE/16)); + prefetchw(pmd + j + PREFETCH_STRIDE/sizeof(*pmd)); free_one_pmd(pmd+j); } pmd_free(pmd); @@ -511,7 +512,7 @@ int ret; spin_unlock(&mm->page_table_lock); - ret = handle_mm_fault(current->mm, vma, ptr, datain); + ret = handle_mm_fault(current->mm, vma, ptr, datain ? VM_WRITE : VM_READ); if (ret <= 0) { if (!ret) goto out_unlock; @@ -1166,7 +1167,6 @@ UnlockPage(page); flush_page_to_ram(page); - flush_icache_page(vma, page); set_pte(page_table, pte); /* No need to invalidate - it was non-present before */ @@ -1267,7 +1267,6 @@ if (pte_none(*page_table)) { ++mm->rss; flush_page_to_ram(new_page); - flush_icache_page(vma, new_page); entry = mk_pte(new_page, vma->vm_page_prot); if (write_access) { entry = pte_mkwrite(pte_mkdirty(entry)); @@ -1306,8 +1305,10 @@ */ static inline int handle_pte_fault(struct mm_struct *mm, struct vm_area_struct * vma, unsigned long address, - int write_access, pte_t * pte) + int access_type, pte_t * pte) { + int write_access = is_write_access(access_type); + int exec_access = is_exec_access(access_type); pte_t entry; entry = *pte; @@ -1328,6 +1329,8 @@ entry = pte_mkdirty(entry); } + if (exec_access) + entry = pte_mkexec(entry); entry = pte_mkyoung(entry); establish_pte(vma, address, pte, entry); return 1; @@ -1337,7 +1340,7 @@ * By the time we get here, we already hold the mm semaphore */ int handle_mm_fault(struct mm_struct *mm, struct vm_area_struct * vma, - unsigned long address, int write_access) + unsigned long address, int access_type) { int ret = -1; pgd_t *pgd; @@ -1356,7 +1359,7 @@ if (pmd) { pte_t * pte = pte_alloc(mm, pmd, address); if (pte) - ret = handle_pte_fault(mm, vma, address, write_access, pte); + ret = handle_pte_fault(mm, vma, address, access_type, pte); } spin_unlock(&mm->page_table_lock); return ret; @@ -1447,7 +1450,7 @@ if (addr >= end) BUG(); do { - if (handle_mm_fault(mm, vma, addr, write) < 0) + if (handle_mm_fault(mm, vma, addr, write ? VM_WRITE : VM_READ) < 0) return -1; addr += PAGE_SIZE; } while (addr < end); diff -urN linux-2.4.10/mm/mmap.c linux-2.4.10-lia/mm/mmap.c --- linux-2.4.10/mm/mmap.c Mon Sep 24 15:08:39 2001 +++ linux-2.4.10-lia/mm/mmap.c Mon Sep 24 15:24:14 2001 @@ -204,6 +204,12 @@ _trans(prot, PROT_WRITE, VM_WRITE) | _trans(prot, PROT_EXEC, VM_EXEC); flag_bits = +#ifdef MAP_WRITECOMBINED + _trans(flags, MAP_WRITECOMBINED, VM_WRITECOMBINED) | +#endif +#ifdef MAP_NONCACHED + _trans(flags, MAP_NONCACHED, VM_NONCACHED) | +#endif _trans(flags, MAP_GROWSDOWN, VM_GROWSDOWN) | _trans(flags, MAP_DENYWRITE, VM_DENYWRITE) | _trans(flags, MAP_EXECUTABLE, VM_EXECUTABLE); diff -urN linux-2.4.10/mm/shmem.c linux-2.4.10-lia/mm/shmem.c --- linux-2.4.10/mm/shmem.c Mon Sep 24 15:08:39 2001 +++ linux-2.4.10-lia/mm/shmem.c Mon Sep 24 15:24:14 2001 @@ -26,7 +26,7 @@ #include #include #include -#include +#include #include diff -urN linux-2.4.10/net/ipv4/fib_semantics.c linux-2.4.10-lia/net/ipv4/fib_semantics.c --- linux-2.4.10/net/ipv4/fib_semantics.c Tue Aug 22 08:59:00 2000 +++ linux-2.4.10-lia/net/ipv4/fib_semantics.c Tue Aug 14 00:53:33 2001 @@ -155,7 +155,7 @@ return 0; } -extern __inline__ struct fib_info * fib_find_info(const struct fib_info *nfi) +static __inline__ struct fib_info * fib_find_info(const struct fib_info *nfi) { for_fib_info() { if (fi->fib_nhs != nfi->fib_nhs) diff -urN linux-2.4.10/net/ipv4/ip_fragment.c linux-2.4.10-lia/net/ipv4/ip_fragment.c --- linux-2.4.10/net/ipv4/ip_fragment.c Mon Sep 24 15:08:41 2001 +++ linux-2.4.10-lia/net/ipv4/ip_fragment.c Mon Sep 24 15:24:16 2001 @@ -130,19 +130,19 @@ atomic_t ip_frag_mem = ATOMIC_INIT(0); /* Memory used for fragments */ /* Memory Tracking Functions. */ -extern __inline__ void frag_kfree_skb(struct sk_buff *skb) +static __inline__ void frag_kfree_skb(struct sk_buff *skb) { atomic_sub(skb->truesize, &ip_frag_mem); kfree_skb(skb); } -extern __inline__ void frag_free_queue(struct ipq *qp) +static __inline__ void frag_free_queue(struct ipq *qp) { atomic_sub(sizeof(struct ipq), &ip_frag_mem); kfree(qp); } -extern __inline__ struct ipq *frag_alloc_queue(void) +static __inline__ struct ipq *frag_alloc_queue(void) { struct ipq *qp = kmalloc(sizeof(struct ipq), GFP_ATOMIC);